© 2009 Semtech Corporation 1
SC414/SC424
6A Integrated FET Regulator
with 5V LDO
Features
Input voltage — 3V to 28V
Internal power MOSFETs — 6A
Integrated bootstrap switch
Smart power-save protection
Integrated 5V, 150mA LDO with bypass capability
TC compensated RDS(ON) sensed current limit
Pseudo- xed frequency adaptive on-time control
Designed for use with ceramic capacitors
Programmable VIN UVLO threshold
Independent enable for switcher and LDO
Selectable ultrasonic power-save (SC414)
Selectable power-save (SC424)
Internal soft-start and soft-shutdown at output
Internal reference — 1% tolerance
Over-voltage and under-voltage fault protection
Power good output
SmartDriveTM
Lead-free 4x4mm, 28 Pin MLPQ package
Fully WEEE and RoHS compliant, and halogen free
Applications
Notebook, desktop, tablet, and server computers
Networking and telecommunication equipment
Printers, DSL, and STB applications
Embedded applications
Power supply modules
Point of load power supplies
Description
The SC414/SC424 is a stand-alone synchronous buck regu-
lated power supply. It features integrated power MOSFETs,
a bootstrap switch, and a 5V LDO in a space-saving MLPQ-
4x4mm 28-pin package. The device is highly e cient and
uses minimal PCB area. It uses pseudo- xed frequency
adaptive on-time operation to provide fast transient
response.
The SC414/SC424 supports using standard capacitor types
such as electrolytic or special polymer, in addition to
ceramic, at switching frequencies up to 1MHz. The pro-
grammable frequency, synchronous operation, and select-
able power-save provide high e ciency operation over a
wide load range.
Additional features include cycle-by-cycle current limit,
soft-start, under and over-voltage protection, program-
mable over-current protection, soft shutdown, and select-
able power-save. The device also provides separate enable
inputs for the PWM controller and LDO as well as a power
good output for the PWM controller.
The input voltage can range from 3V to 28V. The wide
input voltage range, programmable frequency, and 5V
LDO make the device extremely  exible and easy to use in
a broad range of applications. It can be used for single cell
or multi-cell battery systems in addition to traditional DC
power supply applications.
The 5V LDO or an external 3.3V to 5V supply can be used
to provide the bias voltage for the SC414/SC424. When
the SC414/SC424 is used as a 5V output switching regula-
tor, the 5V LDO can be used as an initial bias supply for the
device. Once the switch regulator output is in the switch
over range, the LDO will be bypassed by the switcher
output for optimum e ciency.
September 11, 2009
POWER MANAGEMENT
SC414/SC424
2
ENABLE PSAVE
FB
1
V5V
2
AGND
3
VOUT
4
VIN
5
VLDO
6
BST
7
VIN
8
VIN
9
VIN
10
VIN
11
LXBST
12
PGND
13
PGND
14
LX 15
PGND 16
PGND 17
PGND 18
PGND 19
LX 20
LX 21
PGOOD
22
ILIM
23
LXS
24
EN/PSV
25
AGND
26
TON
27
ENL
28
AGND PAD 1
VIN
PAD 2
LX PAD 3
RGND
0
PGOOD
RILIM
9.09KΩ
RFB1
10KΩ
L1
C3
100nF
+12V
ENABLE LDO
RTON
154KΩ
+
COUT
220μF
C4
10nF
RFB2
30KΩ
C1 C2
1μF
1V @ 6A, 250kHz
VIN
VOUT
RPGOOD
10KΩ
V5V
CBST
1μF
All other small signal components (resistors and capacitors) are standard SMT devices.
Component Value Manufacturer Part Number Web
CIN 10μF/25V Murata GRM32DR71E106KA12L www.murata.com
www.panasonic.comCOUT 220μF/15mΩ/6.3V Panasonic EEFUE0J221R
www.vishay.com
L1 1.5μH/9A Vishay IHLP2525CZER1R5M01
Key Components
SC414/SC424
VOUT
V5V
1.5μH
FB
FB
VOUT
1μF
CIN
10μF
CIN
10μF
Typical Application Circuit
SC414/SC424
3
Pin Con guration Ordering Information
Marking Information
SC414
yyww
xxxxx
xxxxx
EN/PSV
PGOOD
AGND
PAD 1
LX
PAD 3
BST
7
VOUT
4
VLDO
6
VIN
5
V5V
2
AGND
3
FB
1Top View
LX
15
PGND
18
PGND
16
PGND
17
LX
20
PGND
19
LX
21
VIN
8
VIN
10
911 12 13 14
VIN
VIN
LXBST
PGND
PGND
28 26
27 25 24 23 22
ENL
TON
AGND
LXS
ILIM
VIN
PAD 2
Notes:
1) Available in tape and reel only. A reel contains 3000 devices.
2) Lead-free packaging only. Device is WEEE and RoHS compliant,
and halogen free.
yyww = Date Code
xxxxx = Semtech Lot Number
SC414 and SC424
MLPQ-28; 4x4, 28 LEAD
SC424
yyww
xxxxx
xxxxx
yyww = Date Code
xxxxx = Semtech Lot Number
Device Package
SC414MLTRT(1)(2) MLPQ-28 4x4
SC424MLTRT(1)(2) MLPQ-28 4x4
SC414EVB Evaluation Board
SC424EVB Evaluation Board
SC414/SC424
4
Absolute Maximum Ratings
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
LX to PGND (V) (transient — 100ns max.) . . . . . . -2 to +30
VIN to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
EN/PSV, PGOOD, ILIM, to GND (V) . . . . . . -0.3 to +(V5V + 0.3)
VOUT, VLDO, FB, to GND (V) . . . . . . . . . . . -0.3 to +(V5V + 0.3)
V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
TON to PGND (V) . . . . . . . . . . . . . . . . . . . . . -0.3 to +(V5V - 1.5)
ENL (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN
BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35
AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Recommended Operating Conditions
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28
V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5
VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 to 5.5
Thermal Information
Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . . 150
Operating Junction Temperature (°C) . . . . . . . .-40 to +125
Thermal resistance, junction to ambient (2) (°C/W)
High-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PWM controller and LDO thermal resistance . . . . . 40
Peak IR Re ow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260
Exceeding the above speci cations may result in permanent damage to the device or device malfunction. Operation outside of the parameters
speci ed in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Unless speci ed: VIN =12V, TA = +25°C for Typical, -40 to +85 °C for Min. and Max., TJ < 125°C, V5V = +5V, Typical Application Circuit
Electrical Characteristics
Parameter Conditions Min Typ Max Units
Input Supplies
VIN UVLO Threshold(1)
(not available for V5V < 4.5V)
Sensed at ENL pin, rising edge 2.40 2.60 2.95
V
Sensed at ENL pin, falling edge 2.235 2.40 2.565
VIN UVLO Hysteresis EN/PSV = High 0.2 V
V5V UVLO Threshold
Measured at V5V pin, rising edge 2.50 2.9 3.0
V
Measured at V5V pin, falling edge 2.40 2.7 2.90
V5V UVLO Hysteresis 0.2 V
VIN Supply Current
ENL, EN/PSV = 0V, VIN = 28V 8.5 20
A
Standby mode; ENL=V5V, EN/PSV = 0V 130
SC414/SC424
5
Electrical Characteristics (continued)
Parameter Conditions Min Typ Max Units
Input Supplies (continued)
V5V Supply Current
ENL, EN/PSV = 0V , V5V = 5V 3 7
A
ENL, EN/PSV = 0V , V5V = 3V 2
SC414, EN/PSV = V5V, no load (fSW = 25kHz),
VFB > 750mV(2) 1
mA
SC424, EN/PSV = V5V, no load, VFB > 750mV(2) 0.4
V5V = 5V, fSW = 250kHz, EN/PSV =  oating, no load(2) 4
V5V = 3V, fSW = 250kHz, EN/PSV =  oating, no load(2) 2.5
FB Comparator Threshold
Static VIN and load, 0 to +85 °C, V5V = 3V or 5V 0.744 0.750 0.756 V
Static VIN and load, -40 to +85 °C, V5V = 3V or 5V 0.7425 0.7575 V
Frequency Range
Continuous mode operation 1000
kHz
Minimum fSW , (SC414 only), EN/PSV = V5V, no load 25
Bootstrap Switch Resistance 10 Ω
Timing
On-Time
Continuous mode operation,
VIN = 15V, VOUT = 3V, RTON = 300kΩ 1350 1500 1650 ns
V5V < 4.5V(3)
Minimum On-Time (2) 80 ns
Minimum O -Time (2)
V5V = 5V 320
ns
V5V = 3V 390
Soft-Start
Soft-Start Ramp Time (2) 1.7 ms
Analog Inputs/Outputs
VOUT Input Resistance 500 kΩ
Current Sense
Zero-Crossing Detector Threshold LX - PGND, V5V = 3V or 5V -3 0 +3 mV
SC414/SC424
6
Electrical Characteristics (continued)
Parameter Conditions Min Typ Max Units
Power Good
Power Good Threshold
Upper limit, VFB > internal 750mV reference +20 %
Lower limit, VFB < internal 750mV reference -10 %
Start-Up Delay Time (Time between EN going
high and PGOOD going high)
V5V = 3V 2
ms
V5V = 5V 4
Fault (noise immunity) Delay Time(2) 5µs
Leakage 1µA
Power Good On-Resistance 10 Ω
Fault Protection
Valley Current Limit V5V = 5V, RILIM = 5k Ω 3 4 5 A
Valley Current Limit V5V = 3V, RILIM = 5k Ω 3.4 A
ILIM Source Current 8A
ILIM Comparator O set With respect to AGND -8 0 +8 mV
Output Under-Voltage Fault VFB with respect to internal 750mV reference,
8 consecutive clock cycles -25 %
Smart Power-save Protection Threshold (2) VFB with respect to internal 750mV reference +10 %
Over-Voltage Protection Threshold VFB with respect to internal 750mV reference +20 %
Over-Voltage Fault Delay(2) 5s
Over-Temperature Shutdown(2) 10°C hysteresis 150 °C
Logic Inputs/Outputs
Logic Input High Voltage ENL 1 V
Logic Input Low Voltage ENL 0.4 V
EN/PSV Input for PSAVE Operation (2) % of V5V 45 100 %
EN/PSV Input for Forced Continuous Operation (2) % of V5V 1V 42 %
EN/PSV Input for Disabling Switcher (2) 0 0.4 V
EN/PSV Input Bias Current EN/PSV= V5V or AGND -10 +10 A
ENL Input Bias Current VIN = 28V 11 18 A
FB Input Bias Current FB = V5V or AGND -1 +1 A
SC414/SC424
7
Electrical Characteristics (continued)
Parameter Conditions Min Typ Max Units
Linear Regulator — LDO (not available for V5V < 5V)
VLDO Accuracy VLDO load = 10mA 4.9 5.0 5.1 V
LDO Current Limit
Start-up and foldback, VIN = 12V 85
mA
Operating current limit, VIN = 12V 135 200
VLDO to VOUT Switch-over Threshold (4) -140 +140 mV
VLDO to VOUT Non-switch-over Threshold (4) -450 +450 mV
VLDO to VOUT Switch-over Resistance VOUT = +5V 2 Ω
LDO Drop Out Voltage (5) From VIN to VVLDO, VVLDO = +5V, IVLDO = 100mA 1.2 V
Notes:
(1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
(2) Guaranteed by design.
(3) For V5V less than 4.5V, the On-Time may be limited by the V5V supply voltage and by VIN. See the TON Limitations and V5V Supply Voltage
section in the applications Information.
(4) The switch-over threshold is the maximum voltage di erential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage di erential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT.
(5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point. Thermal resistance, junction
to ambient — guaranteed by design (°C/W)
SC414/SC424
8
Typical Characteristics
E ciency vs. Load — Forced Continuous Mode
I
OUT
(A)
Efficiency (%)
0
20
40
60
80
100
0.001 0.01 0.1 1 10
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
E ciency vs. Load — Powersave Mode (SC414)
I
OUT
(A)
Efficiency (%)
0
20
40
60
80
100
0.001 0.01 0.1 1 10
VOUT vs. Load — Forced Continuous Mode
I
OUT
(A)
Output Voltage (V)
0.95
0.97
0.99
1.01
1.03
1.05
0.001 0.01 0.1 110
E ciency vs. Load — Powersave Mode (SC414)
IOUT (A)
Efficiency (%)
0
20
40
60
80
100
0.001 0.01 0.1 110
5V Bias
3V Bias
E ciency vs. Load — Powersave Mode (SC424) E ciency vs. Load — Powersave Mode (SC424)
I
OUT
(A)
Efficiency (%)
0
20
40
60
80
100
0.001 0.01 0.1 110
5V Bias 3V Bias
I
OUT
(A)
Efficiency (%)
0
20
40
60
80
100
0.001 0.01 0.1 1 10
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Externally biased, VIN = 12V, VOUT = 1V
Externally biased, VIN = 12V, VOUT = 1V
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
SC414/SC424
9
Typical Characteristics (continued)
VOUT vs. Load — Powersave Mode (SC414)
I
OUT
(A)
V
OUT
(V)
0.95
0.97
0.99
1.01
1.03
1.05
0.001 0.01 0.1 1 10
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
Frequency vs. Load — Forced Continuous Mode
Frequency (kHz)
100
150
200
250
300
350
400
0.001 0.01 0.1 1 10
I
OUT
(A)
VRIPPLE vs. Load — Forced Continuous Mode
IOUT (A)
VRIPPLE (mVP_P)
0
20
40
60
80
100
0.001 0.01 0.1 110
VOUT vs. Load — Powersave Mode (SC424)
I
OUT
(A)
V
OUT
(V)
0.95
0.97
0.99
1.01
1.03
1.05
0.001 0.01 0.1 1 10
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
VOUT vs. Line — Forced Continuous Mode
Input Voltage (V)
Output Voltage (V)
0A 1.5A
6A
0.95
0.97
0.99
1.01
1.03
1.05
57 9
11 13 15 17 19 21
3A
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
VOUT vs. Line — Forced Continuous Mode
Input Voltage (V)
V
RIPPLE
(mV
P_P
)
0
20
40
60
80
100
5 7 9 111315171921
6A
3A
1.5A 0A
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
SC414/SC424
10
Ultrasonic Powersave Mode — No Load (SC414)
Time (10μs/div)
(50mV/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
Forced Continuous Mode — No Load
Time (2μs/div)
(50mV/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = ENL = 5V, EN/PSV=  oat
Enabled Loaded Output — Power Good True
(500mV/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V
Time (1ms/div)
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
Powersave Mode — No Load (SC424)
Time (10ms/div)
(50mV/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
Time (10ms/div)
Self-Biased Start-Up — Power Good True
(500mV/div)
(10V/div)
(5V/div)
VIN = 0V to 12V step, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
(2V/div)
Output Over-current Response — Normal Operation
Time (100μs/div)
(500mV/div)
(5V/div)
(5V/div)
(5A/div)
VIN = 12V, VOUT = 1V, VLDO = V5V = ENL = 5V, EN/PSV=  oating; IOUT ramped to trip point
SC414/SC424
11
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
Transient Response — Load Rising (SC414)
Time (10μs/div)
(50mV/div)
(5A/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 200mA to 6A, VLDO = V5V = EN/PSV= ENL = 5V
Transient Response — Load Falling (SC414)
Time (10μs/div)
(50mV/div)
(5A/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 6A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
Transient Response — Load Rising (SC424)
Time (10μs/div)
(50mV/div)
(5A/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 0A to 6A, VLDO = V5V = EN/PSV= ENL = 5V
Transient Response — Load Falling (SC424)
Time (10μs/div)
(50mV/div)
(5A/div)
(10V/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 6A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
Shorted Output Response — Normal Operation
Time (40μs/div)
(500mV/div)
(10V/div)
(5A/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
Shorted Output Response — Power-UP Operation
Time (1ms/div)
(500mV/div)
(10V/div)
(5A/div)
(5V/div)
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
SC414/SC424
12
Pin Descriptions
Pin # Pin Name Pin Function
1FB
Feedback input for switching regulator used to program the output voltage — connect to an external resis-
tor divider from VOUT to AGND.
2 V5V Bias input for internal analog circuits and gate drives — connect to external 3V or 5V supply or bias connec-
tion to VLDO.
3, 26, PAD 1 AGND Analog ground
4 VOUT Switcher output voltage sense pin, and also the input to the internal switch-over between VOUT and VLDO.
5, 8-11
PAD 2 VIN Input supply voltage
6 VLDO 5V LDO output
7 BST Bootstrap pin — connect a capacitor from BST to LXBST to develop the  oating supply for the high-side gate
drive.
12 LXBST LX Boost — connect to the BST capacitor.
15,20, 21,
PAD 3 LX Switching (phase) node
13, 14, 16-19 PGND Power ground
22 PGOOD Open-drain power good indicator — high impedance indicates power is good. An external pull-up
resistor is required.
23 ILIM Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS.
24 LXS LX sense — connects to RILIM resistor
25 EN/PSV
Enable/power save input for the switching regulator — connect to AGND to disable the switching regula-
tor. Float to operate in forced continuous mode (power save disabled). For SC414, connect to V5V to operate
with ultrasonic power save mode enabled. For SC424, connect to V5V to operate with power save mode
enabled with no minimum frequency.
27 TON On-time programming input — set the on-time by connecting through a resistor to AGND
28 ENL Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic con-
trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
SC414/SC424
13
Block Diagram
Reference
Soft Start
FB
AGND
On- time
Generator
Control & Status
PGOOD
Gate Drive
Control
VIN
PGND
TON
VOUT
Zero Cross Detector
ILIM
ENL
VLDO Switchover MUX
A
Y
BLDO
VLDO
BST
FB Comparator
V5V
-
EN/PSV
Bypass ComparatorBypass Comparator
DL
A
7
3
28
6
4
27
1
222 25
A = connected to pins 5, 8-11, PAD 2
B = connected to pins 15, 20, 21, PAD 3
C = connected to pins 13, 14, 16-19
D = connect to pins 3, 26, PAD 1
C
D
V
IN
V5V
V5V
V5V
V
IN
Bootstrap
Switch
Lo-side
MOSFET
Hi-side
MOSFET
Valley Current Limit
LX
B
LXBST
12
LXS
24
DL
SC414/SC424
14
Synchronous Buck Converter
The SC414/SC424 is a step down synchronous DC-DC buck
converter with integrated power MOSFETs and a 5V LDO.
The device is capable of 6A operation at very high e -
ciency. A space saving 4x4 (mm) 28-pin package is used.
The programmable operating frequency range of 200kHz
to 1MHz enables optimizing the configuration for PCB
area and e ciency.
The buck controller uses a pseudo- xed frequency adap-
tive on-time control. This control method allows fast tran-
sient response which permits the use of smaller output
capacitors.
Input Voltage Requirements
The SC414/SC424 requires two input supplies for normal
operation: VIN and V5V. VIN operates over the wide range
from 3V to 28V. V5V requires a 3.3 or 5V supply input that
can be an external source or the internal LDO con gured
to supply 5V. If the LDO is enabled, V5V voltage must be
> 5V.
Psuedo- xed Frequency Adaptive On-time Control
The PWM control method used by the SC414/SC424 is
pseudo- xed frequency, adaptive on-time, as shown in
Figure 1. The ripple voltage generated at the output
capacitor (ESR) is used as a PWM ramp signal. This ripple is
used to trigger the on-time of the controller.
Q1
Q2
L
C
OUT
ESR
+
C
IN
V
OUT
FB Threshold
V
FB
V
LX
V
LX
TON
FB
V
IN
Figure 1 — PWM Control Method, VOUT Ripple
The adaptive on-time is determined by an internal one-
shot timer. When the one-shot is triggered by the output
ripple, the device sends a single on-time pulse to the high-
side MOSFET. The pulse period is determined by VOUT and
VIN. The period is proportional to output voltage and
inversely proportional to input voltage. With this adaptive
on-time con guration, the device automatically antici-
pates the on-time needed to regulate VOUT for the present
VIN condition and at the selected frequency.
The advantages of adaptive on-time control are:
Predictable operating frequency compared to
other variable frequency methods.
Reduced component count by eliminating the
error ampli er and compensation components.
Reduced component count by removing the
need to sense and control inductor current.
Fast transient response — the response time is
controlled by a fast comparator instead of a typi-
cally slow error ampli er.
Reduced output capacitance due to fast tran-
sient response
One-Shot Timer and Operating Frequency
One-shot timer operation is shown in Figure 2. The FB
Comparator output goes high when VFB is less than the
internal 750mV reference. This feeds into the gate drive
and turns on the high-side MOSFET, and starts the one-
shot timer. The one-shot timer uses an internal compara-
tor and a capacitor. One comparator input is connected to
VOUT, the other input is connected to the capacitor. When
the on-time begins, the internal capacitor charges from
zero volts through a current which is proportional to VIN.
When the capacitor voltage reaches VOUT, the on-time is
completed and the high-side MOSFET turns o .
Gate
Drives
FB Comparator
One-Shot
Timer
On-time = K x R
TON
x (V
OUT
/V
IN
)
V
OUT
V
IN
FB
750mV Q1
Q2
L
C
OUT
V
IN
ESR
+
V
OUT
V
LX
FB
DH
DL
R
TON
+
-
Figure 2 — On-Time Generation
•
•
•
•
•
Applications Information
SC414/SC424
15
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
INON
OUT
SW VT
V
fu
The SC414/SC424 uses an external resistor to set the on-
time which indirectly sets the frequency. The on-time can
be programmed to provide an operating frequency from
200kHz to 1MHz using a resistor between the TON pin and
ground. The resistor value is selected by the following
equation.
OUT
IN
SW
TON V
V
400
fpF25
1
Ru:
u
The maximum RTON value allowed is shown by the follow-
ing equation.
A5.110
V
RMIN_IN
MAX_TON Pu
Immediately after the on-time, the DL (drive signal for the
low side FET) output drives high to turn on the low-side
MOSFET. DL has a minimum high time of ~320ns, after
which DL continues to stay high until one of the following
occurs:
VFB falls below the 750mV reference
The Zero Cross Detector senses that the voltage
on the LX node is below ground. Power Save is
activated when a zero crossing is detected.
TON limitations and V5V Supply Voltage
For V5V below 4.5V, the TON accuracy may be limited by
the input voltage.
The original RTON equation is accurate if VIN satis es the
below relation over the entire VIN range:
V
IN < (V5V - 1.6V) x 10
If VIN exceeds (V5V - 1.6V) x 10, for all or part of the VIN
range, the RTON equation is not accurate. In all cases
where VIN > (V5V - 1.6V) x 10, the RTON equation must be
modi ed as follows.
•
•
OUTSW
TON V
101.6V)(V5V
400
f25pF
1
Ru
u:
u
Note that when VIN > (V5V - 1.6V) x 10 , the actual on-time
is  xed and does not vary with VIN. When operating in this
condition, the switching frequency will vary inversely with
VIN rather than approximating a  xed frequency.
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin to the
internal 750mV reference voltage (see Figure 3).
R
1
V
OUT
To FB pin
R
2
Figure 3 — Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is o set by the output ripple according to the
following equation.
¸
¹
·
¨
©
§
¸
¸
¹
·
¨
¨
©
§u 2
V
R
R
175.0V RIPPLE
2
1
OUT
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
2
TOP
12
12
2
TOP1RIPPLE
2
1
OUT
C
RR
RR
1
)CR(1
2
V
R
R
175.0V
¸
¸
¹
·
¨
¨
©
§Z
u
Z
u
¸
¹
·
¨
©
§
¸
¸
¹
·
¨
¨
©
§u
Where ω is the angular switching frequency.
Enable and Power-save Inputs
The EN/PSV and ENL inputs are used to enable or disable
the switching regulator and the LDO. When EN/PSV is low
(grounded), the switching regulator is o and in its lowest
power state. When o , the output of the switching regula-
tor soft-discharges the output into a 10Ω internal resistor
via the VOUT pin. When EN/PSV is allowed to  oat, the pin
voltage will  oat to 33% of the voltage at V5V. The switch-
ing regulator turns on with power-save disabled and all
switching is in forced continuous mode. For V5V < 4.5V, it
Applications Information (continued)
SC414/SC424
16
is recommended to force 33% of the V5V voltage on the
EN/PSV pin to operate in forced continuous mode.
When EN/PSV is high (above 45% of the voltage at V5V)
for SC414, the switching regulator turns on with ultrasonic
power-save enabled. The SC414 ultrasonic power-save
operation maintains a minimum switching frequency of
25kHz, for applications with stringent audio
requirements.
When EN/PSV is high (above 45% of the voltage at V5V)
for SC424, the switching regulator turns on with power-
save enabled. The SC424 power-save operation is designed
to maximize e ciency at light loads with no minimum
frequency limits. This makes the SC424 an excellent choice
for portable and battery-operated systems.
The ENL input is used to control the internal LDO. This
input provides a second function by acting as a VIN ULVO
sensor for the switching regulator. When ENL is low
(grounded), the LDO is o . When ENL is a logic high but
below the VIN UVLO threshold (2.6V typical), then the LDO
is on and the switcher is o . When ENL is above the VIN
UVLO threshold, the LDO is enabled and the switcher is
also enabled if the EN/PSV pin is not grounded.
Forced Continuous Mode Operation
The SC414/SC424 operates the switcher in Forced
Continuous Mode (FCM) by  oating the EN/PSV pin (see
Figure 4). In this mode of operation, the MOSFETs are
turned on alternately to each other with a short dead time
between them to avoid cross conduction. This feature
results in uniform frequency across the full load range
with the trade-o being poor e ciency at light loads due
to the high-frequency switching of the MOSFETs.
For V5V < 4.5V, it is recommended to force 33% of the V5V
voltage on the EN/PSV pin to operate in forced continuous
mode.
FB Ripple
Voltage (VFB)FB threshold
DL
DH
Inductor
Current
DC Load Current
DH on-time is triggered when
VFB reaches the FB Threshold.
(750mV)
On-time
(TON)
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 4 — Forced Continuous Mode Operation
Ultrasonic Power-save Operation (SC414)
The SC414 provides ultrasonic power-save operation at
light loads, with the minimum operating frequency  xed
at slightly under 25kHz. This is accomplished by using an
internal timer that monitors the time between consecu-
tive high-side gate pulses. If the time exceeds 40µs, DL
drives high to turn the low-side MOSFET on. This draws
current from VOUT through the inductor, forcing both VOUT
and VFB to fall. When VFB drops to the 750mV threshold, the
next DH (the drive signal for the high side FET) on-time is
triggered. After the on-time is completed the high-side
MOSFET is turned o and the low-side MOSFET turns on.
The low-side MOSFET remains on until the inductor
current ramps down to zero, at which point the low-side
MOSFET is turned o .
Applications Information (continued)
SC414/SC424
17
Because the on-times are forced to occur at intervals no
greater than 40µs, the frequency will not fall far below
25kHz. Figure 5 shows ultrasonic power-save operation.
FB Ripple
Voltage (VFB)
FB threshold
(750mV)
Inductor
Current
DH
DL
(0A)
40μs time-out
minimum fSW ~ 25kHz
After the 40μsec time-out, DL drives high if VFB
has not reached the FB threshold.
DH On-time is triggered when
VFB reaches the FB Threshold
On-time
(TON)
Figure 5 — Ultrasonic Power-save Operation
Power-save Mode Operation (SC424)
The SC424 provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors
the inductor current via the voltage across the low-side
MOSFET during the o -time. If the inductor current falls to
zero for 8 consecutive switching cycles, the controller
enters power-save operation. It will turn o the low-side
MOSFET on each subsequent cycle provided that the
current crosses zero. At this time both MOSFETs remain
o until VFB drops to the 750mV threshold. Because the
MOSFETs are o , the load is supplied by the output capaci-
tor. If the inductor current does not reach zero on any
switching cycle, the controller immediately exits power-
save and returns to forced continuous mode. Figure 6
shows power-save operation at light loads.
FB Ripple
Voltage
(V
FB
)FB threshold
DL
DH
Inductor
Current
Zero (0A)
DH On-time is triggered when
V
FB
reaches the FB Threshold.
(750mV)
On-time (T
ON
)
DL drives high when on-time is completed.
DL remains high until inductor current reaches zero.
Dead time varies
according to load
Figure 6 — Power-save Operation
Smart Power-save Protection
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
power-save enabled, this can force VOUT to slowly rise and
reach the over-voltage threshold, resulting in a hard shut-
down. Smart power-save prevents this condition. When
the FB voltage exceeds 10% above nominal (exceeds
825mV), the device immediately disables power-save, and
DL drives high to turn on the low-side MOSFET. This draws
current from VOUT through the inductor and causes VOUT to
fall. When VFB drops back to the 750mV trip point, a normal
TON switching cycle begins. This method prevents a hard
OVP shutdown and also cycles energy from VOUT back to
VIN. It also minimizes operating power by avoiding forced
conduction mode operation. Figure 7 shows typical wave-
forms for the Smart Power-save feature.
SmartDriveTM
For each DH pulse, the DH driver initially turns on the
high-side MOSFET at a slower speed, allowing a softer,
smooth turn-o of the low-side diode. Once the DH node
is high and the LX voltage has risen 1V above PGND, the
SmartDrive circuit automatically drives the high-side
MOSFET on at a rapid rate. This technique reduces ringing
while maintaining high efficiency and also avoids the
need for snubbers or series resistors in the gate drive.
Applications Information (continued)
SC414/SC424
18
FB
threshold
High-side
Drive (DH)
Low-side
Drive (DL)
V
OUT
drifts up to due to leakage
current flowing into C
OUT
DH and DL off
DL turns on when Smart
PSAVE threshold is reached
Smart Power Save
Threshold (825mV)
DL turns off when FB
threshold is reached
Single DH on-time pulse
after DL turn-off
V
OUT
discharges via inductor
and low-side MOSFET
Normal DL pulse after DH
on-time pulse
Normal V
OUT
ripple
Figure 7 — Smart Power-save
Current Limit Protection
The device features programmable current limiting, which
is accomplished by using the RDSON of the lower MOSFET
for current sensing. The current limit is set by RILIM resistor.
The RILIM resistor connects from the ILIM pin to the LXS pin
which is also the drain of the low-side MOSFET. When the
low-side MOSFET is on, an internal ~8A current flows
from the ILIM pin and through the RILIM resistor, creating a
voltage drop across the resistor. While the low-side
MOSFET is on, the inductor current  ows through it and
creates a voltage across the RDSON. The voltage across the
MOSFET is negative with respect to ground. If this MOSFET
voltage drop exceeds the voltage across RILIM, the voltage
at the ILIM pin will be negative and current limit will acti-
vate. The current limit then keeps the low-side MOSFET on
and will not allow another high-side on-time, until the
current in the low-side MOSFET reduces enough to bring
the ILIM voltage to zero. This method regulates the induc-
tor valley current at the level shown by ILIM in Figure 8.
Time
I
PEAK
I
LOAD
I
LIM
Inductor Current
Figure 8 — Valley Current Limit
Setting the valley current limit to 6A results in a peak
inductor current of 6A plus peak ripple current. In this situ-
ation, the average (load) current through the inductor is
6A plus one-half the peak-to-peak ripple current.
The internal 8A current source is temperature compen-
sated at 4100ppm in order to provide tracking with the
RDSON.
The RILIM value is calculated by the following equation.
RILIM = 1250 x ILIM x [0.088 x (5V - V5V) + 1]
When selecting a value for RILIM do not exceed the absolute
maximum voltage value for the ILIM pin. Note that because
the low-side MOSFET with low RDSON is used for current
sensing, the PCB layout, solder connections, and PCB con-
nection to the LX node must be done carefully to obtain
good results. RILIM should be connected directly to LXS
(pin 24).
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB compara-
tor. The voltage ramp is generated using an internal
charge pump which drives the reference from zero to
750mV in ~1.8mV increments, using an internal ~500kHz
oscillator. When the ramp voltage reaches 750mV, the
ramp is ignored and the FB comparator switches over to a
fixed 750mV threshold. During soft-start the output
voltage tracks the internal ramp, which limits the start-up
inrush current and provides a controlled soft-start pro le
for a wide range of applications. Typical soft-start ramp
time is 1.7ms.
Applications Information (continued)
SC414/SC424
19
During soft-start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero.
This prevents negative inductor current, allowing the
device to start into a pre-biased output. This soft start
operation is implemented even if FCM is selected. FCM
operation is allowed only after PGOOD is high.
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage
is 10% below the nominal voltage, PGOOD is pulled low. It
is held low until the output voltage returns to the nominal
voltage. PGOOD is held low during start-up and will not
be allowed to transition high until soft-start is completed
(when VFB reaches 750mV) and typically 4ms has passed.
PGOOD will transition low if the VFB pin exceeds +20% of
nominal, which is also the over-voltage shutdown thresh-
old (900mV). PGOOD also pulls low if the EN/PSV pin is
low when V5V is present.
Output Over-Voltage Protection
Over-Voltage Protection (OVP) becomes active as soon as
the device is enabled. The threshold is set at 750mV + 20%
(900mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains o , until the EN/PSV input
is toggled or V5V is cycled. There is a 5s delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
Output Under-Voltage Protection
When VFB falls to 75% of its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
is shut o and the DH and DL drives are pulled low to turn
o the MOSFETs. The controller stays o until EN/PSV is
toggled or V5V is cycled.
V5V UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-
ing and tri-states the DH/DL drivers until V5V rises above
2.9V. An internal Power-On Reset (POR) occurs when V5V
exceeds 2.9V, which resets the fault latch and soft-start
counter to begin the soft-start cycle. The SC414/SC424
then begins a soft-start cycle. The PWM will shut o if V5V
falls below 2.7V.
LDO Regulator
The device features an integrated LDO regulator with a
fixed output voltage of 5V. There is also an enable pin
(ENL) for the LDO that provides independent control. The
LDO voltage can also be used to provide the bias voltage
for the switching regulator.
A minimum capacitance of 1F referenced to AGND is
normally required at the output of the LDO for stability. If
the LDO is providing bias power to the device, then a
minimum 0.1F capacitor referenced to AGND is required,
along with a minimum 1F capacitor referenced to PGND
to  lter the gate drive pulses. Refer to the layout guide-
lines section.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
ENL pin
VLDO output
VIN input voltage
When the ENL pin is high, the LDO will begin start-up, see
Figure 10. During the initial phase, when the LDO output
voltage is near zero, the LDO initiates a current-limited
start-up (typically 85mA) to charge the output capacitor.
When VLDO has reached 90% of the  nal value, the LDO
current limit is increased to ~200mA and the LDO output
is quickly driven to the nominal value by the internal LDO
regulator.
V
VLDO
Final
90% of V
VLDO
Final
Constant current startup
Voltage regulating with
~200mA current limit
Figure 10 — LDO Start-Up
1.
2.
3.
Applications Information (continued)
SC414/SC424
20
LDO Switch-Over Operation
The SC414/SC424 includes a switch-over function for the
LDO. The switch-over function is designed to increase
e ciency by using the more e cient DC-DC converter to
power the LDO output, avoiding the less efficient LDO
regulator when possible. The switch-over function con-
nects the VLDO pin directly to the VOUT pin using an
internal switch. When the switch-over is complete the
LDO is turned o , which results in a power savings and
maximizes e ciency. If the LDO output is used to bias the
SC414/SC424, then after switch-over the device is self-
powered from the switching regulator with the LDO
turned o .
The switch-over logic waits for 32 switching cycles before
it starts the switch-over. There are two methods that
determine the switch-over of VLDO to VOUT.
In the  rst method, the LDO is already in regulation and
the DC-DC converter is later enabled. As soon as the
PGOOD output goes high, the 32 cycle counter is started.
The voltages at the VLDO and VOUT pins are then com-
pared; if the two voltages are within ±300mV (typically) of
each other, within 32 cylces, the VLDO pin connects to the
VOUT pin using an internal switch, and the LDO is turned
o .
In the second method, the DC-DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90% of its  nal
value. At this time, the VLDO and VOUT pins are compared,
and if within ±300mV (typically) the switch-over occurs
and the LDO is turned o .
Switch-over Limitations on VOUT and VLDO
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are voltage
limitations on permissible combinations of these pins.
Consider the situation where VOUT is programmed to 4.7V.
After start-up, the device would connect VOUT to VLDO
and disable the LDO, since the two voltage are within the
±300mV switch-over window. To avoid unwanted switch-
over, the minimum di erence between the voltages for
VOUT and VLDO should be ±500mV.
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that
are inherent to its construction, as shown in Figure 11.
Switchover
MOSFET
Parasitic diode Parasitic diode
V5V
V
LDO
V
OUT
Switchover
control
Figure 11— Switch-over MOSFET Parasitic Diodes
There are some important design rules that must be fol-
lowed to prevent forward bias of these diodes. The fol-
lowing two conditions need to be satis ed in order for the
parasitic diodes to stay o .
V5V ≥ VLDO
V5V ≥ VOUT
If either VLDO or VOUT is higher than V5V, then the respective
diode will turn on and the SC414/SC424 operating current
will flow through this diode. This has the potential of
damaging the device.
ENL pin and VIN UVLO
The ENL pin also acts as the switcher under-voltage
lockout for the VIN supply. The VIN UVLO voltage is pro-
grammable via a resistor divider at the VIN, ENL, and AGND
pins.
ENL is the enable/disable signal for the LDO. In order to
implement the VIN UVLO there is also a timing requirement
that needs to be satis ed.
If the ENL pin transitions low within 2 switching cycles and
is < 1V, then the LDO will turn o but the switcher remains
on. If ENL goes below the VIN UVLO threshold and stays
above 1V, then the switcher will turn off but the LDO
remains on.
The VIN UVLO function has a typical threshold of 2.6V on
the VIN rising edge. The falling edge threshold is 2.4V.
•
•
Applications Information (continued)
SC414/SC424
21
Applications Information (continued)
Note that it is possible to operate the switcher with the
LDO disabled, but the ENL pin must be below the logic
low threshold (0.4V maximum). The table below summa-
rizes the function of the ENL and EN pins, with respect to
the rising edge of ENL.
EN ENL LDO status Switcher status
low low, < 0.4V o o
high low, < 0.4V o on
low high, < 2.6V on o
high high, < 2.6V on o
low high, > 2.6V on o
high high, > 2.6V on on
Figure 12 below shows the ENL voltage thresholds and
their e ect on LDO and Switcher operation.
AGND
ENL low
threshold
(min 0.4V)
2.6V
2.4V
LDO on
LDO on
LDO off
VIN UVLO hysteresis
ENL voltage
Switcher on if EN = high
Switcher on if EN = high
Switcher off by VIN UVLO
Figure 12 — ENL Thresholds
ENL Logic Control of PWM Operation
When the ENL input is driven above 2.6V, it is impossible to
determine if the LDO output is going to be used to power
the device or not. In self-powered operation where the
LDO will power the device, it is necessary during the LDO
start-up to hold the PWM switching o until the LDO has
reached 90% of the  nal value. This prevents overloading
the current-limited LDO output during the LDO start-up.
However, if the switcher was previously operating (with
EN/PSV high but ENL at ground, and V5V supplied exter-
nally), then it is undesirable to shut down the switcher. To
prevent this, when the ENL input is above 2.6V (above the
VIN UVLO threshold), the internal logic checks the PGOOD
signal. If PGOOD is high, then the switcher is already
running and the LDO will run through the start-up cycle
without a ecting the switcher. If PGOOD is low, then the
LDO will not allow any PWM switching until the LDO
output has reached 90% of it’s  nal value.
Using the On-chip LDO to Bias the SC414/SC424
The following steps must be followed when using the
internal LDO to bias the device.
Connect V5V to VLDO before enabling the LDO.
Any external load on VLDO should not exceed
40mA until the LDO voltage has reached 90% of
nal value.
Do not connect the EN pin directly to the V5V or
any other supply voltage if Vout is greater than
or equal to 4.5V
Many applications connect the EN pin to V5V and control
the on/o of the LDO and PWM simultaneously with the
ENL pin. This allows one signal to control both the bias
and power output of the SC414. When VOUT > 4.5V this
configuration can cause problems due to the parasitic
diodes in the LDO switchover circuitry. After the Vout >
4.5V PWM output is up and running the switchover diodes
can hold up V5V > UVLO even if the ENL pin is grounded,
turning o the LDO. Operating in this way can potentially
damage the part.
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be speci ed.
The maximum input voltage (VINMAX) is the highest speci-
ed input voltage. The minimum input voltage ( VINMIN) is
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters de ne the design.
Nominal output voltage (VOUT)
Static or DC output tolerance
Transient response
Maximum load current (IOUT)
•
•
•
•
•
•
•
SC414/SC424
22
Applications Information (continued)
There are two values of load current to evaluate — con-
tinuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses and
ltering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design.
VIN = 12V + 10%
VOUT = 1V + 4%
fSW = 250kHz
Load = 6A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-o between the size and cost of the external  lter
components (inductor and output capacitor) and the
power conversion e ciency.
The desired switching frequency is 250kHz which results
from using components selected for optimum size and
cost .
A resistor (RTON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
OUT
IN
SW
TON V
V
400
fpF25
1
Ru:
u
To select RTON, use the maximum value for VIN, and for TON
use the value associated with maximum VIN.
SWINMAX
OUT
ON fV
V
Tu
T
ON = 303 ns at 13.2VIN, 1VOUT, 250kHz
Substituting for RTON results in the following solution.
R
TON = 130.9kΩ, use RTON = 130kΩ
Inductor Selection
In order to determine the inductance, the ripple current
must  rst be de ned. Low inductor values result in smaller
size but create higher ripple current which can reduce
e ciency. Higher inductor values will reduce the ripple
current/voltage and for a given DC resistance are more
•
•
•
•
e cient. However, larger inductance translates directly
into larger packages and higher cost. Cost, size, output
ripple, and e ciency are all used in the selection process.
The ripple current will also set the boundary for power-
save operation. The switching will typically enter power-
save mode when the load current decreases to 1/2 of the
ripple current. For example, if ripple current is 4A then
Power-save operation will typically start for loads less than
2A. If ripple current is set at 40% of maximum load current,
then power-save will start for loads less than 20% of
maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25% to 50% of the maximum load
current. This provides an optimal trade-o between cost,
e ciency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
RIPPLE
ONOUTIN
I
T)VV(
Lu
Example
In this example, the inductor ripple current is set equal to
50% of the maximum load current. Therefore ripple
current will be 50% x 6A or 3A. To find the minimum
inductance needed, use the VIN and TON values that corre-
spond to VINMAX.
H26.1
A3
ns318)V1V2.13(
LP
u
A slightly larger value of 1.5µH is selected. This will
decrease the maximum IRIPPLE to 2.53A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
ns311ns10
V
VRpF25
T
INMIN
OUTTON
VINMIN_ON
uu
SC414/SC424
23
Applications Information (continued)
L
T)VV(
IONOUTIN
RIPPLE
u
A03.2
H5.1
ns311)V18.10(
IVINMIN_RIPPLE
P
u
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is con-
trolled by the output ripple requirement and the DC toler-
ance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is for the output voltage regulation to be
±4% under static conditions. The internal 750mV refer-
ence tolerance is 1%. Assuming a 1% tolerance from the
FB resistor divider, this allows 2% tolerance due to VOUT
ripple. Since this 2% error comes from 1/2 of the ripple
voltage, the allowable ripple is 4%, or 40mV for a 1V
output.
The maximum ripple current of 2.53A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
A53.2
mV40
I
V
ESR
RIPPLEMAX
RIPPLE
MAX
ESRMAX = 15.8 mΩ
The output capacitance is chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor
current is at the peak, determines the required capaci-
tance. If the load release is instantaneous (load changes
from maximum to zero in < 1µs), the output capacitor
must absorb all the inductor’s stored energy. This will
cause a peak voltage on the capacitor according to the
following equation.

2
OUT
2
PEAK
2
RIPPLEMAXOUT
MIN
VV
I
2
1
IL
COUT
¸
¹
·
¨
©
§u
Assuming a peak voltage VPEAK of 1.150 (100mV rise upon
load release), and a 6A load release, the required capaci-
tance is shown by the next equation.

22
2
MIN
V1V05.1
A53.2
2
1
A6H5.1
COUT
¸
¹
·
¨
©
§uP
COUTMIN = 772μF
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-VOUT. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
The following can be used to calculate the needed capaci-
tance for a given dILOAD/dt. Peak inductor current is shown
by the next equation.
I
LPK = IMAX + 1/2 x IRIPPLEMAX
I
LPK = 6A + 1/2 x 2.53A = 7.26A
dt
dl
CurrentLoadofchangeofRate LOAD
I
MAX = maximum load release = 6A

OUTPK
LOAD
MAX
OUT
LPK
LPKOUT VV2
dt
dl
I
V
I
L
IC
uu
u
Example
s1
A25.1
dt
dlLOAD
P
SC414/SC424
24
Applications Information (continued)
This causes the output current to move from 6A to 0A in
4.8µs, giving the minimum output capacitance require-
ment shown in the following equation.

V1V05.12
s1
A25.1
A6
V1
A26.7
H5.1
A26.7COUT
PuuP
u
F443COUT P
Note that COUT is much smaller in this example, 443µF
compared to 772µF based on a worst-case load release. To
meet the two design criteria of minimum 443µF and
maximum 15mΩ ESR, select two capacitors rated at 220µF
and 15mΩ ESR or less.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to  lter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
minimum o -time has expired. In extreme cases the noise
can cause three or more successive on-times. Double-
pulsing will result in higher ripple voltage at the output,
but in most applications it will not a ect operation. This
form of instability can usually be avoided by providing the
FB pin with a smooth, clean ripple signal that is at least
10mVp-p, which may dictate the need to increase the ESR
of the output capacitors. It is also imperative to provide a
proper PCB layout as discussed in the Layout Guidelines
section.
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resis-
tor, as shown in Figure 13. This capacitor should be left
unpopulated unless it can be confirmed that double-
pulsing exists. Adding the CTOP capacitor will couple more
ripple into FB to help eliminate the problem. An optional
connection on the PCB should be available for this
capacitor.
V
OUT
To FB pin
R2
R1
C
TOP
Figure 13 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resis-
tance in the high current output path. A side e ect of
adding trace resistance is a decrease in load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insu -
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
charging during the switching cycle. For most applica-
tions, the total output ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
swOUT
MIN fC2
3
SRE uuSu
SC414/SC424
25
Applications Information (continued)
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
criteria. In these applications it is necessary to add a small
virtual ESR network composed of two capacitors and one
resistor, as shown in Figure 14. This network creates a
ramp voltage across CL, analogous to the ramp voltage
generated across the ESR of a standard capacitor. This
ramp is then capacitively coupled into the FB pin via
capacitor CC.
R1
R2
FB
pin
C
C
C
OUT
L
Low-
side
High-
side C
L
R
L
Figure 14 — Virtual ESR Ramp Current
Output Voltage Dropout
The output voltage adjustable range for continuous-con-
duction operation is limited by the  xed 320ns (typical)
minimum o -time. When working with low input volt-
ages, the duty-factor limit must be calculated using worst-
case values for on and o times.
The duty-factor limitation is shown by the next equation.
)MIN(OFF)MIN(ON
)MIN(ON
TT
T
DUTY
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy — VOUT Controller
Three factors a ect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator o set is trimmed so that under static condi-
tions it trips when the feedback pin is 750mV, 1%.
The on-time pulse from the SC414/SC424 in the design
example is calculated to give a pseudo- xed frequency of
250kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple
voltage. Because constant on-time converters regulate to
the valley of the output ripple, ½ of the output ripple
appears as a DC regulation error. For example, if the
output ripple is 50mV with VIN = 6 volts, then the measured
DC output will be 25mV above the comparator trip point.
If the ripple increases to 80mV with VIN = 25V, then the
measured DC output will be 40mV above the comparator
trip. The best way to minimize this e ect is to minimize
the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capaci-
tor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors may result in up to an
additional 1% error. If tighter DC accuracy is required,
resistors with lower tolerances should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor e ect on the DC output voltage. The output ESR
also a ects the output ripple and thus has a minor e ect
on the DC output voltage.
Switching Frequency Variations
The switching frequency will vary depending on line and
load conditions. The line variations are a result of  xed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net e ect is
that frequency tends to falls slightly with increasing input
voltage.
SC414/SC424
26
Applications Information (continued)
VOUT Plane
on Top layer
L
C
IN
CFF
RFB2RFB1
RILIM
CBST
LX plane on inner
or bottom layer
All components
shown Top Side
AGND plane on
inner layer
V
IN
plane on inner
or bottom layer
RES_GND — AGND connects
to PGND close to SC414/SC424
Pin 1 marking
SC414/SC424 with
vias for LX, AGND,
VIN
PGND on inner
or bottom layer
PGND
C
OUT
Note: This figure is not
to scale
Figure 15 — PCB Layout
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the induc-
tor. For a conventional PWM constant-frequency con-
verter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A constant on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). The on-time is essen-
tially constant for a given VOUT and VIN combination, to
o set the losses the o -time will tend to reduce slightly as
load increases. The net e ect is that switching frequency
increases slightly with increasing load.
PCB Layout Guidelines
The optimum layout for the SC414/SC424 is shown in
Figure 15. This layout shows an integrated FET buck regu-
lator with a maximum current of 6A. The total PCB area is
approximately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
Capacitors and Current Loops
IC Decoupling Capacitors
A 0.1 F capacitor must be located as close as
possible to the IC and directly connected to pins
2 (V5V) and 3 (AGND).
•
•
•
•
•
•
•
SC414/SC424
27
Applications Information (continued)
All other decoupling capacitors must be located
as close as possible to the IC.
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias, and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors, and PGND pins
must be as small as and as compact as possible
to reduce the area of the PCB that is exposed to
noise due to current  ow on this node.
Connect PGND to AGND with a short trace or
0Ω resistor. This connection should be as close
to the IC as possible.
AGND Island
AGND should have its own island of copper with
no other signal traces routed on this layer that
connects the AGND pins and pad of the IC to the
analog control components.
All of the components for the analog control cir-
cuitry should be located so that the connections
to AGND are done by wide copper traces or vias
down to AGND.
Connect PGND to AGND with a short trace or 0Ω
resistor. This connection should be as close to
the IC as possible.
FB, VOUT, and Other Analog Control Signals
The connection from the VOUT power to the
analog control circuitry must be routed from the
output capacitors and located on a quiet layer.
The traces between VOUT and the analog control
circuitry (VOUT, and FB pins) must be short and
routed away from noise sources, such as BST, LX,
VIN, and PGND between the input capacitors,
output capacitors, and the IC.
ILIM and TON nodes must be as short as possible
to ensure the best accuracy in current limit and
on time.
•
•
•
•
•
•
•
•
•
•
•
RILIM should be close to the IC and connected to
LXS with a Kelvin trace to pin 24 on the IC. This
will be a su cient connection and will prevent
the need to connect the resistor further into the
LX plane.
The feedback components for the switcher need
to be as close to the FB pin of the IC as possible
to reduce the possibility of noise corrupting
these analog signals.
BST, ILIM and LX
LX and BST are very noisy nodes and must be
carefully routed to minimized the PCB area that
is exposed to these signals.
The connections for the boost capacitor
between the IC and LX must be short and directly
connected to the LXBST (pin 12).
The connections for the current limit resistor
between the ILIM pin and LX must be as short as
possible and directly connected to pin 24 (LXS).
The LX node between the IC and the inductor
should be wide enough to handle the inductor
current and short enough to eliminate the pos-
sibility of LX noise corrupting other signals.
Multiple vias should be used to provide a good
connection to LX between the IC and the
inductor.
Capacitors and Current Loops
The current loops between the input capacitors,
the IC, the inductor, and the output capacitors
must be as close as possible to each other to
reduce IR drop across the copper.
All bypass and output capacitors must be con-
nected as close as possible to the respective pin
on the IC.
•
•
•
•
•
•
•
•
•
SC414/SC424
28
Outline Drawing — MLPQ-4x4-28
LxN
bxN
1.29
D/2
E1
D1
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
NOTES:
2.
1.
E
ADB
PIN 1
INDICATOR
(LASER MARK)
A1
aaa C
A2
C
SEATING
PLANE
1
2
N
R 0.20
PIN 1
IDENTIFICATION
e
bbb C A B
D1
E/2
1.45±0.10
0.73±0.10
2.58
1.29
A
MILLIMETERS
0.45 BSC
0.00
2.48
0.30
3.90
3.90
0.96
-
0.17
DIMENSIONS
0.80
MIN
-0.05
4.10
4.10
2.68
1.16
0.50
0.29
2.58
0.40
0.10
0.08
28
4.00
(0.20)
1.06
4.00
0.23
-
1.00
MAX
-
NOM
A1
E1
aaa
bbb
N
e
L
A2
D1
D
E
b
DIM
A
SC414/SC424
29
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
Land Pattern — MLPQ-4x4-28
2.58
X
K
P
1.29
K
G
H1
H2 1.29
H
Y
(C) Z
NOTES:
3. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
2.
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
0.73
1.45
MILLIMETERS
(3.95)
0.30
0.75
2.58
0.45
1.06
3.20
DIMENSIONS
4.70
H1
H2
DIM
X
Y
H
K
P
C
G
Z