NT5DS64M4BG-5T - Nanya Technology Corporation

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 1

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

•Double data rate architecture: two data transfers per

clock cycle

•Bidirectional data strobe (DQS) is transmitted and

received with data, to be used in capturing data at the

receiver

•DQS is edge-aligned with data for reads and is center-

aligned with data for writes

•Differential clock inputs (CK and CK)

•Four internal banks for concurrent operation

•Data mask (DM) for write data

•DLL aligns DQ and DQS transitions with CK transitions

•Commands entered on each positive CK edge; data and

data mask referenced to both edges of DQS

•Burst lengths: 2, 4, or 8

•CAS Latency: 2.5, 3

•Auto Precharge option for each burst access

•Auto Refresh and Self Refresh Modes

•7.8µs Maximum Average Periodic Refresh Interval

•SSTL_2 compatible I/O interface

•VDDQ = 2.6V ± 0.1V

•VDD = 2.6V ± 0.1V

•Lead-free and Halogen-free product available

Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic

random-access memory containing 268,435,456 bits. It is

internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architec-

ture to achieve high-speed operation. The double data rate

architecture is essentially a 2n prefetch architecture with an

interface designed to transfer two data words per clock cycle

at the I/O pins. A single read or write access for the 256Mb

DDR SDRAM effectively consists of a single 2n-bit wide, one

clock cycle data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads

and by the memory controller during Writes. DQS is edge-

aligned with data for Reads and center-aligned with data for

Writes.

The 256Mb DDR SDRAM operates from a differential clock

(CK and CK; the crossing of CK going high and CK going

LOW is referred to as the positive edge of CK). Commands

(address and control signals) are registered at every positive

edge of CK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well

as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst ori-

ented; accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write com-

mand. The address bits registered coincident with the Active

command are used to select the bank and row to be

accessed. The address bits registered coincident with the

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4, or 8 locations. An Auto Precharge func-

tion may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architec-

ture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row pre-

charge and activation time.

An auto refresh mode is provided along with a power-saving

Power Down mode. All inputs are compatible with the JEDEC

Standard for SSTL_2. All outputs are SSTL_2, Class II com-

patible.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode

of operation.

CAS Latency and Frequency

CAS

Latency

Maximum Operating Frequency (MHz)

DDR400B

(-5T)

3200

2.5 166

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 2

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 400mil TSOP II (x4 / x8 / x16)

27 41

VDD

DQ0

VDDQ

DQ1

VSSQ

VDDQ

DQ3

VSSQ

DQ2

VDDQ

VDD

CAS

RAS

BA0

BA1

VSS

DQ7

VSSQ

DQ6

VDDQ

VSSQ

DQ4

VDDQ

DQ5

VSSQ

DQS

VREF

VSS

DM*

CKE

A12

A11

VDD

VDDQ

DQ0

VSSQ

VDDQ

DQ1

VSSQ

VDDQ

VDD

CAS

RAS

BA0

BA1

VSS

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

VSSQ

DQS

VREF

VSS

DM*

CKE

A12

A11

A10/AP

VDD

A10/AP

VDD

VSS

Column Address Table

Organization Column Address

64Mb x 4 A0-A9, A11

32Mb x 8 A0-A9

16Mb x 16 A0-A8

*DM is internally loaded to match DQ and DQS identically.

64Mb x 4

32Mb x 8

66-pin Plastic TSOP-II 400mil

16Mb x 16

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

VDDQ

DQ5

DQ6

VSSQ

DQ7

DQ3

DQ4

VDDQ

LDQS

VDD

LDM*

CAS

RAS

BA0

BA1

A10/AP

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

VSSQ

DQ10

DQ9

VDDQ

DQ8

DQ12

DQ11

VSSQ

UDQS

VREF

VSS

UDM*

CKE

A12

A11

VSS

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 3

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package

See the balls through the package.

64 X 4

32 X 8

VSSQ

VREF

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ3

DQ2

DQS

DQM

CLK

CKE

VSS

VDD

DQ0

DQ1

QFC

RAS

BA1

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

VSSQ

VREF

DQ7

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ6

DQ5

DQ4

DQS

DQM

CLK

CKE

VSS

VDD

DQ1

DQ2

DQ3

QFC

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 4

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package

See the balls through the package.

16 X 16

VSSQ

DQ14

DQ12

DQ10

DQ8

VREF

DQ15

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ13

DQ11

DQ9

DQS

DQM

CLK

CKE

VSS

VDD

DQ2

DQ4

DQ6

LDQS

LDW

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

DQ1

DQ3

DQ5

DQ7

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 5

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol Type Function

CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-

enced to the crossings of CK and CK (both directions of crossing).

CKE, CKE0, CKE1 Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device

input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self

Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-

chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self

refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are

disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might

include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control

of stacked devices.

CS, CS0, CS1Input

Chip Select: All commands are masked when CS is registered high. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the command code. The

standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in

addition to CS0, to allow upper or lower deck selection on stacked devices.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled high coincident with that input data during a Write access. DM is sampled on both edges

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-

ing a Read, DM can be driven high, low, or floated.

BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. BA0 and BA1 also determines if the mode register or extended mode

A0 - A12 Input

Address Inputs: Provide the row address for Active commands, and the column address and

Auto Precharge bit for Read/Write commands, to select one location out of the memory array in

the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-

charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,

the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode

DQ Input/Output Data Input/Output: Data bus.

DQS, LDQS, UDQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered

in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-

DQ7; UDQS corresponds to the data on DQ8-DQ15

NC No Connect: No internal electrical connection is present.

NU Electrical connection is present. Should not be connected at second level of assembly.

VDDQ Supply DQ Power Supply: 2.6V ± 0.1V.

VSSQ Supply DQ Ground

VDD Supply Power Supply: 2.6V ± 0.1V.

VSS Supply Ground

VREF Supply SSTL_2 reference voltage: (VDDQ / 2) ± 1%.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 6

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Ordering Information

Org. Part Number Package Speed Comments

Clock (MHz) CL-tRCD-tRP Clock (MHz) CL-tRCD-tRP

64M x 4

NT5DS64M4BT-5T 66 pin TSOP-II 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

NT5DS64M4BF-5T 60ball BGA

0.8mmx1.0mm

Pitch 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

32M x 8

NT5DS32M8BT-5T 66 pin TSOP-II 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

NT5DS32M8BF-5T 60ball BGA

0.8mmx1.0mm

Pitch 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

16M x 16

NT5DS16M16BT-5T 66 pin TSOP-II 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

NT5DS16M16BF-5T 60ball BGA

0.8mmx1.0mm

Pitch 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

64M x 4

NT5DS64M4BS-5T166 pin TSOP-II 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

NT5DS64M4BG-5T160ball BGA

0.8mmx1.0mm

Pitch 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

32M x 8

NT5DS32M8BS-5T166 pin TSOP-II 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

NT5DS32M8BG-5T160ball BGA

0.8mmx1.0mm

Pitch 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

16M x 16

NT5DS16M16BS-5T166 pin TSOP-II 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

NT5DS16M16BG-5T160ball BGA

0.8mmx1.0mm

Pitch 200 3-3-3/3-4-4 166 2.5-3-3 DDR400B

Note:

1. Lead-free and Halogen-free product

2. At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information only

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 7

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (64Mb x 4)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 1024 x 8)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

DQ0-DQ3,

DQS

Read Latch

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

1024

(x8)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (32Mb x 8)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

8816

DQ0-DQ7,

DQS

Read Latch

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

512

(x16)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 9

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (16Mb x 16)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 256 x 32)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

16 16

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

16 1632

DQ0-DQ15,

LDM, UDM

LDQS,UDQS

Read Latch

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

256

(x32)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 10

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb

DDR SDRAM is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architec-

ture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O

pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at

the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a pro-

grammed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is

then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select

the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident

with the Read or Write command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering

device initialization, register definition, command descriptions and device operation.

Initialization

Only one of the following two conditions must be met.

• No power sequencing is specified during power up or power down given the following criteria:

VDD and VDDQ are driven from a single power converter output

VTT meets the specification

A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and

VREF tracks VDDQ /2

• The following relationships must be followed:

VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V

VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V

VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After

all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to

applying an executable command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.

Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be

issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode

Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and

any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state

Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode

Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed.

Following these cycles, the DDR SDRAM is ready for normal operation.

DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base

or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or

extended mode register can be modified at any valid time during device operation without affecting the state of the internal

address refresh counters used for device refresh.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 11

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Mode Register

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of

a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register

Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses

power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the

CAS latency, and A7-A12 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the

subsequent operation. Violating either of these requirements results in unspecified operation.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length

determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths

of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is

uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when

the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining

(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length

applies to both Read and Write bursts.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 12

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Mode Register Operation

A8 A7 A6 A5 A4

CAS Latency

A3 A2 A1 A0

Burst LengthBT

Address Bus

CAS Latency

A6 A5 A4 Latency

000 Reserved

001 Reserved

0 1 0 2

0 1 1 3

100 Reserved

101 1.5 (Option)

110 2.5

111 Reserved

Burst Length

A2 A1 A0 Burst Length

0 0 0 Reserved

0 0 1 2

0 1 0 4

0 1 1 8

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

BA1 BA0 A11 A10 A9

0* 0* Mode Register

Operating Mode

* BA0 and BA1 must be 0, 0 to select the Mode Register

(vs. the Extended Mode Register).

A12 - A9 A8 A7 A6 - A0 Operating Mode

0 0 0 Valid Normal operation

Do not reset DLL

0 1 0 Valid Normal operation

in DLL Reset

0 0 1 VS** Vendor-Specific

Test Mode

− − − Reserved

A3 Burst

Type

0Sequential

1Interleave

VS** Vendor Specific

A12

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

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Notes:

1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.

3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type

and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-

ing column address, as shown in Burst Definition on page 13.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability

of the first burst of output data. The latency can be programmed 2.5 or 3 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with

clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Burst Definition

Burst Length Starting Column Address Order of Accesses Within a Burst

A2 A1 A0 Type = Sequential Type = Interleaved

20 0-1 0-1

11-0 1-0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

010 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

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Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set

to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to

zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should

always be followed by a Mode Register Set command to select normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states

should not be used as unknown operation or incompatibility with future versions may result.

CAS Latencies

NOP NOP NOP NOP NOPRead

CAS Latency = 3, BL = 4

Shown with nominal tAC, tDQSCK, and tDQSQ.

Command

DQS

Don’t Care

CL=3

NOP NOP NOP NOP NOPRead

CAS Latency = 2.5, BL = 4

Command

DQS

CL=2.5

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Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions

include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC

optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended

Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-

tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are

idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these require-

ments result in unspecified operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-

mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when

entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,

200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command

can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Com-

mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (tMRD) or 10 clocks after

the DLL is enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read Command).

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II.

QFC Enable/Disable

The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by

means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature

for NANYA and is not included on all DDR SDRAM devices.

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Extended Mode Register Definition

A8A7A6A5A4A3A2A1A0Address Bus

Drive Strength

A1Drive Strength

0Normal

1Reserved

BA1 BA0

Operating Mode

A11 A10 A9

0*1*

* BA0 and BA1 must be 1, 0 to select the Extended Mode Register

Mode Register

Extended

DS DLL

A0DLL

0Enable

1Disable

A12 - A3 A2 - A0 Operating Mode

0Valid Normal Operation

− − All other states

Reserved

(vs. the base Mode Register)

QFC

A2QFC

0Disable

1Enable

(Optional)

A12

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Commands

Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each

commands follows.

Truth Table 1a: Commands

Name (Function) CS RAS CAS WE Address MNE Notes

Deselect (Nop) HX X X X NOP 1, 9

No Operation (Nop) LH H H XNOP 1, 9

Active (Select Bank And Activate Row) LLH H Bank/Row ACT 1, 3

Read (Select Bank And Column, And Start Read Burst) LHLHBank/Col Read 1, 4

Write (Select Bank And Column, And Start Write Burst) LHL L Bank/Col Write 1, 4

Burst Terminate LHHLXBST 1, 8

Precharge (Deactivate Row In Bank Or Banks) LLHLCode PRE 1, 5

Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L HXAR / SR 1, 6, 7

Mode Register Set L L L L Op-Code MRS 1, 2

1. CKE is high for all commands shown except Self Refresh.

2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects

Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-

charge feature (non-persistent), A10 low disables the Auto Precharge feature.

5. A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”

6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.

7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto

Precharge enabled or for write bursts

9. Deselect and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function) DM DQs Notes

Write Enable L Valid 1

Write Inhibit H X1

1. Used to mask write data; provided coincident with the corresponding data.

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Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is

effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from

being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode reg-

ister descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle

and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,

BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for

accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with

Auto Precharge) command must be issued and completed before opening a different row in the same bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects

the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is

selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains

open for subsequent accesses.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects

the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is

selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains

open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic

level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if

the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column

location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The

bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10

determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs

BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle

state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated

as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.

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Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring

an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write

command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon

completion of the Read or Write burst. Auto Precharge is non-persistent in that it is either enabled or disabled for each individual

Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is

determined as if an explicit Precharge command was issued at the earliest possible time without violating tRAS(min). The user

must not issue another command to the same bank until the precharge (tRP) is completed.

The NTC DDR SDRAM devices supports the optional tRAS

lockout feature. This feature allows a Read command with Auto Pre-

charge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS

(min) specification. The tRAS

lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst

length of data has been successfully prefetched from the memory array; and two, tRAS(min) has been satisfied.

As a means to specify whether a DDR SDRAM device supports the tRAS lockout feature, a new parameter has been defined,

tRAP (RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Pre-

charge). For devices that support the tRAS lockout feature, tRAP = tRCD(min). This allows any Read Command (with or without

Auto Precharge) to be issued to an open bank once tRCD(min) is satisfied.

Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered

Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write

burst cycles are not to be terminated with the Burst Terminate command.

tRAP Definition

Command

DQ (BL=2)

tRAPmin

NOP ACT NOP RD A NOP NOP NOP NOP ACT NOP NOP

tRCDmin

tRASmin

DQ0 DQ1

The above timing diagrams show the effects of tRAP for devices that support tRAS lockout. In these cases, the Read

with Auto Precharge command (RDA) is issued with tRCD(min) and dataout is available with the shortest latency from the

Bank Activate command (ACT). The internal precharge operation, however, does not begin until after tRAS(min) is satisfied.

CL=3, tCK=10ns

Command

DQ (BL=4)

NOP ACT NOP RD A NOP NOP NOP NOP ACT NOP NOP

DQ0 DQ1 DQ2 DQ3

Command

DQ (BL=8)

NOP ACT NOP RD A NOP NOP NOP NOP NOP ACT NOP

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

*Indicates Auto Precharge begins here

tRPmin

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Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in pre-

vious DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.

The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto

Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8µs (maximum).

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down.

When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated

as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self

Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can

be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning

high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of

any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200

clock cycles before applying any other command.

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Operations

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened”

(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row

in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active

command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active com-

mand to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The

minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active com-

mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access

overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.

Activating a Specific Row in a Specific Bank

HIGH

RA = row address.

BA = bank address.

CKE

RAS

CAS

A0-A12

BA0, BA1 Don’t Care

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Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a

Read command.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or dis-

abled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the

burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is

disabled.

During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the

Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the

next crossing of CK and CK). The following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the

general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low

state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read post-

amble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data

from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a con-

tinuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed

burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x

cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n

prefetch architecture). This is shown in timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”.

A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data

is shown in timing figure entitled “Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)”. Full-speed Random Read

Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 27.

tRCD and tRRD Definition

ROW

ACT NOP

COLROW

BA y BA yBA x

ACT NOP NOP

Command

A0-A12

BA0, BA1

Don’t Care

RD/WR

tRCD

tRRD

RD/WR NOP NOP

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Read Command

HIGH

CA = column address

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

x4: A0-A9, A11

x8: A0-A9 EN AP

DIS AP

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

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Read Burst: CAS Latencies (Burst Length = 4)

CAS Latency = 3

NOP NOP NOP NOP NOPRead

Command

Address

DQS

CAS Latency = 2.5

Don’t Care

BA a,COL n

DOa-n

CL=2.5

NOP NOP NOP NOP NOPRead

Command

Address

DQS

BA a,COL n

DOa-n

DO a-n = data out from bank a, column n.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.

CL=3

QFC

tQCS tQCH

(Optional)

tQCH

(Optional)

tQCS

QFC is an open drain driver. The output high level is achieved through an external pull up resistor connected to VDDQ.

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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

DOa-n DOa-b

CAS Latency = 3

NOP Read NOP NOP NOPRead

Command

Address

DQS

BAa, COL n BAa, COL b

Don’t Care

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

When burst length = 4, the bursts are concatenated.

When burst length = 8, the second burst interrupts the first.

3 subsequent elements of data out appear in the programmed order following DO a-n.

3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.

Shown with nominal tAC , tDQSCK, and tDQSQ.

CAS Latency = 2.5

NOP Read NOP NOP NOPRead

Command

Address

DQS

CL=2.5

BAa, COL n BAa,COL b

DOa- n DOa- b

CL=3

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Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

NOP NOP Read NOP NOPRead

DO a- nDOa- b

BAa, COL n BAa, COL b

CL=3

NOP

CAS Latency = 3

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).

Shown with nominal tAC , tDQSCK, and tDQSQ.Don’t Care

CAS Latency = 2.5

NOP NOP Read NOP NOPRead

DO a- nDOa- b

BAa, COL n BAa, COL b

CL=2.5

Command

Address

DQS

NOP

Command

Address

DQS

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Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

DOa-n

CAS Latency = 3

Read Read Read NOP NOPRead

DOa- bDOa-n' DOa-xDOa-x' DOa-

b’

Command

Address

DQS

DO a-n, etc. = data out from bank a, column n etc.

n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).

Reads are to active rows in any banks.

Shown with nominal tAC, tDQSCK

, and tDQSQ.

Don’t Care

BAa, COL n BAa, COL x BAa, COL b BAa, COL g

CL=3

DOa-n

CAS Latency = 2.5

Read Read Read NOP NOPRead

DOa-bDOa- n' DOa-xDOa-x' DOa-b’

Command

Address

DQS

BAa, COL n BAa, COL x BAa, COL b BAa, COL g

CL=2.5

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 28

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a

Read Burst: CAS Latencies (Burst Length = 8) on page 29. The Burst Terminate latency is equal to the read (CAS) latency, i.e.

the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data

element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is

necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst

Length = 4 or 8) on page 30. The example is shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle

time. tDQSS(min) and tDQSS(max) are defined in the section on Writes.

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge

was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of

desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Pre-

charge: CAS Latencies (Burst Length = 4 or 8) on page 31 for Read latencies of 2 and 2.5. Following the Precharge command,

a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden

during the access of the last data elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above)

provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the

Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the

command. The advantage of the Precharge command is that it can be used to truncate bursts.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 29

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Terminating a Read Burst: CAS Latencies (Burst Length = 8)

CAS Latency = 3

NOP BST NOP NOP NOPRead

Command

Address

DQS

DO a-n = data out from bank a, column n.

Cases shown are bursts of 8 terminated after 4 data elements.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.

DOa-n

Don’t Care

BAa, COL n

CAS Latency = 2.5

NOP BST NOP NOP NOPRead

Command

Address

DQS

DQ DOa-n

BAa, COL n

CL=2.5

No further output data after this point.

DQS tristated.

No further output data after this point.

DQS tristated.

CL=3

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 30

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read to Write: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 3

BST NOP NOP NOP WriteRead

DIa-b

Command

Address

DQS

DOa-n

DO a-n = data out from bank a, column n

1 subsequent elements of data out appear in the programmed order following DO a-n.

Data In elements are applied following Dl a-b in the programmed order, according to burst length. Don’t Care

BAa, COL n

CL=3 t

DQSS

(min)

CAS Latency = 2.5

BST NOP NOP Write NOPRead

Command

Address

DQS

DOa-n

BAa, COL n

CL=2.5 tDQSS (min)

Dla-b

Shown with nominal tAC, tDQSCK, and tDQSQ.

DI a-b = data in to bank a, column b

BAa, COL b

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 31

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 3

NOP PRE NOP NOP ACTRead

Command

Address

DQS

DQ DOa-n

DO a-n = data out from bank a, column n.

Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.Don’t Care

BA a, COL n BA a or all BA a, ROW

CL=2.5

CAS Latency = 2.5

NOP PRE NOP NOP ACTRead

Command

Address

DQS

DQ DOa-n

tRP

BA a, COL n BA a or all BA a, ROW

CL=3

tRP

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Writes

Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 33.

The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or dis-

abled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For

the generic Write commands used in the following illustrations, Auto Precharge is disabled.

During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and

subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command

and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as

the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified

with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the

two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 34 shows the two

extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs

and DQS enters High-Z and any additional input data is ignored.

Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous

flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previ-

ous Write command. The first data element from the new burst is applied after either the last element of a completed burst or

the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles

after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch

architecture). Timing figure Write to Write (Burst Length = 4) on page 35 shows concatenated bursts of 4. An example of non-

consecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 36. Full-

speed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst

Length = 2, 4 or 8) on page 37. Data for any Write burst may be followed by a subsequent Read command. To follow a Write

without truncating the write burst, tWTR (Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting

(CAS Latency = 3; Burst Length = 4) on page 38.

Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures

“Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum DQSS, Odd Number of Data (3 bit

Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2;

Burst Length = 8)”. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array,

and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously.

Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write

burst, tWR should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 42.

Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Pre-

charge: Interrupting (Burst Length = 4 or 8) on page 43 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst

Length = 4 or 8) on page 45. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal

array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to

the same bank cannot be issued until tRP is met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described

above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Pre-

charge command is that it requires that the command and address busses be available at the appropriate time to issue the com-

mand. The advantage of the Precharge command is that it can be used to truncate bursts.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write Command

HIGH

CA = column address

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

x4: A0-A9, A11

x8: A0-A9

EN AP

DIS AP

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 34

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write Burst (Burst Length = 4)

T1 T2 T3 T4

tDQSS (max)

NOP NOP NOPWrite

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

A10 is Low with the Write command (Auto Precharge is disabled).

Command

Address

DQS

Don’t Care

Maximum DQSS

BA a, COL b

T1 T2 T3 T4

tDQSS (min)

NOP NOP NOPWrite

Command

Address

DQS

Minimum DQSS

BA a, COL b

Dla-b

QFC tQCSW(max) tQCHW(min)

(Optional)

QFC tQCSW(max) tQCHW(max)

QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to VDDQ.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 35

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Write (Burst Length = 4)

T1 T2 T3 T4 T5 T6

tDQSS (max)

Maximum DQSS

NOP Write NOP NOP NOPWrite

DI a-b = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Each Write command may be to any bank.

Command

Address

DQS

Don’t Care

T1 T2 T3 T4 T5 T6

Minimum DQSS

NOP Write NOP NOP NOPWrite

Command

Address

DQS

BAa, COL b BAa, COL n

BA, COL b BA, COL n

tDQSS (min)

DI a-b DI a-n

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)

T1 T2 T3 T4 T5

tDQSS (max)

NOP NOP Write NOPWrite

DI a-b, etc. = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Each Write command may be to any bank.

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

DI a-b DI a-n

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 37

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Random Write Cycles (Burst Length = 2, 4 or 8)

T1 T2 T3 T4 T5

tDQSS (max)

Maximum DQSS

Write Write Write Write

Write

DI a-b DI a-n

DI a-b, etc. = data in for bank a, column b, etc.

b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).

Each Write command may be to any bank.

DI a-b’ DI a-x DI a-x’ DI a-n’ DI a-a DI a-a’

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL x BAa, COL n BAa, COL a BAa, COL g

T1 T2 T3 T4 T5

Minimum DQSS

Write Write Write Write

Write

DI a-b DI a-nDI a-b’ DI a-x DI a-x’ DI a-n’ DI a-a DI a-a’

Command

Address

DQS

BAa, COL b BAa, COL x BAa, COL n BAa, COL a BAa, COL g

tDQSS (min)

DI a-g

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 38

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Read: Non-Interrupting (CAS Latency = 3; Burst Length = 4)

CL = 3

T1 T2 T3 T4 T5 T6

tWTR

NOP NOP NOP ReadWrite

DI a- b

NOP

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

tWTR is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands may be to any bank.

Command

Address

DQS

Don’t Care

Maximum DQSS

BAa, COL b BAa, COL n

T1 T2 T3 T4 T5 T6

tWTR

NOP NOP NOP ReadWrite NOP

Command

Address

Minimum DQSS

BAa, COL b BAa, COL n

tDQSS (max)

DI a- b

DQS

tDQSS (min)

CL = 3

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 39

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Read: Interrupting (CAS Latency = 3; Burst Length = 8)

T1 T2 T3 T4 T5 T6

tDQSS (max)

Maximum DQSS

NOP NOP NOP ReadWrite NOP

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from the first positive CK edge after the last data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

DIa- b

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

tWTR

CL = 3

T1 T2 T3 T4 T5 T6

Minimum DQSS

NOP NOP NOP ReadWrite NOP

Command

Address BAa, COL b BAa, COL n

tWTR

DI a-b

DQS

CL = 3

tDQSS (min)

1 = These bits are incorrectly written into the memory array if DM is low.

1 1

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 40

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS

Latency = 3; Burst Length = 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 3 data elements are written.

2 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP ReadWrite NOP

Command

Address BAa, COL b BAa, COL n

tWTR

DI a-b

DQS

CL = 3

tDQSS (min)

DM 1 2 2

1 = This bit is correctly written into the memory array if DM is low.

2 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 41

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Read: Nominal DQSS, Interrupting (CAS Latency = 3; Burst Length = 8)

T1 T2 T3 T4 T5 T6

tDQSS (nom)

NOP NOP NOP ReadWrite NOP

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from the first positive CK edge after the last desired data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

DI a- b

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

tWTR

CL = 3

1 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 42

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Precharge: Non-Interrupting (Burst Length = 4)

T1 T2 T3 T4 T5 T6

tDQSS (max)

NOP NOP NOP NOPWrite

DI a-b

PRE

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

tWR is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

Command

Address

DQS

Don’t Care

BA a, COL b BA (a or all)

tWR

Maximum DQSS

T1 T2 T3 T4 T5 T6

NOP NOP NOP NOPWrite PRE

Command

Address BA a, COL b BA (a or all)

tWR

Minimum DQSS

DI a-b

DQS

tDQSS (min)

tRP

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 43

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Precharge: Interrupting (Burst Length = 4 or 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst, for burst length = 8.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point. Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address

Maximum DQSS

DI a-b

1 1

DQS

tDQSS (max) tRP

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or all)

Minimum DQSS

tWR

tRP

DI a-b

1 1

DQS

tDQSS (min) 2

BA a, COL b BA (a or all)

tWR

3 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 44

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting

(Burst Length = 4 or 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 1 data element is written.

tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or all)

tWR

tRP

DI a-b

DQS

tDQSS (min) 2

1 1

DM 344

3 = This bit is correctly written into the memory array if DM is low.

4 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

06/2003 45

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)

DI a-b = Data In for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point. Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or all)

tRP

tDQSS (nom)

DI a-b

DQS

DM 1

tWR

3 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The

bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is

issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank

is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are

treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any

Read or Write commands being issued to that bank.

Precharge Command

HIGH

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

All Banks

One Bank

(if A10 is Low, otherwise Don’t Care).

A0-A9, A11, A12

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Power Down

Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all banks

are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in any bank, this

mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK, CK

and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the

DLL prior to entering Power Down. In that case, the DLL must be enabled after exiting Power Down, and 200 clock cycles must

occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at

the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, Power Down duration is limited by the

refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled Power

Down mode.

The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,

executable command may be applied one clock cycle later.

Power Down

tIS

CKE

Command

No column

access in

progress

VALID NOP VALID

Don’t Care

Exit

power down

mode

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

NOP

tPDEX

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Truth Table 2: Clock Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command n is the command registered at clock edge n, and action n is a result of command n.

4. All states and sequences not shown are illegal or reserved.

Current State

CKE n-1 CKEn

Command n Action n Notes

Cycle Current

Cycle

Self Refresh L L XMaintain Self-Refresh

Self Refresh LHDeselect or NOP Exit Self-Refresh 1

Power Down L L XMaintain Power Down

Power Down LHDeselect or NOP Exit Power Down

All Banks Idle HLDeselect or NOP Precharge Power Down Entry

All Banks Idle HLAuto Refresh Self Refresh Entry

Bank(s) Active HLDeselect or NOP Active Power Down Entry

H H See “Truth Table 3: Current State

Bank n - Command to Bank n (Same

Bank)” on page 49

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of

200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)

Current State CS RAS CAS WE Command Action Notes

Any HXXX Deselect NOP. Continue previous operation 1-6

LHHH No Operation NOP. Continue previous operation 1-6

Idle

LLH H Active Select and activate row 1-6

L L L HAuto Refresh 1-7

L L L L Mode Register Set 1-7

Row Active

LHLHRead Select column and start Read burst 1-6, 10

LHL L Write Select column and start Write burst 1-6, 10

LLHLPrecharge Deactivate row in bank(s) 1-6, 8

Read

(Auto Precharge

Disabled)

LHLHRead Select column and start new Read burst 1-6, 10

LLHLPrecharge Truncate Read burst, start Precharge 1-6, 8

LH H LBurst Terminate Burst Terminate 1-6, 9

Write

(Auto Precharge

Disabled)

LHLHRead Select column and start Read burst 1-6, 10, 11

LHL L Write Select column and start Write burst 1-6, 10

LLHLPrecharge Truncate Write burst, start Precharge 1-6, 8, 11

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed

to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in

progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.

Precharging: Starts with registration of a Precharge command and ends when tRP

is met. Once tRP is met, the bank is in the idle

state.

Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row

active” state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive

clock edge during these states.

Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is

in the “all banks idle” state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is

met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle

state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

11. Requires appropriate DM masking.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 1 of 2)

Current State CS RAS CAS WE Command Action Notes

Any HXXX Deselect NOP/continue previous operation 1-6

LHHH No Operation NOP/continue previous operation 1-6

Idle XXXXAny Command Otherwise

Allowed to Bank m 1-6

Row Activating,

Active, or

Precharging

LLH H Active Select and activate row 1-6

LHLHRead Select column and start Read burst 1-7

LHL L Write Select column and start Write burst 1-7

LLHLPrecharge 1-6

Read

(Auto Precharge

Disabled)

LLH H Active Select and activate row 1-6

LHLHRead Select column and start new Read burst 1-7

LLHLPrecharge 1-6

Write

(Auto Precharge

Disabled)

LLH H Active Select and activate row 1-6

LHLHRead Select column and start Read burst 1-8

LHL L Write Select column and start new Write burst 1-7

LLHLPrecharge 1-6

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-

ered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.

5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access

period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with

Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.

For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or tRP

) begins. During the precharge period

of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands

to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In

either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

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Read (With

Auto Precharge)

LLH H Active Select and activate row 1-6

LHLHRead Select column and start new Read burst 1-7,10

LHL L Write Select column and start Write burst 1-7,9,10

LLHLPrecharge 1-6

Write (With

Auto Precharge)

LLH H Active Select and activate row 1-6

LHLHRead Select column and start Read burst 1-7,10

LHL L Write Select column and start new Write burst 1-7,10

LLHLPrecharge 1-6

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 2 of 2)

Current State CS RAS CAS WE Command Action Notes

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-

ered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.

5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access

period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with

Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.

For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or tRP

) begins. During the precharge period

of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands

to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In

either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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Simplified State Diagram

Self

Auto

Idle

MRS

EMRS

Row

Precharge

Power

Write

Power

ACT

Read A

Read

REFS

REFSX

REFA

CKEL

MRS

CKEH

CKEL

Write

Power

Applied

Automatic Sequence

Command Sequence

Read A

Write A

Read

PRE PRE

PRE

Refresh

Down

Power

Down

Active

Read

Write A

Burst Stop

Preall

Active

Precharge

Preall

Read

Write

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register Set

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, VOUT Voltage on I/O pins relative to VSS −0.5 to VDDQ+ 0.5 V

VIN Voltage on Inputs relative to VSS −0.5 to +3.6 V

VDD Voltage on VDD

supply relative to VSS −0.5 to +3.6 V

VDDQ Voltage on VDDQ supply relative to VSS −0.5 to +3.6 V

TAOperating Temperature (Ambient) 0 to +70 °C

TSTG Storage Temperature (Plastic) −55 to +150 °C

PDPower Dissipation 1.0 W

IOUT Short Circuit Output Current 50 mA

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rat-

ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci-

fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DQS/DQ/DM Slew Rate

Parameter Symbol

DDR400

(-5) Unit Notes

Min Max

DCS/DQ/DM

input slew rate DCSLEW TBD TBD V/ns 1, 2

1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC).

2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and pre-

serve setup and hold times. Signal transition through the DC region must be monotonic.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

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Capacitance

Parameter Symbol Min. Max. Units Notes

Input Capacitance: CK, CK CI12.0 3.0 pF 1

Delta Input Capacitance: CK, CK delta CI10.25 pF 1

Input Capacitance: All other input-only pins (except DM) CI22.0 3.0 pF 1

Delta Input Capacitance: All other input-only pins (except DM) delta CI20.5 pF 1

Input/Output Capacitance: DQ, DQS, DM CIO 4.0 5.0 pF 1, 2

Delta Input/Output Capacitance: DQ, DQS, DM delta CIO 0.5 pF 1

1. VDDQ = VDD

= 2.6V ± 0.1V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak =0.2V.

2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is

required to match input propagation times of DQ, DQS and DM in the system.

DC Electrical Characteristics and Operating Conditions

(0°C £ TA £ 70×C; VDDQ = +2.6V ± 0.1V, VDD = +2.6V ± 0.1V, see AC Characteristics)

Symbol Parameter Min Max Units Notes

VDD Supply Voltage 2.5 2.7 V1

VDDQ I/O Supply Voltage 2.5 2.7 V1

VSS, VSSQ Supply Voltage

I/O Supply Voltage 0 0 V

VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V1, 2

VTT I/O Termination Voltage (System) VREF − 0.04 VREF + 0.04 V1, 3

VIH(DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V1

VIL(DC) Input Low (Logic0) Voltage − 0.3 VREF − 0.15 V1

VIN(DC) Input Voltage Level, CK and CK Inputs − 0.3 VDDQ + 0.3 V1

VID(DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V1, 4

VIX(DC) Input Crossing Point Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V1, 4

VIRatio V-I Matching Pullup Current to Pulldown Current Ratio 0.71 1.4 5

IIInput Leakage Current

Any input 0V ≤ VIN ≤ VDD

; (All other pins not under test = 0V) − 5 5 µA1

IOZ Output Leakage Current

(DQs are disabled; 0V ≤ Vout ≤ VDDQ − 5 5 µA1

IOH Output Current: Nominal Strength Driver

High current (VOUT= VDDQ

-0.373V, min VREF, min VTT)

Low current (VOUT= 0.373V, max VREF, max VTT)

− 16.8 mA 1

IOL 16.8

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed ± 2% of the DC value.

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and

must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and

voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference

between pullup and pulldown drivers due to process variation.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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Normal Strength Driver Pulldown and Pullup Characteristics

1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the

outer bounding lines of the V-I curve.

2. It is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve.

3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the

outer bounding lines of the V-I curve.

4. It is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve.

IOHW Output Current: Half- Strength Driver

High current (VOUT= VDDQ

-0.763V, min VREF, min VTT)

Low current (VOUT= 0.763V, max VREF, max VTT)

− 9.0 mA 1

IOLW 9.0

Normal Strength Driver Pulldown Characteristics

DC Electrical Characteristics and Operating Conditions

(0°C £ TA £ 70×C; VDDQ = +2.6V ± 0.1V, VDD = +2.6V ± 0.1V, see AC Characteristics)

Symbol Parameter Min Max Units Notes

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed ± 2% of the DC value.

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and

must track variations in the DC level of VREF.

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and

voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference

between pullup and pulldown drivers due to process variation.

02.70

140

IOUT (mA)

VOUT (V)

Maximum

Typical High

Typical Low

Minimum

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device

drain to source voltages from 0.1 to 1.0.

6. The full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity + 10%, for device

drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.

7. These characteristics are intended to obey the SSTL_2 class II standard.

8. This specification is intended for DDR SDRAM only.

Normal Strength Driver Pullup Characteristics

Maximum

Typical High

Typical Low

Minimum

VOUT (V) 2.70

-200

IOUT (mA)

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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Normal Strength Driver Pulldown and Pullup Currents

Pulldown Current (mA) Pullup Current (mA)

Voltage (V) Typical

Low Typical

High Min Max Typical

Low Typical

High Min Max

0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0

0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0

0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8

0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8

0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8

0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4

0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8

0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5

0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3

1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2

1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0

1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6

1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1

1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5

1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0

1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4

1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7

1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2

1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5

2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9

2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2

2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6

2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0

2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3

2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6

2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9

2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2

Normal Strength Driver Evaluation Conditions

Typical Minimum Maximum

Temperature (Tambient)25 °C70 °C0 °C

VDDQ 2.5V 2.3V 2.7V

Process conditions typical process slow-slow process fast-fast process

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD

Specifications and Conditions, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced

to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels

under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and

VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a

result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above

(below) the DC input low (high) level.

AC Output Load Circuit Diagrams

50Ω

Timing Reference Point

Output

(VOUT)

30pF

VTT

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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REV 1.3

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AC Input Operating Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = +2.6V ± 0.1V; VDD = +2.6V ± 0.1V, See AC

Characteristics)

Symbol Parameter/Condition Min Max Unit Notes

VIH(AC) Input High (Logic 1) Voltage, DQ, DQS, and DM Signals VREF + 0.31 V1, 2

VIL(AC) Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals VREF − 0.31 V1, 2

VID(AC) Input Differential Voltage, CK and CK Inputs 0.62 VDDQ + 0.6 V1, 2, 3

VIX(AC) Input Crossing Point Voltage, CK and CK Inputs 0.5*VDDQ − 0.2 0.5*VDDQ + 0.2 V1, 2, 4

1. Input slew rate = 1V/ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

IDD Specifications and Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = +2.6V ± 0.1V; VDD = +2.6V ± 0.1V, See AC

Characteristics)

Symbol Parameter/Condition DDR400A

(-5)

tCK=5ns

DDR400B

(-5T)

tCK=5ns Unit Notes

IDD0 Operating Current: one bank; active / precharge; tRC = tRC

(min); DQ, DM,

and DQS inputs changing twice per clock cycle; address and control inputs

changing once per clock cycle 115 115 mA 1

IDD1

Operating Current: one bank; active / read / precharge; Burst = 2; tRC =

tRC

(min); CL = 2.5; IOUT = 0mA; address and control inputs changing once

per clock cycle 120 120 mA 1

IDD2P Precharge Power Down Standby Current: all banks idle; Power Down

mode; CKE ≤ VIL (max) 20 20 mA 1

IDD2N Idle Standby Current: CS ≥ VIH

(min); all banks idle; CKE ≥ VIH (min);

address and control inputs changing once per clock cycle 45 45 mA 1

IDD3P

Active Power Down Standby Current: one bank active; Power Down

mode;

CKE ≤ VIL (max) 21 21 mA 1

IDD3N

Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);

CKE ≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing

twice per clock cycle; address and control inputs changing once per clock

cycle

75 75 mA 1

IDD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address

and control inputs changing once per clock cycle; DQ and DQS outputs

changing twice per clock cycle; CL = 2.5; IOUT = 0mA 200 200 mA 1

IDD4W

Operating Current: one bank; Burst = 2; writes; continuous burst; address

and control inputs changing once per clock cycle; DQ and DQS inputs

changing twice per clock cycle; CL = 2.5 195 195 mA 1

IDD5 Auto-Refresh Current: tRC = tRFC (min) 225 225 mA 1

IDD6 Self-Refresh Current: CKE ≤ 0.2V 3 3 mA 1, 2

IDD7

Operating current: four bank; four bank interleaving with BL = 4, address

and control inputs randomly changing; 50% of data changing at every trans-

fer;

t RC = t RC (min); I OUT = 0mA.

325 325 mA 1

1. IDD specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Electrical Characteristics & AC Timing - Absolute Specifications

(0 °C ≤ TA ≤ 70 °C; VDDQ = +2.6V ± 0.1V; VDD = 2.6V ± 0.1V, See AC Characteristics) (Part 1 of 2)

Symbol Parameter

DDR400

(-5) DDR400

(-5T) Unit Notes

Min Max Min Max

tAC DQ output access time from CK/CK − 0.6 + 0.6 − 0.65 + 0.65 ns 1-4

tDQSCK DQS output access time from CK/CK − 0.5 + 0.5 − 0.55 + 0.55 ns 1-4

tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4

tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4

tCK Clock cycle time CL = 3.0 5 8 5 8 ns 1-4

CL = 2.5 5 12 6 12

tDH DQ and DM input hold time 0.4 0.4 ns 1-4,

15, 16

tDS DQ and DM input setup time 0.4 0.4 ns 1-4,

15, 16

tIPW Input pulse width 2.2 2.2 ns 2-4, 12

tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4

tHZ Data-out high-impedance time from CK/CK − 0.6 + 0.6 − 0.6 + 0.6 ns 1-4, 5

tLZ Data-out low-impedance time from CK/CK − 0.6 + 0.6 − 0.6 + 0.6 ns 1-4, 5

tDQSQ DQS-DQ skew (DQS & associated

DQ signals) TSOP Package + 0.4 + 0.4 ns 1-4

BGA Package + 0.4 + 0.4 ns 1-4

tHP Minimum half clk period for any given cycle; defined by clk

high (tCH) or clk low (tCL

) time min

(tCL, tCH)min

(tCL, tCH)tCK 1-4

tQH Data output hold time from DQS tHP - tQHS tHP - tQHS tCK 1-4

tQHS Data hold Skew Factor TSOP Package 0.5 0.5 tCK 1-4

BGA Package 0.5 0.5 tCK 1-4

tDQSS Write command to 1st DQS latching

transition 0.72 1.28 0.72 1.28 tCK 1-4

tDQSH DQS input high pulse width (write cycle) 0.35 0.35 tCK 1-4

tDQSL DQS input low pulse width (write cycle) 0.35 0.35 tCK 1-4

tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 tCK 1-4

tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 tCK 1-4

tMRD Mode register set command cycle time 2 2 tCK 1-4

tWPRES Write preamble setup time 0 0 ns 1-4, 7

tWPST Write postamble 0.40 0.60 0.40 0.60 tCK 1-4, 6

tWPRE Write preamble 0.25 0.25 tCK 1-4

tIH Address and control input hold time

(fast slew rate) 0.6 0.6 ns 2-4, 9,

11, 12

tIS Address and control input setup time

(fast slew rate) 0.6 0.6 ns 2-4, 9,

11, 12

tIH Address and control input hold time

(slow slew rate) 0.7 0.7 ns 2-4, 10,

11, 12, 14

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

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tIS Address and control input setup time

(slow slew rate) 0.7 0.7 ns 2-4, 10,

11, 12, 14

tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 1-4

tRPST Read postamble 0.40 0.60 0.40 0.60 tCK 1-4

tRAS Active to Precharge command 40 120,000 40 120,000 ns 1-4

tRC Active to Active/Auto-refresh command period 55 55 ns 1-4

tRFC Auto-refresh to Active/Auto-refresh command period 70 70 ns 1-4

tRCD Active to Read or Write delay 15 15 ns 1-4

tRAP Active to Read Command with Autoprecharge min

(tRCD, tRAS)min

(tRCD, tRAS)ns 1-4

tRP Precharge command period 15 15 ns 1-4

tRRD Active bank A to Active bank B command 10 10 ns 1-4

tWR Write recovery time 15 15 ns 1-4

tDAL Auto precharge write recovery + precharge time (tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)tCK 1-4, 13

tWTR Internal write to read command delay 2 2 tCK 1-4

tPDEX Power down exit time 5 5 ns 1-4

tXSNR Exit self-refresh to non-read command 75 75 ns 1-4

tXSRD Exit self-refresh to read command 200 200 tCK 1-4

tREFI Average Periodic Refresh Interval 7.8 7.8 µs1-4, 8

Electrical Characteristics & AC Timing - Absolute Specifications

(0 °C ≤ TA ≤ 70 °C; VDDQ = +2.6V ± 0.1V; VDD = 2.6V ± 0.1V, See AC Characteristics) (Part 2 of 2)

Symbol Parameter

DDR400

(-5) DDR400

(-5T) Unit Notes

Min Max Min Max

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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Electrical Characteristics & AC Timing - Absolute Specifications Notes

1. Input slew rate = 1V/ns.

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross; the

input reference level for signals other than CK/CK is VREF.

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics

(Note 3) is VTT.

5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are

not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving

(LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this

parameter, but system performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this

CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the

device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic

LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this

time, depending on tDQSS.

8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC).

10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and

VOL (AC).

11. CK/CK slew rates are ≥ 1.0V/ns.

12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may

be guaranteed by design or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal

to the actual system clock cycle time. For example, for DDR266B at CL = 2.5, tDAL = (15ns/7.5ns) +

(20ns/7.5ns) = 2+3 = 5.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew

rate is below 0.5 V/ns.

15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate

is below 0.5 V/ns.

16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS

slew rates differ.

Input Slew Rate delta (tIS)delta (t IH)Unit Notes

0.5 V/ns 0 0 ps 1,2

0.4 V/ns +50 0ps 1,2

0.3 V/ns +100 0ps 1,2

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising

transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

Input Slew Rate delta (tDS

)delta (tDH)Unit Notes

0.5 V/ns 0 0 ps 1,2

0.4 V/ns +75 +75 ps 1,2

0.3 V/ns +150 +150 ps 1,2

1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising

transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

Input Slew Rate delta (tDS

)delta (tDH)Unit Notes

0.0 V/ns 0 0 ps 1,2,3,4

0.25 V/ns +50 +50 ps 1,2,3,4

0.5 V/ns +100 +100 ps 1,2,3,4

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising

transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]

For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns

Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]

= -0.5 ns/V

Using the table above, this would result in an increase in t DS and t DH of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Package Dimensions (400mil; 66 lead; Thin Small Outline Package)

10.16 ±. 0.13

11.76 ± 0.20

Lead #1

0.65 Basic 0.30 - 0.08

+ 0.03 0.71REF

Detail A

0.10

Seating Plane

Detail A

0.5 ± 0.1

0.05 Min

1.20 Max

0.25 Basic Gage Plane

22.22 ± 0.10

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.3

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Package Dimensions (60 balls; 0.8mmx1.0mm Pitch; CSP Package)

0.80 0.80

8.0

1.00

0.50

13.0

1.0

1.60 0.35

1.15

Dia.

0.45

Note : All dimensions are typical unless otherwise stated.

Unit : Millimeters

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

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256Mb DDR SDRAM

REV 1.3

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Revision Log

Rev Date Modification

0.1 01/2003 Preliminary Release

0.2 02/2003 Updated tQHS from 0.55ns to 0.5ns in Electrical Characteristics & AC Timing Table

1.0 03/2003

Updated IDD values in IDD Specifications and Conditions Table

Removed CL2 support

Added DDR400B (-5T) speed grade

Official Release

1.1 04/2003 Fixed typo for tWTR in Electrical Characteristics & AC Timing Table

1.2 05/2003 Added Lead-free and Halogen-free component part numbers

1.3 06/2003 Fixed various typos regarding CAS Latency 3 support

1.4 10/2003 Removed CAS Latency 2.5 support

Nanya Technology Corporation.

Printed in Taiwan, R.O.C. June 2002

The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both.

NANYA NANYA logo

Other company, product and service names may be trademarks or service marks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance

of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s

standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this

warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government

requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or

environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE

FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such

applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should

be directed to NTC through a local sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be

provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents

or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under

any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination,

machine, or process in which such semiconductor products or services might be or are used.

NANYA TECHNOLOGY CORPORATION

HWA YA Technology Park

669, FU HSING 3rd Rd., Kueishan,

Taoyuan, Taiwan, R.O.C.

The NANYA TECHNOLOGY CORPORATION home page can be found at

http:\\www.nanya.com