To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual 78K0S/KU1+ 8-Bit Single-Chip Microcontrollers PD78F9200 PD78F9500 PD78F9201 PD78F9501 Document No. U18172EJ3V0UD00 (3rd edition) Date Published November 2009 NS (c) Printed in Japan 2006 PD78F9202 PD78F9502 [MEMO] 2 User's Manual U18172EJ3V0UD NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U18172EJ3V0UD 3 Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, inc. * The information in this document is current as of November, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anticrime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note 1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). (M8E0909) 4 User's Manual U18172EJ3V0UD INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KU1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. <R> * 78K0S/KU1+: PD78F9200, 78F9201, 78F9202, 78F9500, 78F9501, 78F9502 Purpose This manual is intended to give users on understanding of the functions described in the Organization below. Organization Two manuals are available for 78K0S/KU1+: this manual and the Instruction Manual (common to the 78K/0S Series). 78K/0S Series 78K0S/KU1+ Instructions User's Manual User's Manual * Pin functions * CPU function * Internal block functions * Instruction set * Interrupts * Instruction description * Other internal peripheral functions * Electrical specifications How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of 78K0S/KU1+ Read this manual in the order of the CONTENTS. The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. How to read register formats For a bit number enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. To learn the detailed functions of a register whose register name is known See APPENDIX B REGISTER INDEX. To learn the details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series Instructions User's Manual (U11047E) separately available. To learn the electrical specifications of the 78K0S/KU1+ See CHAPTER 19 ELECTRICAL SPECIFICATIONS. User's Manual U18172EJ3V0UD 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0S/KU1+ User's Manual This manual 78K/0S Series Instructions User's Manual U11047E <R> Documents Related to Development Software Tools (User's Manuals) Document Name RA78K0S Ver.2.00 Assembler Package CC78K0S Ver.2.00 C Compiler SM+ System Simulator ID78K0S-QB Ver.3.00 Integrated Debugger Document No. Operation U17391E Language U17390E Structured Assembly Language U17389E Operation U17416E Language U17415E Operation U18601E User Open Interface U18212E Operation U18493E PM+ Ver.6.30 U18416E Documents Related to Development Hardware Tools (User's Manuals) Document Name Document No. QB-78K0SKX1 In-Circuit Emulator U18219E QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E Documents Related to Flash Memory Writing (User's Manuals) Document Name Document No. PG-FP5 Flash Memory Programmer <R> U18865E QB-Programmer Programming GUI Caution Operation The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 6 U18527E User's Manual U18172EJ3V0UD Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U18172EJ3V0UD 7 CONTENTS CHAPTER 1 OVERVIEW.........................................................................................................................14 1.1 Features .........................................................................................................................................14 1.2 Ordering Information....................................................................................................................15 1.3 Pin Configuration (Top View) ......................................................................................................16 1.3.1 PD78F920x .....................................................................................................................................16 1.3.2 PD78F950x .....................................................................................................................................16 1.4 78K0S/Kx1+ Product Lineup........................................................................................................17 1.5 Block Diagram...............................................................................................................................18 1.5.1 PD78F920x .....................................................................................................................................18 1.5.2 PD78F950x .....................................................................................................................................19 1.6 Functional Outline ........................................................................................................................20 CHAPTER 2 PIN FUNCTIONS ...............................................................................................................21 2.1 Pin Function List...........................................................................................................................21 2.1.1 PD78F920x .....................................................................................................................................21 2.1.2 PD78F950x .....................................................................................................................................23 2.2 Pin Functions ................................................................................................................................24 2.2.1 P20 to P23 (Port 2)............................................................................................................................24 2.2.2 P32 and P34 (Port 3).........................................................................................................................25 2.2.3 P40 and P43 (Port 4).........................................................................................................................25 2.2.4 RESET ..............................................................................................................................................25 2.2.5 X1 and X2 (PD78F920x) .................................................................................................................25 2.2.6 EXCLK (PD78F950x) ......................................................................................................................26 2.2.7 VDD ....................................................................................................................................................26 2.2.8 VSS ....................................................................................................................................................26 2.3 Pin I/O Circuits and Connection of Unused Pins ......................................................................27 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................29 3.1 Memory Space ..............................................................................................................................29 3.1.1 Internal program memory space........................................................................................................32 3.1.2 Internal data memory space ..............................................................................................................33 3.1.3 Special function register (SFR) area..................................................................................................33 3.1.4 Data memory addressing ..................................................................................................................33 3.2 Processor Registers.....................................................................................................................36 3.2.1 Control registers ................................................................................................................................36 3.2.2 General-purpose registers.................................................................................................................39 3.2.3 Special function registers (SFRs) ......................................................................................................40 3.3 Instruction Address Addressing.................................................................................................44 3.3.1 Relative addressing ...........................................................................................................................44 3.3.2 Immediate addressing .......................................................................................................................45 3.3.3 Table indirect addressing ..................................................................................................................45 8 User's Manual U18172EJ3V0UD 3.3.4 Register addressing .......................................................................................................................... 46 3.4 Operand Address Addressing .................................................................................................... 47 3.4.1 Direct addressing .............................................................................................................................. 47 3.4.2 Short direct addressing ..................................................................................................................... 48 3.4.3 Special function register (SFR) addressing ....................................................................................... 49 3.4.4 Register addressing .......................................................................................................................... 50 3.4.5 Register indirect addressing.............................................................................................................. 51 3.4.6 Based addressing ............................................................................................................................. 52 3.4.7 Stack addressing............................................................................................................................... 53 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 54 4.1 Functions of Ports........................................................................................................................ 54 4.2 Port Configuration........................................................................................................................ 55 4.2.1 Port 2 ................................................................................................................................................ 56 4.2.2 Port 3 ................................................................................................................................................ 64 4.2.3 Port 4 ................................................................................................................................................ 66 4.3 Registers Controlling Port Functions ........................................................................................ 66 4.4 Operation of Port Function.......................................................................................................... 71 4.4.1 Writing to I/O port .............................................................................................................................. 71 4.4.2 Reading from I/O port........................................................................................................................ 71 4.4.3 Operations on I/O port....................................................................................................................... 71 CHAPTER 5 CLOCK GENERATORS................................................................................................... 72 5.1 Functions of Clock Generators................................................................................................... 72 5.1.1 System clock oscillators .................................................................................................................... 72 5.1.2 Clock oscillator for interval time generation....................................................................................... 72 5.2 Configuration of Clock Generators ............................................................................................ 73 5.3 Registers Controlling Clock Generators.................................................................................... 76 5.4 System Clock Oscillators ............................................................................................................ 79 5.4.1 High-speed internal oscillator ............................................................................................................ 79 5.4.2 Crystal/ceramic oscillator (PD78F920x only)................................................................................... 79 5.4.3 External clock input circuit................................................................................................................. 81 5.4.4 Prescaler ........................................................................................................................................... 81 5.5 Operation of CPU Clock Generator ............................................................................................ 82 5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware............................... 88 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY)......................................... 90 6.1 6.2 6.3 6.4 Functions of 16-Bit Timer/Event Counter 00 ............................................................................. 90 Configuration of 16-Bit Timer/Event Counter 00....................................................................... 91 Registers to Control 16-Bit Timer/Event Counter 00 ................................................................ 95 Operation of 16-Bit Timer/Event Counter 00 ...........................................................................101 6.4.1 Interval timer operation ................................................................................................................... 101 6.4.2 External event counter operation .................................................................................................... 103 6.4.3 Pulse width measurement operations ............................................................................................. 106 6.4.4 Square-wave output operation ........................................................................................................ 114 User's Manual U18172EJ3V0UD 9 6.4.5 PPG output operations ....................................................................................................................116 6.4.6 One-shot pulse output operation .....................................................................................................119 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 ...............................................................124 CHAPTER 7 8-BIT TIMER H1 .............................................................................................................131 7.1 7.2 7.3 7.4 Functions of 8-Bit Timer H1.......................................................................................................131 Configuration of 8-Bit Timer H1 ................................................................................................131 Registers Controlling 8-Bit Timer H1........................................................................................134 Operation of 8-Bit Timer H1 .......................................................................................................136 7.4.1 Operation as interval timer/square-wave output ..............................................................................136 7.4.2 Operation as PWM output mode .....................................................................................................140 CHAPTER 8 WATCHDOG TIMER .......................................................................................................146 8.1 8.2 8.3 8.4 Functions of Watchdog Timer ...................................................................................................146 Configuration of Watchdog Timer ............................................................................................148 Registers Controlling Watchdog Timer....................................................................................149 Operation of Watchdog Timer ...................................................................................................151 8.4.1 Watchdog timer operation when "low-speed internal oscillator cannot be stopped" is selected by option byte ......................................................................................................................................151 8.4.2 Watchdog timer operation when "low-speed internal oscillator can be stopped by software" is selected by option byte ...................................................................................................................153 8.4.3 Watchdog timer operation in STOP mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) ...............................................................................................155 8.4.4 Watchdog timer operation in HALT mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) ...............................................................................................156 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) .......................................................................157 9.1 9.2 9.3 9.4 Functions of A/D Converter .......................................................................................................157 Configuration of A/D Converter ................................................................................................159 Registers Used by A/D Converter .............................................................................................161 A/D Converter Operations .........................................................................................................166 9.4.1 Basic operations of A/D converter ...................................................................................................166 9.4.2 Input voltage and conversion results ...............................................................................................168 9.4.3 A/D converter operation mode.........................................................................................................169 9.5 How to Read A/D Converter Characteristics Table .................................................................171 9.6 Cautions for A/D Converter .......................................................................................................173 CHAPTER 10 INTERRUPT FUNCTIONS ............................................................................................176 10.1 10.2 10.3 10.4 Interrupt Function Types .........................................................................................................176 Interrupt Sources and Configuration .....................................................................................176 Interrupt Function Control Registers .....................................................................................178 Interrupt Servicing Operation .................................................................................................181 10.4.1 Maskable interrupt request acknowledgment operation ................................................................181 10.4.2 Multiple interrupt servicing.............................................................................................................183 10 User's Manual U18172EJ3V0UD 10.4.3 Interrupt request pending .............................................................................................................. 185 CHAPTER 11 STANDBY FUNCTION..................................................................................................186 11.1 Standby Function and Configuration .....................................................................................186 11.1.1 Standby function ........................................................................................................................... 186 11.1.2 Registers used during standby (PD78F920x only) ...................................................................... 188 11.2 Standby Function Operation ...................................................................................................189 11.2.1 HALT mode ................................................................................................................................... 189 11.2.2 STOP mode .................................................................................................................................. 192 CHAPTER 12 RESET FUNCTION .......................................................................................................196 12.1 Register for Confirming Reset Source...................................................................................203 CHAPTER 13 POWER-ON-CLEAR CIRCUIT .....................................................................................204 13.1 13.2 13.3 13.4 Functions of Power-on-Clear Circuit .....................................................................................204 Configuration of Power-on-Clear Circuit ...............................................................................205 Operation of Power-on-Clear Circuit......................................................................................205 Cautions for Power-on-Clear Circuit ......................................................................................206 CHAPTER 14 LOW-VOLTAGE DETECTOR.......................................................................................208 14.1 14.2 14.3 14.4 14.5 Functions of Low-Voltage Detector........................................................................................208 Configuration of Low-Voltage Detector .................................................................................208 Registers Controlling Low-Voltage Detector.........................................................................209 Operation of Low-Voltage Detector........................................................................................211 Cautions for Low-Voltage Detector ........................................................................................ 215 CHAPTER 15 OPTION BYTE ...............................................................................................................218 15.1 Functions of Option Byte ........................................................................................................218 15.1.1 PD78F920x ................................................................................................................................. 218 15.1.2 PD78F950x ................................................................................................................................. 219 15.2 Format of Option Byte .............................................................................................................220 15.2.1 PD78F920x ................................................................................................................................. 220 15.2.2 PD78F950x ................................................................................................................................. 222 15.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34) .............................223 CHAPTER 16 FLASH MEMORY..........................................................................................................224 16.1 16.2 16.3 16.4 16.5 16.6 Features.....................................................................................................................................224 Memory Configuration .............................................................................................................225 Functional Outline ....................................................................................................................225 Writing with Flash Memory Programmer ...............................................................................226 Programming Environment .....................................................................................................227 Processing of Pins on Board ..................................................................................................229 16.6.1 X1 and X2 pins (PD78F920x)...................................................................................................... 229 16.6.2 EXCLK pin (PD78F950x) ............................................................................................................ 230 User's Manual U18172EJ3V0UD 11 16.6.3 RESET pin.....................................................................................................................................231 16.6.4 Port pins ........................................................................................................................................231 16.6.5 Power supply.................................................................................................................................231 16.7 On-Board and Off-Board Flash Memory Programming ........................................................232 16.7.1 Flash memory programming mode................................................................................................232 16.7.2 Communication commands ...........................................................................................................232 16.7.3 Security settings ............................................................................................................................233 16.8 Flash Memory Programming by Self Programming..............................................................234 16.8.1 Outline of self programming ..........................................................................................................234 16.8.2 Cautions on self programming function .........................................................................................237 16.8.3 Registers used for self-programming function ...............................................................................237 16.8.4 Example of shifting normal mode to self programming mode ........................................................244 16.8.5 Example of shifting self programming mode to normal mode ........................................................247 16.8.6 Example of block erase operation in self programming mode .......................................................250 16.8.7 Example of block blank check operation in self programming mode .............................................253 16.8.8 Example of byte write operation in self programming mode ..........................................................256 16.8.9 Example of internal verify operation in self programming mode ....................................................259 16.8.10 Examples of operation when command execution time should be minimized in self programming mode ...........................................................................................................................................263 16.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode ...........................................................................................................................................269 CHAPTER 17 ON-CHIP DEBUG FUNCTION .......................................................................................280 17.1 Connecting QB-MINI2 to 78K0S/KU1+....................................................................................280 17.1.1 Connection of INTP1 pin ...............................................................................................................281 17.1.2 Connection of X1 and X2 pins .......................................................................................................282 17.2 Securing of user resources .....................................................................................................283 CHAPTER 18 INSTRUCTION SET OVERVIEW .................................................................................284 18.1 Operation ...................................................................................................................................284 18.1.1 Operand identifiers and description methods ................................................................................284 18.1.2 Description of "Operation" column .................................................................................................285 18.1.3 Description of "Flag" column..........................................................................................................285 18.2 Operation List ...........................................................................................................................286 18.3 Instructions Listed by Addressing Type ................................................................................291 CHAPTER 19 ELECTRICAL SPECIFICATIONS .................................................................................294 CHAPTER 20 PACKAGE DRAWING ..................................................................................................308 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS...........................................................309 12 User's Manual U18172EJ3V0UD APPENDIX A DEVELOPMENT TOOLS ..............................................................................................310 A.1 Software Package ......................................................................................................................313 A.2 Language Processing Software ...............................................................................................313 A.3 Flash Memory Writing Tools.....................................................................................................314 A.3.1 When using flash memory programmer PG-FP5 and FL-PR5........................................................ 314 A.3.2 When using on-chip debug emulator with programming function QB-MINI2................................... 314 A.4 Debugging Tools (Hardware)....................................................................................................314 A.4.1 When using in-circuit emulator QB-78K0SKX1............................................................................... 314 A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................... 315 A.5 Debugging Tools (Software).....................................................................................................315 APPENDIX B NOTES ON DESIGNING TARGET SYSTEM ................................................................316 APPENDIX C REGISTER INDEX.........................................................................................................318 C.1 Register Index (Register Name) ...............................................................................................318 C.2 Register Index (Symbol)............................................................................................................320 APPENDIX D LIST OF CAUTIONS.....................................................................................................322 APPENDIX E REVISION HISTORY .....................................................................................................337 E.1 Major Revisions in This Edition................................................................................................337 E.2 Revision History up to Previous Editions ...............................................................................338 User's Manual U18172EJ3V0UD 13 CHAPTER 1 OVERVIEW 1.1 Features O 78K0S CPU core O ROM and RAM capacities Item Program Memory (Flash Memory) Memory (Internal High-Speed RAM) Part number <R> PD78F9200, 78F9500 1 KB <R> PD78F9201, 78F9501 2 KB <R> PD78F9202, 78F9502 4 KB 128 bytes O Minimum instruction execution time: 0.2 s (with 10 MHz@4.0 to 5.5 V operation) O Clock * High-speed system clock ... Selected from the following three sources - Ceramic/crystal resonator: 2 to 10 MHz - External clock: 2 to 10 MHz - High-speed internal oscillator PD78F920x: 8 MHz 3% (-10 to +70C), 8 MHz 5% (-40 to +85C) PD78F950x: 8 MHz 2% (-10 to +85C), 8 MHz 5% (-40 to +85C) * Low-speed internal oscillator 240 kHz (TYP.) ... Watchdog timer, timer clock in intermittent operation O I/O ports: 8 (CMOS I/O: 7, CMOS input: 1) O Timer: 3 channels * 16-bit timer/event counter : 1 channel ... Timer output x 1, capture input x 2 Note * 8-bit timer: 1 channel ... PWM output x 1 * Watchdog timer: 1 channel ... Operable with low-speed internal oscillation clock Note O 10-bit resolution A/D converter : 4 channels O On-chip power-on-clear (POC) circuit (A reset is automatically generated when the voltage drops to 2.1 V (TYP.) or below) O On-chip low voltage detector (LVI) circuit (An interrupt/reset (selectable) is generated when the detection voltage is reached) * Detection voltage: Selectable from ten levels between 2.35 and 4.3 V O Single-power-supply flash memory * Flash self programming enabled * Software protection function: Protected from outside party copying (no flash reading command) * Time required for writing by dedicated flash memory programmer: Approximately 3 seconds (4 KB) Flash programming on mass production lines supported O Safety function * Watchdog timer operated by clock independent from CPU ... A hang-up can be detected even if the system clock stops * Supply voltage drop detectable by LVI ... Appropriate processing can be executed before the supply voltage drops below the operation voltage * Equipped with option byte function ... Important system operation settings set in hardware Note PD78F920x only 14 User's Manual U18172EJ3V0UD CHAPTER 1 OVERVIEW O Assembler and C language supported O Enhanced development environment * Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator O Supply voltage: VDD = 2.0 to 5.5 V Use these products at VDD = 2.2 to 5.5 V because the POC detection voltage (VPOC) is the supply voltage range. O Operating temperature range: TA = -40 to +85C 1.2 Ordering Information Part Number PD78F9 xxx - xx (x) - xxx -A Semiconductor component Lead-free Product contains no lead in any area -A (Terminal finish is Sn/Bi plating) Quality Grades Blank Standard (for ordinary electronic systems) MA-CAC 10-pin Plastic SSOP Package type 1 K bytes 16-bit timer, A/D converter Mounted 2 K bytes Mounted 4 K bytes Mounted High-speed RAM 200 128 bytes Flash memory 500 Not mounted 201 501 Not mounted 202 Not mounted 502 Product type F Flash memory versions Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. [Part number list] <R> PD78F9200MA-CAC-A PD78F9500MA-CAC-A <R> PD78F9201MA-CAC-A PD78F9501MA-CAC-A <R> PD78F9202MA-CAC-A PD78F9502MA-CAC-A User's Manual U18172EJ3V0UD 15 CHAPTER 1 OVERVIEW 1.3 Pin Configuration (Top View) 1.3.1 PD78F920x 10-pin plastic SSOP P20/ANI0/TI000/TOH1 1 10 P40 2 9 P43 VSSNote1 3 8 P32/INTP1 VDDNote2 4 7 P34/RESET P23/X1/ANI3 5 6 P22/X2/ANI2 P21/ANI1/TI010/TO00/INTP0 ANI0 to ANI3: Analog input TI000, TI010: INTP0, INTP1: External interrupt input TO00, TOH1: P20 to P23: Port 2 VDD P30, P34: Port 3 VSS P40, P43: Port 4 X1, X2: RESET: Reset Timer input Timer output Note2 : Power supply Note1 : Ground Crystal oscillator (X1 input clock) Notes 1. In PD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 2. In PD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). <R> 1.3.2 PD78F950x 10-pin plastic SSOP 16 P20/TOH1 1 10 P40 2 9 P43 VSS 3 8 P32/INTP1 VDD 4 7 P34/RESET P23/EXCLK 5 6 P22 P21/INTP0 INTP0, INTP1: External interrupt input TOH1: Timer output P20 to P23: Port 2 VDD: Power supply P30, P34: Port 3 VSS: Ground P40, P43: Port 4 EXCLK: External Clock Input RESET: Reset (Main System Clock) User's Manual U18172EJ3V0UD CHAPTER 1 OVERVIEW 1.4 78K0S/Kx1+ Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+ 10 pins 16 pins 20 pins 30/32 pins Item Number of pins <R> Internal memory Flash memory 1 KB, 2 KB, 4 KB 2 KB 4 KB, 8 KB 4 KB, 8 KB 128 bytes 128 bytes 256 bytes 256 bytes RAM VDD = 2.0 to 5.5 V Supply voltage Note 1 0.20 s (10 MHz, VDD = 4.0 to 5.5 V) 0.33 s (6 MHz, VDD = 3.0 to 5.5 V) 0.40 s (5 MHz, VDD = 2.7 to 5.5 V) 1.0 s (2 MHz, VDD = 2.0 to 5.5 V) Minimum instruction execution time High-speed internal oscillation (8 MHz (TYP.)) Note 2 Crystal/ceramic oscillation (2 to 10 MHz) System clock (oscillation frequency) External clock input oscillation (2 to 10 MHz) Clock for TMH1 and WDT (oscillation frequency) Port Timer Low-speed internal oscillation (240 kHz (TYP.)) CMOS I/O 7 13 15 24 CMOS input 1 1 1 1 CMOS output - - 1 1 1 ch 16-bit (TM0) 8-bit (TMH) 1 ch - 8-bit (TM8) 1 ch WDT 1 ch - Serial interface LIN-Bus-supporting UART: 1 ch Note 4 Note 4 A/D converter 10 bits: 4 ch (2.7 to 5.5 V) Multiplier (8 bits x 8 bits) Interrupts - 5 Internal External Reset Provided (selectable by software) WDT 2. 3. 4. 5. 4 2.1 V (TYP.) LVI <R> 9 Provided POC Notes 1. Provided Note 5 2 RESET pin Operating temperature range Note 3 Provided Standard product: -40 to +85C Standard product, (A) grade product: -40 to +85C (A2) grade product: -40 to +125C Use these products in the following voltage range because the detection voltage (VPOC) of the power-onclear (POC) circuit is the supply voltage range. Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V PD78F950x does not support the crystal/ceramic oscillation. The product without A/D converter ( PD78F950x) in the 78K0S/KU1+ is not supported. The product without A/D converter ( PD78F95xx) is provided for the 78K0S/KU1+ and 78K0S/KY1+ respectively. There are 2 and 4 factors for the products without A/D converter in the 78K0S/KU1+ and 78K0S/KY1+, respectively. User's Manual U18172EJ3V0UD 17 CHAPTER 1 OVERVIEW 1.5 Block Diagram 1.5.1 PD78F920x TO00/TI010/P21 PORT 2 16-bit TIMER/ EVENT COUNTER 00 TI000/P20 4 P32 PORT 3 TOH1/P20 78K0S CPU CORE 8-bit TIMER H1 P20-P23 P34 FLASH MEMORY PORT 4 2 P40, P43 LOW-SPEED INTERNAL OSCILLATOR POWER ON CLEAR/ LOW VOLTAGE INDICATOR WATCHDOG TIMER ANI0/P20ANI3/P23 INTP0/P21 INTP1/P32 4 A/D CONVERTER INTERNAL HIGH-SPEED RAM RESET CONTROL SYSTEM CONTROL INTERRUPT CONTROL VDDNote1 VSSNote2 POC/LVI CONTROL HIGH-SPEED INTERNAL OSCILLATOR RESET/P34 X1/P23 X2/P22 Notes 1. In PD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). 2. In PD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 18 User's Manual U18172EJ3V0UD CHAPTER 1 OVERVIEW <R> 1.5.2 PD78F950x PORT 2 4 P32 PORT 3 TOH1/P20 8-bit TIMER H1 78K0S CPU CORE P20-P23 P34 FLASH MEMORY PORT 4 2 P40, P43 LOW-SPEED INTERNAL OSCILLATOR POWER ON CLEAR/ LOW VOLTAGE INDICATOR WATCHDOG TIMER INTERNAL HIGH-SPEED RAM INTP0/P21 INTP1/P32 RESET CONTROL SYSTEM CONTROL INTERRUPT CONTROL VDD POC/LVI CONTROL VSS User's Manual U18172EJ3V0UD RESET/P34 EXCLK/P23 HIGH-SPEED INTERNAL OSCILLATOR 19 CHAPTER 1 OVERVIEW 1.6 Functional Outline Item <R> Internal memory <R> PD78F9200 PD78F9201 PD78F9202 PD78F9500 PD78F9501 PD78F9502 Flash memory 1 KB High-speed RAM 128 bytes 2 KB Memory space 64 KB X1 input clock (oscillation frequency) * PD78F920x 4 KB Crystal/ceramic/external clock input: 10 MHz (VDD = 2.0 to 5.5 V) * PD78F950x External clock input: 10 MHz (VDD = 2.7 to 5.5 V) Internal High speed (oscillation oscillation frequency) clock Low speed (for TMH1 Internal oscillation: 8 MHz (TYP.) Internal oscillation: 240 kHz (TYP.) and WDT) General-purpose registers 8 bits x 8 registers Instruction execution time 0.2 s/0.4 s/0.8 s/1.6 s/3.2 s (X1 input clock: fX = 10 MHz) I/O port Total: 8 pins CMOS I/O: 7 pins CMOS input: 1 pin * 16-bit timer/event counter Note 1 Timer Timer output A/D converter interrupt sources 1 channel * Watchdog timer: 1 channel 2 pins (PWM: 1 pin) 10-bit resolution x 4 channels Note 1 Vectored : 1 channel * 8-bit timer (timer H1): External 2 Internal PD78F920x: 5, PD78F950x: 2 * Reset by RESET pin * Internal reset by watchdog timer * Internal reset by power-on clear Reset * Internal reset by low-voltage detector <R> Note 2 Supply voltage VDD = 2.0 to 5.5 V Operating temperature range TA = -40 to +85C Package 10-pin plastic SSOP Notes 1. PD78F920x only 2. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V (TYP.). 20 User's Manual U18172EJ3V0UD CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List 2.1.1 PD78F920x (1) Port pins Pin Name I/O Function After Reset Alternate-Function Pin I/O P20 Port 2. Input 4-bit I/O port. P21 ANI1/TI010/ Can be set to input or output mode in 1-bit units. P22 Note 1 P23 Note 1 ANI0/TI000/TOH1 TO00/INTP0 An on-chip pull-up resistor can be connected by setting software. P32 I/O Port 3 Can be set to input or output mode in X2/ANI2 Note 1 X1/ANI3 Note 1 Input INTP1 Input RESET 1-bit units. An on-chip pull-up resistor can be connected by setting software. P34 Note 1 P40, P43 Input Note 2 I/O Input only Port 4. Input Note 1 - 2-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software. Notes 1. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. 2. At program initialization, set PM41, PM42, and PM44 to PM47 to "0". Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset. User's Manual U18172EJ3V0UD 21 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name I/O Function After Reset AlternateFunction Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input P21/ANI1/TI010/ TO00 falling edge, or both rising and falling edges) can be specified INTP1 P32 TI000 Input External count clock input to 16-bit timer/event counter 00. Input P20/ANI0/TOH1 Capture trigger input to capture registers (CR000 and CR010) of 16-bit timer/event counter 00 TI010 TO00 Output Capture trigger input to capture register (CR000) of 16-bit P21/ANI1/TO00/ timer/event counter 00 INTP0 16-bit timer/event counter 00 output Input P21/ANI1/TI010/ INTP0 TOH1 Output 8-bit timer H1 output Input P20/ANI0/TI000 ANI0 Input Analog input of A/D converter Input P20/TI000/TOH1 ANI1 P21/TI010/TO00/ INTP0 ANI2 Note P22/X2 ANI3 Note P23/X1 RESET X1 Note Note Note Note Input System reset input Input Input Connection of crystal/ceramic oscillator for system clock P34 Note - P23/ANI3 Note - P22/ANI2 Note oscillation. External clock input X2 Note - Connection of crystal/ceramic oscillator for system clock oscillation. VDD - Positive power supply - - VSS - Ground potential - - Note For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset. 22 User's Manual U18172EJ3V0UD CHAPTER 2 PIN FUNCTIONS <R> 2.1.2 PD78F950x (1) Port pins Pin Name I/O Function After Reset Alternate-Function Pin I/O P20 Port 2. Input port 4-bit I/O port. P21 TOH1 INTP0 Can be set to input or output mode in 1-bit units. P22 P23 - An on-chip pull-up resistor can be connected by setting Note software. P32 I/O EXCLK Port 3 Can be set to input or output mode in An on-chip pull-up 1-bit units. Note Input port INTP1 Input port RESET resistor can be connected by setting P34 Note Input P40, P43 I/O software. Input only Port 4. Note - Input port 2-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software. Note For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. Caution The P22 and P23/EXCLK pins are pulled down during reset. The P34/RESET pin is pulled up during reset by the reset pin function/power-on clear circuit. (2) Non-port pins Pin Name I/O Function After Reset AlternateFunction Pin Input INTP0 External interrupt input for which the valid edge (rising edge, Input port falling edge, or both rising and falling edges) can be specified INTP1 TOH1 RESET EXCLK Note Note P21 P32 Output 8-bit timer H1 output Input port P20 Input System reset input Input port P34 Note Input External clock input for main system clock Input port P23 Note VDD - Positive power supply - - VSS - Ground potential - - Note For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. Caution The P22 and P23/EXCLK pins are pulled down during reset. The P34/RESET pin is pulled up during reset by the reset pin function/power-on clear circuit. User's Manual U18172EJ3V0UD 23 CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port. In addition to the function as I/O port pins, these pins also have a function to input an analog signal to the A/D converter, input/output a timer signal, and input an external interrupt request signal. P22 and P23 also function as the X2/ANI2 and X1/ANI3, respectively. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 2 (PU2). (2) Control mode P20 to P23 function to input an analog signal to the A/D converter, input/output a timer signal, and input an external interrupt request signal. (a) ANI0 to ANI3 (PD78F920x only) <R> These are the analog input pins of the A/D converter. When using these pins as analog input pins, refer to 9.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23. <R> (b) TI000 (PD78F920x only) This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the capture registers (CR000 and CR010) of 16-bit timer/event counter 00. (c) TI010 (PD78F920x only) <R> This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00. (d) TO00 (PD78F920x only) <R> This pin outputs a signal from 16-bit timer/event counter 00. (e) TOH1 This pin outputs a signal from 8-bit timer H1. (f) INTP0 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Caution 24 The P22 and P23 pins are pulled down during reset. User's Manual U18172EJ3V0UD CHAPTER 2 PIN FUNCTIONS 2.2.2 P32 and P34 (Port 3) P32 is a 1-bit I/O port. In addition to the function as an I/O port pin, this pin also has a function to input an external interrupt request signal. P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the reset function. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. <R> When P34 in PD78F920x is used as an input port pin, connect the pull-up resistor. P32 and P34 can be set to the following operation modes in 1-bit units. (1) Port mode P32 functions as a 1-bit I/O port. This pin can be set to the input or output mode by using port mode register 3 (PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pull-up resistor option register 3 (PU3). <R> P34 functions as a 1-bit input-only port. In PD78F950x, an on-chip pull-up resistor can be connected to the port by using pull-up resistor option register 3 (PU3). (2) Control mode P32 functions as an external interrupt request input pin (INTP1) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. <R> Caution In PD78F950x, the P34/RESET pin is pulled up during reset by the reset pin function/power-on clear circuit. 2.2.3 P40 and P43 (Port 4) P40 and P43 constitute a 2-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4) Note . In addition, an on-chip pull-up resistor can be connected to the port by using pull-up resistor option register 4 (PU4). Note In PD78F920x, set PM41, PM42, and PM44 to PM47 to "0" at program initialization. 2.2.4 RESET This pin inputs an active-low system reset signal. When the power is turned on, this is the reset function, regardless of the option byte setting. <R> Caution In PD78F950x, the P34/RESET pin is pulled up during reset by the reset pin function/power-on clear circuit. 2.2.5 X1 and X2 (PD78F920x) These pins connect an oscillator to oscillate the X1 input clock. X1 and X2 also function as P23/ANI3 and P22/ANI2, respectively. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. Supply an external clock to X1. Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset. User's Manual U18172EJ3V0UD 25 CHAPTER 2 PIN FUNCTIONS 2.2.6 EXCLK (PD78F950x) This is the external clock input pin for the main system clock. EXCLK functions as P23. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. Caution The P23/EXCLK pin is pulled down during reset. 2.2.7 VDD This is the positive power supply pin. In PD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). 2.2.8 VSS This is the ground pin. In PD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 26 User's Manual U18172EJ3V0UD CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Connection of Unused Pins Tables 2-1 and 2-2 show I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins (PD78F920x) Pin Name P20/ANI0/TI000/TOH1 I/O Circuit Type 11 I/O I/O Recommended Connection of Unused Pin Input: Individually connect to VDD or VSS via resistor. Output: Leave open. P21/ANI1/TI010/TO00/ INTP0 36 P22/ANI2/X2 Input: Individually connect to VSS via resistor. Output: Leave open. P23/ANI3/X1 P32/INTP1 8-A Input: Individually connect to VDD or VSS via resistor. Output: Leave open. P34/RESET 2 Input P40 and P43 8-A I/O Connect to VDD via resistor. Input: Individually connect to VDD or VSS via resistor. Output: Leave open. Table 2-2. Types of Pin I/O Circuits and Connection of Unused Pins (PD78F950x) <R> Pin Name P20/TOH1 I/O Circuit Type 8-A I/O I/O Recommended Connection of Unused Pin Input: Individually connect to VDD or VSS via resistor. Output: Leave open. P21/INTP0 P22 P23/EXCLK P32/INTP1 P34/RESET 2-A Input P40 and P43 8-A I/O Set ENPU34 to "1" on the option byte, and leave the pin open. Input: Individually connect to VDD or VSS via resistor. Output: Leave open. User's Manual U18172EJ3V0UD 27 CHAPTER 2 PIN FUNCTIONS <R> Figure 2-1. Pin I/O Circuits Type 36 Type 2 IN feedback cut-off Schmitt-triggered input with hysteresis characteristics P-ch Type 2-A VDD Pull up enable P-ch X1, IN/OUT OSC enable X2, IN/OUT VDD IN Schmitt-triggered input with hysteresis characteristics pullup enable P-ch VDD Type 8-A data P-ch output disable N-ch VDD Pull up enable P-ch VSS Comparator VDD P-ch + N-ch Data Comparison voltage P-ch VSS IN/OUT Output disable VDD N-ch pullup enable P-ch VDD data P-ch output disable N-ch Type 11 VDD Pull up enable P-ch VDD VSS Comparator P-ch + Data IN/OUT Output disable N-ch VSS Comparator P-ch + N-ch Comparison voltage VSS Input enable 28 N-ch - P-ch User's Manual U18172EJ3V0UD Comparison voltage VSS CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The 78K0S/KU1+ can access up to 64 KB of memory space. Figures 3-1 to 3-3 show the memory maps. <R> Figure 3-1. Memory Map (PD78F9200, 78F9500) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 128 x 8 bits FE80H FE7FH Use prohibited Data memory space 03FFH 0400H 03FFH Program area Program memory space Flash memory 1,024 x 8 bits 0 0 0 0 082 081 080 07F H H H H Protect byte area Option byte area CALLT table area 0040H 003FH Program area 0014H 0013H Vector table area 0000H 0000H Remark The option byte and protect byte are 1 byte each. User's Manual U18172EJ3V0UD 29 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD78F9201, 78F9501) <R> FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 128 x 8 bits FE80H FE7FH Use prohibited Data memory space 07FFH 0800H 07FFH Program area Program memory space Flash memory 2,048 x 8 bits 0 0 0 0 082 081 080 07F H H H H Protect byte area Option byte area CALLT table area 0040H 003FH Program area 0014H 0013H Vector table area 0000H 0000H Remark 30 The option byte and protect byte are 1 byte each. User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD78F9202, 78F9502) <R> FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 128 x 8 bits FE80H FD7FH Use prohibited Data memory space 0FFFH 1000H 0FFFH Program area Program memory space Flash memory 4,096 x 8 bits 0 0 0 0 082 081 080 07F H H H H Protect byte area Option byte area CALLT table area 0040H 003FH Program area 0014H 0013H Vector table area 0000H 0000H Remark The option byte and protect byte are 1 byte each. User's Manual U18172EJ3V0UD 31 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KU1+ provide the following internal ROMs (or flash memory) containing the following capacities. <R> Table 3-1. Internal ROM Capacity Part Number Internal ROM Structure PD78F9200, 78F9500 Capacity 1,024 x 8 bits Flash memory PD78F9201, 78F9501 2,048 x 8 bits PD78F9202, 78F9502 4,096 x 8 bits The following areas are allocated to the internal program memory space. (1) Vector table area The 20-byte area of addresses 0000H to 0013H is reserved as a vector table area. This area stores program start addresses to be used when branching by RESET or interrupt request generation. Of a 16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 3-2. Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H Reset 000CH INTTMH1 0006H INTLVI 000EH INTTM000 Note 0008H INTP0 0010H INTTM010 Note 000AH INTP1 0012H INTAD Note Note PD78F920x only <R> (2) CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. (3) Option byte area The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 15 OPTION BYTE. (4) Protect byte area The protect byte area is the 1-byte area of address 0081H. For details, refer to CHAPTER 16 FLASH MEMORY. 32 User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 128-byte internal high-speed RAM is provided in the 78K0S/KU1+. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KU1+ are provided with a wide range of addressing modes to make memory manipulation as efficient as possible. The area (FE80H to FEFFH) which contains a data memory and the special function register (SFR) area can be accessed using a unique addressing mode in accordance with each function. Figures 3-4 to 3-6 illustrate the data memory addressing. Figure 3-4. Data Memory Addressing (PD78F9200, 78F9500) <R> FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FE1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 128 x 8 bits FE80H FE7FH Direct addressing Register indirect addressing Based addressing Use prohibted 0400H 03FFH Flash memory 1,024 x 8 bits 0000H User's Manual U18172EJ3V0UD 33 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Data Memory Addressing (PD78F9201, 78F9501) <R> FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FE1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 128 x 8 bits FE80H FE7FH Direct addressing Register indirect addressing Based addressing Use prohibted 0800H 07FFH Flash memory 2,048 x 8 bits 0000H 34 User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing (PD78F9202, 78F9502) <R> FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FE1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 128 x 8 bits FE80H FE7FH Direct addressing Register indirect addressing Based addressing Use prohibted 1000H 0FFFH Flash memory 4,096 x 8 bits 0000H User's Manual U18172EJ3V0UD 35 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0S/KU1+ provide the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-7. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETI and POP PSW instructions. Reset signal generation sets PSW to 02H. Figure 3-8. Program Status Word Configuration 7 PSW 36 IE 0 Z 0 AC 0 User's Manual U18172EJ3V0UD 0 1 CY CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources. This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. User's Manual U18172EJ3V0UD 37 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack area). Figure 3-9. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented before writing (saving) to the stack memory and is incremented after reading (restoring) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-10 and 3-11. Caution 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack memory. 2. Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits can be actually set. 0FF00H is in the SFR area, not the high-speed RAM area, so it was converted to 0FB00H that is in the high-speed RAM area. When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to become 0FAFFH, but that value is not in the high-speed RAM area, so it is converted to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer. Figure 3-10. Data to Be Saved to Stack Memory PUSH rp instruction Interrupt CALL, CALLT instructions SP SP SP _ 2 SP SP _ 2 SP _ 3 SP _ 3 PC7 to PC0 SP _ 2 Lower half register pairs SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8 SP _ 1 Upper half register pairs SP _ 1 PC15 to PC8 SP _ 1 PSW SP SP SP Figure 3-11. Data to Be Restored from Stack Memory POP rp instruction SP RET instruction RETI instruction SP Lower half register pairs SP PC7 to PC0 SP PC7 to PC0 SP + 1 Upper half register pairs SP + 1 PC15 to PC8 SP + 1 PC15 to PC8 SP + 2 PSW SP + 2 SP SP + 2 SP 38 User's Manual U18172EJ3V0UD SP + 3 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-12. General-Purpose Register Configuration (a) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 0 (b) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 User's Manual U18172EJ3V0UD 0 39 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address and bit. * 8-bit manipulation Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying an address, describe an even address. Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the implemented special function registers. It is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special function register can be read or written. R/W: Read/write R: Read only W: Write only * Number of bits manipulated simultaneously Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated. * After reset Indicates the status of the special function register when a reset is input. 40 User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously - FF00H, 7 6 5 4 3 2 1 0 - - - - - - - - 1 8 16 - - - - - - R/W - 00H 68 - 00H 68 page Address Reference Table 3-3. Special Function Registers (1/3) FF01H FF02H P2 0 0 0 0 P23 P22 P21 P20 FF03H P3 0 0 0 P34 0 P32 0 0 FF04H P4 Note 1 FF05H to - 0 0 0 0 P43 0 0 P40 - 00H 68 - - - - - - - - - - - - - - R/W - - 00H 133 - - 00H 133 - - - 0000H 92 0000H 92 0000H 94 Undefined 164 FF0DH FF0EH CMP01 - - - - - - - - FF0FH CMP11 - - - - - - - - - - - - - - - - - - - - TM00 - - - - - - - - R - - - - - - - - - - - - - - - - - - R/W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 PM23 PM22 PM21 PM20 R/W - FFH FF10H, FF11H FF12H Note 2 FF13H FF14H CR000 Note 2 FF15H FF16H CR010 Note 2 FF17H ADCR FF18H Note 2 FF19H FF1AH ADCRH R Note 3 Note 3 Note 3 Note 3 165 Note 2 FF1BH to - - FF21H FF22H PM2 67, 100, 136, 165 FF23H PM3 FF24H PM4 FF25H to - 1 1 1 1 1 1 1 - - PM32 1 1 1 1 - - PM43 1 1 PM40 - - - - - R/W - FFH 67 - FFH 67 - - - - - - 00H 70 - 00H 70 FF31H FF32H PU2 0 0 0 0 PU23 PU22 PU21 PU20 FF33H PU3 0 0 0 PU34 0 PU32 0 0 Note 4 FF34H PU4 FF35H to - 0 0 0 0 PU43 0 0 PU40 - - - - - - - - 0 1 1 - 00H 70 - - - - - - R/W - - 67H 149 - - 9AH 150 FF47H FF48H FF49H WDTM WDTE - - WDCS WDCS WDCS WDCS WDCS - 4 3 2 1 0 - - - - - Notes 1. Only P34 is an input-only port. <R> 2. PD78F920x only 3. A 16-bit access is possible only by the short direction addressing. <R> 4. PD78F950x only Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. User's Manual U18172EJ3V0UD 41 CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF50H LVIM 7 6 5 4 3 2 1 0 <LVI 0 0 0 0 0 <LVI <LVI MD> F> LVIS1 LVIS0 ON> FF51H LVIS 0 0 0 0 LVIS3 LVIS2 R/W 1 8 16 - 00H page Address Reference Table 3-3. Special Function Registers (2/3) 209 Note 1 - - 00H 210 Note 1 - FF52H, - - - - - - - - - - - - 0 0 0 WDT 0 0 0 LVIRF R - - - - FF53H FF54H RESF - - - - - - - - LSRCM 0 0 0 0 0 0 0 FF55H to 00H 203 Note 2 RF - - - - - - - <LSR R/W - 00H 77 FF57H FF58H STOP> - FF59H to - - - - - - - - - - - - - - 0 0 0 0 TMC TMC TMC <OVF R/W - 00H 95 003 002 001 00> 0 0 PRM PRM - 00H 99 001 000 CRC CRC CRC - 00H 97 002 001 000 - 00H 98 - - - - - - R/W - 00H FF5FH FF60H TMC00 Note 3 FF61H PRM00 ES110 ES100 ES010 ES000 Note 3 FF62H CRC00 0 0 0 0 0 Note 3 FF63H TOC00 0 Note 3 <OSPT <OSPE TOC <LVS <LVR TOC <TOE 00> 00> 004 00> 00> 001 00> - - - - - - - - - TMHMD <TMH CKS12 CKS11 CKS10 TMMD TMMD 11 10 V1> 1> FF64H to FF6FH FF70H 1 FF71H to E1> - <TOLE <TOEN 134 - - - - - - - - - - - - - - <ADCS> 0 FR2 FR1 FR0 0 0 <ADCE> R/W - 00H 161 0 0 0 0 0 0 ADS1 ADS0 - 00H 164 - - - - - - - - - - - - - 0 0 0 0 R/W - 00H FF7FH FF80H ADM Note 3 FF81H ADS Note 3 - FF82H, - FF83H FF84H PMC2 PMC23 PMC22 PMC21 PMC20 FF85H to - 68, 100, 136, 165 Note 3 - - - - - - - - - - - - - - FF9FH Notes 1. Retained only after a reset by LVI. 2. Varies depending on the reset cause. <R> 3. PD78F920x only Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. 42 User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FFA0H PFCMD FFA1H PFS FFA2H FLPMC FFA3H FLCMD FFA4H FLAPL FFA5H FLAPH FFA6H FLAPHC FFA7H FLAPLC FFA8H FLW - FFA9H to page Address Reference Table 3-3. Special Function Registers (3/3) 7 6 5 4 3 2 1 0 1 8 16 REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 W - - Undefined 239 0 0 0 0 0 WEPR VCE FPR R/W - 00H 239 ERR RR ERR 0 FLSPM - - Undefined 238 - 00H 241 - 00H 242 - - 00H 242 - 243 0 0 PRSEL PRSEL PRSEL PRSEL PRSEL F4 F3 F2 F1 F0 0 0 0 0 FLCM FLCM FLCMD D2 D1 0 FLA FLA FLA FLA FLA FLA FLA FLA P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 FLA FLA FLA FLA P11 P10 P9 P8 FLAP FLAP FLAP FLAP C11 C10 C9 C8 0 0 0 0 FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP C7 C6 C5 C4 C3 C2 C1 C0 FLW7 FLW6 FLW5 FLW4 FLW3 FLW2 FLW1 FLW0 - - 00H - - - - - - - - - - - - - <ADIF> <TMIF <TMIF <TMIF 0 R/W - 00H 010> 000> H1> Note 1 Note 1 - - - - - - - - - - - - 1 R/W - FFH - - - - - FFDFH FFE0H IF0 Note 1 FFE1H to - - <PIF1> <PIF0> <LVIIF> 179 - FFE3H FFE4H MK0 FFE5H to - <ADM <TMM <TMM <TMM <PMK <PMK <LVI K> K010> K000> KH1> 1> 0> MK> 180 Note 1 Note 1 Note 1 - - - - - - - - - 0 0 ES11 ES10 ES01 ES00 0 0 R/W - - 00H - - - - - - - - - - - - - - R/W - 02H 76 - - Undefined 78, 188 - FFEBH FFECH FFEDH INTM0 - 180 to FFF2H FFF3H PPCC 0 0 0 0 0 0 PPCC1 PPCC0 FFF4H OSTS 0 0 0 0 0 0 OSTS1 OSTS0 Note 1 FFF5H to Note 2 - - - - - - - - - - - - - - - PCC 0 0 0 0 0 0 PCC1 0 R/W - 02H 76 FFFAH FFFBH <R> Notes 1. PD78F920x only 2. The oscillation stabilization time that elapses after release of reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. User's Manual U18172EJ3V0UD 43 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination address information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) to branch. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes the sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC is the start address of PC the next instruction of a BR instruction. + 8 15 7 6 0 S jdisp8 15 0 PC When S = 0, indicates that all bits are "0". When S = 1, indicates that all bits are "1". 44 User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 0 PC CALL or BR PC+1 Low addr. PC+2 High addr. 15 8 7 0 PC 3.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH. [Illustration] Instruction code 7 6 0 1 5 1 ta4-0 0 15 Effective address 0 7 0 0 0 0 0 0 Memory (Table) 0 8 7 6 0 0 1 5 1 0 0 0 Low addr. High addr. Effective address + 1 15 8 7 0 PC User's Manual U18172EJ3V0UD 45 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 X 8 7 PC 46 0 User's Manual U18172EJ3V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE80H; When setting !addr16 to FE80H Instruction code 0 0 1 0 1 0 0 1 OP Code 1 0 0 0 0 0 0 0 80H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (low) addr16 (high) Memory User's Manual U18172EJ3V0UD 47 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH (FE80H to FEFFH (internal high-speed RAM) + FF00H to FF1FH (special function registers)). The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 80H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. Identifier Description saddr Label or FE80H to FF1FH immediate data saddrp Label or FE80H to FF1FH immediate data (even address only) [Description example] EQU DATA1 0FE90H ; DATA1 shows FE90H of a saddr area, MOV DATA1, #50H ; When setting the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 0 OP code saddr-offset Short direct memory 15 Effective address 1 8 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. 48 User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 0 OP code sfr-offset SFR 15 Effective address 1 8 7 1 1 1 1 1 1 0 1 User's Manual U18172EJ3V0UD 49 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL `r' and `rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specify code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code 50 User's Manual U18172EJ3V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [DE], [HL] [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 8 7 E D DE 0 7 0 Memory address specified by register pair DE The contents of addressed memory are transferred 7 0 A User's Manual U18172EJ3V0UD 51 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier Description - [HL+byte] [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 [Illustration] 16 8 7 0 L H HL 7 Memory The contents of addressed memory are transferred 7 0 A 52 User's Manual U18172EJ3V0UD 0 +10H CHAPTER 3 CPU ARCHITECTURE 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only. [Description example] In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 [Illustration] 7 SP SP FEE0H FEDEH Memory 0 FEE0H FEDFH D FEDEH E User's Manual U18172EJ3V0UD 53 CHAPTER 4 PORT FUNCTIONS 4.1 Functions of Ports The 78K0S/KU1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Functions P20 P40 P43 Port 4 Port 2 P23 P32 P34 Port 3 Table 4-1. Port Functions (PD78F920x) Pin Name I/O Function After Reset AlternateFunction Pin I/O P20 Port 2. Input 4-bit I/O port. P21 P22 Note 1 P23 Note 1 ANI1/TI010/TO00/ INTP0 Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software. P32 I/O Port 3 Can be set to input or output mode in 1- ANI0/TI000/TOH1 X2/ANI2 Note 1 X1/ANI3 Note 1 Input INTP1 Input RESET bit units. On-chip pull-up resistor can be connected by setting software. P34 Note 1 Input P40 and P43 Note 2 I/O Input only Port 4. Input Note 1 - 2-bit I/O port. Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected setting software. Notes 1. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. 2. At program initialization, set PM41, PM42, and PM44 to PM47 to "0". Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset. Remarks 1. P22 and P23 can be allocated when the high-speed internal oscillation is selected as the system clock. 2. P22 can be allocated when an external clock input is selected as the system clock. 54 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (PD78F950x) <R> Pin Name I/O Function After Reset AlternateFunction Pin P20 I/O P21 Input TOH1 INTP0 Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software. P22 P23 Port 2. 4-bit I/O port. - Note EXCLK P32 I/O Port 3. Can be set to input or output mode in 1- On-chip pull-up bit units. Note Input INTP1 Input RESET resistor can be P34 Note Input P40 and P43 I/O connected by setting software. Input only Port 4. Input Note - 2-bit I/O port. Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected setting software. Note For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. Caution The P22 and P23/EXCLK pins are pulled down during reset. The P34/RESET pin is pulled up during reset by the reset pin function/power-on clear circuit. Remark 4.2 P23 can be allocated when the high-speed internal oscillation is selected as the system clock. Port Configuration Ports consist of the following hardware units. Table 4-3. Configuration of Ports Item Control registers Configuration Port mode registers (PM2 to PM4) Port registers (P2 to P4) Port mode control register 2 (PMC2) (PD78F920x only) Pull-up resistor option registers (PU2 to PU4) <R> Ports Total: 8 (CMOS I/O: 7, CMOS input: 1) Pull-up resistor Total: 7 User's Manual U18172EJ3V0UD 55 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 2 (1) PD78F920x Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port can also be used for A/D converter analog input, timer I/O, and external interrupt request input. The P22 and P23 pins are also used as the X2 and X1 pins of the system clock oscillator. The functions of the P22 and P23 pins differ, therefore, depending on the selected system clock oscillator. The following three system clock oscillators can be used. <1> High-speed internal oscillator The P22 and P23 pins can be used as I/O port pins or analog input pins to the A/D converter. <2> Crystal/ceramic oscillator The P22 and P23 pins cannot be used as I/O port pins or analog input pins to the A/D converter because they are used as the X2 and X1 pins. <3> External clock input The P22 pin can be used as an I/O port pin or an analog input pin to the A/D converter. The P23 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin or an analog input pin to the A/D converter. The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Reset signal generation sets port 2 to the input mode. Figures 4-2 and 4-4 show the block diagrams of port 2. 56 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P20 and P21 (PD78F920x) VDD WRPU PU2 PU20, PU21 P-ch WRPMC PMC2 PMC20, PMC21 Alternate function Selector Internal bus RD WRPORT P2 Output latch (P20, P21) P20/ANI0/TI000/TOH1, P21/ANI1/TI010/TO00/INTP0 WRPM PM2 PM20, PM21 Alternate function A/D converter P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 RD: Read signal WRxx: Write signal User's Manual U18172EJ3V0UD 57 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P22 (PD78F920x) VDD WRPU PU2 PU22 P-ch WRPMC PMC2 PMC22 Selector Internal bus RD WRPORT P2 Output latch (P22) P22/ANI2/X2 WRPM PM2 PM22 A/D converter P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 RD: Read signal WRxx: Write signal 58 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P23 (PD78F920x) VDD WRPU PU2 PU23 P-ch WRPMC PMC2 PMC23 Selector Internal bus RD WRPORT P2 Output latch (P23) P23/ANI3/X1 WRPM PM2 PM23 A/D converter P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 RD: Read signal WRxx: Write signal User's Manual U18172EJ3V0UD 59 CHAPTER 4 PORT FUNCTIONS <R> (2) PD78F950x Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port can also be used for timer I/O, and external interrupt request input. The P23 pin is also used as the EXCLK pin of the system clock oscillator. The functions of the EXCLK pin differs, therefore, depending on the selected system clock oscillator. The following two system clock oscillators can be used. <1>High-speed internal oscillator The P23 pin can be used as I/O port pin. <2>External clock input The P23 pin is used as the EXCLK pin to input an external clock, and therefore it cannot be used as an I/O port pin. The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Reset signal generation sets port 2 to the input mode. Figures 4-5 to 4-7 show the block diagrams of port 2. 60 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P20 and P21 (PD78F950x) <R> VDD WRPU PU2 PU20, PU21 P-ch Alternate function Selector Internal bus RD WRPORT P2 Output latch (P20, P21) P20/TOH1, P21/INTP0 WRPM PM2 PM20, PM21 Alternate function P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal User's Manual U18172EJ3V0UD 61 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-6. Block Diagram of P22 (PD78F950x) VDD WRPU PU2 PU22 P-ch Selector Internal bus RD WRPORT P2 Output latch (P22) P22 WRPM PM2 PM22 P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal 62 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P23 (PD78F950x) <R> VDD WRPU PU2 PU23 P-ch Selector Internal bus RD WRPORT P2 Output latch (P23) P23/EXCLK WRPM PM2 PM23 P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal User's Manual U18172EJ3V0UD 63 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 3 The P32 pin is a 1-bit I/O port with an output latch. This pin can be set to the input or output mode by using port mode register 3 (PM3). When this pin is used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3). This pin can also be used for external interrupt request input. The P32 pin is a Reset signal generation sets port 3 to the input mode. The P34 pin is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the reset function. For the setting method for pin functions, see CHAPTER 15 OPTION BYTE. When P34 in PD78F920x is used as an input port pin, connect the pull-up resistor. When P34 in PD78F950x is used as an input port pin, an on-chip pull-up resistor can be connected in 1-bit units <R> by using pull-up resistor option register 3 (PU3). Figures 4-8 and 4-10 show the block diagrams of port 3. Figure 4-8. Block Diagram of P32 VDD WRPU PU3 PU32 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P32) P32/INTP1 WRPM PM3 PM32 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal 64 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P34 (PD78F920x) Internal bus RD P34/RESET Reset Option byte RD: Read signal Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Also, since the option byte is referenced after the reset release, if low level is input to the RESET pin before the referencing, then the reset state is not released. When it is used as an input port pin, connect the pull-up resistor. Figure 4-10. Block Diagram of P34 (PD78F950x) <R> VDD WRPU PU3 Internal bus PU34 P-ch RD P34/RESET Reset Option byte RD: Read signal Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Also, since the option byte is referenced after the reset release, if low level is input to the RESET pin before the referencing, then the reset state is not released. When it is used as an input port pin, connect an on-chip pull-up resistor by using bit 4 (PU34) of pull-up resistor option register 3 (PU3). User's Manual U18172EJ3V0UD 65 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 4 Port 4 is a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4) Note . When the P40 and P43 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 4 (PU4). Reset signal generation sets port 4 to the input mode. Figures 4-11 shows the block diagram of port 4. Note In PD78F920x, set PM41, PM42, and PM44 to PM47 to "0" at program initialization. Figure 4-11. Block Diagram of P40 and P43 VDD WRPU PU4 PU40, PU43 P-ch Selector Internal bus RD WRPORT P4 Output latch (P40, P43) P40, P43 WRPM PM4 PM40, PM43 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal 4.3 Registers Controlling Port Functions The ports are controlled by the following four types of registers. * Port mode registers (PM2 to PM4) * Port registers (P2 to P4) * Port mode control register 2 (PMC2) (PD78F920x only) <R> * Pull-up resistor option registers (PU2 to PU4) 66 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS (1) Port mode registers (PM2 to PM4) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When a port pin is used as an alternate-function pin, set its port mode register and output latch as shown in Table 4-4. Caution Because P21 and P32 are also used as external interrupt pins, the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. To use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. Figure 4-12. Format of Port Mode Register Address: FF22H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 Address: FF23H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 1 PM32 1 1 3 2 1 0 Note Note Address: FF24H, After reset: FFH, R/W Symbol 7 6 5 4 PM4 Note Note Note Note 1 PMmn 1 1 1 PM43 1 1 PM40 Selection of I/O mode of Pmn pin (m = 2 to 4; n = 0 to 3) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) Note In PD78F920x, set PM41, PM42, and PM44 to PM47 to "0" at program initialization. User's Manual U18172EJ3V0UD 67 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P2 to P4) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output latch of the port is read in the output mode. P20 to P23, P32, P40 and P43 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 4-13. Format of Port Register Address: FF02H, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P2 0 0 0 0 P23 P22 P21 P20 Address: FF03H, After reset: 00H Note (Output latch) R/W Note Symbol 7 6 5 4 3 2 1 0 P3 0 0 0 P34 0 P32 0 0 Address: FF04H, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P4 0 0 0 0 P43 0 0 P40 Pmn m = 2 to 4; n = 0 to 4 Controls of output data (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Note Because P34 is read-only, its reset value is undefined. (3) Port mode control register 2 (PMC2) (PD78F920x only) This register specifies the port/alternate function (except the A/D converter function) mode or the A/D converter mode. Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units. PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PMC2 to 00H. 68 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Mode Control Register 2 (PD78F920x only) Address: FF84H, After reset: R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) 0 Port/alternate-function (except the A/D converter function) mode 1 A/D converter mode Caution When PMC20 to PMC23 are set to 1, the port function on the P20/ANI0 to P23/ANI3 pins cannot be used. Moreover, be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for the pins set to A/D converter mode. Table 4-4. Setting of Port Mode Register, Port Register (Output Latch), and Port Mode Control Register When Alternate Function Is Used Port Name Alternate-Function Pin PMxx Pxx PMC2n Note Name Note Input 1 x 1 TI000 Input 1 x 0 TOH1 Output 0 0 0 ANI0 P20 Note ANI1 P21 Note Input 1 x 1 Note Input 1 x 0 Note Output 0 0 0 TI010 TO00 Input 1 x 0 ANI2 Note Input 1 x 1 P23 ANI3 Note Input 1 x 1 P32 INTP1 Input 1 x - INTP0 P22 <R> (n = 0 to 3) I/O Note PD78F920x only Remark x: don't care PMxx: Port mode register, Pxx: Port register (output latch of port) PMC2x: Port mode control register User's Manual U18172EJ3V0UD 69 CHAPTER 4 PORT FUNCTIONS (4) Pull-up resistor option registers (PU2 to PU4) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P32, P34, P40 and P43. By setting PU2 to PU4, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2 to PU4. PU2 to PU4 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation set these registers to 00H. Figure 4-15. Format of Pull-up Resistor Option Register Address: FF32H, After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU2 0 0 0 0 PU23 PU22 PU21 PU20 5 4 3 2 1 0 0 PU32 0 0 Address: FF33H, After reset: 00H R/W Symbol PU3 7 6 0 0 0 PU34 Note Address: FF34H, After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU4 0 0 0 0 PU43 0 0 PU40 PUmn Selection of connection of on-chip pull-up resistor of Pmn (m = 2 to 4; n = 0 to 4) 0 Does not connect on-chip pull-up resistor 1 Connects on-chip pull-up resistor Note PD78F950x only <R> 70 User's Manual U18172EJ3V0UD CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch by a transfer instruction. In addition, the contents of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to the output latch. When a reset signal is generated, cleans the data in the output latch. (2) In input mode A value can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the pin status remains unchanged. Once data is written to the output latch, it is retained until new data is written to the output latch. When a reset signal is generated, cleans the data in the output latch. 4.4.2 Reading from I/O port (1) In output mode The contents of the output latch can be read by a transfer instruction. The contents of the output latch remain unchanged. (2) In input mode The pin status can be read by a transfer instruction. The contents of the output latch remain unchanged. 4.4.3 Operations on I/O port (1) In output mode An operation is performed on the contents of the output latch and the result is written to the output latch. The contents of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to the output latch. Reset signal generation clears the data in the output latch. (2) In input mode The pin level is read and an operation is performed on its contents. The operation result is written to the output latch. However, the pin status remains unchanged because the output buffer is off. When a reset signal is generated, cleans the data in the output latch. User's Manual U18172EJ3V0UD 71 CHAPTER 5 CLOCK GENERATORS 5.1 Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1). 5.1.1 System clock oscillators The following three types of system clock oscillators are used. * High-speed internal oscillator This circuit internally oscillates a clock of 8 MHz (TYP.). Its oscillation can be stopped by execution of the STOP instruction. If the High-speed internal oscillator is selected to supply the system clock, the X1 and X2 pins in PD78F920x, <R> and the EXCLK pin in PD78F950x can be used as I/O port pins. * Crystal/ceramic oscillator Note 1 This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can oscillate a clock of 2 MHz to 10 MHz. Oscillation of this circuit can be stopped by execution of the STOP instruction. * External clock input circuit This circuit supplies a clock from an external IC to the X1 pin Note 2 . A clock of 2 MHz to 10 MHz can be supplied. Internal clock supply can be stopped by execution of the STOP instruction. Note 1 If the external clock input is selected as the system clock, the X2 pin can be used as an I/O port pin. The system clock source is selected by using the option byte. For details, refer to CHAPTER 15 OPTION BYTE. When using the X1 and X2 pins in PD78F920x, and the EXCLK pin in PD78F950x as I/O port pins, refer to <R> CHAPTER 4 PORT FUNCTIONS for details. <R> <R> Notes 1. 2. 5.1.2 PD78F920x only PD78F920x: X1 pin, PD78F950x: EXCLK pin Clock oscillator for interval time generation The following circuit is used as a clock oscillator for interval time generation. * Low-speed internal oscillator This circuit oscillates a clock of 240 kHz (TYP.). Its oscillation can be stopped by using the low-speed internal oscillation mode register (LSRCM) when it is specified by the option byte that its oscillation can be stopped by software. 72 User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS 5.2 Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Control registers Configuration Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization time select register (OSTS) (PD78F920x only) <R> <R> Oscillators Crystal/ceramic oscillator (PD78F920x only) High-speed internal oscillator External clock input circuit Low-speed internal oscillator User's Manual U18172EJ3V0UD 73 CHAPTER 5 CLOCK GENERATORS Figure 5-1. Block Diagram of Clock Generators (1/2) (1) PD78F920x Internal bus Oscillation stabilization time select register (OSTS) OSTS1 OSTS0 Preprocessor clock control register (PPCC) PPCC1 PPCC0 Processor clock control register (PCC) PCC1 System clock oscillation stabilization time counter CPU Controller STOP CPU clock (fCPU) Watchdog timer Crystal/ceramic oscillation X2/P22/ANI2 External clock input Prescaler fX fX 2 fX 22 Selector X1/P23/ANI3 System clock oscillatorNote Selector High-speed internal oscillation fXP 22 fXP Prescaler Clock to peripheral hardware (fXP) Low-speed internal oscillator fRL 8-bit timer H1, watchdog timer Option byte 1: Cannot be stopped. 0: Can be stopped. LSRSTOP Low-speed internal oscillation mode register (LSRCM) Internal bus Note Select the high-speed internal oscillator, crystal/ceramic oscillator, or external clock input circuit as the system clock source by using the option byte. 74 User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS Figure 5-1. Block Diagram of Clock Generators (2/2) (2) PD78F950x Internal bus Preprocessor clock control register (PPCC) Processor clock control register (PCC) PCC1 CPU PPCC1 PPCC0 STOP CPU clock (fCPU) Watchdog timer External clock input High-speed internal oscillation Prescaler fX fX 2 fX 22 Selector EXCLK/P23 System clock oscillatorNote Selector <R> fXP 22 fXP Prescaler Clock to peripheral hardware (fXP) Low-speed internal oscillator fRL 8-bit timer H1, watchdog timer Option byte 1: Cannot be stopped. 0: Can be stopped. LSRSTOP Low-speed internal oscillation mode register (LSRCM) Internal bus Note Select the high-speed internal oscillator or external clock input circuit as the system clock source by using the option byte. User's Manual U18172EJ3V0UD 75 CHAPTER 5 CLOCK GENERATORS 5.3 Registers Controlling Clock Generators The clock generators are controlled by the following four registers. * Processor clock control register (PCC) * Preprocessor clock control register (PPCC) * Low-speed internal oscillation mode register (LSRCM) * Oscillation stabilization time select register (OSTS) (PD78F920x only) <R> (1) Processor clock control register (PCC) and preprocessor clock control register (PPCC) These registers are used to specify the division ratio of the system clock. PCC and PPCC are set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC and PPCC to 02H. Figure 5-2. Format of Processor Clock Control Register (PCC) Address: FFFBH, After reset: 02H, R/W Symbol 7 6 5 4 3 2 1 0 PCC 0 0 0 0 0 0 PCC1 0 Figure 5-3. Format of Preprocessor Clock Control Register (PPCC) Address: FFF3H, After reset: 02H, R/W Symbol 7 6 5 4 3 2 1 0 PPCC 0 0 0 0 0 0 PPCC1 PPCC0 PPCC1 PPCC0 PCC1 0 0 0 fX 0 1 0 fX/2 0 0 1 fX/2 2 1 0 0 fX/2 2 Note 3 0 1 1 fX/2 3 Note 2 1 0 1 fX/2 4 Note 3 Other than above <R> Selection of CPU clock (fCPU) Note 1 Note 2 Setting prohibited Notes 1. The setting range of the CPU clock differs depending on the supply voltage to be used. Be sure to refer to CPU clock and peripheral clock frequencies described in AC Characteristics in CHAPTER 19. 2. If PPCC = 01H, the clock (fXP) supplied to the peripheral hardware is fX/2. 3. If PPCC = 02H, the clock (fXP) supplied to the peripheral hardware is fX/22. 76 User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS The fastest instruction of the 78K0S/KU1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Note 1 Minimum Instruction Execution Time: 2/fCPU High-speed internal oscillation clock (at 8.0 MHz (TYP.)) fX Note 2 Crystal/ceramic oscillation clock or external clock input (at 10.0 MHz) 0.25 s 0.2 s 0.5 s 0.4 s fX/2 2 1.0 s 0.8 s fX/2 3 2.0 s 1.6 s fX/2 4 4.0 s 3.2 s fX/2 Notes 1. The CPU clock (high-speed internal oscillation clock, crystal/ceramic oscillation clockNote 2, or external clock input) is selected by the option byte. <R> 2. PD78F920x only (2) Low-speed internal oscillation mode register (LSRCM) This register is used to select the operation mode of the low-speed internal oscillator (240 kHz (TYP.)). This register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped by software. If it is specified by the option byte that the low-speed internal oscillator cannot be stopped by software, setting of this register is invalid, and the low-speed internal oscillator continues oscillating. In addition, the source clock of WDT is fixed to the low-speed internal oscillator. For details, refer to CHAPTER 8 WATCHDOG TIMER. LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LSRCM to 00H. Figure 5-4. Format of Low-Speed internal oscillation Mode Register (LSRCM) Address: FF58H, After reset: 00H, R/W Symbol 7 6 5 4 3 2 1 <0> LSRCM 0 0 0 0 0 0 0 LSRSTOP LSRSTOP Oscillation/stop of low-speed internal oscillator 0 Low-speed internal oscillates 1 Low-speed internal oscillator stops User's Manual U18172EJ3V0UD 77 CHAPTER 5 CLOCK GENERATORS <R> (3) Oscillation stabilization time select register (OSTS) (PD78F920x only) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released. If the high-speed internal oscillator or external clock input is selected as the system clock source, no wait time elapses. The system clock oscillator and the oscillation stabilization time that elapses after power application or release of reset are selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. OSTS is set by using an 8-bit memory manipulation instruction. Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFF4H, After reset: Undefined, R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 0 0 2 /fX (102.4 s) 0 1 2 /fX (409.6 s) 1 0 2 /fX (3.27 ms) 1 1 2 /fX (13.1 ms) Selection of oscillation stabilization time 10 12 15 17 Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS 2. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset signal generation or interrupt generation. STOP mode is released Voltage waveform of X1 pin a 3. The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Remarks 1. ( ): fX = 10 MHz 2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. 78 User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS 5.4 System Clock Oscillators The following three types of system clock oscillators are available. * High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). * Crystal/ceramic oscillator Oscillates a clock of 2 MHz to 10 MHz. Note 1 * External clock input circuit: <R> <R> Notes 1. 2. 5.4.1 : Supplies a clock of 2 MHz to 10 MHz to the X1 pin Note 2 . PD78F920x only PD78F920x: X1 pin, PD78F950x: EXCLK pin High-speed internal oscillator The 78K0S/KU1+ include a high-speed internal oscillator (8 MHz (TYP.)). If the high-speed internal oscillation is selected by the option byte as the clock source, the X1 and X2 pins in PD78F920x, and the EXCLK pin in PD78F950x can be used as I/O port pins. For details of the option byte, refer to CHAPTER 15 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. 5.4.2 Crystal/ceramic oscillator (PD78F920x only) The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2 pins. If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are used as crystal or ceramic resonator connection pins. For details of the option byte, refer to CHAPTER 15 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. Figure 5-6 shows the external circuit of the crystal/ceramic oscillator. Figure 5-6. External Circuit of Crystal/Ceramic Oscillator (PD78F920x Only) VSS X1 X2 Crystal resonator or ceramic resonator Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. User's Manual U18172EJ3V0UD 79 CHAPTER 5 CLOCK GENERATORS Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORT VSS X1 X2 VSS (c) Wiring near high fluctuating current X1 X2 (d) Current flowing through ground line of oscillator (Potential at points A, B, and C fluctuates.) VDD PORT X1 X2 VSS X1 A B X2 High current VSS High current 80 User's Manual U18172EJ3V0UD C CHAPTER 5 CLOCK GENERATORS Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched VSS 5.4.3 X1 X2 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin Note 1 . If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin. Note 2 For details of the option byte, refer to CHAPTER 15 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. <R> <R> Notes 1. 2. 5.4.4 PD78F920x: X1 pin, PD78F950x: EXCLK pin PD78F920x only Prescaler The prescaler divides the clock (fX) output by the system clock oscillator to generate a clock (fXP) to be supplied to the peripheral hardware. It also divides the clock to peripheral hardware (fXP) to generate a clock to be supplied to the CPU. Remark The clock output by the oscillator selected by the option byte (high-speed internal oscillator, crystal/ceramic oscillator Note , or external clock input circuit) is divided. For details of the option byte, refer to CHAPTER 15 OPTION BYTE. Note PD78F920x only User's Manual U18172EJ3V0UD 81 CHAPTER 5 CLOCK GENERATORS 5.5 Operation of CPU Clock Generator A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of oscillators. * High-speed internal oscillator: Note 1 * Crystal/ceramic oscillator : Notes 1. 2. Oscillates a clock of 2 MHz to 10 MHz. Note 2 * External clock input circuit: <R> <R> Internally oscillates a clock of 8 MHz (TYP.). Supplies a clock of 2 MHz to 10 MHz to X1 pin . PD78F920x only PD78F920x: X1 pin, PD78F950x: EXCLK pin The system clock oscillator is selected by the option byte. For details of the option byte, refer to CHAPTER 15 OPTION BYTE. (1) High-speed internal oscillator When the high-speed internal oscillation is selected by the option byte, the following is possible. * Shortening of start time If the high-speed internal oscillator is selected as the oscillator, the CPU can be started without having to wait for the oscillation stabilization time of the system clock. Therefore, the start time can be shortened. * Improvement of expandability If the high-speed internal oscillator is selected as the oscillator, the X1 and X2 pins in PD78F920x, and the <R> EXCLK pin in PD78F950x can be used as I/O port pins. For details, refer to CHAPTER 4 PORT FUNCTIONS. Figures 5-8 and 5-9 show the timing chart and status transition diagram of the default start by the high-speed internal oscillation. Remark When the high-speed internal oscillation is used, the clock accuracy is 5%. Figure 5-8. Timing Chart of Default Start by High-Speed Internal Oscillation (a) VDD RESET H Internal reset (b) System clock CPU clock High-speed internal oscillation clock PCC = 02H, PPCC = 02H Option byte is read. System clock is selected. (Operation stopsNote) Note Operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). 82 User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation clock operates as the system clock. Figure 5-9. Status Transition of Default Start by High-Speed internal oscillation Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal High-speed internal oscillator selected by option byte Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt Interrupt HALT instruction STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register User's Manual U18172EJ3V0UD 83 CHAPTER 5 CLOCK GENERATORS <R> (2) Crystal/ceramic oscillator (PD78F920x only) If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected and the accuracy of processing is improved because the frequency deviation is small, as compared with highspeed internal oscillation (8 MHz (TYP.)). Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic oscillator. Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator (PD78F920x Only) (a) VDD RESET H Internal reset (b) System clock (c) Crystal/ceramic oscillator clock PCC = 02H, PPCC = 02H CPU clock Option byte is read. System clock is selected. (Operation stopsNote 1) Clock oscillation stabilization timeNote 2 Notes 1. Operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). 2. The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is released is selected by the oscillation stabilization time select register (OSTS). (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) After high-speed internal oscillation clock is generated, the option byte is referenced and the system clock is selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock. (c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. 84 User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation (PD78F920x Only) Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal Crystal/ceramic oscillation selected by option byte Wait for clock oscillation stabilization Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt HALT instruction Interrupt STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register User's Manual U18172EJ3V0UD 85 CHAPTER 5 CLOCK GENERATORS (3) External clock input circuit If external clock input is selected by the option byte, the following is possible. * High-speed operation The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.)) because an oscillation frequency of 2 MHz to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied. * Improvement of expandability If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. Note For details, refer to CHAPTER 4 PORT FUNCTIONS. Note PD78F920x only Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input. Figure 5-12. Timing of Default Start by External Clock Input (a) VDD RESET H Internal reset (b) System clock External clock input PCC = 02H, PPCC = 02H CPU clock Option byte is read. System clock is selected. (Operation stopsNote) Note Operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the external clock operates as the system clock. 86 User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS Figure 5-13. Status Transition of Default Start by External Clock Input Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal External clock input selected by option byte Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt HALT instruction Interrupt STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register User's Manual U18172EJ3V0UD 87 CHAPTER 5 CLOCK GENERATORS 5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. * Clock to peripheral hardware (fXP) * Low-speed internal oscillation clock (fRL) (1) Clock to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock (fX). The division ratio is selected by the pre-processor clock control register (PPCC). Three types of frequencies are selectable: "fX", "fX/2", and "fX/22". Table 5-3 lists the clocks supplied to the peripheral hardware. Table 5-3. Clocks to Peripheral Hardware PPCC1 PPCC0 Selection of clock to peripheral hardware (fXP) 0 0 fX 0 1 fX/2 1 0 fX/2 1 1 Setting prohibited 2 (2) Low-speed internal oscillation clock The low-speed internal oscillator of the clock oscillator for interval time generation is always started after release of reset, and oscillates at 240 kHz (TYP.). It can be specified by the option byte whether the low-speed internal oscillator can or cannot be stopped by software. If it is specified that the low-speed internal oscillator can be stopped by software, oscillation can be started or stopped by using the low-speed internal oscillation mode register (LSRCM). If it is specified that it cannot be stopped by software, the clock source of WDT is fixed to the low-speed internal oscillation clock (fRL). The low-speed internal oscillator is independent of the CPU clock. If it is used as the source clock of WDT, therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed internal oscillator is used as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status. Table 5-4 shows the operation status of the low-speed internal oscillator when it is selected as the source clock of WDT and the count clock of 8-bit timer H1. Figure 5-14 shows the status transition of the low-speed internal oscillator. Table 5-4. Operation Status of Low-Speed Internal Oscillator Option Byte Setting Can be stopped by software LSRSTOP = 1 CPU Status Operation mode LSRSTOP = 0 LSRSTOP = 1 Standby LSRSTOP = 0 Cannot be stopped Operation mode WDT Status Stopped Stopped Operates Operates Stopped Stopped Stopped Operates Operates Standby 88 TMH1 Status User's Manual U18172EJ3V0UD CHAPTER 5 CLOCK GENERATORS Figure 5-14. Status Transition of Low-Speed Internal Oscillator Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal Select by option byte if low-speed internal oscillator can be stopped or not Can be stopped Cannot be stopped Clock source of WDT is selected by softwareNote Clock source of WDT is fixed to fRL Low-speed internal oscillator can be stopped Low-speed internal oscillator cannot be stopped LSRSTOP = 1 LSRSTOP = 0 Low-speed internal oscillator stops Note The clock source of the watchdog timer (WDT) is selected from fX or fRL, or it may be stopped. For details, refer to CHAPTER 8 WATCHDOG TIMER. User's Manual U18172EJ3V0UD 89 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) <R> 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. * Number of counts: 2 to 65536 (2) External event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level pulse width or more of a signal input externally. * Valid level pulse width: 2/fXP or more (3) Pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. * Valid level pulse width: 2/fXP or more (4) Square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. * Cycle: (2 to 65536) x 2 x count clock cycle (5) PPG output 16-bit timer/event counter 00 can output a square wave that have arbitrary cycle and pulse width. * 1 < Pulse width < Cycle 65536 (6) One-shot pulse output 16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any desired value. 90 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010 Timer output TO00, output controller Control registers 16-bit timer mode control register 00 (TMC00) Capture/compare control register 00 (CRC00) 16-bit timer output control register 00 (TOC00) Prescaler mode register 00 (PRM00) Port mode register 2 (PM2) Port register 2 (P2) Port mode control register 2 (PMC2) Figure 6-1 shows a block diagram of these counters. Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) Selector CRC002CRC001 CRC000 TI010/TO00/ANI1/ INTP0/P21 Selector to CR010 Noise eliminator 16-bit timer capture/compare register 000 (CR000) INTTM000 Match Noise eliminator 16-bit timer counter 00 (TM00) Output controller TO00/TI010/ANI1/ INTP0/P21 Match 2 Output latch (P21) Noise eliminator TI000/ANI0/ TOH1/P20 Clear PM21 16-bit timer capture/compare register 010 (CR010) Selector fX Selector fXP fXP/22 fXP/28 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus User's Manual U18172EJ3V0UD 91 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00) Address: FF12H, FF13H Symbol After reset: 0000H R FF13H 7 6 5 4 FF12H 3 2 1 0 7 6 5 4 3 2 1 0 TM00 The count value is reset to 0000H in the following cases. <1> At reset input <2> If TMC003 and TMC002 are cleared <3> If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000 <4> If TM00 and CR000 match in the clear & start mode entered on a match between TM00 and CR000 <5> If OSPT00 is set to 1 in the one-shot pulse output mode Cautions 1. Even if TM00 is read, the value is not captured by CR010. 2. When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. (2) 16-bit timer capture/compare register 000 (CR000) CR000 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register 00 (CRC00). CR000 is set by 16-bit memory manipulation instruction. A reset signal generation clears CR000 to 0000H. Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000) Address: FF14H, FF15H Symbol After reset: 0000H R/W FF15H 7 6 5 4 3 FF14H 2 1 0 7 6 5 4 3 2 1 0 CR000 * When CR000 is used as a compare register The value set in CR000 is constantly compared with the 16-bit timer/counter 00 (TM00) count value, and an interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the interval time then TM00 is set to interval timer operation. 92 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) * When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 62). Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Rising edge 0 1 Rising edge Falling edge 0 0 No capture operation Both rising and falling edges 1 1 (2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1) CR000 Capture Trigger TI010 Pin Valid Edge ES110 ES100 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited. 2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) ES110, ES100: Bits 7 and 6 of prescaler mode register 00 (PRM00) CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00) Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be performed when this register is used as an external event counter. However, in the free-running mode and in the clear & start mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H following overflow (FFFFH). 2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR000 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR000 is changed. 3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed. 4. The capture operation may not be performed for CR000 set in compare mode even if a capture trigger is input. 5. When P21 is used as the input pin for the valid edge of TI010, it cannot be used as a timer output (TO00). Moreover, when P21 is used as TO00, it cannot be used as the input pin for the valid edge of TI010. 6. If the register read period and the input of the capture trigger conflict when CR000 is used as a capture register, the read data is undefined (the capture data itself is a normal value). Also, if the count stop of the timer and the input of the capture trigger conflict, the capture trigger is undefined. 7. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. User's Manual U18172EJ3V0UD 93 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). CR010 is set by 16-bit memory manipulation instruction. Reset signal generation clears CR010 to 0000H. Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Address: FF16H, FF17H Symbol After reset: 0000H R/W FF17H 7 6 5 4 FF16H 3 2 1 0 7 6 5 4 3 2 1 0 CR010 * When CR010 is used as a compare register The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an interrupt request (INTTM010) is generated if they match. * When CR010 is used as a capture register It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by means of prescaler mode register 00 (PRM00) (refer to Table 6-3). Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1) CR010 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited. 2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) CRC002: Bit 2 of capture/compare control register 00 (CRC00) Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010 changes from 0000H to 0001H following overflow (FFFFH). 2. If the new value of CR010 is less than the value of 16-bit timer counter 00 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR010 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR010 is changed. 3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed. 4. The capture operation may not be performed for CR010 set in compare mode even if a capture trigger is input. 5. If the register read period and the input of the capture trigger conflict when CR010 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. Also, if the timer count stop and the input of the capture trigger conflict, the capture data is undefined. 94 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Cautions 6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. 6.3 Registers to Control 16-Bit Timer/Event Counter 00 The following seven types of registers are used to control 16-bit timer/event counter 00. * 16-bit timer mode control register 00 (TMC00) * Capture/compare control register 00 (CRC00) * 16-bit timer output control register 00 (TOC00) * Prescaler mode register 00 (PRM00) * Port mode register 2 (PM2) * Port register 2 (P2) * Port mode control register 2 (PMC2) (1) 16-bit timer mode control register 00 (TMC00) This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output timing, and detects an overflow. TMC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of TMC00 to 00H. Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation. User's Manual U18172EJ3V0UD 95 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H Symbol 7 6 5 4 TMC00 0 0 0 0 R/W 3 2 1 <0> TMC003 TMC002 TMC001 OVF00 Operating mode and clear TMC003 TMC002 TMC001 TO00 inversion timing selection Interrupt request generation mode selection 0 0 0 Operation stop 0 0 1 (TM00 cleared to 0) 0 1 0 Free-running mode 0 1 1 0 1 0 Clear & start occurs on valid No change Not generated Match between TM00 and < When operating as compare CR000 or match between register > TM00 and CR010 Generated on match between Match between TM00 and TM00 and CR000, or match CR000, match between TM00 between TM00 and CR010 and CR010 or TI000 pin valid < When operating as capture edge register > - 1 0 1 edge of TI000 pin 1 1 0 Clear & start occurs on match Match between TM00 and between TM00 and CR000 CR000 or match between Generated on TI000 pin and TI010 pin valid edge TM00 and CR010 1 1 1 Match between TM00 and CR000, match between TM00 and CR010 or TI000 pin valid edge OVF00 Overflow detection of 16-bit timer counter 00 (TM00) 0 Overflow not detected 1 Overflow detected Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag. 2. If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the TI000/TI010 pins. 3. Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. 4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00) after stopping the timer operation. 5. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at the valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. 6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. 7. The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0), however, occurs at the rise of the next count clock. 96 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Remark TM00: 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of CRC00 to 00H. Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00) Address: FF62H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC00 0 0 0 0 0 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection 0 Operate as compare register 1 Operate as capture register CRC001 CR000 capture trigger selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase CRC000 Note CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register Note When the CRC001 bit value is 1, capture is not performed if both the rising and falling edges have been selected as the valid edges of the TI000 pin. Cautions 1. The timer operation must be stopped before setting CRC00. 2. When the clear & start mode entered on a match between TM00 and CR000 is selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. 3. To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00) (refer to Figure 6-18). User's Manual U18172EJ3V0UD 97 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and output trigger of one-shot pulse by software. TOC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of TOC00 to 00H. Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FF63H After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software 0 No one-shot pulse output trigger 1 One-shot pulse output trigger OSPE00 One-shot pulse output operation control 0 Successive pulse output mode 1 One-shot pulse output mode TOC004 Note Timer output F/F control using match of CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation LVS00 LVR00 0 0 No change Timer output F/F status setting 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited TOC001 Timer output F/F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 Timer output control 0 Disables output (output fixed to level 0) 1 Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than OSPT00. 2. If LVS00 and LVR00 are read, 0 is read. 3. OSPT00 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT00 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively. 98 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Caution 6. When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with the 8-bit memory manipulation instruction. When the TOE00 is 1, the LVS00 and LVR00 can be set with the 1-bit memory manipulation instruction. (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of PRM00 to 00H. Figure 6-8. Format of Prescaler Mode Register 00 (PRM00) Address: FF61H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000 ES110 ES100 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES010 ES000 0 0 Falling edge 0 1 Rising edge TI010 pin valid edge selection TI000 pin valid edge selection 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 0 0 fXP (10 MHz) 0 1 fXP/2 (2.5 MHz) 1 0 fXP/2 (39.06 kHz) 1 1 TI000 pin valid edge Count clock (fsam) selection 2 8 Note Remarks 1. fXP: Oscillation frequency of clock supplied to peripheral hardware 2. ( ): fXP = 10 MHz Note The external clock requires a pulse longer than two cycles of the internal count clock (fXP). Cautions 1. Always set data to PRM00 after stopping the timer operation. 2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin. User's Manual U18172EJ3V0UD 99 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. <1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. <2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled after a low level is input to the TI0n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is enabled. <3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled after a high level is input to the TI0n0 pin If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. 4. The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. 5. When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer output (TO00). When using P21 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. Remark n = 0, 1 (5) Port mode register 2 (PM2) and port mode control register 2 (PMC2) When using the P21/TO00/TI010/ANI1/INTP0 pin for timer output, clear PM21, the output latch of P21, and PMC21 to 0. When using the P20/TI000/TOH1/ANI0 and P21/TO00/TI010/ANI1/INTP0 pins as a timer input, set PM20 and PM21 to 1, and clear PMC20 and PMC21 to 0. At this time, the output latches of P20 and P21 can be either 0 or 1. PM2 and PMC2 are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of PM2 to FFH, and clears the value of PMC2 to 00H. Figure 6-9. Format of Port Mode Register 2 (PM2) Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 PM2n 100 P2n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-10. Format of Port Mode Control Register 2 (PMC2) Address: FF84H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n 6.4 Specification of operation mode (n = 0 to 3) 0 Port/Alternate-function (except A/D converter) mode 1 A/D converter mode Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-11 allows operation as an interval timer. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-11 for the set value). <2> Set any value to the CR000 register. <3> Set the count clock by using the PRM00 register. <4> Set the TMC00 register to start the operation (see Figure 6-11 for the set value). Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Remark For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS. Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000 (CR000) beforehand as the interval. When the count value of 16-bit timer counter 00 (TM00) matches the value set to CR000, counting continues with the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated. The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). User's Manual U18172EJ3V0UD 101 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-11. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. Figure 6-12. Interval Timer Configuration Diagram 16-bit timer capture/compare register 000 (CR000) INTTM000 Selector fXP fXP/22 fXP/28 TI000/ANI0/ TOH1/P20 16-bit timer counter 00 (TM00) Noise eliminator Note OVF00 Clear circuit fXP Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH. 102 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-13. Timing of Interval Timer Operation t Count clock TM00 count value 0000H 0001H N Timer operation enabled CR000 0000H 0001H N Clear N 0000H 0001H N Clear N N N INTTM000 Interrupt request generated Remark Interrupt request generated Interval time = (N + 1) x t N = 0001H to FFFFH (settable range) When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N) before the change, it is necessary to restart the timer after changing CR000. Figure 6-14. Timing After Change of Compare Register During Timer Count Operation (N M: N > M ) Count clock N CR000 TM00 count value Remark 6.4.2 X-1 M X FFFFH 0000H 0001H 0002H N>X>M External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-15 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set any value to the CR000 register (0000H cannot be set). <4> Set the TMC00 register to start the operation (see Figure 6-15 for the set value). Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control register 2 (PMC2). 2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS. User's Manual U18172EJ3V0UD 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated. Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.) The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00). Because an operation is carried out only when the valid edge of the TI000 pin is detected twice after sampling with the internal clock (fXP), noise with a short pulse width can be removed. Figure 6-15. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 1 1 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. 104 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-16. External Event Counter Configuration Diagram Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear fXP OVF00Note 16-bit timer counter 00 (TM00) Noise eliminator Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH. Figure 6-17. External Event Counter Operation Timing (with Rising Edge Specified) (1) INTTM000 generation timing immediately after operation starts Counting is started after a valid edge is detected twice. Timer operation starts Count starts TI000 pin input 1 TM00 count value 2 3 0000H 0001H 0002H 0003H N-2 N-1 N 0000H 0001H 0002H N CR000 INTTM000 (2) INTTM000 generation timing after INTTM000 has been generated twice TI000 pin input TM00 count value CR000 N 0000H 0001H 0002H 0003H 0004H N-1 N 0000H 0001H 0002H 0003H N INTTM000 Caution When reading the external event counter count value, TM00 should be read. User's Manual U18172EJ3V0UD 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin. When an interrupt occurs, necessary pulse width is calculable by reading the valied value of the capture register. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width ( see Figure 6-18 ). Figure 6-18. CR010 Capture Operation with Rising Edge Specified Count clock TM00 N-3 N-2 N-1 N N+1 TI000 Rising edge detection N CR010 INTTM010 Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figures 6-19, 6-22, 6-24, and 6-26 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set the TMC00 register to start the operation (see Figures 6-19, 6-22, 6-24, and 6-26 for the set value). Caution To use two capture registers, set the TI000 and TI010 pins. Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control register 2 (PMC2). 2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS. (1) Pulse width measurement with free-running counter and one capture register Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ES010) of PRM00. When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the valid edge specified by PRM00 is input, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set. Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. 106 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 0/1 0 CR000 used as compare register CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES101 ES100 ES010 ES000 PRM00 0/1 0/1 1 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. Figure 6-20. Configuration Diagram for Pulse Width Measurement by Free-Running Counter fXP/22 fXP/28 TI000/ANI0/ TOH1/P20 Selector fXP 16-bit timer/counter 00 (TM00) 16-bit timer capture/compare register 010 (CR010) INTTM010 Internal bus User's Manual U18172EJ3V0UD 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-21. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 TI000 pin input CR010 capture value D0 D1 D2 D3 INTTM010 (D1 - D0) x t (D2 - D1) x t Note (D3 - D2) x t Note The carry flag is set to 1. Ignore this setting. (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. Specify both the rising and falling edges as the valid edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00. When the valid edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the valid edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal (INTTM000) is set. Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. 108 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-22. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 0 1 CR000 used as capture register Captures valid edge of TI010 pin to CR000. CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 1 1 1 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection. (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. User's Manual U18172EJ3V0UD 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 TI000 pin input CR010 capture value D0 D1 D2 INTTM010 TI010 pin input CR000 capture value D1 D2 + 1 INTTM000 (D1 - D0) x t (D2 - D1) x t Note (D3 - D2) x t ((D2 + 1) - D1) x t Note Note The carry flag is set to 1. Ignore this setting. (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ES010) of PRM00. When the rising or falling edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000). Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. 110 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000Note. CR010 used as capture register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. User's Manual U18172EJ3V0UD 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-25. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H D0 D1 D0 + 1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 TI000 pin input CR010 capture value D0 D2 CR000 capture value D1 D3 INTTM010 (D1 - D0) x t (D2 - D1) x t Note (D3 - D2) x t Note The carry flag is set to 1. Ignore this setting. (4) Pulse width measurement by means of restart Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ES010) of PRM00. When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count. The edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (1/2) (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000Note. CR010 used as capture register Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare register 000 (CR000) cannot perform the capture operation. 112 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (2/2) (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (c) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 0 0/1 0 Clears and starts at valid edge of TI000 pin. Figure 6-27. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H TI000 pin input CR010 capture value D0 D2 D1 CR000 capture value INTTM010 (D1 + 1) x t (D2 + 1) x t User's Manual U18172EJ3V0UD 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-28 for the set value). <3> Set the TOC00 register (see Figure 6-28 for the set value). <4> Set any value to the CR000 register (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figure 6-28 for the set value). Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control register 2 (PMC2). 2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS. A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 000 (CR000). The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 + 1 by setting bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave with any selected frequency to be output. Figure 6-28. Control Register Settings in Square-Wave Output Mode (1/2) (a) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register 114 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-28. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 0 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited). Does not invert output on match between TM00 and CR010. Disables one-shot pulse output. (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. Figure 6-29. Square-Wave Output Operation Timing Count clock TM00 count value CR000 0000H 0001H 0002H N-1 N 0000H 0001H 0002H N-1 N 0000H N INTTM000 TO00 pin output User's Manual U18172EJ3V0UD 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-30 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-30 for the set value). <2> Set any value to the CR000 register as the cycle. <3> Set any value to the CR010 register as the duty factor. <4> Set the TOC00 register (see Figure 6-30 for the set value). <5> Set the count clock by using the PRM00 register. <6> Set the TMC00 register to start the operation (see Figure 6-30 for the set value). Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control register 2 (PMC2). 2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS. 3. n = 0 or 1 In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer capture/compare register 000 (CR000), respectively. 116 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-30. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 x 0 0 CR000 used as compare register CR010 used as compare register (b) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 1 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited). Inverts output on match between TM00 and CR010. Disables one-shot pulse output. (c) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. Cautions 1. Values in the following range should be set in CR000 and CR010: 0000H < CR010 < CR000 FFFFH 2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). Remark x: Don't care User's Manual U18172EJ3V0UD 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-31. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Selector fXP fXP/22 fXP/28 Noise eliminator Output controller TI000/ANI0/ TOH1/P20 Clear circuit 16-bit timer counter 00 (TM00) fXP 16-bit timer capture/compare register 010 (CR010) Figure 6-32. PPG Output Operation Timing t Count clock TM00 count value N 0000H 0001H M-1 M Clear CR000 capture value N CR010 capture value M Pulse width: (M + 1) x t 1 cycle: (N + 1) x t 118 N 0000H 0001H Clear TO00 Remark N-1 0000H < M < N FFFFH User's Manual U18172EJ3V0UD TO00/TI010/ANI1/ INTP0/P21 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figures 6-33 and 6-35 for the set value). <3> Set the TOC00 register (see Figures 6-33 and 6-35 for the set value). <4> Set any value to the CR000 and CR010 registers (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figures 6-33 and 6-35 for the set value). Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control register 2 (PMC2). 2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-33, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software. By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000 (CR000)Note. Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00 register, the TMC003 and TMC002 bits of the TMC00 register must be cleared to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Do not set N to M. Cautions 1. Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. User's Manual U18172EJ3V0UD 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-33. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0/1 0/1 0 0 PRM001 PRM010 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0 0/1 0 CR000 as compare register CR010 as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 LVR00 TOC001 TOE00 0/1 0/1 1 1 Enables TO00 output. Inverts output upon match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010. Sets one-shot pulse output mode. Set to 1 for output. (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 0 1 0 OVF00 0 Free-running mode Caution Do not set 0000H to the CR000 and CR010 registers. 120 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-34. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock TM00 count 0000H 0001H N N+1 0000H N-1 N M-1 M M+1 M+2 CR010 set value N N N N CR000 set value M M M M OSPT00 INTTM010 INTTM000 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC003 and TMC002 bits. Remark N<M (2) One-shot pulse output with external trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-35, and by using the valid edge of the TI000 pin as an external trigger. The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES010) of prescaler mode register 00 (PRM00). The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 000 (CR000)Note. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Do not set N to M. Caution Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. User's Manual U18172EJ3V0UD 121 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-35. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0 1 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0 0/1 0 CR000 used as compare register CR010 used as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 LVR00 TOC001 TOE00 0/1 0/1 1 1 Enables TO00 output. Inverts output upon match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010. Sets one-shot pulse output mode. (d) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 0 1 0 Clears and starts at valid edge of TI000 pin. Caution Do not set 0000H to the CR000 and CR010 registers. 122 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-36. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H 0000H N N+1 N+2 M-2 M-1 M M+1 M+2 CR010 set value N N N N CR000 set value M M M M TI000 pin input INTTM010 INTTM000 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. Remark N<M User's Manual U18172EJ3V0UD 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. Figure 6-37. Start Timing of 16-Bit Timer Counter 00 (TM00) Count clock TM00 count value 0000H 0001H 0002H 0003H 0004H Timer start (2) 16-bit timer counter 00 (TM00) operation <1> 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation. <2> Even if TM00 is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <3> When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. <4> If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the TI000/TI010 pins. (3) Setting of 16-bit timer capture/compare registers 000, 010 (CR000, CR010) <1> Set 16-bit timer capture/compare register 000 (CR000) to other than 0000H in the clear & start mode entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be performed when this register is used as an external event counter. <2> When the clear & start mode entered on a match between TM00 and CR000 is selected, CR000 should not be specified as a capture register. <3> In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR0n0 is set to 0000H, an interrupt request (INTTM0n0) is generated when CR0n0 changes from 0000H to 0001H following overflow (FFFFH). <4> If the new value of CR0n0 is less than the value of TM00, TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR0n0 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR0n0 is changed. 124 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) (4) Capture register data retention The values of 16-bit timer capture/compare registers 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped are not guaranteed. Remark n = 0, 1 (5) Setting of 16-bit timer mode control register 00 (TMC00) The timer operation must be stopped before writing to bits other than the OVF00 flag. (6) Setting of capture/compare control register 00 (CRC00) The timer operation must be stopped before setting CRC00. (7) Setting of 16-bit timer output control register 00 (TOC00) <1> Timer operation must be stopped before setting other than OSPT00. <2> If LVS00 and LVR00 are read, 0 is read. <3> OSPT00 is automatically cleared after data is set, so 0 is read. <4> Do not set OSPT00 to 1 other than in one-shot pulse output mode. <5> A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively. (8) Setting of prescaler mode register 00 (PRM00) Always set data to PRM00 after stopping the timer operation. (9) Valid edge setting Set the valid edge of the TI000 pin with bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) after stopping the timer operation. (10) One-shot pulse output One-shot pulse output normally operates only in the free-running mode or in the clear & start mode at the valid edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between TM00 and CR000, one-shot pulse output is not possible. (11) One-shot pulse output by software <1> Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. <2> When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. User's Manual U18172EJ3V0UD 125 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) <3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H. (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. <2> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H. (13) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid edge of the TI000 pin, or free-running mode is selected. CR000 is set to FFFFH. When TM00 is counted up from FFFFH to 0000H. Figure 6-38. Operation Timing of OVF00 Flag Count clock CR000 TM00 FFFFH FFFEH FFFFH 0000H 0001H OVF00 INTTM000 <2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is reset newly and clear is disabled. (14) Conflicting operations If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of the timer and the input of the capture trigger conflict, the captured data is undefined. 126 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) Figure 6-39. Capture Register Data Retention Timing Count clock TM00 count value N N+1 N+2 M M+1 M+2 Edge input INTTM010 Capture read signal CR010 capture value X M+1 N+2 Capture Capture, but read value is not guaranteed (15) Capture operation <1> If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin. <2> When the CRC001 bit value is 1, capture is not performed in the CR000 register if both the rising and falling edges have been selected as the valid edges of the TI000 pin. <3> When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing. <4> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00). <5> The capture operation is performed at the fall of the count clock. A interrupt request input (INTTM0n0), however, occurs at the rise of the next count clock. <6> To use two capture registers, set the TI000 and TI010 pins. Remark n = 0, 1 (16) Compare operation The capture operation may not be performed for CR0n0 set in compare mode even if a capture trigger is input. Remark n = 0, 1 User's Manual U18172EJ3V0UD 127 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) (17) Changing compare register during timer operation <1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer counting, INTTM000 interrupt servicing performs the following operation. <Changing cycle (CR000)> 1. Disable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 0). 2. Disable the INTTM000 interrupt (TMMK000 = 1). 3. Rewrite CR000. 4. Wait for 1 cycle of the TM00 count clock. 5. Enable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 1). 6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0). 7. Enable the INTTM000 interrupt (TMMK000 = 0). <Changing duty (CR010)> 1. Disable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 0). 2. Disable the INTTM000 interrupt (TMMK000 = 1). 3. Rewrite CR010. 4. Wait for 1 cycle of the TM00 count clock. 5. Enable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 1). 6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0). 7. Enable the INTTM000 interrupt (TMMK000 = 0). While interrupts and timer output inversion are disabled (1 to 4 above), timer counting is continued. If the value to be set in CR0n0 is small, the value of TM00 may exceed CR0n0. Therefore, set the value, considering the time lapse of the timer clock and CPU after an INTTM000 interrupt has been generated. Remark n = 0 or 1 <2> If CR010 is changed during timer counting without performing processing <1> above, the value in CR010 may be rewritten twice or more, causing an inversion of the output level of the TO00 pin at each rewrite. 128 User's Manual U18172EJ3V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. (b) If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled after a low level is input to the TI0n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is enabled. (c) When the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled after a high level is input to the TI0n0 pin If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. Remark n = 0, 1 <2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short pulse width. (19) External event counter <1> The timing of the count start is after two valid edge detections. <2> When reading the external event counter count value, TM00 should be read. (20) PPG output <1> Values in the following range should be set in CR000 and CR010: 0000H < CR010 < CR000 FFFFH <2> The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). (21) STOP mode or system clock stop mode setting Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. (22) P21/TI010/TO00 pin When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00). When using P21 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. User's Manual U18172EJ3V0UD 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (PD78F920x ONLY) (23) External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the AC characteristics, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. <2> When an external waveform is input to 16-bit timer/event counter 00, it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device. Count clock (fsam) TI000 Sampling time on filter Input pulse through noise limiter circuit Remark The count clock (fsam) can be selected using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). 130 User's Manual U18172EJ3V0UD CHAPTER 7 8-BIT TIMER H1 7.1 Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. * Interval timer * PWM output mode * Square-wave output 7.2 Configuration of 8-Bit Timer H1 8-bit timer H1 consists of the following hardware. Table 7-1. Configuration of 8-Bit Timer H1 Item Configuration Timer register 8-bit timer counter H1 Registers 8-bit timer H compare register 01 (CMP01) 8-bit timer H compare register 11 (CMP11) Timer output TOH1 Control registers 8-bit timer H mode register 1 (TMHMD1) Port mode register 2 (PM2) Port register 2 (P2) <R> Port mode control register 2 (PMC2) (PD78F920x only) Figure 7-1 shows a block diagram. User's Manual U18172EJ3V0UD 131 132 Figure 7-1. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 8-bit timer H compare register 11 (CMP11) 8-bit timer H compare register 01 (CMP01) 2 TOH1/TI000Note/ ANI0Note/P20 Decoder Selector Selector fXP fXP/22 fXP/24 fXP/26 fXP/212 fRL/27 Interrupt generator F/F R Output controller Level inversion Output latch (P20) 8-bit timer counter H1 Clear PWM mode signal Timer H enable signal 1 0 INTTMH1 <R> Note PD78F920x only PM20 CHAPTER 7 8-BIT TIMER H1 User's Manual U18172EJ3V0UD Match CHAPTER 7 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-2. Format of 8-Bit Timer H Compare Register 01 (CMP01) Address: FF0EH Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 CMP01 Caution CMP01 cannot be rewritten during timer count operation. (2) 8-bit timer H compare register 11 (CMP11) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-3. Format of 8-Bit Timer H Compare Register 11 (CMP11) Address: FF0FH Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 CMP11 CMP11 can be rewritten during timer count operation. If the CMP11 value is rewritten during timer operation, the compare value after the rewrite takes effect at the timing at which the count value and the compare value before the rewrite match. If the timing at which the count value and compare value match conflicts with the timing of the writing from the CPU to CMP11, the compare value after the rewrite takes effect at the timing at which the next count value and the compare value before the rewrite match. Caution In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). User's Manual U18172EJ3V0UD 133 CHAPTER 7 8-BIT TIMER H1 7.3 Registers Controlling 8-Bit Timer H1 The following four registers are used to control 8-Bit Timer H1. * 8-bit timer H mode register 1 (TMHMD1) * Port mode register 2 (PM2) * Port register 2 (P2) <R> * Port mode control register 2 (PMC2) (PD78F920x only) (1) 8-bit timer H mode register 1 (TMHMD1) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. 134 User's Manual U18172EJ3V0UD CHAPTER 7 8-BIT TIMER H1 Figure 7-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF70H Symbol TMHMD1 After reset: 00H R/W <7> 6 5 4 TMHE1 CKS12 CKS11 CKS10 TMHE1 3 2 <0> <1> TMMD11 TMMD10 TOLEV1 TOEN1 Timer operation enable 0 Stop timer count operation (counter is cleared to 0) 1 Enable timer count operation (count operation started by inputting clock) CKS12 CKS11 CKS10 0 0 0 0 0 1 0 1 0 0 1 1 fXP/26 1 0 0 1 0 1 Other than above Count clock (fCNT) selection (10 MHz) fXP fXP/2 2 (2.5 MHz) fXP/2 4 (625 kHz) (2.44 kHz) 7 (1.88 kHz (TYP.)) fXP/2 fRL/2 Setting prohibited TMMD11 TMMD10 Timer operation mode 0 0 Interval timer mode 1 0 PWM output mode Other than above TOLEV1 (156.25 kHz) 12 Setting prohibited Timer output level control (in default mode) 0 Low level 1 High level TOEN1 Timer output control 0 Disable output 1 Enable output Cautions 1. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. 2. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware 2. fRL: Low-speed internal oscillation clock oscillation frequency 3. Figures in parentheses apply to operation at fXP = 10 MHz, fRL = 240 kHz (TYP.). User's Manual U18172EJ3V0UD 135 CHAPTER 7 8-BIT TIMER H1 Note <R> (2) Port mode register 2 (PM2) and port mode control register 2 (PMC2) When using the P20/TOH1/TI000/ANI0 pin for timer output, clear PM20, the output latch of P20, and PMC20 to 0. PM2 and PMC2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM2 to FFH, and clears PMC2 to 00H. Note PD78F920x only Figure 7-5. Format of Port Mode Register 2 (PM2) Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 PM2n P2n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Figure 7-6. Format of Port Mode Control Register 2 (PMC2) (PD78F920x Only) Address: FF84H After reset: 00H Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n 7.4 7.4.1 R/W Specification of operation mode (n = 0 to 3) 0 Port/Alternate-function (except A/D converter) mode 1 A/D converter mode Operation of 8-Bit Timer H1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode. Since a match of 8-bit timer counter H1 and the CMP11 register is not detected even if the CMP11 register is set, timer output is not affected. By setting bit 0 (TOEN1) of timer H mode register 1 (TMHMD1) to 1, a square wave of any frequency (duty = 50%) is output from TOH1. 136 User's Manual U18172EJ3V0UD CHAPTER 7 8-BIT TIMER H1 (1) Usage Generates the INTTMH1 signal repeatedly at the same interval. <1> Set each register. Figure 7-7. Register Setting During Interval Timer/Square-Wave Output Operation (i) TMHMD1 Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 0 0 0/1 TOEN1 0/1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (N) <2> Count operation starts when TMHE1 = 1. <3> When the values of 8-bit timer counter H1 and the CMP01 register match, the INTTMH1 signal is generated and 8-bit timer counter H1 is cleared to 00H. Interval time = (N +1)/fCNT <4> Subsequently, the INTTMH1 signal is generated at the same interval. To stop the count operation, clear TMHE1 to 0. (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. User's Manual U18172EJ3V0UD 137 CHAPTER 7 8-BIT TIMER H1 Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H CMP01 FEH) Count clock Count start 8-bit timer counter H1 00H 01H N 00H 01H N Clear 00H 01H 00H Clear N CMP01 TMHE1 INTTMH1 Interval time TOH1 <2> Level inversion, match interrupt occurrence, 8-bit timer counter H1 clear <1> <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter H1 clear <1> The count operation is enabled by setting the TMHE1 bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1 is cleared, the TOH1 output level is inverted, and the INTTMH1 signal is output. <3> The INTTMH1 signal and TOH1 output become inactive by clearing the TMHE1 bit to 0 during timer H1 operation. If these are inactive from the first, the level is retained. Remark 138 01H N FEH User's Manual U18172EJ3V0UD CHAPTER 7 8-BIT TIMER H1 Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 00H 01H FEH FFH 00H FEH Clear FFH 00H Clear FFH CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1 00H CMP01 00H TMHE1 INTTMH1 TOH1 Interval time User's Manual U18172EJ3V0UD 139 CHAPTER 7 8-BIT TIMER H1 7.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited. 8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register during timer operation is possible. The operation in PWM output mode is as follows. TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1 and the CMP11 register match. (1) Usage In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 7-9. Register Setting in PWM Output Mode (i) TMHMD1 Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 1 0 0/1 TOEN1 1 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP01 register * Compare value (N): Cycle setting (iii) Setting CMP11 register * Compare value (M): Duty setting Remark 00H CMP11 (M) < CMP01 (N) FFH <2> The count operation starts when TMHE1 = 1. <3> The CMP01 register is the compare register that is to be compared first after count operation is enabled. When the values of 8-bit timer counter H1 and the CMP01 register match, 8-bit timer counter H1 is cleared, an interrupt request signal (INTTMH1) is generated, and TOH1 output becomes active. At the same time, the compare register to be compared with 8-bit timer counter H1 is changed from the CMP01 register to the CMP11 register. 140 User's Manual U18172EJ3V0UD CHAPTER 7 8-BIT TIMER H1 <4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N+1)/fCNT Duty = Active width : Total width of PWM = (M + 1) : (N + 1) Cautions 1. In PWM output mode, the setting value for the CMP11 register can be changed during timer count operation. However, three operation clocks (signal selected using the CKS12 to CKS10 bits of the TMHMD1 register) or more are required to transfer the register value after rewriting the CMP11 register value. 2. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. 00H CMP11 (M) < CMP01 (N) FFH User's Manual U18172EJ3V0UD 141 CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (1/4) (a) Basic operation (00H < CMP11 < CMP01 < FFH) Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H CMP01 A5H CMP11 01H A5H 00H 01H 02H A5H 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <2> <3> <4> TOH1 (TOLEV1 = 1) <1> The count operation is enabled by setting the TMHE1 bit to 1. Start 8-bit timer counter H1 by masking one count clock to count up. At this time, TOH1 output remains inactive (when TOLEV1 = 0). <2> When the values of 8-bit timer counter H1 and the CMP01 register match, the TOH1 output level is inverted, the value of 8-bit timer counter H1 is cleared, and the INTTMH1 signal is output. <3> When the values of 8-bit timer counter H1 and the CMP11 register match, the level of the TOH1 output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMH1 signal is not output. <4> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive. 142 User's Manual U18172EJ3V0UD CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H CMP01 FFH CMP11 00H FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, CMP11 = FEH Count clock 8-bit timer counter H1 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H CMP01 FFH CMP11 FEH FEH FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) User's Manual U18172EJ3V0UD 143 CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP01 01H CMP11 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) 144 User's Manual U18172EJ3V0UD CHAPTER 7 8-BIT TIMER H1 Figure 7-10. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H 03H, CMP01 = A5H) Count clock 8-bit timer counter H1 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 02H (03H) 02H CMP11 <2> 03H <2>' TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count clock to count up. At this time, the TOH1 output remains inactive (when TOLEV1 = 0). <2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1 is cleared, the TOH1 output becomes active, and the INTTMH1 signal is output. <4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter H1 and the CMP11 register before the change match, the value is transferred to the CMP11 register and the CMP11 register value is changed (<2>'). However, three count clocks or more are required from when the CMP11 register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter H1 and the CMP11 register after the change match, the TOH1 output becomes inactive. 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated. <6> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive. User's Manual U18172EJ3V0UD 145 CHAPTER 8 WATCHDOG TIMER 8.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 12 RESET FUNCTION. Table 8-1. Loop Detection Time of Watchdog Timer Loop Detection Time During Low-Speed Internal oscillation Clock Operation During System Clock Operation 11 2 /fX (819.2 s) 12 2 /fX (1.64 ms) 13 2 /fX (3.28 ms) 14 2 /fX (6.55 ms) 15 2 /fX (13.11 ms) 16 2 /fX (26.21 ms) 17 2 /fX (52.43 ms) 18 2 /fX (104.86 ms) 13 2 /fRL (4.27 ms) 14 2 /fRL (8.53 ms) 15 2 /fRL (17.07 ms) 16 2 /fRL (34.13 ms) 17 2 /fRL (68.27 ms) 18 2 /fRL (136.53 ms) 19 2 /fRL (273.07 ms) 20 2 /fRL (546.13 ms) Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: System clock oscillation frequency 3. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz. The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip low-speed internal oscillator as shown in Table 8-2. 146 User's Manual U18172EJ3V0UD CHAPTER 8 WATCHDOG TIMER Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software Watchdog timer clock * Selectable by software (fX, fRL or stopped) Note 1 Fixed to fRL . * When reset is released: fRL source Operation after reset 18 Operation starts with the maximum interval (2 /fRL). Operation starts with the maximum interval 18 (2 /fRL). Operation mode The interval can be changed only once. selection The clock selection/interval can be changed only once. Features The watchdog timer cannot be stopped. The watchdog timer can be stopped Note 2 . Notes 1. As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset period). 2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> If the clock source is fX, clock supply to the watchdog timer is stopped under the following conditions. * When fX is stopped * In HALT/STOP mode * During oscillation stabilization time <2> If the clock source is fRL, clock supply to the watchdog timer is stopped under the following conditions. * If the CPU clock is fX and if fRL is stopped by software before execution of the STOP instruction * In HALT/STOP mode Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: System clock oscillation frequency User's Manual U18172EJ3V0UD 147 CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 8-1. Block Diagram of Watchdog Timer fRL/22 fX/2 4 211/fRL to 218/fRL Clock input controller 16-bit counter 2 Watchdog timer enable register (WDTE) Selector or 213/fX to 220/fX 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Watchdog timer mode register (WDTM) Internal bus Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: System clock oscillation frequency 148 Internal reset signal 3 Clear 0 Output controller User's Manual U18172EJ3V0UD Option byte (to set "low-speed internal oscillator cannot be stopped" or "low-speed internal oscillator can be stopped by software") CHAPTER 8 WATCHDOG TIMER 8.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. * Watchdog timer mode register (WDTM) * Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. Reset signal generation sets this register to 67H. Figure 8-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF48H After reset: 67H R/W Symbol 7 6 5 4 3 2 1 0 WDTM 0 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 WDCS4 Note 1 WDCS3 Note 1 Operation clock selection 0 0 Low-speed internal oscillation clock (fRL) 0 1 System Clock (fX) 1 x Watchdog timer operation stopped WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 Overflow time setting During low-speed internal During system clock operation oscillation clock operation 11 2 /fX (819.2 s) 12 2 /fX (1.64 ms) 13 2 /fX (3.28 ms) 14 2 /fX (6.55 ms) 15 2 /fX (13.11 ms) 16 2 /fX (26.21 ms) 17 2 /fX (52.43 ms) 18 2 /fX (104.86 ms) 0 0 0 2 /fRL (4.27 ms) 0 0 1 2 /fRL (8.53 ms) 0 1 0 2 /fRL (17.07 ms) 0 1 1 2 /fRL (34.13 ms) 1 0 0 2 /fRL (68.27 ms) 1 0 1 2 /fRL (136.53 ms) 1 1 0 2 /fRL (273.07 ms) 1 1 1 2 /fRL (546.13 ms) Notes 1. 13 14 15 16 17 18 19 20 If "low-speed internal oscillator cannot be stopped" is specified by the option byte, this cannot be set. The low-speed internal oscillation clock will be selected no matter what value is written. 2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1). Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. User's Manual U18172EJ3V0UD 149 CHAPTER 8 WATCHDOG TIMER Cautions 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if "1" and "x" are set for WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed. * Second write to WDTM * 1-bit memory manipulation instruction to WDTE * Writing of a value other than "ACH" to WDTE 3. WDTM cannot be set by a 1-bit memory manipulation instruction. 4. When using the flash memory programming by self programming, set the overflow time for the watchdog timer so that enough overflow time is secured (Example 1byte writing: 200 s MIN., 1-block deletion: 10 ms MIN.). Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency 2. fX: System clock oscillation frequency 3. x: Don't care 4. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz. (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH. Figure 8-3. Format of Watchdog Timer Enable Register (WDTE) Address: FF49H Symbol 7 After reset: 9AH 6 R/W 5 4 3 2 1 0 WDTE Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. 3. The value read from WDTE is 9AH (this differs from the written value (ACH)). 150 User's Manual U18172EJ3V0UD CHAPTER 8 WATCHDOG TIMER 8.4 8.4.1 Operation of Watchdog Timer Watchdog timer operation when "low-speed internal oscillator cannot be stopped" is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Low-speed internal oscillation clock * Cycle: 218/fRL (546.13 ms: At operation with fRL = 480 kHz (MAX.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2. * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. The operation clock (low-speed internal oscillation clock) cannot be changed. If any value is written to bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored. 2. As soon as WDTM is written, the counter of the watchdog timer is cleared. Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-speed internal oscillation clock can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. A status transition diagram is shown below User's Manual U18172EJ3V0UD 151 CHAPTER 8 WATCHDOG TIMER Figure 8-4. Status Transition Diagram When "Low-Speed Internal Oscillator Cannot Be Stopped" Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 546.13 ms (MAX.) WDTE = "ACH" Clear WDT counter. WDT clock is fixed to fRL. Select overflow time (settable only once). WDT clock: fRL Overflow time: 4.27 ms to 546.13 ms (MAX.) WDT count continues. HALT instruction STOP instruction Interrupt HALT WDT count continues. 152 Interrupt STOP WDT count continues. User's Manual U18172EJ3V0UD CHAPTER 8 WATCHDOG TIMER 8.4.2 Watchdog timer operation when "low-speed internal oscillator can be stopped by software" is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or system clock. After reset is released, operation is started at the maximum cycle of the low-speed internal oscillation clock (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Low-speed internal oscillation clock * Cycle: 218/fRL (546.13 ms: At operation with fRL = 480 kHz (MAX.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2, 3. * Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4). Low-speed internal oscillation clock (fRL) Syatem clock (fX) Watchdog timer operation stopped * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared. 2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values. 3. At the first write, If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x, respectively, an internal reset signal is not generated even if the following processing is performed. * WDTM is written a second time. * A 1-bit memory manipulation instruction is executed to WDTE. * A value other than ACH is written to WDTE. Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. For the watchdog timer operation during STOP mode and HALT mode in each status, see 8.4.3 Watchdog timer operation in STOP mode and 8.4.4 Watchdog timer operation in HALT mode. A status transition diagram is shown below. User's Manual U18172EJ3V0UD 153 CHAPTER 8 WATCHDOG TIMER Figure 8-5. Status Transition Diagram When "Low-Speed Internal Oscillator Can Be Stopped by Software" Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 546.13 ms (MAX.) WDCS4 = 1 WDT clock = fX Select overflow time (settable only once). WDTE = "ACH" Clear WDT counter. WDT clock = fRL Select overflow time (settable only once). WDT operation stops. WDTE = "ACH" Clear WDT counter. WDTE = "ACH" Clear WDT counter. LSRSTOP = 1 WDT clock: fRL Overflow time: 4.27 ms to 546.13 ms (MAX.) LSRSTOP = 0 WDT count continues. WDT clock: fX Overflow time: 213/fX to 220/fX WDT count continues. WDT clock: fRL WDT count stops. HALT instruction HALT instruction Interrupt STOP instruction Interrupt STOP instruction HALT instruction Interrupt STOP instruction Interrupt Interrupt HALT WDT count stops. 154 STOP WDT count stops. HALT WDT count stops. User's Manual U18172EJ3V0UD STOP WDT count stops. Interrupt CHAPTER 8 WATCHDOG TIMER 8.4.3 Watchdog timer operation in STOP mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation clock is being used. (1) When the watchdog timer operation clock is the system clock (fX) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 34 s (TYP.) (after waiting for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 8-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware) <1> CPU clock: Crystal/ceramic oscillation clock (PD78F920x Only) <R> Normal CPU operation operation STOP Operation stoppedNote Normal operation Oscillation stabilization time fCPU Oscillation stopped Watchdog timer Oscillation stabilization time (set by OSTS register) Operation stopped Operating Operating <2> CPU clock: High-speed internal oscillation clock or external clock input CPU operation Normal operation STOP Operation stoppedNote Normal operation fCPU Oscillation stopped Watchdog timer Operating Operation stopped Operating Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). User's Manual U18172EJ3V0UD 155 CHAPTER 8 WATCHDOG TIMER (2) When the watchdog timer operation clock is the low-speed internal oscillation clock (fRL) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 34 s (TYP.) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 8-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Internal Oscillation Clock) <1> CPU clock: Crystal/ceramic oscillation clock (PD78F920x Only) <R> Normal CPU operation operation STOP Operation stoppedNote Oscillation stabilization time Normal operation fCPU Oscillation stopped Oscillation stabilization time (set by OSTS register) fRL Watchdog timer Operating Operating Operation stopped <2> CPU clock: High-speed internal oscillation clock or external clock input CPU operation Normal operation STOP Operation stoppedNote Normal operation fCPU Oscillation stopped fRL Watchdog timer Operating Operating Operation stopped Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). 8.4.4 Watchdog timer operation in HALT mode (when "low-speed internal oscillator can be stopped by software" is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer is the system clock (fX) or low-speed internal oscillation clock (fRL). After HALT mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 8-8. Operation in HALT Mode CPU operation Normal operation HALT Normal operation fCPU fX or fRL Watchdog timer Operating Operation stopped 156 User's Manual U18172EJ3V0UD Operating CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) <R> 9.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. * 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Figure 9-1 shows the timing of sampling and A/D conversion, and Table 9-1 shows the sampling time and A/D conversion time. Figure 9-1. Timing of A/D Converter Sampling and A/D Conversion ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Note Sampling time Sampling time Conversion time Conversion time Note 2 or 3 clocks are required from the ADCS rising to sampling start. User's Manual U18172EJ3V0UD 157 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) Table 9-1. Sampling Time and A/D Conversion Time Reference Sampling Note 2 Voltage Time fXP = 8 MHz Conversion fXP = 10 MHz FR2 FR1 FR0 Note 3 Time RangeNote 1 Sampling Time Note 2 Conversion Sampling Note 3 Time Time Note 2 Conversion TimeNote 3 VDD 4.5 V 12/fXP 36/fXP 1.5 s 4.5 s 1.2 s 3.6 s 0 0 0 VDD 4.0 V 24/fXP 72/fXP 3.0 s 9.0 s 2.4 s 7.2 s 1 0 0 VDD 2.85 V 96/fXP 144/fXP 12.0 s 18.0 s 9.6 s 14.4 s 1 1 0 48/fXP 96/fXP 6.0 s 12.0 s 4.8 s 9.6 s 1 0 1 48/fXP 72/fXP 6.0 s 9.0 s 4.8 s 7.2 s 0 1 0 24/fXP 48/fXP 3.0 s 6.0 s 0 0 1 1 1 1 0 1 1 VDD 2.7 V Setting Setting prohibitedNote 4 prohibitedNote 4 (2.4 s) (4.8 s) 176/fXP 224/fXP 22.0 s 28.0 s 17.6 s 22.4 s 88/fXP 112/fXP 11.0 s 14.0 s Setting prohibited (8.8 s) Notes 1. Setting Note 4 prohibited Note 4 (11.2 s) Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3 below are satisfied. Example When VDD 2.7 V, fXP = 8 MHz * The sampling time is 11.0 s or more and the A/D conversion time is 14.0 s or more and 100 s or less. * Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1. 2. 3. Set the sampling time as follows. * VDD 4.5 V: 1.0 s or more * VDD 4.0 V: 2.4 s or more * VDD 2.85 V: 3.0 s or more * VDD 2.7 V: 11.0 s or more Set the A/D conversion time as follows. * VDD 4.5 V: 4. 3.0 s or more and less than 100 s * VDD 4.0 V: 4.8 s or more and less than 100 s * VDD 2.85 V: 6.0 s or more and less than 100 s * VDD 2.7 V: 14.0 s or more and less than 100 s Setting is prohibited because the values do not satisfy the condition of Notes 2 or 3. Caution The above sampling time and conversion time do not include the clock frequency error. Select the sampling time and conversion time such that Notes 2 and 3 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). Remarks 1. 2. fXP: Oscillation frequency of clock to peripheral hardware The conversion time refers to the total of the sampling time and the time from successively comparing with the sampling value until the conversion result is output. 158 User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) Figure 9-2 shows the block diagram of A/D converter. Figure 9-2. Block Diagram of A/D Converter ANI0/P20/TI000 TOH1 ANI1/P21/TI010/ TO00/INTP0 Selector Sample & hold circuit ANI2/X2/P22 Voltage comparator VDD D/A converter VSS VSS ANI3/X1/P23 Successive approximation register (SAR) Controller 2 ADS1 ADS0 A/D conversion result register (ADCR, ADCRH) 3 ADCS FR2 FR1 Analog input channel specification register (ADS) INTAD FR0 ADCE A/D converter mode register (ADM) Internal bus Cautions 1. In PD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 2. In PD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). 9.2 Configuration of A/D Converter The A/D converter consists of the following hardware. (1) ANI0 to ANI3 pins These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification register (ADS) can be used as I/O port pins. (2) Sample & hold circuit The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion. (3) D/A converter The D/A converter is connected between VDD and VSS, and generates a voltage to be compared with the analog input signal. (4) Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the D/A converter. User's Manual U18172EJ3V0UD 159 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). (6) 10-bit A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its lower 10 bits (the higher 6 bits are fixed to 0). (7) 8-bit A/D conversion result register (ADCRH) The result of A/D conversion is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register holds the result of A/D conversion in its higher 8 bits. (8) Controller When A/D conversion has been completed, INTAD is generated. (9) VDD pin This is the positive power supply pin. In the 78K0S/KU1+, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). (10) VSS pin This is the ground potential pin. In the 78K0S/KU1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). (11) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (13) Port mode control register 2 (PMC2) This register is used when the P20/ANI0/TI000/TOH1, P21/ANI1/TI010/TO00/INTP0, P22/ANI2, and P23/ANI3 pins are used as the analog input pins of the A/D converter. 160 User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) 9.3 Registers Used by A/D Converter The A/D converter uses the following six registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) * Port mode register 2 (PM2) * Port mode control register 2 (PMC2) (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. User's Manual U18172EJ3V0UD 161 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) Figure 9-3. Format of A/D Converter Mode Register (ADM) Address: FF80H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> ADM ADCS 0 FR2 FR1 FR0 0 0 ADCE ADCS 0 1 A/D conversion operation control Stops conversion operation Note 1 FR2 Starts conversion operation FR1 FR0 Reference Voltage Note 2 Range Sampling Note 3 Time Conversion Note 4 Time fXP = 8 MHz fXP = 10 MHz Sampling Note 3 Time Conversion Note 4 Time Sampling Note 3 Time Conversion Note 4 Time 0 0 0 VDD 4.5 V 12/fXP 36/fXP 1.5 s 4.5 s 1.2 s 3.6 s 1 0 0 VDD 4.0 V 24/fXP 72/fXP 3.0 s 9.0 s 2.4 s 7.2 s 1 1 0 96/fXP 144/fXP 12.0 s 18.0 s 9.6 s 14.4 s 1 0 1 VDD 2.85 V 48/fXP 96/fXP 6.0 s 12.0 s 4.8 s 9.6 s 0 1 0 48/fXP 72/fXP 6.0 s 9.0 s 4.8 s 7.2 s 0 0 1 24/fXP 48/fXP 3.0 s 6.0 s Setting prohibited Setting prohibited Note 5 Note 5 (2.4 s) (4.8 s) 1 1 1 0 1 1 VDD 2.7 V 176/fXP 224/fXP 22.0 s 28.0 s 17.6 s 22.4 s 88/fXP 112/fXP 11.0 s 14.0 s Setting prohibited Setting prohibited Note 5 Note 5 (8.8 s) (11.2 s) ADCE 0 Note 1 1 Comparator operation control Note 6 Stops operation of comparator Enables operation of comparator Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware 2. The conversion time refers to the total of the sampling time and the time from successively comparing with the sampling value until the conversion result is output. Notes 1. Even when the ADCE = 0 (comparator operation stopped), the A/D conversion operation starts if the ADCS is set to 1. However, the data of the first conversion is out of the guaranteed-value range, so ignore it. 2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3 below are satisfied. Example When VDD 2.7 V, fXP = 8 MHz * The sampling time is 11.0 s or more and the A/D conversion time is 14.0 s or more and 100 s or less. * Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1. 162 User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) Notes 3. Set the sampling time as follows. 1.0 s or more * VDD 4.5 V: * VDD 4.0 V: 2.4 s or more * VDD 2.85 V: 3.0 s or more * VDD 2.7 V: 11.0 s or more 4. Set the A/D conversion time as follows. * VDD 4.5 V: 3.0 s or more and less than 100 s * VDD 4.0 V: 4.8 s or more and less than 100 s * VDD 2.85 V: 6.0 s or more and less than 100 s * VDD 2.7 V: 14.0 s or more and less than 100 s 5. Setting is prohibited because the values do not satisfy the condition of Notes 3 or 4. 6. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. If the ADCS is set to 1 without waiting for 1 s or longer, ignore the first conversion data. Table 9-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation 0 0 Stop status (DC power consumption path does not exist) 0 1 Conversion waiting mode (only comparator consumes power) 1 x Conversion mode Figure 9-4. Timing Chart When Comparator Is Used Comparator operating ADCE Comparator Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 s or longer to stabilize the internal circuit. Cautions 1. The above sampling time and conversion time do not include the clock frequency error. Select the sampling time and conversion time such that Notes 3 and 4 above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). 2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ADCS to 1. 3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2. 4. Be sure to clear bits 6, 2, and 1 to 0. User's Manual U18172EJ3V0UD 163 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-5. Format of Analog Input Channel Specification Register (ADS) Address: FF81H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS 0 0 0 0 0 0 ADS1 ADS0 ADS1 ADS0 0 0 ANI0 0 1 ANI1 1 0 ANI2 1 1 ANI3 Analog input channel specification Caution Be sure to clear bits 2 to 7 of ADS to 0. (3) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result, and FF18H indicates the lower 8 bits of the conversion result. ADCR can be read by a 16-bit memory manipulation instruction. Reset signal generation makes ADCR undefined. Figure 9-6. Format of 10-Bit A/D Conversion Result Register (ADCR) Address: FF18H, FF19H R FF19H Symbol ADCR After reset: Undefined 0 0 0 0 0 FF18H 0 Caution When writing to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using timing other than the above may cause an incorrect conversion result to be read. 164 User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation makes ADCRH undefined. Figure 9-7. Format of 8-Bit A/D Conversion Result Register (ADCRH) Address: FF1AH Symbol After reset: Undefined 7 6 R 5 4 3 2 1 0 ADCRH (5) Port mode register 2 (PM2) and port mode control register 2 (PMC2) When using the when the P20/ANI0/TI000/TOH1, P21/ANI1/TI010/TO00/INTP0, P22/ANI2, and P23/ANI3 pins for analog input, set PM20 to PM23 and PMC20 to PMC23 to 1. At this time, the output latches of P20 to P23 may be 0 or 1. PM2 and PMC2 are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM2 to 00H and clears PMC2 to FFH. Figure 9-8. Format of Port Mode Register 2 (PM2) Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 PM2n Pmn pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Figure 9-9. Format of Port Mode Control Register 2 (PMC2) Address: FF84H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Operation mode specification (n = 0 to 3) 0 Port/Alternate-function (except A/D converter) mode 1 A/D converter mode Caution If PMC20 to PMC23 are set to 1, the P20/ANI0/TI000/TOH1, P21/ANI1/TIO10/TO00/INTP0, P22/ANI2, and P23/ANI3 pins cannot be used for any purpose other than the A/D converter function. Be sure to set 0 to the Pull-up resistor option register of the pin set in A/D converter mode. User's Manual U18172EJ3V0UD 165 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) 9.4 9.4.1 A/D Converter Operations Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). <2> Set ADCE to 1 and wait for 1 s or longer. <3> Execute two NOP instructions or an instruction equivalent to two machine cycles. <4> Set ADCS to 1 and start the conversion operation. (<5> to <11> are operations performed by hardware.) <5> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <6> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation has ended. <7> Bit 9 of the successive approximation register (SAR) is set. The D/A converter voltage tap is set to (1/2) VDD by the tap selector. <8> The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVDD, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) VDD, the MSB is reset to 0. <9> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A converter voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) VDD * Bit 9 = 0: (1/4) VDD The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <10> Comparison is continued in this way up to bit 0 of SAR. <11> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <12> Repeat steps <5> to <11>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the status of ADCE = 0, start from <2>. Cautions 1. 2. Remark 166 Make sure the period of <1> to <4> is 1 s or more. It is no problem if the order of <1> and <2> is reversed. The following two types of A/D conversion result registers can be used. * ADCR (16 bits): Stores a 10-bit A/D conversion value. * ADCRH (8 bits): Stores an 8-bit A/D conversion value. User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) Figure 9-10. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined ADCR, ADCRH Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to ADM or the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation makes the A/D conversion result register (ADCR, ADCRH) undefined. User's Manual U18172EJ3V0UD 167 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) 9.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( VAIN VDD x 1024 + 0.5) or (ADCR - 0.5) x where, INT( ): VDD 1024 VAIN < (ADCR + 0.5) x VDD 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage VDD: VDD pin voltage ADCR: 10-bit A/D conversion result register (ADCR) value Figure 9-11 shows the relationship between the analog input voltage and the A/D conversion result. Figure 9-11. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 03FFH 1022 03FEH 1021 03FDH 3 0003H 2 0002H 1 0001H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/VDD 168 User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) 9.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The A/D conversion operations are repeated until new data is written to ADS. If ADM or ADS is written during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the conversion result is undefined. Figure 9-12. A/D Conversion Operation Rewriting ADM ADCS = 1 A/D conversion ANIn Rewriting ADS ANIn ANIn ADCS = 0 ANIm ANIm Conversion is stopped Conversion result is not retained ADCR, ADCRH ANIn ANIn Stopped ANIm INTAD Remarks 1. n = 0 to 3 2. m = 0 to 3 User's Manual U18172EJ3V0UD 169 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Execute two NOP instructions or an instruction equivalent to two machine cycles. <4> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion. <5> An interrupt request signal (INTAD) is generated. <6> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Change the channel> <7> Change the channel using bits 1 and 0 (ADS1, ADS0) of ADS to start A/D conversion. <8> An interrupt request signal (INTAD) is generated. <9> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Complete A/D conversion> <10> Clear ADCS to 0. <11> Clear ADCE to 0. Cautions 1. Make sure the period of <1> to <4> is 1 s or more. 2. It is no problem if the order of <1> and <2> is reversed. 3. <1> can be omitted. However, ignore the data resulting from the first conversion after <4> in this case. 4. The period from <5> to <8> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set using FR2 to FR0. 170 User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) 9.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 9-13. Overall Error Figure 9-14. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 VDD 0 0......0 Analog input 0 Analog input VDD (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. User's Manual U18172EJ3V0UD 171 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 9-15. Zero-Scale Error Figure 9-16. Full-Scale Error Full-scale error Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 Ideal line 011 010 001 Zero-scale error 000 111 110 101 Ideal line 000 0 1 2 3 VDD VDD-3 0 Analog input (LSB) VDD-2 VDD-1 VDD Analog input (LSB) Figure 9-17. Integral Linearity Error Figure 9-18. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Differential linearity error Integral linearity error 0......0 0 0......0 0 VDD Analog input Analog input VDD (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time 172 Conversion time User's Manual U18172EJ3V0UD CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) 9.6 Cautions for A/D Converter (1) Supply current in STOP mode To satisfy the DC characteristics of supply current in STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before executing the STOP instruction. (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of VDD or higher and VSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR, ADCRH. <2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the VDD pin and ANI0 to ANI3 pins. <1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply. <2> Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 9-19, to reduce noise. <3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their alternate functions during conversion. <4> The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts. Figure 9-19. Analog Input Pin Connection If there is a possibility that noise equal to or higher than VDD or equal to or lower than VSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input VDD ANI0 to ANI3 C = 0.01 to 0.1 F VSS User's Manual U18172EJ3V0UD 173 CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access P20 to P23 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI3 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed during sampling time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates both during sampling and otherwise. If the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended to make the output impedance of the analog input source 1 k or lower, or attach a capacitor of around 0.01 F to 0.1 F to the ANI0 to ANI3 pins (see Figure 9-19). When writing the flash memory on-board, supply a stabilized analog voltage to the ANI2 and ANI3 pins, without attaching a capacitor. Because the communication pulse may change and the communication may fail if a capacitor is attached to remove noise. (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 9-20. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ADCR, ADCRH ANIn ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ADIF Remarks 1. n = 0 to 3 2. m = 0 to 3 174 User's Manual U18172EJ3V0UD ANIm ANIm ANIm CHAPTER 9 A/D CONVERTER (PD78F920x ONLY) (8) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (9) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. (10) The operating current at the conversion waiting mode The DC characteristic of the operating current at the STOP mode is not satisfied at the conversion waiting mode (when A/D converter mode register (ADM) is set up with bit 7(ADCS) =0 and bit 0 (ADCE) =1) (only comparator consumes power). (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 9-21. Internal Equivalent Circuit of ANIn Pin ROUT RIN ANIn COUT CIN LSI internal Table 9-3. Resistance and Capacitance Values (Reference Values) of Equivalent Circuit VDD ROUT RIN COUT CIN 4.5 V VDD 5.5 V 1 k 3 k 8 pF 15 pF 2.7 V VDD < 4.5 V 1 k 60 k 8 pF 15 pF Remarks 1. The resistance and capacitance values shown in Table 9-3 are not guaranteed values. 2. n = 0 to 3 3. ROUT: Allowable signal source impedance RIN: Analog input equivalent resistance COUT: Internal pin capacitance CIN: Analog Input equivalent capacitance User's Manual U18172EJ3V0UD 175 CHAPTER 10 INTERRUPT FUNCTIONS 10.1 Interrupt Function Types There are two types of interrupts: maskable interrupts and resets. * Maskable interrupts These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs, and if an interrupt can be acknowledged then the program corresponding to the address written in the vector table address is executed (vector interrupt servicing). When several interrupt requests are generated at the same time, processing takes place in the priority order of the vector interrupt servicing. For details on the priority order, see Table 10-1. There are internal sources and external sources of maskable interrupts. * PD78F920x: external sources: 2, internal sources: 5 * PD78F950x: external sources: 2, internal sources: 2 <R> * Reset The CPU and SFR are returned to their initial states by the reset signal. The causes for reset signal occurrences are shown in Table 10-1. When a reset signal occurs, program execution starts from the programs at the addresses written in addresses 0000H and 0001H. 10.2 Interrupt Sources and Configuration <R> There are a total of seven maskable interrupt sources in PD78F920x, and four maskable interrupt sources in PD78F950x, and up to four reset sources (see Table 10-1). 176 User's Manual U18172EJ3V0UD CHAPTER 10 INTERRUPT FUNCTIONS Table 10-1. Interrupt Sources Interrupt Type Note 1 Priority Interrupt Source Name Maskable Trigger Note 4 Internal/ Vector Table Basic External Address Configuration Note 2 Type 1 INTLVI Low-voltage detection Internal 0006H (A) 2 INTP0 Pin input edge detection External 0008H (B) 3 INTP1 4 INTTMH1 Match between TMH1 and CMP01 5 INTTM000 Match between TM00 and CR000 Note 3 (when compare register is specified), 000AH Internal 000CH (A) 000EH TI010 pin valid edge detection (when capture register is specified) 6 INTTM010 Match between TM00 and CR010 Note 3 (when compare register is specified), 0010H TI000 pin valid edge detection (when capture register is specified) Reset Notes 1. Note 3 7 INTAD End of A/D conversion - RESET Reset input POC Power-on-clear LVI Low-voltage detection WDT WDT overflow 0012H - 0000H - Note 5 Priority is the vector interrupt servicing priority order when several maskable interrupt requests are generated at the same time. 1 is the highest and 7 is the lowest. <R> 2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 10-1. 3. PD78F920x only 4. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 0 is selected. 5. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 1 is selected. User's Manual U18172EJ3V0UD 177 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (B) External maskable interrupt Internal bus External interrupt mode register (INTM0) Interrupt request Edge detector MK IE IF Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag 10.3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers. * Interrupt request flag register 0 (IF0) * Interrupt mask flag register 0 (MK0) * External interrupt mode register 0 (INTM0) * Program status word (PSW) Table 10-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. 178 User's Manual U18172EJ3V0UD CHAPTER 10 INTERRUPT FUNCTIONS Table 10-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag INTLVI LVIIF LVIMK INTP0 PIF0 PMK0 INTP1 PIF1 PMK1 TMIFH1 INTTMH1 INTTM000 Note INTTM010 Note Note TMMKH1 TMIF000 Note TMMK000 Note TMIF010 Note TMMK010 Note Note INTAD <R> Interrupt Mask Flag ADIF ADMK Note Note PD78F920x only (1) Interrupt request flag register 0 (IF0) An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is acknowledged or when a reset signal is input. IF0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears IF0 to 00H. Figure 10-2. Format of Interrupt Request Flag Register 0 (IF0) Address: FFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> 0 IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0 Note Note Note xxIFx <R> Interrupt request flag 0 No interrupt request signal has been issued. 1 An interrupt request signal has been issued; an interrupt request status. Note PD78F920x only Caution Because P21 and P32 have an alternate function as external interrupt inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. User's Manual U18172EJ3V0UD 179 CHAPTER 10 INTERRUPT FUNCTIONS (2) Interrupt mask flag register 0 (MK0) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets MK0 to FFH. Figure 10-3. Format of Interrupt Mask Flag Register 0 (MK0) Address: FFE4H After reset: FFH Symbol <7> <6> MK0 ADMK R/W <5> <4> TMMK010 TMMK000 TMMKH1 Note Note <1> 0 PMK1 PMK0 LVIMK 1 Interrupt servicing control 0 Enables interrupt servicing. 1 Disables interrupt servicing. Note <2> Note xxMKx <R> <3> PD78F920x only Caution Because P21 and P32 have an alternate function as external interrupt inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. (3) External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 and INTP1. INTM0 is set with an 8-bit memory manipulation instruction. Reset signal generation clears INTM0 to 00H. Figure 10-4. Format of External Interrupt Mode Register 0 (INTM0) Address: FFECH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 INTM0 0 0 ES11 ES10 ES01 ES00 0 0 ES11 ES10 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES01 ES00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges 180 INTP1 valid edge selection INTP0 valid edge selection User's Manual U18172EJ3V0UD CHAPTER 10 INTERRUPT FUNCTIONS Cautions 1. Be sure to clear bits 0, 1, 6, and 7 to 0. 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (xxMKx = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (xxIFx = 0), then clear the interrupt mask flag (xxMKx = 0), which will enable interrupts. (4) Program status word (PSW) The program status word is used to hold the instruction execution result and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW. PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically saved to a stack, and the IE flag is reset to 0. Reset signal generation sets PSW to 02H. Figure 10-5. Program Status Word (PSW) Configuration Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used in the execution of ordinary instructions Whether to enable/disable interrupt acknowledgment IE 0 Disabled 1 Enabled 10.4 Interrupt Servicing Operation 10.4.1 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. If the interrupt enabled status is in effect (when the IE flag is set to 1), then the request is acknowledged as a vector interrupt. The time required to start the vectored interrupt servicing after a maskable interrupt request has been generated is shown in Table 10-3. See Figures 10-7 and 10-8 for the interrupt request acknowledgment timing. Table 10-3. Time from Generation of Maskable Interrupt Request to Servicing Minimum Time 9 clocks Note Maximum Time 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instructions. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. User's Manual U18172EJ3V0UD 181 CHAPTER 10 INTERRUPT FUNCTIONS A pending interrupt is acknowledged when a status in which it can be acknowledged is set. Figure 10-6 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. Figure 10-6. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (Interrupt request generated) xxMK = 0? No Yes Interrupt request pending No IE = 1? Yes Interrupt request pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag IE: Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) Figure 10-7. Interrupt Request Acknowledgment Timing (Example of MOV A, r) 8 clocks Clock CPU MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set before an instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is acknowledged after the instruction under execution is complete. Figure 10-7 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the instruction fetch starts, the interrupt acknowledgment processing is performed after the MOV A, r instruction is executed. 182 User's Manual U18172EJ3V0UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-8. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed. Figure 10-8 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is executed, and then the interrupt acknowledgment processing is performed. Caution Interrupt requests will be held pending while the interrupt request flag register 0 (IF0) or interrupt mask flag register 0 (MK0) are being accessed. 10.4.2 Multiple interrupt servicing In order to perform multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced, the interrupt mask function must be used to mask interrupts for which a low priority is to be set. User's Manual U18172EJ3V0UD 183 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-9. Example of Multiple Interrupts (1/2) Example 1. Multiple interrupts are acknowledged INTxx servicing Main processing EI IE = 0 EI INTyy servicing IE = 0 INTyy INTxx RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. Before each interrupt request acknowledgement, the EI instruction is issued, the interrupt mask is released, and the interrupt request acknowledgement enable state is set. Caution Multiple interrupts can be acknowledged even for low-priority interrupts. Example 2. Multiple interrupts are not generated because interrupts are not enabled INTxx servicing Main processing EI IE = 0 INTyy servicing INTyy is held pending INTyy RETI INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and acknowledged after the INTxx servicing is performed. IE = 0: Interrupt request acknowledgment disabled 184 User's Manual U18172EJ3V0UD CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-9. Example of Multiple Interrupts (2/2) Example 3. A priority is controlled by the Multiple interrupts The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1. (Interruption priority INTP0 > INTP1 > INTTMH1 (refer to Table10-1)) INTTNH1 servicing Main processing EI INTP1 servicing IE = 0 PMK0 = 1 EI IE = 0 INTTMH1 INTP0 INTP1 RETI INTP0 servicing PMK0 = 0 IE = 0 RETI RETI In the interrupt INTTMH1 servicing, servicing is performed such that the INTP1 interrupt is given priority, since the INTP0 interrupt was first masked. Afterwards, once the interrupt mask for INTP0 is released, INTP0 processing through multiple interrupts is performed. IE = 0: Interrupt request acknowledgment disabled 10.4.3 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated during the execution. The following shows such instructions (interrupt request pending instruction). * Manipulation instruction for interrupt request flag register 0 (IF0) * Manipulation instruction for interrupt mask flag register 0 (MK0) User's Manual U18172EJ3V0UD 185 CHAPTER 11 STANDBY FUNCTION 11.1 Standby Function and Configuration 11.1.1 Standby function Table 11-1. Relationship Between Operation Clocks in Each Operation Status Status Low-Speed Internal Oscillator Note 1 Operation Mode Reset LSRSTOP = 0 Oscillating Oscillating Note 3 Hardware LSRSTOP = 1 Stopped Stopped Oscillating Oscillating Stopped HALT Notes 1. Clock Supplied to Peripheral Note 2 Stopped STOP System Clock When "Cannot be stopped" is selected for low-speed internal oscillator by the option byte. 2. When it is selected that the low-speed internal oscillator "can be stopped by software", oscillation of the 3. If the operating clock of the watchdog timer is the low-speed internal oscillation clock, the watchdog low-speed internal oscillator can be stopped by LSRSTOP. timer is stopped. Caution The LSRSTOP setting is valid only when "Can be stopped by software" is set for the low-speed internal oscillator by the option byte. Remark LSRSTOP: Bit 0 of the low-speed internal oscillation mode register (LSRCM) The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. Oscillation of the system clock oscillator continues. If the low-speed internal oscillator is operating before the HALT mode is set, oscillation of the clock of the low-speed internal oscillator continues (refer to Table 11-1. Oscillation of the low-speed internal oscillation clock (whether it cannot be stopped or can be stopped by software) is set by the option byte). In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and frequently carrying out intermittent operations. 186 User's Manual U18172EJ3V0UD CHAPTER 11 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, select the HALT mode if processing must be immediately started by an interrupt request when the operation stop timeNote is generated after the STOP mode is released (because an additional wait time for stabilizing oscillation elapses when crystal/ceramic oscillation is used). Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction (except the peripheral hardware that operates on the low-speed internal oscillation clock). <R> 2. The following sequence is recommended for operating current reduction of the A/D converter in PD78F920x when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 3. If the low-speed internal oscillator is operating before the STOP mode is set, oscillation of the low-speed internal oscillation clock cannot be stopped in the STOP mode (refer to Table 11-1). User's Manual U18172EJ3V0UD 187 CHAPTER 11 STANDBY FUNCTION <R> 11.1.2 Registers used during standby (PD78F920x only) The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS. (1) Oscillation stabilization time select register (OSTS) (PD78F920x only) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released. If the high-speed internal oscillation or external clock input is selected as the system clock source, no wait time elapses. The system clock oscillator and the oscillation stabilization time that elapses after power application or release of reset are selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. OSTS is set by using the 8-bit memory manipulation instruction. Figure 11-1. Format of Oscillation Stabilization Time Select Register (OSTS) (PD78F920x Only) Address: FFF4H, After reset: Undefined, R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 0 0 2 /fX (102.4 s) 0 1 2 /fX (409.6 s) 1 0 2 /fX (3.27 ms) 1 1 2 /fX (13.1 ms) Selection of oscillation stabilization time 10 12 15 17 Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS 2. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset signal generation or interrupt generation. STOP mode is released Voltage waveform of X1 pin a 3. The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Remarks 1. ( ): fX = 10 MHz 2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. 188 User's Manual U18172EJ3V0UD CHAPTER 11 STANDBY FUNCTION 11.2 Standby Function Operation 11.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set. Table 11-2. Operating Statuses in HALT Mode Setting of HALT Mode Low-Speed Internal Oscillator cannot be stopped Note 1 . Low-Speed Internal Oscillator can be stopped Note 1 . When Low-Speed Internal When Low-Speed Internal Oscillation Continues Oscillation Stops Item System clock Clock supply to CPU is stopped. CPU Operation stops. Port (latch) Holds status before HALT mode was set. Note 2 16-bit timer/event counter 00 8-bit timer Operable Sets count clock to fXP to fXP/2 H1 Sets count clock to fRL/2 Watchdog "System clock" selected as timer operating clock 12 7 Operable Operable Operable Setting disabled. Operation stops. "Low-speed internal oscillation Operable Operation stops. clock" selected as operating (Operation continues) Operation stops. clock Note 2 A/D converter Operable Power-on-clear circuit Always operates. Low-voltage detector Operable External interrupt Operable Notes 1. "Cannot be stopped" or "Stopped by software" is selected for low-speed internal oscillator by the option byte (for the option byte, see CHAPTER 15 OPTION BYTE). <R> 2. PD78F920x only User's Manual U18172EJ3V0UD 189 CHAPTER 11 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 11-2. HALT Mode Release by Interrupt Request Generation Interrupt request HALT instruction Wait Standby release signal Status of CPU Operating mode HALT mode Wait Operating mode Oscillation System clock oscillation Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 11 to 13 clocks * When vectored interrupt servicing is not carried out: 3 to 5 clocks 190 User's Manual U18172EJ3V0UD CHAPTER 11 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 11-3. HALT Mode Release by Reset Signal Generation (1) When CPU clock is high-speed internal oscillation clock or external input clock HALT instruction Reset signal CPU status Operation mode Reset period HALT mode Oscillates System clock oscillation Operation stopsNote Oscillation stops Operation mode Oscillates Note Operation is stopped (277 s (MIN.), 544 s (TYP.), 1.075 ms (MAX.)) because the option byte is referenced. <R> (2) When CPU clock is crystal/ceramic oscillation clock (PD78F920x only) HALT instruction Reset signal CPU status Operation mode Oscillation Reset Operation Operation period stopsNote stabilization waits mode HALT mode Oscillates System clock oscillation Oscillation stops Oscillates Oscillation stabilization time (210/fX to 217/fX) Note Operation is stopped (276 s (MIN.), 544 s (TYP.), 1.074 ms (MAX.)) because the option byte is referenced. Remark fX: System clock oscillation frequency Table 11-3. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt request Reset signal generation MKxx IE Operation 0 0 Next address instruction execution 0 1 Interrupt servicing execution 1 x HALT mode held - x Reset processing x: don't care User's Manual U18172EJ3V0UD 191 CHAPTER 11 STANDBY FUNCTION 11.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is restored after the STOP instruction is executed and then the operation is stopped for the duration of 34 s (TYP.) (after an additional wait time for stabilizing oscillation set by the oscillation stabilization time select register (OSTS) has elapsed when crystal/ceramic oscillation is used). The operating statuses in the STOP mode are shown below. Table 11-4. Operating Statuses in STOP Mode Setting of STOP Mode Low-Speed Internal Oscillator cannot be stopped Item Note 1 System clock Oscillation stops. CPU Operation stops. Port (latch) Note 1 . When Low-Speed Internal When Low-Speed Internal Oscillation Continues Oscillation Stops Holds status before STOP mode was set. 16-bit timer/event counter 00 8-bit timer . Low-Speed Internal Oscillator can be stopped Note 2 Operation stops. Sets count clock to fXP to fXP/2 H1 Sets count clock to fRL/2 Watchdog "System clock" selected as timer operating clock 12 7 Operation stops. Operable Operable Setting disabled. Operation stops. "Low-speed internal oscillation Operable Operation stops. clock" selected as operating (Operation continues) Operation stops. clock A/D converter Note 2 Operation stops. Power-on-clear circuit Always operates. Low-voltage detector Operable External interrupt Operable Notes 1. "Cannot be stopped" or "Stopped by software" is selected for low-speed internal oscillator by the option byte (for the option byte, see CHAPTER 15 OPTION BYTE). 2. PD78F920x only <R> 192 User's Manual U18172EJ3V0UD CHAPTER 11 STANDBY FUNCTION (2) STOP mode release Figure 11-4. Operation Timing When STOP Mode Is Released <1> If high-speed internal oscillation clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock <R> Operation stopsNote. High-speed internal oscillation clock or external clock input <2> If crystal/ceramic oscillation clock is selected as system clock to be supplied (PD78F920x only) STOP mode is released. STOP mode System clock oscillation CPU clock Operation stopsNote. HALT status (oscillation stabilization time set by OSTS) Crystal/ceramic oscillation clock Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). The STOP mode can be released by the following two sources. User's Manual U18172EJ3V0UD 193 CHAPTER 11 STANDBY FUNCTION (a) Release by unmasked interrupt request Note When an unmasked interrupt request (8-bit timer H1 , low-voltage detector, external interrupt request) is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Note Only when sets count clock to fRL/27 Figure 11-5. STOP Mode Release by Interrupt Request Generation (1) If CPU clock is high-speed internal oscillation clock or external input clock Interrupt request STOP instruction Standby release signal CPU status System clock oscillation Operation mode Oscillation Operation stopsNote. STOP mode Oscillation stops. Operation mode Oscillation (2) If CPU clock is crystal/ceramic oscillation clock (PD78F920x only) <R> Interrupt request STOP instruction Standby release signal CPU status Operation mode System clock Oscillation STOP mode Operation Waiting for stabilization stopsNote. of oscillation (HALT mode status) Oscillation stops. Operation mode Oscillation Oscillation stabilization time (set by OSTS) Note The operation stop time is 17 s (MIN.), 34 s (TYP.), and 67 s (MAX.). Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 194 User's Manual U18172EJ3V0UD CHAPTER 11 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 11-6. STOP Mode Release by Reset signal generation (1) If CPU clock is high-speed internal oscillation clock or external input clock STOP instruction Reset signal CPU status System clock oscillation Operation mode Oscillation Operation stopsNote. Reset period STOP mode Oscillation stops. Operation mode Oscillation Note Operation is stopped (277 s (MIN.), 544 s (TYP.), 1.075 ms (MAX.)) because the option byte is referenced. (2) If CPU clock is crystal/ceramic oscillation clock (PD78F920x only) <R> STOP instruction Reset signal CPU status System clock oscillation Operation mode Reset period STOP mode Oscillation Oscillation Operation Operation stopsNote. stabilization waits mode Oscillation stops. Oscillation Oscillation stabilization time (210/fX to 217/fX) Note Operation is stopped (276 s (MIN.), 544 s (TYP.), 1.074 ms (MAX.)) because the option byte is referenced. Remark fX: System clock oscillation frequency Table 11-5. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt request Reset signal generation MKxx IE Operation 0 0 Next address instruction execution 0 1 Interrupt servicing execution 1 x STOP mode held - x Reset processing x: don't care User's Manual U18172EJ3V0UD 195 CHAPTER 12 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer overflows (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts from the programs at the address written in addresses 0000H and 0001H when the reset signal is generated. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Table 12-1. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after reset release, except for P130, which is low-level output. When a low level is input to the RESET pin, a reset occurs, and when a high level is input to the RESET pin, the reset is released and the CPU starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). A reset generated by the watchdog timer source is automatically released after the reset, and the CPU starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). (see Figures 12-2 to 12-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and the CPU starts program execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected) (see CHAPTER 13 POWER-ON-CLEAR CIRCUIT and CHAPTER 14 LOW-VOLTAGE DETECTOR). Cautions 1. For an external reset, input a low level for 2 s or more to the RESET pin. 2. During reset signal generation, the system clock and low-speed internal oscillation clock stop oscillating. 3. When the RESET pin is used as an input-only port pin (P34), the 78K0S/KU1+ is reset if a low level is input to the RESET pin after reset is released by the POC circuit, the LVI circuit and the watchdog timer and before the option byte is referenced again. retained until a high level is input to the RESET pin. 196 User's Manual U18172EJ3V0UD The reset status is CHAPTER 12 RESET FUNCTION Figure 12-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Reset signal of WDT Set LVIRF Set Clear Clear Reset signal to LVIM/LVIS register RESET Reset signal of POC Internal reset signal Reset signal of LVI Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit. Remarks 1. LVIM: Low-voltage detect register 2. LVIS: Low-voltage detection level select register User's Manual U18172EJ3V0UD 197 CHAPTER 12 RESET FUNCTION Figure 12-2. Timing of Reset by RESET Input <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Reset period (oscillation stops) Normal operation (reset processing, CPU clock) RESET Operation stops because option byte is referencedNote. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin Note The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). <2> With crystal/ceramic oscillation clock (PD78F920x only) <R> Crystal/ceramic oscillation clock Normal operation in progress Reset period (oscillation stops) Oscillation stabilization time (210/fX to 217/fX) RESET Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin Note Remark 198 The operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). fX: System clock oscillation frequency User's Manual U18172EJ3V0UD CHAPTER 12 RESET FUNCTION Figure 12-3. Timing of Reset by Overflow of Watchdog Timer <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Reset period (oscillation stops) Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote. Watchdog overflow Internal reset signal Hi-Z Port pin The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). Note Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer. <2> With crystal/ceramic oscillation clock (PD78F920x only) <R> Crystal/ceramic oscillation clock CPU clock Normal operation in progress Reset period (oscillation stops) Oscillation stabilization time (210/fX to 217/fX) Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote. Watchdog overflow Internal reset signal Hi-Z Port pin Note The operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer. Remark fX: System clock oscillation frequency User's Manual U18172EJ3V0UD 199 CHAPTER 12 RESET FUNCTION Figure 12-4. Reset Timing by RESET Input in STOP Mode <1> With high-speed internal oscillation clock or external clock input STOP instruction is executed. High-speed internal oscillation clock or external clock input CPU clock Normal operation in progress Stop status (oscillation stops) Reset period (oscillation stops) Normal operation (reset processing, CPU clock) RESET Operation stops because option byte is referencedNote. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin Note The operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.). <2> With crystal/ceramic oscillation clock (PD78F920x only) <R> STOP instruction is executed. Crystal/ceramic oscillation clock CPU clock Normal operation in progress Stop status (oscillation stops) Reset period (oscillation stops) Oscillation stabilization time (210/fX to 217/fX) RESET Normal operation (reset processing, CPU clock) Operation stops because option byte is referencedNote. Internal reset signal Delay 100 ns (TYP.) Delay 100 ns (TYP.) Hi-Z Port pin Note The operation stop time is 276 s (MIN.), 544 s (TYP.), and 1.074 ms (MAX.). Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 13 POWER-ON-CLEAR CIRCUIT and CHAPTER 14 LOW-VOLTAGE DETECTOR. 2. fX: System clock oscillation frequency 200 User's Manual U18172EJ3V0UD CHAPTER 12 RESET FUNCTION Table 12-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Note 1 Program counter (PC) Status After Reset Contents of reset vector table (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined General-purpose registers Undefined Ports (P2 to P4) (output latches) FFH Note 3 Port mode control register (PMC2) 00H Pull-up resistor option registers (PU2 to PU4) 00H Processor clock control register (PCC) 02H Preprocessor clock control register (PPCC) 02H Low-speed internal oscillation mode register (LSRCM) 00H Oscillation stabilization time select register (OSTS) Undefined 16-bit timer 00 8-bit timer H1 Watchdog timer Note 3 A/D converter Notes 1. Note 2 00H Port mode registers (PM2 to PM4) Note 3 Note 2 Timer counter 00 (TM00) 0000H Capture/compare registers 000, 010 (CR000, CR010) 0000H Mode control register 00 (TMC00) 00H Prescaler mode register 00 (PRM00) 00H Capture/compare control register 00 (CRC00) 00H Timer output control register 00 (TOC00) 00H Compare registers (CMP01, CMP11) 00H Mode register 1 (TMHMD1) 00H Mode register (WDTM) 67H Enable register (WDTE) 9AH Conversion result registers (ADCR, ADCRH) Undefined Mode register (ADM) 00H Analog input channel specification register (ADS) 00H Only the contents of PC are undefined while reset signal generation and while the oscillation stabilization time elapses. The statuses of the other hardware units remain unchanged. <R> 2. The status after reset is held in the standby mode. 3. PD78F920x only User's Manual U18172EJ3V0UD 201 CHAPTER 12 RESET FUNCTION Table 12-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Status After Reset Note Reset function Reset control flag register (RESF) 00H Low-voltage detector Low-voltage detection register (LVIM) 00H Low-voltage detection level select register (LVIS) 00H Request flag registers (IF0) 00H Mask flag registers (MK0) FFH External interrupt mode registers (INTM0) 00H Flash protect command register (PFCMD) Undefined Flash status register (PFS) 00H Flash programming mode control register (FLPMC) Undefined Interrupt Flash memory Note Note Flash programming command register (FLCMD) 00H Flash address pointer L (FLAPL) Undefined Flash address pointer H (FLAPH) Flash address pointer H compare register (FLAPHC) 00H Flash address pointer L compare register (FLAPLC) 00H Flash write buffer register (FLW) 00H Note These values change as follows depending on the reset source. Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Register RESF WDTRF Cleared (0) Cleared (0) LVIRF LVIM Cleared (00H) Cleared (00H) Set (1) Held Held Set (1) Cleared (00H) Held LVIS 202 User's Manual U18172EJ3V0UD CHAPTER 12 RESET FUNCTION 12.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0S/KU1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset signal generation by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 12-5. Format of Reset Control Flag Register (RESF) Address: FF54H After reset: 00H Note R Symbol 7 6 5 4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. LVIRF Internal reset request by low-voltage detector (LVI) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 12-2. Table 12-2. RESF Status When Reset Request Is Generated Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Flag WDTRF LVIRF Cleared (0) Cleared (0) Set (1) Held Held Set (1) User's Manual U18172EJ3V0UD 203 CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. * Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V), and generates internal reset signal when VDD < VPOC. * Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V), and releases internal reset signal when VDD VPOC. Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. 2. Because the detection voltage (VPOC) of the POC circuit is in a range of 2.1 V 0.1 V, use a voltage in the range of 2.2 to 5.5 V. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage-detection (LVI) circuit. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI. For details of RESF, see CHAPTER 12 RESET FUNCTION. 204 User's Manual U18172EJ3V0UD CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 13-1. Figure 13-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal - Reference voltage source 13.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V) are compared, and an internal reset signal is generated when VDD < VPOC, and an internal reset is released when VDD VPOC. Figure 13-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit Supply voltage (VDD) POC detection voltage (VPOC = 2.1 V 0.1 V) Time Internal reset signal User's Manual U18172EJ3V0UD 205 CHAPTER 13 POWER-ON-CLEAR CIRCUIT 13.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 13-3. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Reset ; Check reset source Note 2 Initialization of ports Setting WDT Initialization processing <1> Power-on clear ; fXP = High-speed internal oscillation clock (8.4 MHz (MAX.)) /22 (default value) Setting 8-bit timer H1 (50 ms is measured) Source : fRL (2.1 MHz (MAX.)) /212, 51 ms when the compare value is 25 Timer starts (TMHE1 = 1) Clears WDT Note 1 No 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> Notes 1. 2. 206 ; Specify the division ratio of the system clock, setting Timaer, setting A/D Converter, etc. If reset is generated again during this period, initialization processing <2> is not started. A flowchart is shown on the next page. User's Manual U18172EJ3V0UD CHAPTER 13 POWER-ON-CLEAR CIRCUIT Figure 13-3. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on clear/external reset generated User's Manual U18172EJ3V0UD 207 CHAPTER 14 LOW-VOLTAGE DETECTOR 14.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. * Detection levels (ten levels) of supply voltage can be changed by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, refer to CHAPTER 12 RESET FUNCTION. 14.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 14-1. Figure 14-1. Block Diagram of Low-Voltage Detector Low-voltage detection level selector VDD VDD N-ch Selector Internal reset signal + - INTLVI Reference voltage source 4 LVION LVIMD LVIS3 LVIS2 LVIS1 LVIS0 Low-voltage detection level select register (LVIS) LVIF Low-voltage detect register (LVIM) Internal bus 208 User's Manual U18172EJ3V0UD CHAPTER 14 LOW-VOLTAGE DETECTOR 14.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detect register (LVIM) * Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00HNote 1. Figure 14-2. Format of Low-Voltage Detect Register (LVIM) After reset: 00HNote 1 R/WNote 2 Address: FF50H Symbol <7> 6 5 4 3 2 <1> <0> LVIM LVION 0 0 0 0 0 LVIMD LVIF Note 3 LVION Enabling low-voltage detection operation 0 Disable operation 1 Enable operation LVIMD Low-voltage detection operation mode selection 0 Generate interrupt signal when supply voltage (VDD) < detection voltage (VLVI) 1 Generate internal reset signal when supply voltage (VDD) < detection voltage (VLVI) Note 4 LVIF Low-voltage detection flag 0 Supply voltage (VDD) detection voltage (VLVI), or when operation is disabled 1 Supply voltage (VDD) < detection voltage (VLVI) Notes 1. For a reset by LVI, the value of LVIM is not initialized. 2. Bit 0 is a read-only bit. 3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is confirmed at LVIF. 4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. Cautions 1. To stop LVI, follow either of the procedures below. * When using 8-bit manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Be sure to set bits 2 to 6 to 0. User's Manual U18172EJ3V0UD 209 CHAPTER 14 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00HNote. Figure 14-3. Format of Low-Voltage Detection Level Select Register (LVIS) Address: FF51H, After reset: 00H Note R/W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 0 0 0 0 VLVI0 (4.3 V 0.2 V) 0 0 0 1 VLVI1 (4.1 V 0.2 V) 0 0 1 0 VLVI2 (3.9 V 0.2 V) 0 0 1 1 VLVI3 (3.7 V 0.2 V) 0 1 0 0 VLVI4 (3.5 V 0.2 V) 0 1 0 1 VLVI5 (3.3 V 0.15 V) 0 1 1 0 VLVI6 (3.1 V 0.15 V) 0 1 1 1 VLVI7 (2.85 V 0.15 V) 1 0 0 0 VLVI8 (2.6 V 0.1 V) 1 0 0 1 VLVI9 (2.35 V 0.1 V) Other than above Detection level Setting prohibited Note For a reset by LVI, the value of LVIS is not initialized. Cautions 1. 2. Bits 4 to 7 must be set to 0. If a value other than the above is written during LVI operation, the value becomes undefined at the very moment it is written, and thus be sure to stop LVI (bit 7(LVION) = 0 on the LVIM register) before writing. 210 User's Manual U18172EJ3V0UD CHAPTER 14 LOW-VOLTAGE DETECTOR 14.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. * Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI, and releases internal reset when VDD VLVI. * Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows. (1) When used as reset * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to instigate a wait of at least 0.2 ms. <5> Wait until "supply voltage (VDD) detection voltage (VLVI)" at bit 0 (LVIF) of LVIM is confirmed. <6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Figure 14-4 shows the timing of generating the internal reset signal of the low-voltage detector. Numbers <1> to <6> in this figure correspond to <1> to <6> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. 2. If supply voltage (VDD) detection voltage (VLVI) when LVIMD is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order. User's Manual U18172EJ3V0UD 211 CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) <2> LVIMK flag (set by software) H Time <1> Note 1 LVION flag (set by software) Not cleared Not cleared <3> Clear <4> 0.2 ms or longer LVIF flag <5> Clear Note 2 LVIMD flag (set by software) Not cleared Not cleared <6> Clear LVIRF flagNote 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1. The LVIMK flag is set to "1" by reset signal generation. 2. The LVIF flag may be set (1). 3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 12 RESET FUNCTION. Remark <1> to <6> in Figure 14-4 above correspond to <1> to <6> in the description of "when starting operation" in 14.4 (1) When used as reset. 212 User's Manual U18172EJ3V0UD CHAPTER 14 LOW-VOLTAGE DETECTOR (2) When used as interrupt * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to instigate a wait of at least 0.2 ms. <5> Wait until "supply voltage (VDD) detection voltage (VLVI)" at bit 0 (LVIF) of LVIM is confirmed. <6> Clear the interrupt request flag of LVI (LVIIF) to 0. <7> Release the interrupt mask flag of LVI (LVIMK). <8> Execute the EI instruction (when vector interrupts are used). Figure 14-5 shows the timing of generating the interrupt signal of the low-voltage detector. Numbers <1> to <7> in this figure correspond to <1> to <7> above. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. User's Manual U18172EJ3V0UD 213 CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) Time <2> LVIMK flag (set by software) <1> Note 1 LVION flag (set by software) <7> Cleared by software <3> <4> 0.2 ms or longer LVIF flag <5> Note 2 INTLVI Note 2 LVIIF flag Note 2 <6> Cleared by software Internal reset signal Notes 1. 2. Remark 214 The LVIMK flag is set to "1" by reset signal generation. An interrupt request signal (INTLVI) may be generated, and the LVIF and LVIIF flags may be set to 1. <1> to <7> in Figure 14-5 above correspond to <1> to <7> in the description of "when starting operation" in 14.4 (2) When used as interrupt. User's Manual U18172EJ3V0UD CHAPTER 14 LOW-VOLTAGE DETECTOR 14.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. <1> When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> When used as interrupt Interrupt requests may be frequently generated. Take (b) of action (2) below. In this system, take the following actions. <Action> (1) When used as reset After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports (see Figure 14-6). (2) When used as interrupt (a) Perform the processingNote for low voltage detection. Check that "supply voltage (VDD) detection voltage (VLVI)" in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt request flag register 0 (IF0) to 0. (b) In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, check that "supply voltage (VDD) detection voltage (VLVI)" using the LVIF flag and clear LVIIF flag to 0. Note For low voltage detection processing, the CPU clock speed is switched to slow speed and the A/D converter is stopped, etc. User's Manual U18172EJ3V0UD 215 CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-6. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check reset source Note Initialization of ports Setting WDT Initialization processing <1> LVI reset ; The detection level is set with LVIS. The low-voltage detector is operated (LVION = 1) Setting LVI ; fXP = High-speed internal oscillation clock (8.4 MHz (MAX.)) /22 (default value) Setting 8-bit timer H1 (50 ms is measured) Source : fRL (2.1 MHz (MAX.)) /212, 51 ms when the compare value is 25 Timer starts (TMHE1 = 1) Clears WDT Detection voltage or more (LVIF = 0 ?) Yes No LVIF = 0 Restarting the timaer H1 (TMHE1 = 0 TMHE1 = 1) No ; Clear low-voltage detection flag. ; Clear timaer counter and timer starts. 50 ms has passed? (TMIFH1 = 1?) Yes Initialization processing <2> Note 216 ; Specify the division ratio of the system clock, setting Timaer, setting A/D Converter, etc. A flowchart is shown on the next page. User's Manual U18172EJ3V0UD CHAPTER 14 LOW-VOLTAGE DETECTOR Figure 14-6. Example of Software Processing After Release of Reset (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector User's Manual U18172EJ3V0UD 217 CHAPTER 15 OPTION BYTE 15.1 Functions of Option Byte The address 0080H of the flash memory of the 78K0S/KU1+ is an option byte area. When power is supplied or when starting after a reset, the option byte is automatically referenced, and settings for the specified functions are performed. When using the product, be sure to set the following functions by using the option byte. 15.1.1 PD78F920x (1) Selection of system clock source * High-speed internal oscillation clock * Crystal/ceramic oscillation clock * External clock input (2) Low-speed internal oscillation clock oscillation * Cannot be stopped. * Can be stopped by software. (3) Control of RESET pin * Used as RESET pin * RESET pin is used as an input port pin (P34) (refer to 15.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34)). (4) Oscillation stabilization time on power application or after reset release * 210/fX * 212/fX * 215/fX 17 * 2 /fX Figure 15-1. Positioning of Option Byte (PD78F920x) 03FFH/ 07FFH/ 0FFFH Flash memory (1024/2048/4096 x 8 bits) 0080H Option byte 1 0000H 218 DEF DEF OSTS1 OSTS0 User's Manual U18172EJ3V0UD 1 RMCE OSCSEL1 OSCSEL0 LIOSP CHAPTER 15 OPTION BYTE <R> 15.1.2 PD78F950x (1) Selection of system clock source * High-speed internal oscillation clock * External clock input (2) Low-speed internal oscillation clock oscillation * Cannot be stopped. * Can be stopped by software. (3) Control of RESET pin * Used as RESET pin * RESET pin is used as an input-only port pin (P34) (see 15.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34)). * The on-chip pull-up resistor on RESET pin is selected, or RESET pin is set open. (4) Oscillation stabilization time on power application or after reset release * 210/fX * 212/fX * 215/fX 17 * 2 /fX Figure 15-2. Positioning of Option Byte (PD78F950x) 03FFH/ 07FFH/ 0FFFH Flash memory (1024/2048/4096 x 8 bits) 0080H Option byte 1 1 1 ENPU34 RMCE OSCSEL1 OSCSEL0 LIOSP 0000H User's Manual U18172EJ3V0UD 219 CHAPTER 15 OPTION BYTE 15.2 Format of Option Byte Format of option bytes is shown below. 15.2.1 PD78F920x Figure 15-3. Format of Option Byte (PD78F920x) (1/2) Address: 0080H 7 6 5 4 3 2 1 0 1 DEFOSTS1 DEFOSTS0 1 RMCE OSCSEL1 OSCSEL0 LIOCP DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or after reset release 0 0 2 /fx (102.4 s) 0 1 2 /fx (409.6 s) 1 0 2 /fx (3.27 ms) 1 1 2 /fx (13.1 ms) 10 12 15 17 Caution The setting of this option is valid only when the crystal/ceramic oscillation clock is selected as the system clock source. No wait time elapses if the high-speed internal oscillation clock or external clock input is selected as the system clock source. RMCE Control of RESET pin 1 RESET pin is used as is. 0 RESET pin is used as input port pin (P34). Caution Because the option byte is referenced after reset release, if a low level is input to the RESET pin before the option byte is referenced, then the reset state is not released. Also, when setting 0 to RMCE, connect the pull-up resistor. OSCSEL1 OSCSEL0 Selection of system clock source 0 0 Crystal/ceramic oscillation clock 0 1 External clock input 1 x High-speed internal oscillation clock Caution Because the X1 and X2 pins are also used as the P23/ANI3 and P22/ANI2 pins, the conditions under which the X1 and X2 pins can be used differ depending on the selected system clock source. (1) Crystal/ceramic oscillation clock is selected The X1 and X2 pins cannot be used as I/O port pins or analog input pins of A/D converter because they are used as clock input pins. (2) External clock input is selected Because the X1 pin is used as an external clock input pin, P23/ANI3 cannot be used as an I/O port pin or an analog input pin of A/D converter. (3) High-speed internal oscillation clock is selected P23/ANI3 and P22/ANI2 pins can be used as I/O port pins or analog input pins of A/D converter. Remark 220 x : don't care User's Manual U18172EJ3V0UD CHAPTER 15 OPTION BYTE Figure 15-3. Format of Option Byte (PD78F920x) (2/2) LIOCP Low-speed internal oscillates 1 Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit) 0 Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit) Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock. 2. If it is selected that low-speed internal oscillator can be stopped by software, supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly, clock supply is also stopped when a clock other than the low-speed internal oscillation clock is selected as a count clock to WDT. While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be supplied to the 8-bit timer H1 even in the STOP mode. Remarks 1. ( ): fX = 10 MHz 2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator to be used. 3. An example of software coding for setting the option bytes is shown below. OPB CSEG AT 0080H DB 10010001B ; Set to option byte ; Low-speed internal oscillator cannot be stopped ; The system clock is a crystal or ceramic resonator. ; The RESET pin is used as an input-only port pin (P34). ; Minimum oscillation stabilization time (210/fX) 4. For details on the timing at which the option byte is referenced, see CHAPTER 12 RESET FUNCTION. User's Manual U18172EJ3V0UD 221 CHAPTER 15 OPTION BYTE <R> 15.2.2 PD78F950x Figure 15-4. Format of Option Byte (PD78F950x) (1/2) Address: 0080H 7 6 5 4 3 2 1 0 1 1 1 ENPU34 RMCE OSCSEL1 OSCSEL0 LIOCP ENPU34 Selection of on-chip pull-up resistor on RESET pin 1 On-chip pull-up resistor on RESET pin is selected. 0 On-chip pull-up resistor on RESET pin is not selected. Remark When used as RESET pin, the pin can be left open by setting ENPU34 to "1". RMCE Control of RESET pin 1 RESET pin is used as is. 0 RESET pin is used as input port pin (P34). Caution Because the option byte is referenced after reset release, if a low level is input to the RESET pin before the option byte is referenced, then the reset state is not released. When used as an input-only port (P34), the setting of the on-chip pull-up resistor can be done by PU34 on PU3 register. OSCSEL1 OSCSEL0 Selection of system clock source 0 0 Setting prohibited 0 1 External clock input 1 x High-speed internal oscillation clock Caution Because the EXCLK pin is also used as the P23 pin, the condition under which the EXCLK pin can be used differ depending on the selected system clock source. (1) External clock input is selected Because the pin is used as an external clock input pin, P23 cannot be used as an I/O port pin. (2) High-speed internal oscillation clock is selected P23 pin can be used as an I/O port pin. Remark 222 x : don't care User's Manual U18172EJ3V0UD CHAPTER 15 OPTION BYTE Figure 15-4. Format of Option Byte (PD78F950x) (2/2) LIOCP Low-speed internal oscillates 1 Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit) 0 Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit) Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock. 2. If it is selected that low-speed internal oscillator can be stopped by software, supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly, clock supply is also stopped when a clock other than the low-speed internal oscillation clock is selected as a count clock to WDT. While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be supplied to the 8-bit timer H1 even in the STOP mode. Remarks 1. ( ): fX = 10 MHz 2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator to be used. 3. An example of software coding for setting the option bytes is shown below. OPB CSEG AT 0080H DB 10010001B ; Set to option byte ; Low-speed internal oscillator cannot be stopped ; The RESET pin is used as an input-only port pin (P34). ; Minimum oscillation stabilization time (210/fX) 4. For details on the timing at which the option byte is referenced, see CHAPTER 12 RESET FUNCTION. 15.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34) Be aware of the following when erasing/writing by on-board programming using a dedicated flash memory programmer once again on the already-written device which has been set as "The RESET pin is used as an input-only port pin (P34)" by the option byte function. Before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on. If the power is supplied to the target system beforehand, it cannot be switched to the flash memory programming mode. User's Manual U18172EJ3V0UD 223 CHAPTER 16 FLASH MEMORY 16.1 Features The internal flash memory of the 78K0S/KU1+ has the following features. { Erase/write even without preparing a separate dedicated power supply { Capacity: 1/2/4 KB * Erase unit: 1 block (256 bytes) * Write unit: 1 block (at onboard/offboard programming time), 1 byte (at self programming time) { Rewriting method * Rewriting by communication with dedicated flash memory programmer (on-board/off-board programming) * Rewriting flash memory by user program (self programming) { Supports rewriting of the flash memory at onboard/offboard programming time through security functions { Supports security functions in block units at self programming time through protect bytes 224 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.2 Memory Configuration The 1/2/4 KB internal flash memory area is divided into 4/8/16 blocks and can be programmed/erased in block units. All the blocks can also be erased at once, by using a dedicated flash memory programmer. <R> Figure 16-1. Flash Memory Mapping PD78F9202, 78F9502 0FFFH Block 15 (256 bytes) 0F00H 0EFFH Block 14 (256 bytes) 0E00H 0DFFH FFFFH Block 13 (256 bytes) 0D00H 0CFFH Special function resister (256 byte) Block 12 (256 bytes) FF00H FEFFH 0C00H 0BFFH Block 11 (256 bytes) 0B00H 0AFFH Internal high-speed RAM (128 byte) Block 10 (256 bytes) 0A00H 09FFH FE80H FE7FH Block 9 (256 bytes) PD78F9201, 78F9501 Block 8 (256 bytes) Block 7 (256 bytes) Block 7 (256 bytes) Block 6 (256 bytes) Block 6 (256 bytes) Block 5 (256 bytes) Block 5 (256 bytes) Use prohibited 0800H 07FFH 0700H 06FFH 0600H 05FFH 0500H 04FFH PD78F9200, 78F9500 Block 4 (256 bytes) Block 3 (256 bytes) Block 3 (256 bytes) Block 3 (256 bytes) Block 2 (256 bytes) Block 2 (256 bytes) Block 2 (256 bytes) Block 1 (256 bytes) Block 1 (256 bytes) Block 1 (256 bytes) Block 0 (256 bytes) Block 0 (256 bytes) Block 0 (256 bytes) 1 KB 2 KB 4 KB Block 4 (256 bytes) 0400H 03FFH Flash memory (1/2/4 KB) 0000H 0900H 08FFH 0300H 02FFH 0200H 01FFH 0100H 00FFH 0000H 16.3 Functional Outline The internal flash memory of the 78K0S/KU1+ can be rewritten by using the rewrite function of the dedicated flash memory programmer, regardless of whether the 78K0S/KU1+ has already been mounted on the target system or not (on-board/off-board programming). The function for rewriting a program with the user program (self programming), which is ideal for an application when it is assumed that the program is changed after production/shipment of the target system, is provided. Refer to Table 16-1 for the flash memory writing control function. In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person. Refer to 16.7.3 Security settings for details on the security function. User's Manual U18172EJ3V0UD 225 CHAPTER 16 FLASH MEMORY Table 16-1. Rewrite Method Rewrite Method On-board programming Off-board programming Functional Outline Flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash memory programmer. Operation Mode Flash memory programming mode Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a dedicated program adapter board (FA series). Self programming Flash memory can be rewritten by executing a user program that has Self programming mode been written to the flash memory in advance by means of on-board/offboard programming. Remarks 1. The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. 2. Refer to the following sections for details on the flash memory writing control function. * 16.7 On-Board and Off-Board Flash Memory Programming * 16.8 Flash Memory Programming by Self Programming 16.4 Writing with Flash Memory Programmer The following two types of dedicated flash memory programmers can be used for writing data to the internal flash memory of the 78K0S/KU1+. * FlashPro5 (PG-FP5, FL-PR5) <R> * QB-MINI2 Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0S/KU1+ have been mounted on the target system. The connectors that connect the dedicated flash memory programmer and the test pad must be mounted on the target system. The test pad is required only when writing data with the crystal/ceramic resonator mounted (refer to Figure 16-4 for mounting of the test pad). (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0S/KU1+ is mounted on the target system. <R> Remark The FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd. 226 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.5 Programming Environment The environment required for writing a program to the flash memory is illustrated below. Figure 16-2. Environment for Writing Program to Flash Memory (FlashPro5/QB-MINI2) <R> VDD FlashPro5 Host machine <R> QB-MINI2 VSS RS-232-C RESET USB SO/TxD 78K0S/KU1+ Dedicated flash memory programmer CLK Remark For QB-MINI2, the name of the SO/TxD signal is DATA. A host machine that controls the dedicated flash memory programmer is necessary. When using the PG-FP5 or FL-PR5, data can be written with just the dedicated flash memory programmer after downloading the program from the host machine. UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash memory programmer and the 78K0S/KU1+. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. Download the latest firmware for flash memory programmer, programming GUI, and parameter file from the download site for development tools (http://www.necel.com/micro/en/ods/). User's Manual U18172EJ3V0UD 227 CHAPTER 16 FLASH MEMORY <R> Table 16-2. Wiring Between 78K0S/KU1+ and FlashPro5/QB-MINI2 FlashPro5/QB-MINI2 Connection Pin Pin Name I/O 78K0S/KU1+ Connection Pin Pin Function Pin Name PD78F920x CLK Output Clock to 78K0S/KU1+ X1/P23/ANI3 EXCLK/P23 SO/TxD Output Receive signal/on-board mode signal X2/P22/ANI2 P22 /RESET Output Reset signal RESET/P34 RESET/P34 VDD - VDD voltage generation/voltage monitor VDD VDD GND - Ground VSS VSS <R> Figure 16-3. Wiring diagram with FlashPro5/QB-MINI2 1 10 FlashPro5/ QB-MINI2 signal name 2 9 3 8 CLK 4 7 SO/TxD 5 6 /RESET 78K0S/KU1+ VDD GND <R> Remark 228 PD78F950x For QB-MINI2, the name of the SO/TxD signal is DATA. User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.6 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. The state of the pins in the self programming mode is the same as that in the HALT mode. 16.6.1 X1 and X2 pins (PD78F920x) The X1 and X2 pins are used as the serial interface of flash memory programming. Therefore, if the X1 and X2 pins are connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the connection with the external device. When connected a capacitor to X1 and X2 pins, waveform at the time of communication is changed. Therefore there is a possibility that cannot communicate depending on capacitor capacitance. When perform flash memory programming, isolate connection with a condenser. Perform the following processing (1) and (2) when on-board programming is performed with the resonator mounted, when it is difficult to isolate the resonator, while a crystal or ceramic resonator is selected as the system clock. (1) Mount the minimum-possible test pads between the device and the resonator, and connect the flash memory programmer via the test pad. Keep the wiring as short as possible (refer to Figure 16-4 and Table 16-3). (2) Set the oscillation frequency of the communication clock for writing using the programming GUI of the dedicated flash memory programmer. Research the series/parallel resonant and antiresonant frequencies of the resonator used, and set the oscillation frequency so that it is outside the range of the resonant frequency 10% (refer to Figure 16-5 and Table 16-4). Figure 16-4. Example of Mounting Test Pads Test pad VSS X1 X2 Table 16-3. Clock to Be Used and Mounting of Test Pads Clock to Be Used High-speed internal oscillation clock Mounting of Test Pads Not required External clock Crystal/ceramic oscillation Before resonator is mounted clock After resonator is mounted User's Manual U18172EJ3V0UD Required 229 CHAPTER 16 FLASH MEMORY Figure 16-5. PG-FP5 Programming GUI Setting Example Set oscillation frequency Click (Standard tab in Device setup window) (Main window) Table 16-4. Oscillation Frequency and PG-FP5 Programming GUI Setting Value Example PG-FP5 GUI Software Setting Value Example Oscillation Frequency (Communication Frequency) 2 MHz fX < 4 MHz 8 MHz 4 MHz fX < 8 MHz 9 MHz 8 MHz fX < 9 MHz 10 MHz 9 MHz fX 10 MHz 8 MHz Caution The above values are recommended values. Depending on the usage environment these values may change, so set them after having performed sufficient evaluations. <R> 16.6.2 EXCLK pin (PD78F950x) The EXCLK pin is used as the serial interface of flash memory programming. Therefore, if the EXCLK pin is connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the connection with the external device. When connected a capacitor to the EXCLK pin, waveform at the time of communication is changed. Therefore there is a possibility that cannot communicate depending on capacitor capacitance. When perform flash memory programming, isolate connection with a condenser. 230 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.6.3 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash memory programmer. Figure 16-6. Signal Collision (RESET Pin) 78K0S/KU1+ Signal collision RESET Dedicated flash programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. Therefore, isolate the signal of the reset signal generator. 16.6.4 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. The state of the pins in the self programming mode is the same as that in the HALT mode. 16.6.5 Power supply Connect the VDD pin to VDD of the flash memory programmer, and the VSS pin to VSS of the flash memory programmer. User's Manual U18172EJ3V0UD 231 CHAPTER 16 FLASH MEMORY 16.7 On-Board and Off-Board Flash Memory Programming 16.7.1 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0S/KU1+ in the flash memory programming mode. When the 78K0S/KU1+ are connected to the flash memory programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode. Change the mode by using a jumper when writing the flash memory on-board. 16.7.2 Communication commands The dedicated flash memory programmer controls the 78K0S/KU1+ by using commands. The signals sent from the flash memory programmer to the 78K0S/KU1+ are called communication commands, and the commands sent from the 78K0S/KU1+ to the dedicated flash memory programmer are called response. <R> Figure 16-7. Communication Commands FlashPro5 QB-MINI2 Communication command Response Dedicated flash memory programmer 78K0S/KU1+ Communication commands are listed in the table below. All these communication commands are issued from the programmer and the 78K0S/KU1+ perform processing corresponding to the respective communication commands. Table 16-5. Communication Commands Classification Erase Write Communication Command Name Function Batch erase (chip erase) command Erases the contents of the entire memory Block erase command Erases the contents of the memory of the specified block Write command Writes to the specified address range and executes a verify check of the contents. Checksum Checksum command Reads the checksum of the specified address range and Blank check Blank check command Confirms the erasure status of the entire memory. Security Security set command Prohibits batch erase (chip erase) command, block erase compares with the written data. command, and write command to prevent operation by third parties. The 78K0S/KU1+ returns a response for the communication command issued by the dedicated flash memory programmer. The response name sent from the 78K0S/KU1+ are listed below. 232 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY Table 16-6. Response Name Command Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. 16.7.3 Security settings The operations shown below can be prohibited using the security setting command. * Batch erase (chip erase) is prohibited Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is prohibited. Once execution of the batch erase (chip erase) command is prohibited, all the prohibition settings can no longer be cancelled. Caution After the security setting of the batch erase is set, erasure cannot be performed for the device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written because the erase command is disabled. * Block erase is prohibited Execution of the block erase command in the flash memory is prohibited. This prohibition setting can be cancelled using the batch erase (chip erase) command. * Write is prohibited Execution of the write and block erase commands for entire blocks in the flash memory is prohibited. This prohibition setting can be cancelled using the batch erase (chip erase) command. Remark The security setting is valid when the programming mode is set next time. The batch erase (chip erase), block erase, and write commands are enabled by the default setting when the flash memory is shipped. The above security settings are possible only for on-board/off-board programming. Each security setting can be used in combination. Table 16-7 shows the relationship between the erase and write commands when the 78K0S/KU1+ security function is enabled. Table 16-7. Relationship Between Commands When Security Function Is Enabled Command Security When batch erase (chip erase) security Batch Erase (Chip Block Erase Erase) Command Command Disabled Disabled Write Command Enabled Note operation is enabled When block erase security operation is Enabled Enabled enabled When write security operation is enabled Disabled Note Since the erase command is disabled, data different from that which has already been written to the flash memory cannot be written. User's Manual U18172EJ3V0UD 233 CHAPTER 16 FLASH MEMORY Table 16-8 shows the relationship between the security setting and the operation in each programming mode. Table 16-8. Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode Security Setting On-Board/Off-Board Programming Security Setting Batch erase (chip erase) Possible Self Programming Security Operation Security Setting Note 1 Valid Security Operation Note 2 Impossible Invalid Block erase Write Notes 1. Execution of each command is prohibited by the security setting. 2. Execution of self programming command is possible regardless of the security setting. 16.8 Flash Memory Programming by Self Programming The 78K0S/KU1+ support a self programming function that can be used to rewrite the flash memory via a user program, making it possible to upgrade programs in the field. Caution Self programming processing must be included in the program before performing self programming. Remarks 1. 2. For usages of self programming, refer to use example mentioned in after 16.8.4. To use the internal flash memory of the 78K0S/KU1+ as the external EEPROM for storing data, refer to 78K0S/Kx1+ EEPROM Emulation Application Note (U17379E). 16.8.1 Outline of self programming To execute self programming, shift the mode from the normal operation of the user program (normal mode) to the self programming mode. Write/erase processing for the flash memory, which has been set to the register in advance, is performed by executing the HALT instruction during self programming mode. The HALT state is automatically released when processing is completed. To shift to the self programming mode, execute a specific sequence for a specific register. Refer to 16.8.4 Example of shifting normal mode to self programming mode for details. Remark Data written by self programming can be referenced with the MOV instruction. Table 16-9. Self Programming Mode Mode User Program Execution Execution of Write/erase for Flash Memory with HALT Instruction Normal mode Self programming mode - Enabled Enabled Note Enabled Note Maskable interrupt servicing is disabled during self programming mode. Figure 16-8 shows a block diagram for self programming, Figure 16-9 shows the self programming state transition diagram, Table 16-10 lists the commands for controlling self programming. 234 User's Manual U18172EJ3V0UD Figure 16-8. Block Diagram of Self Programming Internal bus Flash programming command register (FLCMD) Protect byte PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLCMD2 FLCMD1 FLCMD0 Flash programming mode control register (FLPMC) Self programming mode setting sequencer Flash protect command register (PFCMD) Self programming mode setting register 5 3 HALT signal User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY Self programming command execution Flash memory controller Increment circuit Erase circuit Write circuit Verify circuit HALT release signal Flash address pointer H (FLAPH) Flash memory Match Flash address pointer L (FLAPL) Unmatch Match Flash address pointer H compare register (FLAPHC) Flash address pointer L compare register (FLAPLC) Flash write buffer register (FLW) WEPRERR VCERR FPRERR Flash status register (PFS) Internal bus 235 CHAPTER 16 FLASH MEMORY Figure 16-9. Self Programming State Transition Diagram User program Operation setting Normal mode Specific sequence Operation setting Self programming mode Self programming command completion/error Register for self programming Self programming command execution by HALT instruction Flash memory control block (hardware) Self programming command under execution Operation reference Flash memory Table 16-10. Self Programming Controlling Commands Command Name Function Time Taken from HALT Instruction Execution to Command Execution End Internal verify 1 This command is used to check if data has been Internal verify for 1 block (internal verify correctly written to the flash memory. It is used to command executed once): 6.8 ms check whether data has been written to an entire block. Internal verify 2 This command is used to check if data has been Internal verify for 1 byte: 27 s correctly written to the flash memory. It is used to check whether data has been written in the same block. Block erasure Note This command is used to erase a specified block. 8.5 ms Specify the block number before execution. Block blank check This command is used to check if data in a specified 480 s block has been erased. Specify the block number, then execute this command. Byte write This command is used to write 1-byte data to the 150 s specified address in the flash memory. Specify the write address and write data, then execute this command. Note Set the number of retrials larger than the block erasure time divided by the time (8.5 ms) for one erase, in accordance with the time (MAX. value) required for flash memory block erasures. Remark The command internal verify 1 can be executed by specifying an address in the same block but internal verify 2 is recommended if data is written to two or more addresses in the same block. 236 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.8.2 Cautions on self programming function * No instructions can be executed while a self programming command is being executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. Refer to Table 16-10 for the time taken for the execution of self programming. * Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid this operation, disable interrupt servicing (by setting MK0 to FFH, and executing the DI instruction) before a mode is shifted from the normal mode to the self programming mode with a specific sequence. * RAM is not used while a self programming command is being executed. * If the supply voltage drops or the reset signal is input while the flash memory is being written or erased, writing/erasing is not guaranteed. * The value of the blank data set during block erasure is FFH. * Set the CPU clock so that it is 1 MHz or more during self programming. * Execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, then execute self programming. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). * If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. * Check FPRERR using a 1-bit memory manipulation instruction. * The state of the pins in self programming mode is the same as that in HALT mode. * Since the security function set via on-board/off-board programming is disabled in self programming mode, the self programming command can be executed regardless of the security function setting. To disable write or erase processing during self programming, set the protect byte. * Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the value of these bits is 1 when executing the self programming command, there is a possibility that device does not operate normally. * Clear the value of the FLCMD register to 00H immediately before setting self-programming mode and normal operation mode. 16.8.3 Registers used for self-programming function The following registers are used for the self-programming function. * Flash programming mode control register (FLPMC) * Flash protect command register (PFCMD) * Flash status register (PFS) * Flash programming command register (FLCMD) * Flash address pointers H and L (FLAPH and FLAPL) * Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC) * Flash write buffer register (FLW) The 78K0S/KU1+ has an area called a protect byte at address 0081H of the flash memory. (1) Flash programming mode control register (FLPMC) This register is used to set the operation mode when data is written to the flash memory in the selfprogramming mode, and to read the set value of the protect byte. Data can be written to FLPMC only in a specific sequence (refer to 16.8.3 (2) Flash protect command register (PFCMD)) so that the application system does not stop by accident because of malfunction due to noise or program hang-up. User's Manual U18172EJ3V0UD 237 CHAPTER 16 FLASH MEMORY This register is set with an 8-bit memory manipulation instruction. Reset signal generation makes the contents of this register undefined. Figure 16-10. Format of Flash Programming Mode Control Register (FLPMC) After reset: UndefinedNote 1 Address: FFA2H Symbol 7 FLPMC 0 6 4 3 2 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLSPM 0 5 R/WNote 2 1 0 0 FLSPM Selection of operation mode during self-programming mode Normal mode This is the normal operation status. Executing the HALT instruction sets standby status. 1 Self-programming mode Self programming commands can be executed by executing the specific sequence to change modes while in normal mode. Set a command, an address, and data to be written, then execute the HALT instruction to execute self programming. PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 The set value of the protect byte is read to these bits. Notes 1. Bit 0 (FLSPM) is cleared to 0 when reset is released. The set value of the protect byte is read to bits 2 to 6 (PRSELF0 to PRSELF4) after reset is released. 2. Bits 2 to 6 (PRSELF0 to PRSELF4) are read-only. Cautions 1. Cautions in the case of setting the self programming mode, refer to 16.8.2 Cautions on self programming function. 2. Set the CPU clock so that it is 1 MHz or more during self programming. 3. Execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, then execute self programming. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). 4. If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. 5. Clear the value of the FLCMD register to 00H immediately before setting selfprogramming mode and normal operation mode. 238 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop inadvertently. Writing FLPMC is enabled only when a write operation is performed in the following specific sequence. <1> Write a specific value to PFCMD (A5H) <2> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid) <3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid) <4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid) Caution Interrupt servicing cannot be executed in self-programming mode. Disable interrupt servicing (by executing the DI instruction while MK0 = FFH) before executing the specific sequence that sets self-programming mode and after executing the specific sequence that changes the mode to the normal mode. This rewrites the value of the register, so that the register cannot be written illegally. Occurrence of an illegal store operation can be checked by bit 0 (FPRERR) of the flash status register (PFS). Check FPRERR using a 1-bit memory manipulation instruction. A5H must be written to PFCMD each time the value of FLPMC is changed. PFCMD can be set by an 8-bit memory manipulation instruction. Reset signal generation makes PFCMD undefined. Figure 16-11. Format of Flash Protect Command Register (PFCMD) Address: FFA0H After reset: Undefined W Symbol 7 6 5 4 3 2 1 0 PFCMD REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 (3) Flash status register (PFS) If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1. When FPRERR is 1, it can be cleared to 0 by writing 0 to it. Errors that may occur during self-programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. VCERR or WEPRERR can be cleared by writing 0 to them. All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly. PFS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears PFS to 00H. Caution Check FPRERR using a 1-bit memory manipulation instruction. User's Manual U18172EJ3V0UD 239 CHAPTER 16 FLASH MEMORY Figure 16-12. Format of Flash Status Register (PFS) Address: FFA1H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PFS 0 0 0 0 0 WEPRERR VCERR FPRERR 1. Operating conditions of FPRERR flag <Setting conditions> * If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value (A5H) to FLPMC * If the first store instruction operation after <1> is on a peripheral register other than FLPMC * If the first store instruction operation after <2> is on a peripheral register other than FLPMC * If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction after <2> * If the first store instruction operation after <3> is on a peripheral register other than FLPMC * If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction after <3> Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command register (PFCMD). <Reset conditions> * If 0 is written to the FPRERR flag * If the reset signal is generation 2. Operating conditions of VCERR flag <Setting conditions> * Erasure verification error * Internal writing verification error If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the memory again in the specified procedure. Remark The VCERR flag may also be set if an erase or write protect error occurs. <Reset conditions> * When 0 is written to the VCERR flag * When the reset signal generation 3. Operating conditions of WEPRERR flag <Setting conditions> * If the area specified by the protect byte to be protected from erasing or writing is specified by the flash address pointer H (FLAPH) and a command is executed to this area * If 1 is written to a bit that has not been erased (a bit for which the data is 0). <Reset conditions> * When 0 is written to the WEPRERR flag * When the reset signal generation 240 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY (4) Flash programming command register (FLCMD) This register is used to specify whether the flash memory is erased, written, or verified in the self-programming mode. This register is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 16-13. Format of Flash Programming Command Register (FLCMD) Address: FFA3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 FLCMD 0 0 0 0 0 FLCMD2 FLCMD1 FLCMD0 FLCMD2 FLCMD1 FLCMD0 0 0 1 Command Name Internal verify 1 Function This command is used to check if data has been correctly written to the flash memory. It is used to check whether data has been written to an entire block. If an error occurs, bit 1 (VCERR) or bit 2 (WEPRERR) of the flash status register (PFS) is set to 1. Internal verify 2 This command is used to check if data has been correctly written to the flash memory. It is used to check whether data has been written in the same block. If an error occurs, bit 1 (VCERR) or bit 2 (WEPRERR) of the flash status register (PFS) is set to 1. 0 1 1 Block erase This command is used to erase specified block. It is used both in the on-board mode and self- programming mode. 1 0 0 Block blank check This command is used to check if the 1 0 1 Byte write This command is used to write 1-byte specified block has been erased. data to the specified address in the flash memory. Specify the write address and write data, then execute this command. If 1 is written to a bit that has not been erased (a bit for which the data is 0), then bit 2 (WEPRERR) of the flash status register (PFS) becomes 1. Other than aboveNote Setting prohibited Note If any command other than those above is executed, command execution may immediately be terminated, and bit 1 or 2 (WEPRERR or VCERR) of the flash status register (PFS) may be set to 1. User's Manual U18172EJ3V0UD 241 CHAPTER 16 FLASH MEMORY (5) Flash address pointers H and L (FLAPH and FLAPL) These registers are used to specify the start address of the flash memory when the memory is erased, written, or verified in the self-programming mode. FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of FLAPHC and FLAPLC when the programming command is not executed. When the programming command is executed, therefore, set the value again. These registers are set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation makes these registers undefined. Figure 16-14. Format of Flash Address Pointer H/L (FLAPH/FLAPL) Address: FFA4H, FFA5H After reset: Undefined R/W FLAPH (FFA5H) 0 0 0 0 FLAPL (FFA4H) FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Caution Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. (6) Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC) These registers are used to specify the address range in which the internal sequencer operates when the flash memory is verified in the self-programming mode. Set FLAPHC to the same value as that of FLAPH. Set the last address of the range in which verification is to be executed to FLAPLC. These registers are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 16-15. Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC) Address: FFA6H, FFA7H After reset: 00H R/W FLAPHC (FFA6H) 0 0 0 0 FLAPLC (FFA7H) FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Cautions 1. Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. 2. Set the number of the block subject to a block erase, verify, or blank check (same value as FLAPH) to FLAPHC. 3. Clear FLAPLC to 00H when a block erase is performed, and set this register to FFH when a blank check is performed. 242 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY (7) Flash write buffer register (FLW) This register is used to store the data to be written to the flash memory. This register is set with an 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 16-16. Format of Flash Write Buffer Register (FLW) Address: FFA8H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 FLW FLW7 FLW6 FLW5 FLW4 FLW3 FLW2 FLW1 FLW0 (8) Protect byte This protect byte is used to specify the area that is to be protected from writing or erasing. The specified area is valid only in the self-programming mode. Because self-programming of the protected area is invalid, the data written to the protected area is guaranteed. Figure 16-17. Format of Protect Byte (1/2) Address: 0081H 7 6 5 4 3 2 1 0 1 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 1 1 * PD78F9200, 78F9500 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 Other than above Status Blocks 3 to 0 are protected. Blocks 1 and 0 are protected. Blocks 2 and 3 can be written or erased. All blocks can be written or erased. Setting prohibited * PD78F9201, 78F9501 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 Other than above User's Manual U18172EJ3V0UD Status Blocks 7 to 0 are protected. Blocks 5 to 0 are protected. Blocks 6 and 7 can be written or erased. Blocks 3 to 0 are protected. Blocks 4 to 7 can be written or erased. Blocks 1 and 0 are protected. Blocks 2 to 7 can be written or erased. All blocks can be written or erased. Setting prohibited 243 CHAPTER 16 FLASH MEMORY Figure 16-17. Format of Protect Byte (2/2) * PD78F9202, 78F9502 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 Other than above Status Blocks 15 to 0 are protected. Blocks 13 to 0 are protected. Blocks 14 and 15 can be written or erased. Blocks 11 to 0 are protected. Blocks 12 to 15 can be written or erased. Blocks 9 to 0 are protected. Blocks 10 to 15 can be written or erased. Blocks 7 to 0 are protected. Blocks 8 to 15 can be written or erased. Blocks 5 to 0 are protected. Blocks 6 to 15 can be written or erased. Blocks 3 to 0 are protected. Blocks 4 to 15 can be written or erased. Blocks 1 and 0 are protected. Blocks 2 to 15 can be written or erased. All blocks can be written or erased. Setting prohibited 16.8.4 Example of shifting normal mode to self programming mode The operating mode must be shifted from normal mode to self programming mode before performing self programming. An example of shifting to self programming mode is explained below. <1> Disable interrupts if the interrupt function is used (by setting the interrupt mask flag registers (MK0) to FFH and executing the DI instruction). <2> Clear FLCMD (FLCMD=00H). <3> Clear the flash status register (PFS). <4> Set self programming mode using a specific sequence. Note * Write a specific value (A5H) to PFCMD. * Write 01H to FLPMC (writing in this step is invalid). * Write 0FEH (inverted value of 01H) to FLPMC (writing in this step is invalid). * Write 01H to FLPMC (writing in this step is valid). <5> Execute NOP instruction and HALT instruction. <6> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS. Abnormal <3>, normal <7> <7> Mode shift is completed. Note Set the CPU clock so that it is 1 MHz or more during self programming. Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. 244 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY Figure 16-18. Example of Shifting to Self Programming Mode Shift to self programming mode <1> Disable interrupts (by setting MK0 to FFH and executing DI instruction) ; When interrupt function is used <2> Clear FLCMD (FLCMD=00H). <3> Clear PFS PFCMD = A5H FLPMC = 01H (set value) ; Set value is invalid <4> FLPMC = 0FEH (inverted set value) FLPMC = 01H (set value) ; Set value is valid NOP instruction <5> HALT instruction <6> Check execution result (FPRERR flag) Abnormal Normal <7> Termination Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. Remark <1> to <7> in Figure 16-18 correspond to <1> to <7> in 16.8.4 (previous page). User's Manual U18172EJ3V0UD 245 CHAPTER 16 FLASH MEMORY An example of the program that shifts the mode to self programming mode is shown below. ;---------------------------;START ;---------------------------MOV MK0,#11111111B ; Masks all interrupts MOV FLCMD,#00H ; Clear FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode with FLPMC register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: ; control (sets value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. ;---------------------------;END ;---------------------------- 246 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.8.5 Example of shifting self programming mode to normal mode The operating mode must be returned from self programming mode to normal mode after performing self programming. An example of shifting to normal mode is explained below. <1> Clear FLCMD (FLCMD=00H). <2> Clear the flash status register (PFS). <3> Set normal mode using a specific sequence. * Write the specific value (A5H) to PFCMD. * Write 00H to FLPMC (writing in this step is invalid) * Write 0FFH (inverted value of 00H) to FLPMC (writing in this step is invalid) * Write 00H to FLPMC (writing in this step is valid) <4> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS. Abnormal <2>, normal <5> <5> Enable interrupt servicing (by executing the EI instruction and changing MK0) to restore the original state. <6> Mode shift is completed Note After the specific sequence is correctly executed, restore the CPU clock to its setting before the self programming. Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. User's Manual U18172EJ3V0UD 247 CHAPTER 16 FLASH MEMORY Figure 16-19. Example of Shifting to Normal Mode Shift to normal mode <1> Clear FLCMD (FLCMD=00H) <2> Clear PFS PFCMD = A5H FLPMC = 00H (set value) ; Set value is invalid <3> FLPMC = 0FFH (inverted set value) FLPMC = 00H (set value) <4> Check execution result (FPRERR flag) ; Set value is valid Abnormal Normal Restore the CPU clock to its setting before the self programming <5> Enable interrupts (by executing EI instruction and changing MK0) ; When interrupt function is used <6> Termination Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. Remark 248 <1> to <6> in Figure 16-19 correspond to <1> to <6> in 16.8.5 (previous page). User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY An example of a program that shifts the mode to normal mode is shown below. ;---------------------------;START ;---------------------------- MOV FLCMD,#00H ; Clear FLCMD register ModeOffLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs ; Restore the CPU clock to its setting before the self ; programming MOV MK0,#INT_MK0 ; Restores interrupt mask flag EI ;---------------------------;END ;---------------------------- User's Manual U18172EJ3V0UD 249 CHAPTER 16 FLASH MEMORY 16.8.6 Example of block erase operation in self programming mode An example of the block erase operation in self programming mode is explained below. <1> Set 03H (block erase) to the flash program command register (FLCMD). <2> Set the block number to be erased, to flash address pointer H (FLAPH). <3> Set flash address pointer L (FLAPL) to 00H. <4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC). <5> Set the flash address pointer L compare register (FLAPLC) to 00H. <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note 1. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFSNote 2. Abnormal <10> Normal <R> <12> <10> If the number of times the erase command can be executed has not been exceeded, return to step <6> and re-execute the command. If the number of times the erase command can be executed has been exceeded, block erasure ends abnormally. <11> Block erase processing is abnormally terminated. <12> Block erase processing is normally terminated. Notes 1. <R> 2. This setting is not required when the watchdog timer is not used. Separately check the WEPRERR bit to check for errors in executing the erase command on a writeprohibited area. 250 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY <R> Figure 16-20. Example of Block Erase Operation in Self Programming Mode Block erasure <1> Set erase command (FLCMD = 03H) <2> Set no. of block to be erased to FLAPH <3> Set FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5> Set FLAPLC to 00H <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result Abnormal The erase command can be re-executed. <10> Check the number of executions of the erase command Normal <12> Normal termination The erase command cannot be re-executed. <11> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark <1> to <12> in Figure 16-20 correspond to <1> to <12> in 16.8.6 (previous page). User's Manual U18172EJ3V0UD 251 CHAPTER 16 FLASH MEMORY An example of a program that performs a block erase in self programming mode is shown below. ;---------------------------;START ;---------------------------- <R> MOV B,#48 ; Specifies the number of times the erase command can be ; executed. ; (4.0 V to 5.5 V Time for executing block erasure 100 times) FlashBlockErase: MOV FLCMD,#03H ; Sets flash control command (block erase) MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of FLAPH) MOV FLAPLC,#00H ; Fixes FLAPLC to "00H" EraseRetry: MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT <R> ; Self programming is started MOV A,PFS CMP A,#00H ; Checks execution result BZ $StatusNormal ; Normal termination DBNZ B,$EraseRetry ; Checks whether to re-execute the erase command. ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: 252 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.8.7 Example of block blank check operation in self programming mode An example of the block blank check operation in self programming mode is explained below. <1> Set 04H (block blank check) to the flash program command register (FLCMD). <2> Set the number of block for which a blank check is performed, to flash address pointer H (FLAPH). <3> Set flash address pointer L (FLAPL) to 00H. <4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC). <5> Set the flash address pointer L compare register (FLAPLC) to FFH. <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <10> Normal <11> <10> Block blank check is abnormally terminated. <11> Block blank check is normally terminated. Note This setting is not required when the watchdog timer is not used. User's Manual U18172EJ3V0UD 253 CHAPTER 16 FLASH MEMORY Figure 16-21. Example of Block Blank Check Operation in Self Programming Mode Block blank check <1> Set block blank check command (FLCMD = 04H) <2> Set no. of block for blank check to FLAPH <3> Set FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5> Set FLAPLC to 00H <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <11> Normal termination <10> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark 254 <1> to <11>in Figure 16-21 correspond to <1> to <11> in 16.8.7 (previous page). User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY An example of a program that performs a block blank check in self programming mode is shown below. ;---------------------------;START ;---------------------------- FlashBlockBlankCheck: MOV FLCMD,#04H ; Sets flash control command (block blank check) MOV FLAPH,#07H ; Sets number of block for blank check (block 7 is specified ; here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets blank check block compare number (same value as that of MOV FLAPLC,#0FFH ; Fixes FLAPLC to "FFH" MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT ; FLAPH) HALT ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- User's Manual U18172EJ3V0UD 255 CHAPTER 16 FLASH MEMORY 16.8.8 Example of byte write operation in self programming mode An example of the byte write operation in self programming mode is explained below. <1> Set 05H (byte write) to the flash program command register (FLCMD). <2> Set the number of block to which data is to be written, to flash address pointer H (FLAPH). <3> Set the address at which data is to be written, to flash address pointer L (FLAPL). <4> Set the data to be written, to the flash write buffer register (FLW). <5> Clear the flash status register (PFS). <6> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <7> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <8> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <9> Normal <10> <9> Byte write processing is abnormally terminated. <10> Byte write processing is normally terminated. Note This setting is not required when the watchdog timer is not used. Caution 256 If a write results in failure, erase the block once and write to it again. User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY Figure 16-22. Example of Byte Write Operation in Self Programming Mode Byte write <1> Set byte write command (FLCMD = 05H) <2> Set no. of block to be written, to FLAPH <3> Set address at which data is to be written, to FLAPL <4> Set data to be written to FLW <5> Clear PFS <6> Clear & restart WDT counter (WDTE = ACH)Note <7> Execute HALT instruction <8> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <10> Normal termination <9> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark <1> to <10> in Figure 16-22 correspond to <1> to <10> in 16.8.8 (previous page). User's Manual U18172EJ3V0UD 257 CHAPTER 16 FLASH MEMORY An example of a program that performs a byte write in self programming mode is shown below. ;---------------------------;START ;---------------------------FlashWrite: MOV FLCMD,#05H ; Sets flash control command (byte write) MOV FLAPH,#07H ; Sets address to which data is to be written, with MOV FLAPL,#20H ; Sets address to which data is to be written, with MOV FLW,#10H ; Sets data to be written (10H is specified here) MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT ; FLAPH (block 7 is specified here) ; FLAPL (address 20H is specified here) HALT ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- 258 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.8.9 Example of internal verify operation in self programming mode An example of the internal verify operation in self programming mode is explained below. * Internal verify 1 <1> Set 01H (internal verify 1) to the flash program command register (FLCMD). <2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH). <3> Sets the flash address pointer L (FLAPL) to 00H. <4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC). <5> Sets the flash address pointer L compare register (FLAPLC) to FFH. <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <10> Normal <11> <10> Internal verify processing is abnormally terminated. <11> Internal verify processing is normally terminated. * Internal verify 2 <1> Set 02H (internal verify 2) to the flash program command register (FLCMD). <2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH). <3> Sets flash address pointer L (FLAPL) to the start address. <4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC). <5> Sets flash address pointer L compare register (FLAPLC) to the end address. <6> Clear the flash status register (PFS). <7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note. <8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the HALT instruction if self programming has been executed.) <9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS. Abnormal <10> Normal <11> <10> Internal verify processing is abnormally terminated. <11> Internal verify processing is normally terminated. Note This setting is not required when the watchdog timer is not used. User's Manual U18172EJ3V0UD 259 CHAPTER 16 FLASH MEMORY Figure 16-23. Example of Internal Verify 1 Operation in Self Programming Mode Internal verify 1 <1> Set internal verify 1 command (FLCMD = 01H) <2> Set No. of block for internal verify, to FLAPH <3> Sets FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5> Sets FLAPLC to FFH <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <11> Normal termination <10> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark 260 <1> to <11> in Figure 16-23 correspond to Internal verify 1 <1> to <11> in 16.8.9 (previous page). User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY Figure 16-24. Example of Internal Verify 2 Operation in Self Programming Mode Internal verify 2 <1> Set internal verify 2 command (FLCMD = 02H) <2> Set No. of block for internal verify, to FLAPH <3> Sets FLAPL to the start address <4> Set the same value as that of FLAPH to FLAPHC <5> Sets FLAPLC to the end address <6> Clear PFS <7> Clear & restart WDT counter (WDTE = ACH)Note <8> Execute HALT instruction <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <11> Normal termination <10> Abnormal termination Note This setting is not required when the watchdog timer is not used. Remark <1> to <11> in Figure 16-24 correspond to Internal verify 2 <1> to <11> in 16.8.9 (the page before last). User's Manual U18172EJ3V0UD 261 CHAPTER 16 FLASH MEMORY An example of a program that performs an internal verify in self programming mode is shown below. * Internal verify 1 ;---------------------------;START ;---------------------------FlashVerify: MOV FLCMD,#01H ; Sets flash control command (internal verify 1) MOV FLAPH,#07H ; Set the number of block for which internal verify is ; performed, to FLAPH (Example: Block 7 is specified here) MOV FLAPL,#00H MOV FLAPHC,#07H MOV FLAPLC,#FFH MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Sets FLAPL to 00H ; Sets FLAPLC to FFH ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- * Internal verify 2 ;---------------------------;START ;---------------------------FlashVerify: MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV FLAPH,#07H ; Set the number of block for which internal verify is MOV FLAPL,#00H ; Sets FLAPL to the start address for verify (Example: Address ; performed, to FLAPH (Example: Block 7 is specified here) ; 00H is specified here) MOV FLAPHC,#07H MOV FLAPLC,#20H ; Sets FLAPLC to the end address for verify (Example: Address ; 20H is specified here) MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started MOV A,PFS MOV CmdStatus,A ; Execution result is stored in variable ; (CmdStatus = 0: normal termination, other than 0: abnormal ; termination) ;---------------------------;END ;---------------------------- 262 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY 16.8.10 Examples of operation when command execution time should be minimized in self programming mode Examples of operation when the command execution time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <2> Execution of block erase Error check (<1> to <12> in 16.8.6) <3> Execution of block blank check Error check (<1> to <11> in 16.8.7) <4> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) Figure 16-25. Example of Operation When Command Execution Time Should Be Minimized (from Erasure to Blank Check) Erasure to blank check Figure 16-18 <1> to <7> <1> Shift to self programming mode <2> Execute block erase Figure 16-20 <1> to <12> <2> Check execution result (VCERR and WEPRERR flags) Abnormal Normal <3> Execute block blank check Figure 16-21 <1> to <11> <3> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 16-19 <1> to <6> <4> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark <1> to <4> in Figure 16-25 correspond to <1> to <4> in 16.8.10 (1) above. User's Manual U18172EJ3V0UD 263 CHAPTER 16 FLASH MEMORY An example of a program when the command execution time (from erasure to black check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------MOV MK0,#11111111B ; Masks all interrupts MOV FLCMD,#00H ; Clears FLCMD register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode with FLPMC register control (sets ; value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. FlashBlockErase: MOV FLCMD,#03H ; Sets flash control command (block erase) MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of ; here) ; FLAPH) MOV FLAPLC,#00H ; Fixes FLAPLC to "00H" MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started MOV A,PFS CMP A,#00H BNZ $StatusError ; Checks erase error ; Performs abnormal termination processing when an error ; occurs. FlashBlockBlankCheck: MOV FLCMD,#04H ; Sets flash control command (block blank check) MOV FLAPH,#07H ; Sets number of block for blank check (block 7 is specified ; here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets blank check block compare number (same value as of ; FLAPH) 264 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY MOV FLAPLC,#0FFH ; Fixes FLAPLC to "FFH" MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS CMP A,#00H BNZ $StatusError ; Checks blank check error ; Performs abnormal termination processing when an error ; occurs. MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) ModeOffLoop: BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. ; After the specific sequence is correctly executed, restore ; the CPU clock to its setting before the self programming MOV MK0,#INT_MK0 ; Restores interrupt mask flag EI BR StatusNormal ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: User's Manual U18172EJ3V0UD 265 CHAPTER 16 FLASH MEMORY (2) Write to internal verify <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <2> Specification of source data for write <3> Execution of byte write Error check (<1> to <10> in 16.8.8) <4> <3> is repeated until all data are written. <5> Execution of internal verify Error check (<1> to <11> in 16.8.9) <6> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) Figure 16-26. Example of Operation When Command Execution Time Should Be Minimized (from Write to Internal Verify) Write to internal verify Figure 16-18 <1> to <7> <1> Shift to self programming mode <2> Set source data for write <3> Execute byte write command Figure 16-22 <1> to <10> <3> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Yes <4> All data written? No <5> Execute internal verify command Figure 16-23 <1> to <11> <5> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 16-19 <1> to <6> <6> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark 266 <1> to <6> in Figure 16-26 correspond to <1> to <6> in 16.8.10 (2) above. User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY An example of a program when the command execution time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------MOV MK0,#11111111B ; Masks all interrupts MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode with FLPMC register control DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: ; (sets value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. FlashWrite: MOVW HL,#DataAdrTop ; Sets address at which data to be written is located MOVW DE,#WriteAdr ; Sets address at which data is to be written FLCMD,#05H ; Sets flash control command (byte write) FlashWriteLoop: MOV MOV A,D MOV FLAPH,A MOV A,E MOV FLAPL,A ; Sets address at which data is to be written ; Sets address at which data is to be written MOV A,[HL] MOV FLW,A ; Sets data to be written MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS CMP A,#00H BNZ $StatusError ; Checks write error ; Performs abnormal termination processing when an error ; occurs. INCW HL ; address at which data to be written is located + 1 MOVW AX,HL CMPW AX,#DataAdrBtm ; Performs internal verify processing BNC $FlashVerify ; if write of all data is completed User's Manual U18172EJ3V0UD 267 CHAPTER 16 FLASH MEMORY INCW DE BR FlashWriteLoop ; Address at which data is to be written + 1 FlashVerify: MOVW HL,#WriteAdr ; Sets verify address MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A MOV A,E MOV FLAPLC,A ; Sets verify end address MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Sets verify start address ; Sets verify start address ; Sets verify end address ; Self programming is started MOV A,PFS CMP A,#00H BNZ $StatusError ; Checks internal verify error ; Performs abnormal termination processing when an error ; occurs. MOV FLCMD,#00H ; Clears FLCMD register ModeOffLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. ; After the specific sequence is correctly executed, restore ; the CPU clock to its setting before the self programming MOV MK0,#INT_MK0 ; Restores interrupt mask flag EI BR StatusNormal ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: 268 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: ;--------------------------------------------------------------------; Data to be written ;--------------------------------------------------------------------DataAdrTop: DB XXH DB XXH DB XXH DB XXH : : DB XXH DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify s whole block. 16.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode Examples of operation when the interrupt-disabled time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1> Specification of block erase command (<1> to <5> in 16.8.6) <2> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <3> Execution of block erase command Error check (<6> to <12> in 16.8.6) <4> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) <5> Specification of block blank check command (<1> to <5> in 16.8.7) <6> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <7> Execution of block blank check command Error check (<6> to <11> in 16.8.7) <8> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) User's Manual U18172EJ3V0UD 269 CHAPTER 16 FLASH MEMORY Figure 16-27. Example of Operation When Interrupt-Disabled Time Should Be Minimized <R> (from Erasure to Blank Check) Erasure to blank check Figure 16-20 <1> to <5> <1> Specify block erase command Figure 16-18 <1> to <7> <2> Shift to self programming mode <3> Execute block erase command Figure 16-20 <6> to <12> <3> Check execution result Abnormal Normal Figure 16-19 <1> to <6> <4> Shift to normal mode Figure 16-21 <1> to <5> <5> Specify block blank check command Figure 16-18 <1> to <7> <6> Shift to self programming mode <7> Execute block blank check command Figure 16-21 <6> to <11> <7> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 16-19 <1> to <6> <8> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark 270 <1> to <8> in Figure 16-27 correspond to <1> to <8> in 16.8.11 (1) (previous page). User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY An example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------- <R> MOV B,#48 ; Specifies the number of times the erase command can be ; executed. ; (4.0 V to 5.5 V Time for executing block erasure 100 times) FlashBlockErase: ; Sets erase command <R> MOV FLCMD,#03H ; Sets flash control command (block erase) MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of FLAPH) MOV FLAPLC,#00H ; Fixes FLAPLC to "00H" CALL !ModeOn ; Shift to self programming mode EraseRetry: ; Execution of erase command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started MOV A,PFS CMP A,#00H BNZ $RetryCheck ; Checks erase error ; Performs abnormal termination processing when an error ; occurs. CALL !ModeOff ; Shift to normal mode ; Sets blank check command MOV FLCMD,#04H ; Sets flash control command (block blank check) MOV FLAPH,#07H ; Sets block number for blank check (block 7 is specified here) MOV FLAPL,#00H ; Fixes FLAPL to "00H" MOV FLAPHC,#07H ; Sets blank check block compare number (same value as that of MOV FLAPLC,#0FFH ; Fixes FLAPLC to "FFH" CALL !ModeOn ; Shift to self programming mode ; FLAPH) ; Execution of blank check command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS User's Manual U18172EJ3V0UD 271 CHAPTER 16 FLASH MEMORY CMP A,#00H BNZ $StatusError ; Checks blank check error ; Performs abnormal termination processing when an error occurs <R> CALL !ModeOff BR StatusNormal ; Shift to normal mode RetryCheck: DBNZ B,$EraseRetry ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: ;--------------------------------------------------------------------;Processing to shift to self programming mode ;--------------------------------------------------------------------ModeOn: MOV MK0,#11111111B ; Masks all interrupts MOV FLCMD,#00H ; Clears FLCMD register DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets ; value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. RET 272 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY ;--------------------------------------------------------------------; Processing to shift to normal mode ;--------------------------------------------------------------------ModeOffLoop: MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. ; After the specific sequence is correctly executed, restore ; the CPU clock to its setting before the self programming MOV MK0,#INT_MK0 ; Restores interrupt mask flag EI RET User's Manual U18172EJ3V0UD 273 CHAPTER 16 FLASH MEMORY (2) Write to internal verify <1> Specification of source data for write <2> Specification of byte write command (<1> to <4> in 16.8.8) <3> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <4> Execution of byte write command Error check (<5> to <10> in 16.8.8) <5> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) <6> <2> to <5> is repeated until all data are written. <7> The internal verify command is specified (<1> to <5> in 16.8.9) <8> Mode is shifted from normal mode to self programming mode (<1> to <7> in 16.8.4) <9> Execution of internal verify command Error check (<6> to <11> in 16.8.9) <10> Mode is shifted from self programming mode to normal mode (<1> to <6> in 16.8.5) 274 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY Figure 16-28. Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Write to Internal Verify) Write to internal verify <1> Set source data for write Figure 16-22 <1> to <4> <2> Specify byte write command Figure 16-18 <1> to <7> <3> Shift to self programming mode <4> Execute byte write command Figure 16-22 <5> to <10> <4> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 16-19 <1> to <6> <5> Shift to normal mode Yes <6> All data written? No Figure 16-23 <1> to <5> <7> Specify internal verify command Figure 16-18 <1> to <7> <8> Shift to self programming mode <9> Execute internal verify command Figure 16-23 <6> to <11> <9> Check execution result (VCERR and WEPRERR flags) Abnormal Normal Figure 16-19 <1> to <6> <10> Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing. Remark <1> to <10> in Figure 16-28 correspond to <1> to <10> in 16.8.11 (2) (previous page). User's Manual U18172EJ3V0UD 275 CHAPTER 16 FLASH MEMORY An example of a program when the interrupt-disabled time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------;START ;--------------------------------------------------------------------; Sets write command FlashWrite: MOVW HL,#DataAdrTop ; Sets address at which data to be written is located MOVW DE,#WriteAdr ; Sets address at which data is to be written MOV FLCMD,#05H ; Sets flash control command (byte write) MOV A,D MOV FLAPH,A MOV A,E MOV FLAPL,A MOV A,[HL] MOV FLW,A ; Sets data to be written CALL !ModeOn ; Shift to self programming mode FlashWriteLoop: ; Sets address at which data is to be written ; Sets address at which data is to be written ; Execution of write command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started MOV A,PFS CMP A,#00H BNZ $StatusError ; Checks write error ; Performs abnormal termination processing when an error ; occurs. CALL !ModeOff ; Shift to normal mode MOV MK0,#INT_MK0 ; Restores interrupt mask flag EI ; Judgment of writing all data INCW HL ; Address at which data to be written is located + 1 MOVW AX,HL CMPW AX,#DataAdrBtm ; Performs internal verify processing BNC $FlashVerify ; if write of all data is completed INCW DE ; Address at which data is to be written + 1 BR FlashWriteLoop ; Setting internal verify command 276 User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY FlashVerify: MOVW HL,#WriteAdr ; Sets verify address MOV FLCMD,#02H ; Sets flash control command (internal verify 2) MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A ; Sets verify start address ; Sets verify start address ; Sets verify end address MOV A,E MOV FLAPLC,A ; Sets verify end address CALL !ModeOn ; Shift to self programming mode ; Execution of internal verify command MOV PFS,#00H ; Clears flash status register MOV WDTE,#0ACH ; Clears & restarts WDT HALT MOV ; Self programming is started A,PFS CMP A,#00H BNZ $StatusError ; Checks internal verify error ; Performs abnormal termination processing when an error occurs CALL !ModeOff BR StatusNormal ; Shift to normal mode ;--------------------------------------------------------------------;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------StatusError: ;--------------------------------------------------------------------;END (normal termination processing) ;--------------------------------------------------------------------StatusNormal: ;--------------------------------------------------------------------;Processing to shift to self programming mode ;--------------------------------------------------------------------ModeOn: MOV MK0,#11111111B ; Masks all interrupts MOV FLCMD,#00H ; Clears FLCMD register User's Manual U18172EJ3V0UD 277 CHAPTER 16 FLASH MEMORY DI ; Configure settings so that the CPU clock 1 MHz ModeOnLoop: MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#01H ; FLPMC register control (sets value) MOV FLPMC,#0FEH ; FLPMC register control (inverts set value) MOV FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets ; value) NOP HALT BT PFS.0,$ModeOnLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. RET ;--------------------------------------------------------------------; Processing to shift to normal mode ;--------------------------------------------------------------------ModeOffLoop: MOV FLCMD,#00H ; Clears FLCMD register MOV PFS,#00H ; Clears flash status register MOV PFCMD,#0A5H ; PFCMD register control MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs. ; After the specific sequence is correctly executed, restore ; the CPU clock to its setting before the self programming MOV MK0,#INT_MK0 ; Restores interrupt mask flag EI RET ;--------------------------------------------------------------------;Data to be written ;--------------------------------------------------------------------DataAdrTop: 278 DB XXH DB XXH DB XXH User's Manual U18172EJ3V0UD CHAPTER 16 FLASH MEMORY DB XXH : : DB XXH DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify s whole block. User's Manual U18172EJ3V0UD 279 CHAPTER 17 ON-CHIP DEBUG FUNCTION 17.1 Connecting QB-MINI2 to 78K0S/KU1+ Note 1 The 78K0S/KU1+ uses RESET, X1 , X2 Note 2 , INTP1, VDD, and GND pins to communicate with the host machine via an on-chip debug emulator (QB-MINI2). <R> <R> Notes 1. PD78F920x: X1/P23/ANI3, PD78F950x: EXCLK/P23 <R> Caution The 78K0S/KU1+ has an on-chip debug function, which is provided for development and 2. PD78F920x: X2/P22/ANI2, PD78F950x: P22 evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used. Figure 17-1. Recommended Circuit Connection VDD VDD Target connector Target device GND RESET_OUT DATA VDD DATA R.F.U. R.F.U. H/SNote 4 CLK R.F.U. R.F.U. INTP R.F.U. CLK RESET_IN R.F.U. 3 to 10 k 1 2 RESETNote 1 3 X2Note 2 4 5 PD78F920x: X2 PD78F950x: P22 Note 3 VDD 6 VDD 7 1 k 8 9 10 X1Note 2 VDD VSS PD78F920x: X1 PD78F950x: EXCLK Note 3 11 12 INTP1Note 5 13 14 15 10 k 1 to 10 k VDD 16 1 k Reset circuit RESET signal Caution The constants described in the circuit connection example are reference values. If you perform flash programming aiming at mass production, thoroughly evaluate whether the specifications of the target device are satisfied. Note 1. The RESET pin is used to download the monitor program at debugger startup or to implement forced reset. Therefore, a pin that alternately functions as the RESET pin cannot be used. For reset pin connection, refer to QB-MINI2 User's Manual (U18371E). 280 User's Manual U18172EJ3V0UD CHAPTER 17 ON-CHIP DEBUG FUNCTION Notes 2. This is the pin connection when the X1 and X2 pins are not used in the target system. When using the X1 and X2 pins, refer to 17.1.2 Connection of X1 and X2 pins. 3. No problem will occur if the dashed line portions are connected. 4. This pin is connected to enhance the accuracy of time measurement between run and break during debugging. Debugging is possible even if this pin is left open, but measurement error occurs in several ms units. 5. The INTP1 pin is used for communication between QB-MINI2 and the target device during debugging. When debugging is performed with QB-MINI2, therefore, the INTP1 pin and its alternate-function pin cannot be used. For INTP1 pin connection, refer to 17.1.1 Connection of INTP1 pin. Pins for communication depend on whether the monitor program has been written or not. (refer to Table 17-1) X1 and X2 pins can be used as I/O port pins or the pins for oscillation, after the monitor program has been written. Table 17-1. Pins for communication with QB-MINI2 Before writing the monitor program X1 <R> <R> Note 1 , X2 Note 2 , RESET, INTP1, VDD, VSS After writing the monitor program RESET, INTP1, VDD, VSS Notes 1. PD78F920x: X1/P23/ANI3, PD78F950x: EXCLK/P23 2. PD78F920x: X2/P22/ANI2, PD78F950x: P22 17.1.1 Connection of INTP1 pin The INTP1 pin is used only for communication between QB-MINI2 and the target device during debugging. Design circuits appropriately according to the relevant case among the cases shown below. (1) INTP1 pin is not used in target system (as is illustrated in Figure 17-1. Recommended Circuit Connection) See Figure 17-2. (2) QB-MINI2 is used only for programming, not for debugging See Figure 17-3. (3) QB-MINI2 is used for debugging and debugging of the INTP1 pin is performed only with a real machine See Figure 17-4. Figure 17-2. Circuit Connection for the Case Where INTP1 Pin Is Not Used in Target System VDD Target device Target connector 1 k INTP 12 INTP1 Figure 17-3. Circuit Connection for the Case Where QB-MINI2 Is Used Only for Programming Target device Target connector INTP 12 User's Manual U18172EJ3V0UD INTP1 281 CHAPTER 17 ON-CHIP DEBUG FUNCTION Figure 17-4. Circuit Connection for the Case Where QB-MINI2 Is Used for Debugging and Debugging of INTP1 Pin Is Performed Only with Real Machine VDD Target connector 1 k INTP Target device 1 12 2 3 INTP1 External device I/O to INTP1 * Jumper setting Caution When debugging with QB-MINI2 connected: 1-2 shorted Other than above: 2-3 shorted If debugging is performed with a real machine running, without using QB-MINI2, write the user program using the QB-Programmer. Programs downloaded by the debugger include the monitor program, and such a program malfunctions if it is not controlled via QB-MINI2. 17.1.2 Connection of X1 and X2 pins Note 1 The X1 , X2 Note 2 pins are used when the debugger is started for the first time (when downloading the monitor program) and when programming is performed with the QB-Programmer. <R> <R> Notes 1. PD78F920x: X1/P23/ANI3, PD78F950x: EXCLK/P23 2. PD78F920x: X2/P22/ANI2, PD78F950x: P22 Figure 17-5. Circuit Connection for the Case Where X1 and X2 Pins Are Used in Target System Target connector X2 Target device 3 1 2 3 X1 9 X2 PD78F920x: X2 PD78F950x: P22 1 2 3 X1 PD78F920x: X1 PD78F950x: EXCLK External components Oscillator or external device * Jumper setting When debugger is started for the first time (downloading the monitor program) or when 282 programming is performed with QB-Programmer: 1-2 shorted Other than above: 2-3 shorted User's Manual U18172EJ3V0UD CHAPTER 17 ON-CHIP DEBUG FUNCTION 17.2 Securing of user resources The user must prepare the following to perform communication between QB-MINI2 and the target device and implement each debug function. For details of the setting, refer to QB-MINI2 User's Manual (U18371E). * Securement of memory space The shaded portions in Figure 17-6 are the areas reserved for placing the debug monitor program, so user programs cannot be allocated in these spaces. Figure 17-6. Memory Spaces Where Debug Monitor Programs Are Allocated Internal ROM space 304 bytes Internal RAM space Internal RAM end address Internal ROM end address Stack area for debugging (5 bytes) for software break (2 bytes) 0x7EH INTP1 interrupt vector (2 bytes) 0x18H * Securement of serial interface for communication The register settings, concerning the INTP1 pin used for communication between QB-MINI2 and the target device, performed by the debug monitor program must not be changed. User's Manual U18172EJ3V0UD 283 CHAPTER 18 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78K0S/KU1+. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E). 18.1 Operation 18.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 18-1. Operand Identifiers and Description Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp sfr AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even addresses only) addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) addr5 0040H to 007FH Immediate data or labels (even addresses only) word 16-bit immediate data or label byte bit 8-bit immediate data or label 3-bit immediate data or label Remark 284 For symbols of special function registers, see Table 3-3 Special Function Registers. User's Manual U18172EJ3V0UD CHAPTER 18 INSTRUCTION SET OVERVIEW 18.1.2 Description of "Operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag ( ): Memory contents indicated by address or register contents in parentheses xH, xL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : : Exclusive logical sum (exclusive OR) Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 18.1.3 Description of "Flag" column (Blank): Unchanged 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is stored User's Manual U18172EJ3V0UD 285 CHAPTER 18 INSTRUCTION SET OVERVIEW 18.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag Z MOV XCH r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A 1 4 AX 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A sfr A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL, byte] 2 8 A (HL + byte) A, X A, r Notes 1. 2. Remark Note 2 x x x x x x Except r = A. Except r = A, X. One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 286 AC CY User's Manual U18172EJ3V0UD CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z MOVW rp, #word 3 6 rp word AX, saddrp 2 6 AX (saddrp) AC CY 2 8 (saddrp) AX AX, rp Note 1 4 AX rp rp, AX Note 1 4 rp AX XCHW AX, rp Note 1 8 AX rp ADD A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) x x x saddrp, AX ADDC SUB Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U18172EJ3V0UD 287 CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z SUBC AND OR XOR Remark A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 288 AC CY User's Manual U18172EJ3V0UD CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z AC CY A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL + byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am-1 Am) x 1 x ROL A, 1 1 2 (CY, A0 A7, Am+1 Am) x 1 x RORC A, 1 1 2 (CY A0, A7 CY, Am-1 Am) x 1 x ROLC A, 1 1 2 (CY A7, A0 CY, Am+1 Am) x 1 x SET1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 A.bit 2 4 A.bit 1 PSW.bit 3 6 PSW.bit 1 [HL].bit 2 10 (HL).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 A.bit 2 4 A.bit 0 PSW.bit 3 6 PSW.bit 0 [HL].bit 2 10 (HL).bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CMP DEC CLR1 Remark x x x x x x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U18172EJ3V0UD 289 CHAPTER 18 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 8 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 PUSH POP SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X BC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable Interrupt) DI 3 6 IE 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode MOVW BR BF DBNZ Remark R R R R R R One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 290 AC CY User's Manual U18172EJ3V0UD CHAPTER 18 INSTRUCTION SET OVERVIEW 18.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None 1st Operand A r ADD MOVNote MOV MOV ADDC XCHNote XCH SUB ADD ADD SUBC ADDC ADDC AND SUB OR XOR CMP MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD ADD RORC ADDC ADDC ADDC ROLC SUB SUB SUB SUB SUBC SUBC SUBC SUBC SUBC AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP XCH MOV MOV MOV INC DEC B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC DEC ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] MOV [HL] MOV [HL + byte] MOV Note Except r = A. User's Manual U18172EJ3V0UD 291 CHAPTER 18 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX rp ADDW SUBW MOVW CMPW XCHW MOVW MOVW MOVW Note MOVW INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand A.bit sfr.bit saddr.bit PSW.bit BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 [HL].bit SET1 CLR1 CY SET1 CLR1 NOT1 292 User's Manual U18172EJ3V0UD CHAPTER 18 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User's Manual U18172EJ3V0UD 293 CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Input voltage Analog input voltage Output current, high Output current, low Operating ambient Ratings Unit VDD -0.3 to +6.5 V VSS -0.3 to +0.3 Note 2 -0.3 to VDD + 0.3 V VO -0.3 to VDD + 0.3 Note 1 V VAN -0.3 to VDD + 0.3 Note 1 V IOH IOL TA temperature Notes 1. 2. P20 to P23, P32, P34, P40, P43 Per pin -10.0 mA Total of P20 to P23, P32, P40, P43 -44.0 mA Per pin 20.0 mA Total of P20 to P23, P32, P40, P43 44.0 mA -40 to +85 C Flash memory blank status -65 to +150 C Flash memory programming already performed -40 to +125 C In normal operation mode During flash memory programming Storage temperature <R> V Note 1 VI Output voltage Conditions Tstg Must be 6.5 V or lower PD78F920x only Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 294 User's Manual U18172EJ3V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS X1 Oscillator Characteristics (1) PD78F920x (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Recommended Circuit VSS X1 Ceramic X2 Parameter Conditions Oscillation MIN. TYP. MAX. Unit 2.0 10.0 MHz 2.0 10.0 MHz MHz Note 2 frequency (fX) resonator C1 C2 VSS X1 Crystal X2 Oscillation Note 2 frequency (fX) resonator C1 External C2 X1 2.7 V VDD 5.5 V 2.0 10.0 frequency (fX) 2.0 V VDD < 2.7 V 2.0 5.0 X1 input high- 2.7 V VDD 5.5 V 0.045 0.25 /low-level width 2.0 V VDD < 2.7 V 0.09 0.25 X1 input Note 2 clock (tXH, tXL) s Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. <R> (2) PD78F950x (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator External clock Recommended Circuit Parameter EXCLK External main system clock frequency (fEXCLK) Note 2 External main system clock input high-/low-level width (tEXCLKH, tEXCLKL) Notes 1. Conditions MIN. TYP. MAX. Unit MHz 2.7 V VDD 5.5 V 2.0 10.0 2.0 V VDD < 2.7 V 2.0 5.0 2.7 V VDD 5.5 V 0.045 0.25 2.0 V VDD < 2.7 V 0.09 0.25 s Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. User's Manual U18172EJ3V0UD 295 CHAPTER 19 ELECTRICAL SPECIFICATIONS High-Speed Internal Oscillator Characteristics (1) PD78F920x (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator Parameter Conditions High-speed internal Oscillation frequency (fX = 8 oscillator MHz 2.7 V VDD 5.5 V Note 2 ) deviation Oscillation frequency (fX) Notes 1. MAX. Unit TA = -10 to +70C 3 % TA = -40 to +85C 5 % 2.0 V VDD < 2.7 V Note 2 MIN. TYP. 5.5 MHz Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V 0.1 V. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. <R> (2) PD78F950x (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) Resonator High-speed internal Parameter Conditions 2.7 V VDD 5.5 V Note 2 Oscillation frequency (fX) oscillator MAX. Unit TA = -10 to +85C 2 % TA = -40 to +85C 5 % 2.0 V VDD < 2.7 V Notes 1. MIN. TYP. 5.5 MHz Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V 0.1 V. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Low-Speed Internal Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V Resonator Low-speed internal oscillator Note Parameter Conditions Oscillation frequency (fRL) , VSS = 0 V) MIN. TYP. MAX. Unit 120 240 480 kHz Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. 296 Note User's Manual U18172EJ3V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (1/4) (1) PD78F920x (TA = -40 to +85C, VDD = 2.0 to 5.5 V Note, VSS = 0 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Symbol IOH IOL VIH1 Conditions MIN. TYP. MAX. Unit Per pin 2.0 V VDD 5.5 V -5 mA Total of all pins 4.0 V VDD 5.5 V -25 mA 2.0 V VDD < 4.0 V -15 mA Per pin 2.0 V VDD 5.5 V 10 mA Total of all pins 4.0 V VDD 5.5 V 30 mA 2.0 V VDD < 4.0 V 15 mA 0.8VDD VDD V 0.7VDD VDD V 0 0.2VDD V 0 0.3VDD V P23 in external clock mode and pins other than P20 and P21 VIH2 P23 in other than external clock mode, P20 and P21 Input voltage, low VIL1 P23 in external clock mode and pins other than P20 and P21 VIL2 P23 in other than external clock mode, P20 and P21 Output voltage, high Output voltage, low VOH VOL Total of output pins 4.0 V VDD 5.5 V IOH = -15 mA IOH = -5 mA IOH = -100 A 2.0 V VDD < 4.0 V Total of output pins 4.0 V VDD 5.5 V IOL = 30 mA VDD - 1.0 V VDD - 0.5 V 1.3 V 0.4 V IOL = 10 mA 2.0 V VDD < 4.0 V IOL = 400 A Input leakage current, high ILIH VI = VDD Pins other than X1 1 A Input leakage current, low ILIL VI = 0 V Pins other than X1 -1 A Output leakage current, high ILOH VO = VDD Pins other than X2 1 A Output leakage current, low ILOL VO = 0 V Pins other than X2 -1 A Pull-up resistance value RPU VI = 0 V 10 30 100 k Pull-down resistance value RPD P22, P23, reset status 10 30 100 k Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U18172EJ3V0UD 297 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (2/4) (1) PD78F920x (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2) Parameter Note 3 Supply current Symbol IDD1 Note 2 Conditions MIN. TYP. MAX. Unit Crystal/ceramic fX = 10 MHz When A/D converter is stopped 6.1 12.2 oscillation, VDD = 5.0 V 10% When A/D converter is operating 7.6 15.2 fX = 6 MHz When A/D converter is stopped 5.5 11.0 external clock input oscillation operating mode mA Note 4 Note 6 VDD = 5.0 V 10% When A/D converter is operating fX = 5 MHz mA Note 4 14.0 When A/D converter is stopped 3.0 6.0 VDD = 3.0 V 10% When A/D converter is operating 4.5 9.0 Crystal/ceramic fX = 10 MHz When peripheral functions are stopped 1.7 3.8 oscillation, VDD = 5.0 V 10% When peripheral functions are operating fX = 6 MHz When peripheral functions are stopped mA Note 5 IDD2 external clock input HALT mode mA Note 4 VDD = 5.0 V 10% When peripheral functions are operating fX = 5 MHz When peripheral functions are stopped 6.7 1.3 3.0 mA Note 4 Note 6 6.0 0.48 1 VDD = 3.0 V 10% When peripheral functions are operating High-speed fX = 8 MHz When A/D converter is stopped 5.0 10.0 internal oscillation VDD = 5.0 V 10% When A/D converter is operating 6.5 13.0 High-speed fX = 8 MHz When peripheral functions are stopped 1.4 3.2 internal oscillation VDD = 5.0 V 10% When peripheral functions are operating VDD = 5.0 V 10% When low-speed internal oscillation mA Note 5 Note 3 IDD3 2.1 mA Note 4 operating Note 7 mode IDD4 mA Note 4 Note 7 5.9 HALT mode IDD5 STOP mode 3.5 20.0 17.5 32.0 3.5 15.5 11.0 26.0 A is stopped When low-speed internal oscillation is operating VDD = 3.0 V 10% When low-speed internal oscillation A is stopped When low-speed internal oscillation is operating Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on 2. Total current flowing through the internal power supply (VDD). However, the current that flows through the 3. IDD1 and IDD3 include peripheral operation current. 4. When the processor clock control register (PCC) is set to 00H. 5. When the processor clock control register (PCC) is set to 02H. clear (POC) circuit is 2.1 V 0.1 V. pull-up resistors of ports is not included. 6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using the option byte. 7. 298 When high-speed internal oscillation clock is selected as the system clock source using the option byte. User's Manual U18172EJ3V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (3/4) <R> (2) PD78F950x (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote, VSS = 0 V) (1/2) Parameter Output current, high Output current, low Symbol IOH IOL Conditions MIN. TYP. MAX. Unit Per pin 2.0 V VDD 5.5 V -5 mA Total of all pins 4.0 V VDD 5.5 V -25 mA 2.0 V VDD < 4.0 V -15 mA Per pin 2.0 V VDD 5.5 V 10 mA Total of all pins 4.0 V VDD 5.5 V 30 mA 2.0 V VDD < 4.0 V 15 mA Input voltage, high VIH1 0.8VDD VDD V Input voltage, low VIL1 0 0.2VDD V Output voltage, high VOH Output voltage, low VOL Total of output pins 4.0 V VDD 5.5 V IOH = -15 mA IOH = -5 mA IOH = -100 A 2.0 V VDD < 4.0 V Total of output pins 4.0 V VDD 5.5 V IOL = 30 mA IOL = 10 mA VDD - 1.0 V VDD - 0.5 V 2.0 V VDD < 4.0 V 1.3 V 0.4 V IOL = 400 A Input leakage current, high ILIH VI = VDD Pins other than EXCLK 1 A Input leakage current, low ILIL VI = 0 V Pins other than EXCLK -1 A Output leakage current, high ILOH VO = VDD Pins other than EXCLK 1 A Pins other than EXCLK Output leakage current, low ILOL VO = 0 V -1 A Pull-up resistance value RPU VI = 0 V 10 30 100 k VI = 0 V (P34, reset status) 10 30 100 k Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U18172EJ3V0UD 299 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (4/4) <R> (2) PD78F950x (TA = -40 to +85C, VDD = 2.0 to 5.5 VNote 1, VSS = 0 V) (2/2) Parameter Note 3 Supply current Symbol IDD1 Note 2 Conditions External clock fX = 10 MHz input oscillation VDD = 5.0 V 10% operating mode MIN. TYP. MAX. Unit fX = 6 MHz Note 6 6.1 12.2 mA 5.5 11.0 mA 3.0 6.0 mA 1.7 3.8 mA Note 4 VDD = 5.0 V 10% Note 4 fX = 5 MHz VDD = 3.0 V 10% Note 5 IDD2 External clock fX = 10 MHz input HALT VDD = 5.0 V 10% When peripheral functions are operating fX = 6 MHz When peripheral functions are stopped mode When peripheral functions are stopped Note 4 Note 6 VDD = 5.0 V 10% When peripheral functions are operating fX = 5 MHz When peripheral functions are stopped 6.7 1.3 3.0 mA Note 4 VDD = 3.0 V 10% 6.0 0.48 1 mA Note 5 Note 3 IDD3 High-speed fX = 8 MHz internal oscillation VDD = 5.0 V 10% When peripheral functions are operating 2.1 5.0 10.0 mA 1.4 3.2 mA Note 4 operating Note 7 mode IDD4 High-speed fX = 8 MHz internal oscillation VDD = 5.0 V 10% When peripheral functions are operating VDD = 5.0 V 10% When low-speed internal oscillation is When peripheral functions are stopped Note 4 Note 7 5.9 HALT mode IDD5 STOP mode 3.5 20.0 17.5 32.0 3.5 15.5 11.0 26.0 A stopped When low-speed internal oscillation is operating VDD = 3.0 V 10% When low-speed internal oscillation is A stopped When low-speed internal oscillation is operating Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. 2. Total current flowing through the internal power supply (VDD). However, the current that flows through the pull-up resistors of ports is not included. 300 3. IDD1 and IDD3 include peripheral operation current. 4. When the processor clock control register (PCC) is set to 00H. 5. When the processor clock control register (PCC) is set to 02H. 6. When external clock input is selected as the system clock source using the option byte. 7. When high-speed internal oscillation clock is selected as the system clock source using the option byte. User's Manual U18172EJ3V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Characteristics Basic operation (TA = -40 to +85C, VDD = 2.0 to 5.5 V Parameter Symbol Cycle time (minimum TCY tINTH, width, low-level width tINTL RESET input low-level tRSL MAX. Unit 16 s 3.0 V VDD < 4.0 V 0.33 16 s 2.7 V VDD < 3.0 V 0.4 16 s 2.0 V VDD < 2.7 V 1 16 s High-speed internal 4.0 V VDD 5.5 V 0.23 4.22 s oscillation clock 2.7 V VDD < 4.0 V 0.47 4.22 s 2.0 V VDD < 2.7 V 0.95 4.22 s 4.0 V VDD 5.5 V 2/fsam+ Note 3 0.1 s 2.0 V VDD < 4.0 V 2/fsam+ Note 3 0.2 s 1 s 2 s tTIL Interrupt input high-level TYP. 0.2 , external clock input tTIH, MIN. 4.0 V VDD 5.5 V Crystal/ceramic oscillation clock TI000 input high-level width, Note 2 low-level width , VSS = 0 V) Conditions Note 2 instruction execution time) Note 1 width Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. <R> 2. PD78F920x only 3. Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP. CPU Clock Frequency, Peripheral Clock Frequency Parameter Ceramic resonator crystal resonator Conditions Note 1 Note 1 external clock , , 4.0 to 5.5 V 125 kHz fCPU 10 MHz 3.0 to 4.0 V 125 kHz fCPU 6 MHz High-speed internal 4.0 to 5.5 V oscillator 2.7 to 4.0 V 2.0 to 2.7 V Peripheral Clock (fXP) 500 kHz fXP 10 MHz 125 kHz fCPU 5 MHz 2.7 to 3.0 V 2.0 to 2.7 V <R> CPU Clock (fCPU) Note 2 125 kHz fCPU 2 MHz 500 kHz fXP 5 MHz 500 kHz (TYP.) fCPU 8 MHz (TYP.) 2 MHz (TYP.) fXP 8 MHz (TYP.) 500 kHz (TYP.) fCPU 4 MHz (TYP.) Note 2 500 kHz (TYP.) fCPU 2 MHz (TYP.) 2 MHz (TYP.) fXP 4 MHz (TYP.) Notes 1. PD78F920x only 2. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. User's Manual U18172EJ3V0UD 301 CHAPTER 19 ELECTRICAL SPECIFICATIONS Note TCY vs. VDD (Crystal/Ceramic Oscillation Clock , External Clock Input) 60 16 Cycle time TCY [s] 10 Guaranteed operation range 1.0 0.4 0.33 0.1 1 2 2.7 3 4 5 5.5 6 Supply voltage VDD [V] Note PD78F920x only <R> TCY vs. VDD (High-speed internal oscillator Clock) 60 Cycle time TCY [s] 10 4.22 Guaranteed operation range 1.0 0.95 0.47 0.23 0.1 1 302 2 3 4 5 6 2.7 5.5 Supply voltage VDD [V] User's Manual U18172EJ3V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH X1 input, EXCLK input TI000 Timingv (PD78F920x only) tTIL tTIH TI000 Interrupt Input Timing tINTL tINTH INTP0, INTP1 RESET Input Timing tRSL RESET User's Manual U18172EJ3V0UD 303 CHAPTER 19 ELECTRICAL SPECIFICATIONS <R> A/D Converter Characteristics (TA = -40 to +85C, 2.7 V VDD 5.5 VNote 1, VSS = 0 VNote 2) (PD78F920x only) (1) A/D converter basic characteristics Parameter Symbol Conditions Resolution Conversion time tCONV Analog input voltage MIN. TYP. MAX. Unit 10 10 10 bit 4.5 V VDD 5.5 V 3.0 100 s 4.0 V VDD < 4.5 V 4.8 100 s 2.85 V VDD < 4.0 V 6.0 100 s 2.7 V VDD < 2.85 V 14.0 100 s VDD V Note 2 VAIN VSS (2) A/D Converter Characteristics (high-speed internal oscillation clock) Parameter Symbol Notes 3, 4 Overall error Notes 3, 4 Zero-scale error Full-scale error Notes 3, 4 Note 3 Integral non-linearity error Differential non-linearity error Note 3 Conditions MIN. TYP. MAX. Unit AINL -0.1 to +0.2 Note 5 -0.35 to +0.45 %FSR Ezs -0.1 to +0.2 Note 5 -0.35 to +0.45 %FSR Efs -0.1 to +0.2 Note 5 ILE DLE -0.35 to +0.40 %FSR Note 5 1 3 LSB 1 Note 5 1.5 LSB MAX. Unit (3) A/D Converter Characteristics (Crystal/Ceramic Oscillation Clock, External Clock) Parameter Symbol Notes 3, 4 Overall error AINL Notes 3, 4 Zero-scale error Full-scale error Ezs Notes 3, 4 Efs Note 3 Integral non-linearity error Differential non-linearity error Notes 1. Note 3 ILE DLE Conditions MIN. TYP. 4.0 V VDD 5.5 V -0.20 to +0.35 -0.35 to +0.65 %FSR 2.7 V VDD < 4.0 V 0.25 Note 5 -0.35 to +0.55 %FSR 4.0 V VDD 5.5 V -0.20 to +0.35 -0.35 to +0.65 %FSR 2.7 V VDD < 4.0 V 0.25 -0.35 to +0.55 %FSR Note 5 Note 5 Note 5 4.0 V VDD 5.5 V -0.20 to +0.35 -0.35 to +0.55 %FSR 2.7 V VDD < 4.0 V 0.25 -0.35 to +0.50 %FSR 4.0 V VDD 5.5 V 1.5 Note 5 3.0 LSB 2.7 V VDD < 4.0 V 1.5 Note 5 4.0 LSB 4.0 V VDD 5.5 V 1.0 Note 5 2.5 LSB 2.7 V VDD < 4.0 V 1.0 Note 5 2.5 LSB Note 5 Note 5 In PD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). 2. In PD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 3. Excludes quantization error (1/2 LSB). 4. This value is indicated as a ratio (%FSR) to the full-scale value. 5. A value when HALT mode is set by an instruction immediately after A/D conversion starts. Caution The conversion accuracy may be degraded when the analog input pin is used as an alternate I/O port or if the level of a port that is not used for A/D conversion is changed during A/D conversion. 304 User's Manual U18172EJ3V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS POC Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Conditions VPOC Detection voltage MIN. TYP. MAX. Unit 2.0 2.1 2.2 V s tPTH VDD: 0 V 2.1 V Response delay time 1 Note 1 tPTHD When power supply rises, after reaching detection voltage (MAX.) 3.0 ms Response delay time 2 Note 2 tPD When power supply falls 1.0 ms Power supply rise time Minimum pulse width 1.5 tPW 0.2 ms Notes 1. Time required from voltage detection to internal reset release. 2. Time required from voltage detection to internal reset signal generation. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time User's Manual U18172EJ3V0UD 305 CHAPTER 19 ELECTRICAL SPECIFICATIONS LVI Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Detection voltage Note 1 Response time TYP. MAX. Unit VLVI0 4.1 4.3 4.5 V VLVI1 3.9 4.1 4.3 V VLVI2 3.7 3.9 4.1 V VLVI3 3.5 3.7 3.9 V VLVI4 3.3 3.5 3.7 V VLVI5 3.15 3.3 3.45 V VLVI6 2.95 3.1 3.25 V VLVI7 2.7 2.85 3.0 V VLVI8 2.5 2.6 2.7 V VLVI9 2.25 2.35 2.45 V 0.2 2.0 ms tLW Operation stabilization wait time 2. MIN. tLD Minimum pulse width Notes 1. Conditions Note 2 0.2 tLWAIT ms 0.1 0.2 ms Time required from voltage detection to interrupt output or internal reset signal generation. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9 2. VPOC < VLVIm (m = 0 to 9) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tLWAIT LVION tLD 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Conditions MIN. Data retention supply voltage VDDDR 2.0 Release signal set time tSREL 0 306 User's Manual U18172EJ3V0UD TYP. MAX. Unit 5.5 V s CHAPTER 19 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics (TA = -40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Note 1 Erasure count Symbol Conditions IDD VDD = 5.5 V NERASE TA = -40 to +85C MIN. TYP. MAX. Unit 7.0 mA 1000 Times (per 1 block) Chip erase time Block erase time TCERASE TBERASE TA = -10 to +85C, 4.5 V VDD 5.5 V 0.8 s NERASE 100 3.5 V VDD < 4.5 V 1.0 s 2.7 V VDD < 3.5 V 1.2 s TA = -10 to +85C, 4.5 V VDD 5.5 V 4.8 s NERASE 1000 3.5 V VDD < 4.5 V 5.2 s 2.7 V VDD < 3.5 V 6.1 s TA = -40 to +85C, 4.5 V VDD 5.5 V 1.6 s NERASE 100 3.5 V VDD < 4.5 V 1.8 s 2.7 V VDD < 3.5 V 2.0 s TA = -40 to +85C, 4.5 V VDD 5.5 V 9.1 s NERASE 1000 3.5 V VDD < 4.5 V 10.1 s 2.7 V VDD < 3.5 V 12.3 s TA = -10 to +85C, 4.5 V VDD 5.5 V 0.4 s NERASE 100 3.5 V VDD < 4.5 V 0.5 s 2.7 V VDD < 3.5 V 0.6 s TA = -10 to +85C, 4.5 V VDD 5.5 V 2.6 s NERASE 1000 3.5 V VDD < 4.5 V 2.8 s 2.7 V VDD < 3.5 V 3.3 s 4.5 V VDD 5.5 V 0.9 s TA = -40 to +85C, NERASE 100 3.5 V VDD < 4.5 V 1.0 s 2.7 V VDD < 3.5 V 1.1 s TA = -40 to +85C, 4.5 V VDD 5.5 V 4.9 s NERASE 1000 3.5 V VDD < 4.5 V 5.4 s 2.7 V VDD < 3.5 V 6.6 s Byte write time TWRITE TA = -40 to +85C, NERASE 1000 150 s Internal verify TVERIFY Per 1 block 6.8 ms Per 1 byte 27 s Blank check TBLKCHK Retention years Per 1 block 480 , NERASE 1000 Note 2 TA = 85C 10 s Years Notes 1. Depending on the erasure count (NERASE), the erase time varies. Refer to the chip erase time and block erase time parameters. 2. When the average temperature when operating and not operating is 85C. Remark When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. User's Manual U18172EJ3V0UD 307 CHAPTER 20 PACKAGE DRAWING 10-PIN PLASTIC SSOP (5.72 mm (225)) V 10 detail of lead end 6 T I P 5 1 L U V A W W F H G J S E B C K N S D M M (UNIT:mm) ITEM A B 3.60 0.10 0.50 C 0.65 (T.P.) NOTE D 0.24 0.08 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. E 0.100.05 F 1.45 MAX. G 1.20 0.10 H 6.40 0.20 I 4.400.10 J K 1.000.20 + 0.08 0.17 0.07 L 0.50 M 0.13 N T 0.10 + 5 3 3 0.25 (T.P.) U 0.600.15 P V W 308 DIMENSIONS User's Manual U18172EJ3V0UD 0.25 MAX. 0.15 MAX. P10MA-65-CAC CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Caution For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 21-1. Surface Mounting Type Soldering Conditions <R> * 10-pin plastic SSOP (lead-free products) PD78F9200MA-CAC-A, 78F9201MA-CAC-A, 78F9202MA-CAC-A, 78F9500MA-CAC-A, 78F9501MA-CAC-A, 78F9502MA-CAC-A Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Note Count: 3 times or less, Exposure limit: 7 days 10 to 72 hours) Recommended Condition Symbol IR60-107-3 (after that, prebake at 125C for Wave soldering For details, contact an NEC Electronics sales representative. - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). User's Manual U18172EJ3V0UD 309 APPENDIX A DEVELOPMENT TOOLS <R> The following development tools are available for development of systems using the 78K0S/KU1+. Figure A-1 shows the development tool configuration. 310 User's Manual U18172EJ3V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools (1/2) (1) When using the in-circuit emulator QB-78K0SKX1 Software package * Software package Debugging software Language processing software * Assembler package * Integrated debuggerNote 1 * C compiler package * System simulatorNote 2 * Device fileNote 1 Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 Power supply unit QB-78K0SKX1Note 4 < Flash memory write environment > Flash memory programmerNote 4 Off-board programming Emulation probe On-board programming Conversion adapter Flash memory write adapter 78K0/Kx1+ Target connector Target system Notes 1. Download the device file for 78K0S/Kx1+ microcontrollers (DF789234) and the integrated debugger ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/). 2. SM+ for 78K0S (instruction simulation version) is included in the software package. SM+ for 78K0S/Kx1+ (instruction + peripheral simulation version) is not included. 3. The project manager PM+ is included in the assembler package. PM+ cannot be used other than with WindowsTM. 4. QB-78K0SKX1 is supplied with the integrated debugger ID78K0S-QB, a USB interface cable, the onchip debug emulator with programming function QB-MINI2, a connection cable, and a target cable. Any other products are sold separately. User's Manual U18172EJ3V0UD 311 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools (2/2) (2) When using the on-chip debug emulator with programming function QB-MINI2 Software package * Software package Debugging software Language processing software * Assembler package * Integrated debuggerNote 1 * C compiler package * System simulatorNote 2 * Device fileNote 1 Control software * Project manager (Windows only)Note 3 Host machine (PC or EWS) USB interface cableNote 4 QB-MINI2Note 4 Connection cableNote 4 Target connector Target system Notes 1. Download the device file for 78K0S/Kx1+ microcontrollers (DF789234) and the integrated debugger ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/). 2. SM+ for 78K0S (instruction simulation version) is included in the software package. SM+ for 78K0S/Kx1+ (instruction + peripheral simulation version) is not included. 3. The project manager PM+ is included in the assembler package. 4. QB-MINI2 is supplied with USB interface cable and connection cable. Any other products are sold PM+ cannot be used other than with Windows. separately. In addition, download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/). 312 User's Manual U18172EJ3V0UD APPENDIX A DEVELOPMENT TOOLS A.1 Software Package Development tools (software) common to the 78K0S microcontrollers are combined in this package. SP78K0S 78K0S microcontroller software package A.2 Language Processing Software RA78K0S Note 1 This assembler converts programs written in mnemonics into object codes executable with a Assembler package microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF789234). <Precaution when using RA78K0S in PC environment> This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (PM+) on Windows. PM+ is included in assembler package. CC78K0S Note 1 This compiler converts programs written in C language into object codes executable with a C compiler package microcontroller. This compiler should be used in combination with an assembler package and device file. <Precaution when using CC78K0S in PC environment> This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (PM+) on Windows. PM+ is included in assembler package. Note 2 DF789234 This file contains information peculiar to the device. Device file This device file should be used in combination with a tool (RA78K0S, CC78K0S, ID78K0S-QB, and the system simulator). The corresponding OS and host machine differ depending on the tool to be used. Notes 1. If the versions of RA78K0S and CC78K0S are Ver.2.00 or later, different versions of RA78K0S and 2. The DF789234 can be used in common with the RA78K0S, CC78K0S, ID78K0S-QB, and the system CC78K0S can be installed on the same machine. simulator. Download the DF789234 from the download site for development tools (http://www.necel.com/micro/en/ods/). User's Manual U18172EJ3V0UD 313 APPENDIX A DEVELOPMENT TOOLS A.3 Flash Memory Writing Tools A.3.1 When using flash memory programmer PG-FP5 and FL-PR5 FL-PR5, PG-FP5 This is a flash memory programmer dedicated to microcontrollers incorporating a flash Flash memory programmer memory. FA-78F9202MA-CAC-RX Flash memory writing adapter This is a flash memory writing adapter which is used in connection with the flash memory programmer. Remarks 1. FL-PR5 and FA-78F9202MA-CAC-RX are products of Naito Densei Machida Mfg. Co., Ltd (http://www.ndk-m.co.jp/, e-mail: info@ndk-m.co.jp). 2. Use the latest version of the flash memory programming adapter. A.3.2 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 This is a flash memory programmer dedicated to microcontrollers with on-chip flash On-chip debug emulator with memory. It is available also as on-chip debug emulator which serves to debug hardware programming function and software when developing application systems using the 78K0S/Kx1+ microcontrollers. When using this as flash memory programmer, it should be used in combination with a connection cable and a USB interface cable that is used to connect the host machine. Target connector specifications 16-pin general-purpose connector (2.54 mm pitch) Remark Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/). A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator QB-78K0SKX1 QB-78K0SKX1 This in-circuit emulator serves to debug hardware and software when developing application In-circuit emulator systems using the 78K0S/Kx1+ microcontrollers. It supports the integrated debugger (ID78K0S-QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine. Note QB-50-EP-01T This is a flexible type emulation probe and is used to connect the in-circuit emulator and target Emulation probe system. Note QB-10MA-EA-01T Exchange adapter This exchange adapter is used to perform pin conversion from the in-circuit emulator to target connector. Note QB-10MA-NQ-01T This target connector is used to mount on the target system. Target connector Specifications of pin header on 0.635 mm x 0.635 mm (height: 6 mm) target system (Note and Remarks are listed on the next page or later.) 314 User's Manual U18172EJ3V0UD APPENDIX A DEVELOPMENT TOOLS Remarks 1. The QB-78K0SKX1 is supplied with the integrated debugger ID78K0S-QB, a USB interface cable, the on-chip debug emulator QB-MINI2, and a connection cable. Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/) when using the QB-MINI2. 2. The packed contents of QB-78K0SKX1 differ depending on the part number, as follows. Packed Contents In-Circuit Emulator Emulation Probe Exchange Adapter Target Connector Part Number QB-78K0SKX1-ZZZ QB-78K0SKX1 QB-78K0SKX1-T10MA None QB-50-EP-01T QB-10MA-EA-01T QB-10MA-NQ-01T A.4.2 When using on-chip debug emulator with programming function QB-MINI2 QB-MINI2 This on-chip debug emulator serves to debug hardware and software when developing On-chip debug emulator with application systems using the 78K0S/Kx1+ microcontrollers. It is available also as flash programming function memory programmer dedicated to microcontrollers with on-chip flash memory. When using this as on-chip debug emulator, it should be used in combination with a connection cable and a USB interface cable that is used to connect the host machine. Target connector specifications 16-pin general-purpose connector (2.54 mm pitch) Remark Download the software for operating the QB-MINI2 from the download site for development tools (http://www.necel.com/micro/en/ods/). A.5 Debugging Tools (Software) ID78K0S-QB Note This debugger supports the in-circuit emulators for the 78K0S/Kx1+ microcontrollers. The (supporting ID78K0S-QB is Windows-based software. QB-78K0SKX1, QB-MINI2) Provided with the debug function supporting C language, source programming, disassemble Integrated debugger display, and memory display are possible. It should be used in combination with the device file (DF789234). SM+ for 78K0S SM+ for 78K0S/Kx1+ System simulator System simulator is Windows-based software. Note It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of system simulator allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. System simulator should be used in combination with the device file (DF789234). The following two types of system simulators supporting the 78K0S/Kx1+ microcontrollers are available. * SM+ for 78K0S (instruction simulation version) This can only simulate a CPU. It is included in the software package. * SM+ for 78K0S/Kx1+ (instruction + peripheral simulation version) This can simulate a CPU and peripheral hardware (ports, timers, serial interfaces, etc.). Note Download the ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/). User's Manual U18172EJ3V0UD 315 APPENDIX B NOTES ON DESIGNING TARGET SYSTEM <R> This chapter shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when the QB-78K0SKX1 is used. For the package drawings of the target connector, exchange adapter, and emulation probe, see the following website. http://www.necel.com/micro/en/development/asia/iecube/outline_QB.html Figure B-1. When using the 78K0S/Kx1+ emulation probe (For 10-Pin MA Package) Top view Unit : mm 5.9 4.5 7.5 : 1pin Center point of Target connector 4.1 6.4 9.0 : Exchange adapter tip area Components up to 3.5 mm high can be mounted. : Exchange adapter mounted-component area Components up to 2.0 mm high can be mounted. : Target connector area Overview Viewing direction IECUBE TC EP EA Note EP: Emulation probe EA: Exchange adapter TC: Target connector 316 User's Manual U18172EJ3V0UD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. When using the 78K0S/Kx1+ target cable (single track) Top view Unit : mm 2.54 2.54 : A interval pin header More than 2.54mm : A contact area of a pin header 0.635 x 0.635mm (Height: 6mm) Overview Viewing direction IECUBE Target cable Pin header User's Manual U18172EJ3V0UD 317 APPENDIX C REGISTER INDEX C.1 Register Index (Register Name) [A] A/D converter mode register (ADM) ... 161 Analog input channel specification register (ADS) ... 164 [C] Capture/compare control register 00 (CRC00) ... 97 [E] 8-bit A/D conversion result register (ADCRH) ... 165 8-bit timer H compare register 01 (CMP01) ... 133 8-bit timer H compare register 11 (CMP11) ... 133 8-bit timer H mode register 1 (TMHMD1) ... 134 External interrupt mode register 0 (INTM0) ... 180 [F] Flash address pointer H compare register (FLAPHC)... 242 Flash address pointer L compare register (FLAPLC) ... 242 Flash address pointer H (FLAPH) ... 242 Flash address pointer L (FLAPL) ... 242 Flash programming command register (FLCMD) ... 241 Flash programming mode control register (FLPMC) ... 237 Flash protect command register (PFCMD) ... 239 Flash status register (PFS) ... 239 Flash write buffer register (FLW) ... 243 [I] Interrupt mask flag register 0 (MK0) ... 180 Interrupt request flag register 0 (IF0) ... 179 [L] Low-speed internal oscillation mode register (LSRCM) ... 77 Low-voltage detect register (LVIM) ... 209 Low-voltage detection level select register (LVIS) ... 210 [O] Oscillation stabilization time select register (OSTS) ... 78, 188 318 User's Manual U18172EJ3V0UD APPENDIX C REGISTER INDEX [P] Port mode control register 2 (PMC2) ... 68, 100, 136, 165 Port mode register 2 (PM2) ... 67, 100, 136, 165 Port mode register 3 (PM3) ... 67 Port mode register 4 (PM4) ... 67 Port register 2 (P2) ... 68 Port register 3 (P3) ... 68 Port register 4 (P4) ... 68 Preprocessor clock control register (PPCC) ... 76 Prescaler mode register 00 (PRM00) ... 99 Processor clock control register (PCC) ... 76 Pull-up resistor option register 2 (PU2) ... 70 Pull-up resistor option register 3 (PU3) ... 70 Pull-up resistor option register 4 (PU4) ... 70 [R] Reset control flag register (RESF) ... 203 [T] 10-bit A/D conversion result register (ADCR) ... 164 [S] 16-bit timer capture/compare register 000 (CR000) ... 92 16-bit timer capture/compare register 010 (CR010) ... 94 16-bit timer counter 00 (TM00) ... 92 16-bit timer mode control register 00 (TMC00) ... 95 16-bit timer output control register 00 (TOC00) ... 98 [W] Watchdog timer enable register (WDTE) ... 150 Watchdog timer mode register (WDTM) ... 149 User's Manual U18172EJ3V0UD 319 APPENDIX C REGISTER INDEX C.2 Register Index (Symbol) [A] ADCR: 10-bit A/D conversion result register ... 164 ADCRH: 8-bit A/D conversion result register ... 165 ADM: A/D converter mode register ... 161 ADS: Analog input channel specification register ... 164 [C] CMP01: 8-bit timer H compare register 01 ... 133 CMP11: 8-bit timer H compare register 11 ... 133 CR000: 16-bit timer capture/compare register 000 ... 92 CR010: 16-bit timer capture/compare register 010 ... 94 CRC00: Capture/compare control register 00 ... 97 [F] FLAPH: Flash address pointer H ... 242 FLAPHC: Flash address pointer H compare register ... 242 FLAPL: Flash address pointer L ... 242 FLAPLC: Flash address pointer L compare register ... 242 FLCMD: Flash programming command register ... 241 FLPMC: Flash programming mode control register ... 237 FLW: Flash write buffer register ... 243 [I] IF0: Interrupt request flag register 0 ... 179 INTM0: External interrupt mode register 0 ... 180 [L] LSRCM: Low-speed internal oscillation mode register ... 77 LVIM: Low-voltage detect register ... 209 LVIS: Low-voltage detection level select register ... 210 [M] MK0: Interrupt mask flag register 0 ... 180 [O] OSTS: 320 Oscillation stabilization time select register ... 78, 188 User's Manual U18172EJ3V0UD APPENDIX C REGISTER INDEX [P] P2: Port register 2 ... 68 P3: Port register 3 ... 68 P4: Port register 4 ... 68 PCC: Processor clock control register ... 76 PFCMD: Flash protect command register ... 239 PFS: Flash status register ... 239 PM2: Port mode register 2 ... 67, 100, 136, 165 PM3: Port mode register 3 ... 67 PM4: Port mode register 4 ... 67 PMC2: Port mode control register 2 ... 68, 100, 136, 165 PPCC: Preprocessor clock control register ... 76 PRM00: Prescaler mode register 00 ... 99 PU2: Pull-up resistor option register 2 ... 70 PU3: Pull-up resistor option register 3 ... 70 PU4: Pull-up resistor option register 4 ... 70 [R] RESF: Reset control flag register ... 203 [T] TM00: 16-bit timer counter 00 ... 92 TMC00: 16-bit timer mode control register 00 ... 95 TMHMD1: 8-bit timer H mode register 1 ... 134 TOC00: 16-bit timer output control register 00 ... 98 [W] WDTE: Watchdog timer enable register ... 150 WDTM: Watchdog timer mode register ... 149 User's Manual U18172EJ3V0UD 321 APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. "Classification (hard/soft)" in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs Hard Classification Soft Chapter 3 Chapter 2 Chapter (1/15) Function Pin functions Memory space Details of Function Cautions Page P22/X2/ANI2, P23/X1/ANI3 (PD78F920x) The P22/X2/ANI2, P23/X1/ANI3 pins are pulled down during reset. P22, P23/EXCLK, P34/RESET (PD78F950x) The P22 and P23/EXCLK pins are pulled down during reset. The P34/RESET pin is pulled up during reset by the reset pin function/power-on clear circuit. SP: stack pointer Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack memory. p. 38 Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits can be actually set. p. 38 pp. 21, 22, 24, 25 pp. 23 24, 25, 26 Hard Chapter 4 0FF00H is in the SFR area, not the high-speed RAM area, so it was converted to 0FB00H that is in the high-speed RAM area. When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to become 0FAFFH, but that value is not in the high-speed RAM area, so it is converted to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer. Port functions P22/X2/ANI2, P23/X1/ANI3 (PD78F920x) The P22/X2/ANI2, P23/X1/ANI3 pins are pulled down during reset. p. 54 P22, P23/EXCLK, P34/RESET (PD78F950x) The P22 and P23/EXCLK pins are pulled down during reset. The P34/RESET pin is pulled up during reset by the reset pin function/power-on clear circuit. p. 55 P34 Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Also, since the option byte is referenced after the reset release, if low level is input to the RESET pin before the referencing, then the reset state is not released. When it is used as an input port pin, connect the pull-up resistor. p. 65 Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Also, since the option byte is referenced after the reset release, if low level is input to the RESET pin before the referencing, then the reset state is not released. When it is used as an input port pin, connect an on-chip pull-up resistor by using bit 4 (PU34) of pull-up resistor option register 3 (PU3). p. 65 (PD78F920x) P34 (PD78F950x) 322 User's Manual U18172EJ3V0UD APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 4 Chapter (2/15) Function Port functions Details of Function Cautions Page P21, P32 Because P21 and P32 are also used as external interrupt pins, the corresponding p. 67 interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. To use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. PMC2: Port mode control register 2 When PMC20 to PMC23 are set to 1, the port function on the P20/ANI0 to P23/ANI3 pins cannot be used. Moreover, be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for the pins set to A/D converter mode. p. 69 Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. p. 71 To set and then release the STOP mode, set the oscillation stabilization time as follows. p. 78 (PD78F920x only) Soft Chapter 5 - Main clock OSTS: Oscillation stabilization time select register (PD78F920x only) Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS The wait time after the STOP mode is released does not include the time from the p. 78 release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset input or interrupt generation. Hard The oscillation stabilization time that elapses on power application or after release p. 78 of reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. Crystal/ ceramic oscillator - When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance. p. 79 * Keep the wiring length as short as possible. (PD78F9 20x only) * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. Hard Soft Chapter 6 * Do not fetch signals from the oscillator. 16-bit timer/ event counters 00 TM00: 16-bit timer counter 00 CR000: 16-bit (PD78F9 timer capture/ 20x only) compare register 000 Even if TM00 is read, the value is not captured by CR010. pp. 92, 124 When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped and then resumed after the read. pp. 92, 124 Set CR000 to other than 0000H in the clear & start mode entered on match pp. 93, between TM00 and CR000. This means a 1-pulse count operation cannot be 124 performed when this register is used as an external event counter. However, in the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H following overflow (FFFFH). If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), pp.93, TM00 continues counting, overflows, and then starts counting from 0 again. If the 124 new value of CR000 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR000 is changed. User's Manual U18172EJ3V0UD 323 APPENDIX D LIST OF CAUTIONS Soft Classification Hard Chapter 6 Chapter (3/15) Function 16-bit timer/ event counters 00 Details of Function CR000: 16-bit timer capture/ compare register 000 (PD78F9 20x only) Cautions Page The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed. pp. 93, 125 The capture operation may not be performed for CR000 set in compare mode even if a capture trigger is input. pp. 93, 127 When P21 is used as the input pin for the valid edge of TI010, it cannot be used as a timer output (TO00). Moreover, when P21 is used as TO00, it cannot be used as the input pin for the valid edge of TI010. pp. 93, 129 Soft If the register read period and the input of the capture trigger conflict when CR000 pp. 93, is used as a capture register, the capture trigger input takes precedence and the 126 read data is undefined. Also, if the count stop of the timer and the input of the capture trigger conflict, the capture trigger is undefined. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Hard CR010: 16-bit capture/ compare register 010 p. 93 In the free-running mode and in the clear & start mode using the valid edge of the pp. 94, TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated 124 when CR010 changes from 0000H to 0001H following overflow (FFFFH). If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00), pp. 94, TM00 continues counting, overflows, and then starts counting from 0 again. If the 124 new value of CR010 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR010 is changed. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed. pp. 94, 125 The capture operation may not be performed for CR010 set in compare mode even if a capture trigger is input. pp. 94, 127 Soft If the register read period and the input of the capture trigger conflict when CR010 pp. 94, is used as a capture register, the capture trigger input takes precedence and the 126 read data is undefined. Also, if the timer count stop and the input of the capture trigger conflict, the capture data is undefined. Changing the CR010 setting during TM00 operation may cause a malfunction. To p. 95 change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. Soft Hard TMC00: 16-bit timer mode control register 00 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation. pp. 95, 124 The timer operation must be stopped before writing to bits other than the OVF00 flag. pp. 96, 125 If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the TI000/TI010 pins. pp. 96, 124 Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. pp. 96, 129 Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 pp. 96, (PRM00) after stopping the timer operation. 125 If the clear & start mode entered on a match between TM00 and CR000, clear & pp. 96, start mode at the valid edge of the TI000 pin, or free-running mode is selected, 126 when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. 324 User's Manual U18172EJ3V0UD APPENDIX D LIST OF CAUTIONS Soft Classification 16-bit timer/ event counters 00 (PD78F 920x only) Details of Function TMC00: 16-bit timer mode control register 00 Cautions Hard Soft Soft Hard Soft TOC00: 16-bit timer output control register 00 Page Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled. pp. 96, 126 The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0), however, occurs at the rise of the next count clock. pp. 96, 127 CRC00: The timer operation must be stopped before setting CRC00. Capture/ compare control When the clear & start mode entered on a match between TM00 and CR000 is register 00 selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. Hard Chapter 6 Chapter (4/15) Function pp. 97, 125 pp. 97, 124 To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00) (refer to Figure 6-18). pp. 97, 127 Timer operation must be stopped before setting other than OSPT00. pp. 98, 125 If LVS00 and LVR00 are read, 0 is read. pp. 98, 125 OSPT00 is automatically cleared after data is set, so 0 is read. pp. 98, 125 Do not set OSPT00 to 1 other than in one-shot pulse output mode. pp. 98, 125 A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively. pp. 98, 125 When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with the 8-bit memory manipulation instruction. When the TOE00 is 1, the LVS00 and LVR00 can be set with the 1-bit memory manipulation instruction. p. 99 PRM00: Always set data to PRM00 after stopping the timer operation. Prescaler mode register 00 If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin. pp. 99, 125 In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. pp. 100, 129 pp. 99, 127 <1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. <2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled after a low level is input to the TI0n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is enabled. <3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled after a high level is input to the TI0n0 pin If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is enabled. User's Manual U18172EJ3V0UD 325 APPENDIX D LIST OF CAUTIONS Hard Classification Soft Chapter 6 Chapter (5/15) Function Details of Function Cautions 16-bit timer/ event counters 00 PRM00: The sampling clock used to eliminate noise differs when a TI000 valid edge is Prescaler mode used as the count clock and when it is used as a capture trigger. In the former register 00 case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. (PD78F9 20x only) When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer output (TO00). When using P21 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge. Page pp. 100, 129 pp. 100, 129 Interval timer Changing the CR000 setting during TM00 operation may cause a malfunction. To p. 101 change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. External event counter When reading the external event counter count value, TM00 should be read. pp. 105, 129 Pulse width measurement To use two capture registers, set the TI000 and TI010 pins. pp. 106, 127 The measurable pulse width in this operation example is up to 1 cycle of the timer pp. 106, counter. 108, 110, 112 Square-wave output Changing the CR000 setting during TM00 operation may cause a malfunction. To p. 114 change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. PPG output Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register during timer operation. p. 116 Values in the following range should be set in CR000 and CR010. pp. 117, 0000H < CR010 < CR000 FFFFH 129 The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). pp. 117, 129 Hard Do not set 0000H to the CR000 and CR010 registers. Soft Hard When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Soft One-shot pulse Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To pp. 119, output: software output the one-shot pulse again, wait until the current one-shot pulse output is 125 trigger completed. 125 pp. 120, 126 One-shot pulse output: external trigger 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC003 and TMC002 bits. pp. 121, Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. pp. 121, Do not set the CR000 and CR010 registers to 0000H. pp. 122, 124 126 126 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. 326 pp. 119, User's Manual U18172EJ3V0UD pp. 123, 124 APPENDIX D LIST OF CAUTIONS Hard Classification Soft Chapter 6 Chapter (6/15) Function 16-bit timer/ event counters 00 Details of Function Cautions Timer start errors An error of up to one clock may occur in the time required for a match signal to be p. 124 generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. One-shot pulse output One-shot pulse output normally operates only in the free-running mode or in the clear & start mode at the valid edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between TM00 and CR000, oneshot pulse output is not possible. Capture operation When the CRC001 bit value is 1, capture is not performed in the CR000 register if p. 127 both the rising and falling edges have been selected as the valid edges of the TI000 pin. (PD78F9 20x only) When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing. Changing compare register during timer operation Hard Page p. 125 p. 127 With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare p. 128 register, when changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer counting, INTTM000 interrupt servicing performs the following operation. If CR010 is changed during timer counting without performing processing <1> above, the value in CR010 may be rewritten twice or more, causing an inversion of the output level of the TO00 pin at each rewrite. p. 128 External event counter The timing of the count start is after two valid edge detections. p. 129 External clock limitation When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the AC characteristics, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS. p. 130 Soft Hard Soft Chapter 7 When an external waveform is input to 16-bit timer/event counter 00, it is sampled p. 130 by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device. 8-bit timer CMP01: 8-bit H1 timer H compare register 01 CMP01 cannot be rewritten during timer count operation. p. 133 CMP11: 8-bit timer H compare register 11 In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). p. 133 TMHMD1: 8-bit timer H mode register 1 When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. p. 135 PWM output In the PWM output mode, be sure to set 8-bit timer H compare register 11 p. 135 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). In PWM output mode, the setting value for the CMP11 register can be changed during timer count operation. However, three operation clocks (signal selected using the CKS12 to CKS10 bits of the TMHMD1 register) or more are required to transfer the register value after rewriting the CMP11 register value. p. 141 Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). p. 141 User's Manual U18172EJ3V0UD 327 APPENDIX D LIST OF CAUTIONS Soft Classification Details of Function 8-bit timer PWM output H1 Cautions Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. Page p. 141 00H CMP11 (M) < CMP01 (N) FFH Soft Chapter 8 Chapter 7 Chapter (7/15) Function Watchdog WDTM: Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. timer Watchdog timer After reset is released, WDTM can be written only once by an 8-bit memory mode register manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if "1" and "x" are set for WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the internal reset signal does not occur even if the following are executed. p. 149 p. 150 * Second write to WDTM * 1-bit memory manipulation instruction to WDTE * Writing of a value other than "ACH" to WDTE WDTM cannot be set by a 1-bit memory manipulation instruction. p. 150 When using the flash memory programming by self programming, set the overflow p. 150 time for the watchdog timer so that enough overflow time is secured (Example 1byte writing: 200 s MIN., 1-block deletion: 10 ms MIN.). WDTE: If a value other than ACH is written to WDTE, an internal reset signal is p. 150 Watchdog timer generated. enable register If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset p. 150 signal is generated. p. 150 When "lowspeed internal oscillator cannot be stopped" is selected by option byte In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the lowspeed internal oscillation clock can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. p. 151 When "lowspeed internal oscillator can be stopped by software" is selected by option byte In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. p. 153 Sampling time The above sampling time and conversion time do not include the clock frequency and A/D error. Select the sampling time and conversion time such that Notes 2 and 3 (PD78F9 conversion time above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). 20x only) p. 158 Soft Soft Hard Chapter 9 Hard The value read from WDTE is 9AH (this differs from the written value (ACH)). 328 A/D converter In PD78F920x, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). p. 159 In PD78F920x, VDD functions alternately as the A/D converter reference voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V). p. 159 ADM: A/D The above sampling time and conversion time do not include the clock frequency converter mode error. Select the sampling time and conversion time such that Notes 3 and 4 register above are satisfied, while taking the clock frequency error into consideration (an error margin maximum of 5% when using the high-speed internal oscillator). p. 163 Block Diagram User's Manual U18172EJ3V0UD APPENDIX D LIST OF CAUTIONS Soft Classification Hard Soft Chapter 9 Chapter (8/15) Function Details of Function Cautions A/D converter ADM: A/D If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped converter mode (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ADCS to 1. (PD78F9 register 20x only) A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2. Page p. 163 p. 163 Be sure to clear bits 6, 2, and 1 to 0. p. 163 ADS: Analog input channel specification register Be sure to clear bits 2 to 7 of ADS to 0. p. 164 ADCR: 10-bit A/D conversion result register When writing to the A/D converter mode register (ADM) and analog input channel p. 164 specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using timing other than the above may cause an incorrect conversion result to be read. PMC2: Port mode control register 2 If PMC20 to PMC23 are set to 1, the P20/ANI0/TI000/TOH1, P21/ANI1/TIO10/TO00/INTP0, P22/ANI2, and P23/ANI3 pins cannot be used for any purpose other than the A/D converter function. Be sure to set 0 to the Pull-up resistor option register of the pin set in A/D converter mode. p. 165 A/D converter operations Make sure the period of <1> to <4> is 1 s or more. pp. 166, 170 It is no problem if the order of <1> and <2> is reversed. pp. 166, 170 <1> can be omitted. However, ignore the data resulting from the first conversion after <4> in this case. p. 170 The period from <5> to <8> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set using FR2 to FR0. p. 170 Operating To satisfy the DC characteristics of supply current in STOP mode, clear bit 7 current in STOP (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 before mode executing the STOP instruction. p. 173 Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of VDD or higher and VSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. p. 173 Conflicting operations Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR, ADCRH. p. 173 Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. p. 173 User's Manual U18172EJ3V0UD 329 APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 9 Chapter (9/15) Function A/D converter Details of Function Cautions Noise To maintain the 10-bit resolution, attention must be paid to noise input to the VDD countermeasures pin and ANI0 to ANI3 pins. (PD78F9 20x only) Page p. 173 <1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply. <2> Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 9-19, to reduce noise. <3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their alternate functions during conversion. <4> The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts. ANI0/P20 to ANI3/P23 The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23). p. 174 When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access P20 to P23 while conversion is in progress; otherwise the conversion resolution may be degraded. If a digital pulse is applied to the pins adjacent to the pins currently used for A/D p. 174 conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. Input impedance of ANI0 to ANI3 Soft pins Interrupt request flag (ADIF) In this A/D converter, the internal sampling capacitor is charged and sampling is performed during sampling time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates both during sampling and otherwise. If the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended to make the output impedance of the analog input source 1 k or lower, or attach a capacitor of around 0.01 F to 0.1 F to the ANI0 to ANI3 pins (see Figure 9-19). When writing the flash memory on-board, supply a stabilized analog voltage to the ANI2 and ANI3 pins, without attaching a capacitor. Because the communication pulse may change and the communication may fail if a capacitor is attached to remove noise. p. 174 The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. p. 174 Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Conversion results just after A/D conversion start 330 The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. User's Manual U18172EJ3V0UD p. 175 APPENDIX D LIST OF CAUTIONS A/D converter (PD78F9 20x only) Soft Chapter Chapter 10 Hard Chapter 9 Soft Classification (10/15) Function Interrupt functions Details of Function Cautions A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM) p. 175 and analog input channel specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. The operating current at the conversion waiting mode The DC characteristic of the operating current at the STOP mode is not satisfied at the conversion waiting mode (when A/D converter mode register (ADM) is set up with bit 7(ADCS) =0 and bit 0 (ADCE) =1) (only comparator consumes power). p. 175 IF0: Interrupt request flag registers, Because P21 and P32 have an alternate function as external interrupt inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. pp. 179, MK0: Interrupt mask flag registers INTM0: External Be sure to clear bits 0, 1, 6, and 7 to 0. interrupt mode Before setting the INTM0 register, be sure to set the corresponding interrupt register 0 mask flag (xxMKx = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (xxIFx = 0), then clear the interrupt mask flag (xxMKx = 0), which will enable interrupts. Interrupt requests are held pending Interrupt requests will be held pending while the interrupt request flag registers (IF0) or interrupt mask flag registers (MK0) are being accessed. Soft Hard Soft Hard Soft Chapter 11 Interrupt Multiple interrupts can be acknowledged even for low-priority interrupts. request pending Standby function Page - 180 p. 181 p. 181 p. 183 p. 184 The LSRSTOP setting is valid only when "Can be stopped by software" is set for p. 186 the low-speed internal oscillator by the option byte. STOP mode When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction (except the peripheral hardware that operates on the low-speed internal oscillation clock). STOP mode, HALT mode p. 187 The following sequence is recommended for operating current reduction of the A/D converter in PD78F920x when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. STOP mode If the low-speed internal oscillator is operating before the STOP mode is set, oscillation of the low-speed internal oscillation clock cannot be stopped in the STOP mode (refer to Table 11-1). p. 187 OSTS: Oscillation stabilization time select register To set and then release the STOP mode, set the oscillation stabilization time as follows. p. 188 (PD78F920x only) p. 187 Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset signal generation or interrupt generation. p. 188 The oscillation stabilization time that elapses on power application or after p. 188 release of reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE. User's Manual U18172EJ3V0UD 331 APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 11 Chapter (11/15) Function Standby function Details of Function HALT mode setting and operating Hard Reset function Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set. p. 189 Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is restored after the STOP instruction is executed and then the operation is stopped for 34 s (TYP.) (after an additional wait time for stabilizing the oscillation set by the oscillation stabilization time select register (OSTS) has elapsed when crystal/ceramic oscillation is used). p. 192 - For an external reset, input a low level for 2 s or more to the RESET pin. p. 196 During reset signal generation, the system clock and low-speed internal oscillation p. 196 clock stop oscillating. Soft Soft Hard Soft Soft Chapter 12 Chapter 13 Page statuses STOP mode setting and operating statuses Chapter 14 Cautions Poweron-clear circuit Lowvoltage detector When the RESET pin is used as an input-only port pin (P34), the 78K0S/KU1+ is reset if a low level is input to the RESET pin after reset is released by the POC circuit, the LVI circuit and the watchdog timer and before the option byte is referenced again. The reset status is retained until a high level is input to the RESET pin. p. 196 The LVI circuit is not reset by the internal reset signal of the LVI circuit. p. 197 Timing of reset by overflow of watchdog timer The watchdog timer is also reset in the case of an internal reset of the watchdog timer. p. 199 RESF: Reset control flag register Do not read data by a 1-bit memory manipulation instruction. p. 203 Functions of power-on-clear circuit If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. p. 204 Cautions for power-on-clear circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. p. 206 LVIM: Lowvoltage detect register To stop LVI, follow either of the procedures below. p. 209 Because the detection voltage (VPOC) of the POC circuit is in a range of 2.1 V 0.1 p. 204 V, use a voltage in the range of 2.2 to 5.5 V. * When using 8-bit manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. Be sure to set bits 2 to 6 to 0. p. 209 LVIS: Lowvoltage detection level select register Bits 4 to 7 must be set to 0. p. 210 If a value other than the above is written during LVI operation, the value becomes undefined at the very moment it is written, and thus be sure to stop LVI (bit 7(LVION) = 0 on the LVIM register) before writing. p. 210 When used as reset <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. p. 211 If supply voltage (VDD) detection voltage (VLVI) when LVIM is set to 1, an internal p. 211 reset signal is not generated. 332 User's Manual U18172EJ3V0UD APPENDIX D LIST OF CAUTIONS Soft Classification Chapter 14 Chapter (12/15) Function Lowvoltage detector Details of Function Cautions for low-voltage detector Cautions In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. Page p. 215 <1> When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> When used as interrupt Hard Chapter 15 Interrupt requests may be frequently generated. Take (b) of action (2) below. Option byte Oscillation stabilization time on power application or after reset release (PD78F920x) The setting of this option is valid only when the crystal/ceramic oscillation clock is selected as the system clock source. No wait time elapses if the high-speed internal oscillation clock or external clock input is selected as the system clock source. p. 220 Control of RESET pin Because the option byte is referenced after reset release, if a low level is input to the RESET pin before the option byte is referenced, then the reset state is not released. Also, when setting 0 to RMCE, connect the pull-up resistor. p. 220 Because the option byte is referenced after reset release, if a low level is input to the RESET pin before the option byte is referenced, then the reset state is not released. When used as an input-only port (P34), the setting of the on-chip pull-up resistor can be done by PU34 on PU3 register. p. 222 Because the X1 and X2 pins are also used as the P23/ANI3 and P22/ANI2 pins, the conditions under which the X1 and X2 pins can be used differ depending on the selected system clock source. p. 220 (PD78F920x) Control of RESET pin (PD78F950x) Selection of system clock source (PD78F920x) (1) Crystal/ceramic oscillation clock is selected The X1 and X2 pins cannot be used as I/O port pins or analog input pins of A/D converter because they are used as clock input pins. (2) External clock input is selected Because the X1 pin is used as an external clock input pin, P121 cannot be used as an I/O port pin or an analog input pin of A/D converter. (3) High-speed internal oscillation clock is selected P23/ANI3 and P22/ANI2 pins can be used as I/O port pins or analog input pins of A/D converter. Selection of system clock source (PD78F950x) Because the EXCLK pin is also used as the P23 pin, the condition under which the EXCLK pin can be used differ depending on the selected system clock source. p. 222 (1) External clock input is selected Because the pin is used as an external clock input pin, P23 cannot be used as an I/O port pin. (2) High-speed internal oscillation clock is selected P23 pin can be used as an I/O port pin. Low-speed internal oscillates If it is selected that low-speed internal oscillator cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation clock. User's Manual U18172EJ3V0UD pp. 221, 223 333 APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 15 Chapter (13/15) Function Option byte Details of Function Low-speed internal oscillates Cautions Page If it is selected that low-speed internal oscillator can be stopped by software, pp. 221, supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless 223 of the setting of bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly, clock supply is also stopped when a clock other than the low-speed internal oscillation clock is selected as a count clock to WDT. While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be supplied to the 8-bit timer H1 even in the STOP mode. Caution When Flash Be aware of the following when erasing/writing by on-board programming using a p. 223 dedicated flash memory programmer once again on the already-written device which has been set as "The RESET pin is used as an input-only port pin (P34)" by Is Used as an Inport-Only Port the option byte function. Before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on. If the power is Pin (P34) supplied to the target system beforehand, it cannot be switched to the flash memory programming mode. PG-FP5 The above values are recommended values. Depending on the usage p. 230 memory programming Soft Chapter 16 the RESET Pin GUI setting value example Security settings Self programming function 334 environment these values may change, so set them after having performed sufficient evaluations. After the security setting of the batch erase is set, erasure cannot be performed for the device. In addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written because the erase command is disabled. p. 233 Self programming processing must be included in the program before performing self programming. p. 234 No instructions can be executed while a self programming command is being executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. Refer to Table 16-10 for the time taken for the execution of self programming. p. 237 Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid this operation, disable interrupt servicing (by setting MK0 to FFH, and executing the DI instruction) before a mode is shifted from the normal mode to the self programming mode with a specific sequence. p. 237 RAM is not used while a self programming command is being executed. p. 237 If the supply voltage drops or the reset signal is input while the flash memory is being written or erased, writing/erasing is not guaranteed. p. 237 The value of the blank data set during block erasure is FFH. p. 237 Set the CPU clock so that it is 1 MHz or more during self programming. p. 237 Execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, then execute self programming. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). p. 237 If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. p. 237 Check FPRERR using a 1-bit memory manipulation instruction. p. 237 User's Manual U18172EJ3V0UD APPENDIX D LIST OF CAUTIONS Chapter Chapter 16 Soft Classification (14/15) Function Flash memory Details of Function Self programming function Cautions Page The state of the pins in self programming mode is the same as that in HALT mode. p. 237 Since the security function set via on-board/off-board programming is disabled in self programming mode, the self programming command can be executed regardless of the security function setting. To disable write or erase processing during self programming, set the protect byte. p. 237 Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address p. 237 pointer H compare register (FLAPHC) to 0 before executing the self programming command. If the value of these bits is 1 when executing the self programming command, there is a possibility that device does not operate normally. Clear the value of the FLCMD register to 00H immediately before setting selfprogramming mode and normal operation mode. p. 237 Cautions in the case of setting the self programming mode, refer to 16.8.2 Cautions on self programming function. p. 238 Set the CPU clock so that it is 1 MHz or more during self programming. p. 238 Execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, then execute self programming. At this time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU clocks (fCPU). p. 238 If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT instructions immediately after executing a specific sequence to set self-programming mode, wait for 8 s after releasing the HALT status, and then execute self programming. p. 238 Clear the value of the FLCMD register to 00H immediately before setting self programming mode and normal operation mode. p. 238 PFCMD: Flash protect command register Interrupt servicing cannot be executed in self-programming mode. Disable interrupt servicing (by executing the DI instruction while MK0 = FFH) before executing the specific sequence that sets self-programming mode and after executing the specific sequence that changes the mode to the normal mode. p. 239 PFS: Flash status register Check FPRERR using a 1-bit memory manipulation instruction. p. 239 FLAPH, FLAPL: Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self Flash address programming command. If the self programming command is executed with pointers H and these bits set to 1, the device may malfunction. L p. 242 FLAPHC, FLAPLC: Flash address pointer H/L compare registers p. 242 FLPMC: Flash programming mode control register Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self programming command. If the self programming command is executed with these bits set to 1, the device may malfunction. Set the number of the block subject to a block erase, verify, or blank check (same p. 242 value as FLAPH) to FLAPHC. Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank check is performed. Shifting to self programming mode Be sure to perform the series of operations described above using the user program at an address where data is not erased or written. p. 242 pp. 244, 245, 247, 248 Shifting to normal mode Byte write If a write results in failure, erase the block once and write to it again. User's Manual U18172EJ3V0UD p. 256 335 APPENDIX D LIST OF CAUTIONS Hard Classification Chapter 17 Chapter (15/15) Function On-chip debug function Details of Function Connecting QB-MINI2 to 78K0S/KU1+ Cautions The 78K0S/KU1+ has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is not liable for problems occurring when the on-chip debug function is used. Page p. 280 Hard Chapter 19 The constants described in the circuit connection example are reference values. If p. 280 you perform flash programming aiming at mass production, thoroughly evaluate whether the specifications of the target device are satisfied. Electrical specifications For the case where QBMINI2 is used for debugging and debugging of INTP1 pin is performed only with real machine If debugging is performed with a real machine running, without using QB-MINI2, write the user program using the QB-Programmer. Programs downloaded by the debugger include the monitor program, and such a program malfunctions if it is not controlled via QB-MINI2. Absolute maximum ratings Product quality may suffer if the absolute maximum rating is exceeded even p. 294 momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. X1 oscillator characteristics When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. (PD78F920x only) * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. p. 282 p. 295 * Do not fetch signals from the oscillator. A/D converter 336 Hard Chapter 21 (PD78F920x only) Recommended soldering conditions - The conversion accuracy may be degraded if the level of a port that is not used for A/D conversion is changed during A/D conversion. p. 304 For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. p. 309 Do not use different soldering methods together (except for partial heating). p. 309 User's Manual U18172EJ3V0UD APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition Page Description Throughout Addition of PD78F950x products (without 16-bit timer/event counter and A/D converter ) p. 6 Modification of Related Documents p. 17 Modification of 1.4 78K0S/Kx1+ Product Lineup p. 226 16.4 Writing with Flash Memory Programmer * Deletion of FlashPro4 and addition of QB-MINI2 * Modification of Remark p. 227 Modification of and addition of Remark to Figure 16-2 Environment for Writing Program to Flash Memory (FlashPro5/QB-MINI2) p. 228 Modification of Table 16-2 Wiring Between 78K0S/KU1+ and FlashPro5/QB-MINI2 p. 228 Modification of and addition of Remark to Figure 16-3 Wiring diagram with FlashPro5/QB-MINI2 p. 232 Modification of Figure 16-7 Communication Commands pp. 250 to 252 16.8.6 Example of block erase operation in self programming mode * Modification of description and addition of Note 2 * Modification of Figure 16-20 Example of Block Erase Operation in Self Programming Mode * Modification of an example of a program pp. 270 to 272 16.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode * Modification of Figure 16-27 Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Erasure to Blank Check) * Modification of an example of a program p. 280 Modification of Caution in 17.1 Connecting QB-MINI2 to 78K0S/KU1+ p. 310 Modification of APPENDIX A DEVELOPMENT TOOLS p. 338 Addition of E.2 Revision History up to Revision Editions User's Manual U18172EJ3V0UD 337 APPENDIX E REVISION HISTORY <R> E.2 Revision History up to Previous Editions The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/2) Edition 2nd edition Description Applied to: Modification of 1.1 Features CHAPTER 1 Addition of Note 2 to 5 in 1.4 78K0S/Kx1+ Product Lineup OVERVIEW 9.1 Functions of A/D Converter CHAPTER 9 A/D * Addition of Notes 4 to Table 9-1 Sampling Time and A/D Conversion Time CONVERTER 9.3 Registers Used by A/D Converter * Addition of Note 5 to Figure 9-3 Format of A/D Converter Mode Register (ADM) 9.6 Cautions for A/D Converter * Addition of description to (6) Input impedance of ANI0 to ANI3 pins CHAPTER 12 Modification of Caution 3 RESET FUNCTION 16.4 Writing with Flash Memory Programmer CHAPTER 16 FLASH * Addition of FlashPro5 to Dedicated flash memory programmer MEMORY * Deletion of PG-FPL2 from Dedicated flash memory programmer * Modification of Remark 16.5 Programming Environment * Modification of Figure 16-2 Environment for Writing Program to Flash Memory (FlashPro4/FlashPro5/QB-MINI2) and addition of Note * Modification of Table 16-2 Wiring Between 78K0S/KU1+ and FlashPro4/FlashPro5/QB-MINI2 and Addition of Note 2 * Modification of Figure 16-3 Wiring diagram with FlashPro4/FlashPro5/QB-MINI2 * Deletion of PG-FPL2 from dedicated flash memory programmer Modification of Figure 16-5 PG-FP5 GUI Software Setting Example Modification of Figure 16-7 Communication Commands Addition of Note in Table 16-10 Self Programming Controlling Commands CHAPTER 17 ON-CHIP Addition of this chapter DEBUG FUNCTION * Modification of X1 Oscillator Characteristics CHAPTER 19 * Addition of setting range of CPU clock and peripheral clock frequency to AC ELECTRICAL SPECIFICATIONS Characteristics Modification of Figure A-1 Development Tools APPENDIX A A.4 Flash Memory Writing Tools DEVELOPMENT TOOLS * Addition of FlashPro5 * Deletion of PG-FPL2 A.5.1 When using in-circuit emulator QB-78K0SKX1 * Deletion of description of under development Deletion of A.5.3 When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A and A.5.4 When using in-circuit emulator QB-78K0SKX1MINI in old edition Modification of A.6 Debugging Tools (Software) 338 User's Manual U18172EJ3V0UD APPENDIX E REVISION HISTORY (2/2) Edition 2nd edition Description Applied to: APPENDIX B NOTES Addition of this chapter ON DESIGNING TARGET SYSTEM User's Manual U18172EJ3V0UD 339 Published by: NEC Electronics Corporation (http://www.necel.com/) Contact: http://www.necel.com/support/