AK5393 24-Bit, 96kHz Analog-to-Digital Converter Features * * * * * * * * * * * * Description Proprietary dual-bit delta-sigma () architecture Sampling rate from 1kHz to 108kHz Full differential inputs Dynamic range = 117dB Signal-to-noise = 117dB Signal-to-(Noise + Distortion) = 105dB On-chip linear phase digital anti-alias filter - Passband from 0 to 21.768kHz at fs = 48kHz - Ripple = 0.001dB - Stopband attenuation = 110dB Selectable digital HPF or offset calibration Power supplies - Analog: 5V 5% - Digital: from 3V to 5.25V Low power dissipation: 470mW Small 28-pin SOP package Pin compatible with the AK5391, AK5392, and AK5383 The AK5393 is a 24-bit, 96kHz stereo Analog-toDigital Converter (ADC) that offers up to 117dB of dynamic range and a 105dB Signal-to-(Noise + Distortion) Ratio. The improved dynamic range and lowered distortion are achieved using an innovative dual-bit architecture that reduces power consumption and improves reliability. The AK5393 include full differential inputs for maximum signal range and performance. It also includes a reference filter and a digital decimation filter to minimize application requirements for anti-aliasing filtering. The user can select an internal HPF to eliminate DC inputs or offset calibration. The AK5393 outputs data at up to 108kHz, in several selectable formats. The AK5393 is available in a space-saving 28-pin SOP package, and it operates over the full commercial temperature range: -10C to 70C. Block Diagram SMODE1 SMODE2 Voltage Reference VREFL GNDL SCLK LRCK FSYNC Serial Output Interface SDATA VCOML AINL+ AINL - AE* Modulator Decimation Filter HPF AE* Modulator Decimation Filter HPF HPF Enable ZCAL AINR+ AINR - MCLK Double Speed Select VCOMR Voltage Reference VREFR GNDR VA M0038-E-01/00 1/1999 AGND Calibration SRAM Controller BGND CAL RST VD DGND AK5393 ASAHI KASEI Performance Specications Analog Characteristics Ta = 25uC, VA = 5.0V, VD = 3.3V, AGND= SGND = DGND = 0V, fs = 48kHz, Signal Frequency = 1kHz, 24-bit output, and measurement frequency = 10Hz to 20kHz, unless otherwise specified. Parameter Conditions/Comments Min. Typ. Resolution Max. Units 24 Bits Analog Input Characteristics Dynamic Range -60dBFS, A-Weighted 112 117 dB Signal-to-Noise Ratio A-Weighted 112 117 dB Signal-to-(Noise + Distortion) Ratio -1dBFS 98 105 dB -20dBFS 94 -60dBFS -1dBFS, fs = 54 96kHz1 -20dBFS, fs = 96kHz1 -60dBFS, fs = 96kHz1 Interchannel Isolation 96 103 85 45 110 Interchannel Gain Mismatch 120 0.1 Gain Drift Offset Error After Calibration dB 0.5 dB 150 ppm/uC 1000 LSB2 HPF = Off 200 HPF = On 1 Offset Drift HPF = Off 10 LSB/uC Offset Calibration Range HPF = Off 50 mV Input Voltage (AIN+) - (AIN-) Input Impedance 2.3 2.45 2.4 4 2.6 V k Power Supplies Analog Power Supply Current 90 Digital Power Supply Current fs = 96kHz Power Dissipation Power Supply Rejection3 130 mA 6 9 mA 9 14 470 680 70 mW dB Digital Characteristics Ta = 25uC, VA = 5.0V 5%, VD = 3.0V to 5.25V Parameter Conditions/Comments Min. Typ. Max. Units Input High-Level Input Voltage 0.7VD Low-Level Input Voltage Input Leakage Current V 0.3VD V 10 A Output 2 High-Level Output Voltage Iout = -20A Low-Level Output Voltage Iout = 20A M0038-E-01/00 VD - 0.1 V 0.1 V 1/1999 ASAHI KASEI AK5393 Performance Specication (Continued) Filter CharacteristicsNfs = 48kHz fs = 48kHz, Ta = 25uC, VA = 5.0V 5%, VD = 3.0V to 5.25V, DFS = Low. Parameter Conditions/Comments Min. Typ. Max. Units 21.768 kHz ADC Digital Filter (Decimation LPF) PB Passband4 0 SB Stopband4 26.232 PR Passband Ripple SA Stopband Attenuation5 0.001 110 Delay6 GD Group GD Group Delay Distortion kHz dB dB 38.7 1/fs 0 s -3dB 1.0 Hz -0.1dB 6.5 ADC Digital Filter (HPF) FR Frequency Response4 Filter CharacteristicsNfs = 96kHz fs = 96kHz, Ta = 25uC, VA = 5.0V 5%, VD = 3.0V to 5.25V, DFS = High. Parameter Conditions/Comments Min. Typ. Max. Units 43.536 kHz ADC Digital Filter (Decimation LPF) PB Passband4 0 SB Stopband4 52.464 PR Passband Ripple SA Stopband Attenuation7 110 Delay6 GD Group GD Group Delay Distortion kHz 0.003 dB dB 38.8 1/fs 0 s -3dB 2.0 Hz -0.1dB 13.0 ADC Digital Filter (HPF) FR Frequency Response4 Notes: 1. When fs = 96kHz, a measurement bandwidth of 40kHz is used. 2. The LSB refers to the Least Significant Bit of the 24-bit output data. 3. The Power Supply Rejection ratio is measured with a 1kHz, 20mVP-P input to VA and VD. VREFH is held at a constant voltage. 4. The passband and stopband frequencies are proportional to fs. 5. The analog modulator samples the input at 6.144MHz for 48kHz output. There is no rejection of input signals which are multiples of the sampling frequency. That is, there is no rejection for signals of the following frequencies: n x 6.144MHz 21.768kHz, where n = 1, 2, 3, 4, ... 6. The Group Delay is the calculated delay time which takes place due to the digital filtering process. This time is taken from when the analog signal is input, to the time of setting the 24-bit data (from both channels) to the output register. When the HPF is on, this time is typically 40.7/fs if the DFS pin is Low, and 40.8/fs if the DFS pin is High. 7. The analog modulator samples the input at 6.144MHz for 96kHz output. There is no rejection of input signals which are multiples of the sampling frequency. That is, there is no rejection for signals of the following frequencies: n x 6.144MHz 43.536kHz, where n = 1, 2, 3, 4, ... 1/1999 M0038-E-01/00 3 AK5393 ASAHI KASEI Typical Performance Curves THD + N vs. Frequency Linearity -80 -85 +0 -20 -90 -40 dBFS dB -95 -100 -105 -60 -80 -110 -100 -115 -120 -120 20 50 100 200 500 1k 2k 5k -140 -140 10k 20k -120 -100 Hz -40 -40 -60 -60 -80 -100 -80 -120 -140 -140 2k 5k 10k 20k -160 20 Hz 4 0 -100 -120 500 1k -20 16384 Points, 8 Averages, 48kHz Sampling +0 -20 dBFS dBFS 16384 Points, 8 Averages, 48kHz Sampling 100 200 -40 -60dB FFT +0 -20 50 -60 dBr 0dB FFT -160 20 -80 50 100 200 500 1k 2k 5k 10k 20k Hz M0038-E-01/00 1/1999 ASAHI KASEI AK5393 Absolute Maximum Ratings AGND, SGND, and DGND = 0V. All voltages are with respect to ground. Parameter Min. Max. Units Power Supplies VA Analog Power Supply -0.3 6.0 V VD Digital Power Supply -0.3 6.0 V GND1 |SGND - DGND| 0.3 V IIN Input CurrentNAll pins except supply pins 10 mA VINA Analog Input Voltage -0.3 VA + 0.3 V VIND Digital Input Voltage -0.3 VD + 0.3 V Ta Ambient Operating Temperature (Power Applied) -10 70 C Tstg Storage Temperature -65 150 C Temperature Note: 1. AGND and SGND must be at the same voltage. ! Caution: Exceeding minimum and maximum ratings may result in damage to the device. Recommended Operating Conditions AGND, SGND, and DGND = 0V. All voltages are with respect to ground. Parameter Power Min. Typ. Max. Units Supplies1 VA Analog Power Supply 4.75 5.0 5.25 V VD Digital Power Supply 3.0 3.3 5.25 V Note: 1. The VA and VD power-up sequences are not critical. 1/1999 M0038-E-01/00 5 AK5393 ASAHI KASEI Layout Pin Descriptions VREFL GNDL VCOML AINL+ AINLZCAL VD DGND CAL RST SMODE2 SMODE1 LRCK SCLK 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VREFR GNDR VCOMR AINR+ AINRVA AGND SGND TEST HPFE DFS MCLK FSYNC SDATA Note: See Table 1 for compatibility with other AKM devices. Pin Descriptions 6 No. Pin Name I/O Pin Function and Description 1 VREFL O Left Channel Reference Voltage. VREFL = 3.75V. This pin is normally connected to the GNDL pin through a 10F electrolytic capacitor and a 0.1F ceramic capacitor in parallel. Refer to the Design Considerations section for additional information. 2 GNDL - Left Channel Reference Ground. GNDL = 0V. 3 VCOML O Left Common Voltage. VCOML = 2.75V. 4 AINL+ I Left Channel Analog Positive Input. 5 AINL- I Left Channel Analog Negative Input. 6 ZCAL I Zero Calibration Control. This pin controls the calibration reference signal. When ZCAL is Low, the VCOML and VCOMR are selected. When High, the analog inputs (AINL+, AINL-, AINR+, and AINR-) are used for the reference level. 7 VD - Digital Power Supply. VD = 3.3V. 8 DGND - Digital Ground. DGND = 0V. 9 CAL O Calibration Active Signal. When this pin outputs a High signal, it shows that the offset calibration cycle is in progress. The offset calibration cycle starts when the RST pin goes High. The CAL pin goes Low after 8704 clock cycles when DFS is Low or after 17408 cycles when DFS is High. 10 RST I Reset. When this pin is Low, the digital section is powered down. When this pin returns to High, an offset calibration cycle starts. An offset calibration cycle should always be initiated upon powering up the device. 11 SMODE2 I 12 SMODE1 I Serial Interface Mode Select. The serial interface mode data should always be MSB first, 2Os complement formatted. See Table 3 for these pin definitions. 13 LRCK I/O Left Channel and Right Channel Select Clock. During resetNwhen the SMODE1 pin is HighNthe LRCK pin goes High when the SMODE2 pin is Low, and the LRCK pin goes Low when the SMODE2 pin is High. 14 SCLK I/O Serial Data Clock. Data is clocked on the falling edge of SCLK. In the slave mode, the SCLK pin requires a clock greater than 48fs. In the master mode, this pin outputs a 128fs (when DFS is Low) clock or a 64fs clock. SCLK is Low during reset. 15 SDATA O Serial Data Output. Serial data output is MSB first and 2Os complement formatted. This pin is low during reset. 16 FSYNC I/O Frame Synchronization Signal. In slave mode, when FSYNC is High, the data bits are clocked on SDATA. In the master mode, FSYNC outputs a 2fs clock and it is Low during reset. M0038-E-01/00 1/1999 ASAHI KASEI AK5393 Pin Descriptions (Continued) No. Pin Name I/O Pin Function and Description 17 MCLK I Master Clock Input. Set the DFS pin Low for a 256fs input clock. Set the DFS pin High for a 128fs clock. 18 DFS I Double Speed Sampling Mode. When this pin is Low, the chip is in normal speed mode. When High, the double speed mode is selected. 19 HPFE I High Pass Filter Enable. When this pin is High, the high pass filter is enabled. When Low, this pin is disabled. 20 TEST I Test. This pin should be connected to ground. 21 SGND - Substrate Ground. SGND = 0V. 22 AGND - Analog Ground. AGND = 0V. 23 VA - Analog Power Supply. VA = 5V. 24 AINR- I Right Channel Analog Negative Input. 25 AINR+ I Right Channel Analog Positive Input. 26 VCOMR O Right Common Voltage Pin. VCOMR = 2.75V. 27 GNDR - Right Channel Reference Ground. GNDR = 0V. 28 VREFR O Right Channel Reference Voltage. VREFR = 3.75V. This pin is normally connected to the GNDR pin through a 10F electrolytic capacitor and a 0.1F ceramic capacitor in parallel. Refer to the Design Considerations section for additional information. Note: 1. All input pins, except pull-down pins, should not be left floating. Table 1. AK5393 Compatibility with the AK5392 AK5393 AK5392 AK5391 AK5383 Pin 2 GNDL GNDL VREFL- GNDL Pin 18 DFS CMODE CMODE DFS Pin 19 HPFE HPFE SEL24 HPFE Pin 27 GNDR GNDR VREFR- GNDR Maximum fs 108kHz 54kHz 54kHz 108kHz Master Clock at 48kHz 256fs 256fs or 384fs 256fs or 384fs 256fs Master Clock at 96kHz 128fs N/A N/A 128fs 1/1999 M0038-E-01/00 7 AK5393 ASAHI KASEI Swithching Characteristics Ta = 25uC, VA = 5.0V 5%, VD = 3.0V to 5.25V, CL = 20pF. Parameter Conditions/Comments Min. Typ. Max. Units 256fs 0.256 12.288 13.824 MHz Control Clock Frequency fCLK Master Clock Frequency tCLKL Clock Pulse Width Low 29 ns tCLKH Clock Pulse Width High 29 ns fSLK Serial Data Output Clock (SCLK) Frequency fs Channel Select Clock (LRCK) Frequency 1 Duty Cycle 6.144 6.912 MHz 48 108 kHz 75 % 25 1 (SMODE Serial Interface TimingNSlave Mode = Low) tSLK SCLK Period 144.7 ns tSLKL SCLK Pulse Width Low 65 ns tSLKH SCLK Pulse Width High 65 ns tSLR SCLK Falling Edge to LRCK Edge Note 2 -45 45 ns tDLR LRCK Edge to SDATA MSB Valid 45 ns tDSS SCLK Falling Edge to SDATA Valid 45 ns tSF SCLK Falling Edge to FSYNC Edge 45 ns -45 Serial Interface TimingNMaster Mode (SMODE = High) tSCLK SCLK Frequency DFS = Low 128fs DFS = High 64fs Hz SCLK Frequency Duty Cycle 50 % fFSYNC 2fs Hz FSYNC Frequency FSYNC Frequency Duty Cycle tSLR SCLK Falling Edge to LRCK Edge tLRF LRCK Edge to FSYNC Rising Edge tDSS SCLK Falling Edge to SDATA Valid tSF SCLK Falling Edge to FSYNC Edge 50 -20 % 20 1 -20 ns tSLK 45 ns 20 ns Reset and Calibration Timing tRTW RST Pulse Width 150 ns tRCR RST Falling to CAL Rising Edge tRCF RST Rising to CAL Falling Edge Note 3 8704 1/fs tRTV RST Rising Edge to SDATA Valid Note 3 8960 1/fs 50 ns Notes: 1. Refer to the Serial Data Interface section. 2. The specified LRCK edges do not coincide with the rising edges of SCLK. 3. tRCF and tRTV specify the number of LRCK rising edges after RST is brought High. This value is given for when the device is operated in master mode. In slave mode, this value is one LRCK clock (1/fs) longer. When the DFS is High, the number of cycles, 1/fs, is doubled. 8 M0038-E-01/00 1/1999 ASAHI KASEI AK5393 Timing Diagrams LRCK tSLK tSLR tSLKL tSLKH SCLK tDLR tDSS SDATA MSB MSB - 1 MSB - 2 Figure 1. Serial Data Timing (Slave Mode, FSYNC = High) LRCK tSLR SCLK tSF tSF FSYNC tDLR tDSS SDATA MSB D1 D0 Figure 2. Serial Data Timing (Slave Mode) LRCK tSLK tSLR tSLKL tSLKH SCLK tDSS tDSS SDATA MSB MSB - 1 Figure 3. Serial Data Timing (I2S Slave Mode, FSYNC = DonOt Care) 1/1999 M0038-E-01/00 9 AK5393 ASAHI KASEI Timing Diagrams (Continued) LRCK tSLR SCLK tSF FSYNC tSF tLRF tDSS SDATA MSB MSB - 1 Figure 4. Serial Data Timing (Master Mode and I2S Master Mode, DFS = Low) tRTW tRTV RST tRCF CAL tRCR SDATA Figure 5. Reset and Calibration Timing 10 M0038-E-01/00 1/1999 ASAHI KASEI AK5393 Device Operation System Clock Input Three clocks are required to operate the AK5393: the Master Clock (MCLK), the Left/Right Channels Select Clock (LRCK), and the Serial Data Clock (SCLK). Refer to Table 1. The MCLK should be synchronized with the LRCK, but the phase is not critical. MCLK should be 256fs when in the normal sampling mode (i.e. DFS = Low), and should be 128fs when in the double sampling mode. Table 2 shows the standard audio word rates and their corresponding frequencies. Table 1. System Clocks Normal Speed (DFS = Low) LRCK (maximum) Double Speed (DFS = High) 54kHz BICK Up to 128fs MCLK 256fs 108kHz Up to 64fs The AK5393 includes a phase detect circuit for the LRCK; thus, by changing the clock frequencies, the device is reset automatically when synchronization of MCLK on LRCK is not maintained. With this feature, resetting the AK5393 is only needed during power-up. Ideally, all external clocks--MCLK, BICK, and LRCK-- should always be present whenever the AK5393 is in normal operation (that is, when RST is High). In real applications, however, one or more of these clocks may not be present for a short amount of time. When this occurs, the AK5393 should be reset by setting the RST pin Low, which resets and powers down the device. Once all the clocks have been reinstated, the RST pin can again be set High for normal operation, completing the reset procedure. 128fs ! Table 2. System Clocks fs MCLK SCLK 32.0kHz 8.1920MHz 4.0960MHz 44.1kHz 11.2896MHz 5.6448MHz 48.0kHz 12.2880MHz 6.1440MHz 96.0kHz 12.2880MHz 6.1440MHz Caution: Due to its internal dynamic refresh logic, prolonged periods of time without external clock input may result in damage to the device. Serial Data Interface The AK5393 supports four serial data formats which can be selected using the SMODE1 and SMODE2 pins. Refer to Table 3. The data format is MSB first and 2's complement. Figures 6 through 9 show the timing diagrams for the four different types of serial data formats. Table 3. Serial Interface Formats LRCK Timing Diagram SMODE2 SMODE1 Mode Left Channel Right Channel L L Slave Mode H L Figure 7 L H Master Mode H L Figure 8 H L I2S Slave Mode L H Figure 9 H H I2S Master Mode L H Figure 6 1/1999 M0038-E-01/00 11 AK5393 ASAHI KASEI LRCK 0 1 2 3 19 20 21 22 23 24 0 1 2 3 19 20 21 22 23 24 0 1 SCLK FSYNC SDATA 23 22 21 5 4 3 2 1 0 5 4 3 2 1 0 23 22 21 5 4 3 2 1 0 23 22 5 4 3 2 1 0 23 FSYNC SDTA 23 22 23 22 23:MSB, 0:LSB Left Channel Data Right Channel Data Figure 6. Serial Data TimingNSlave Mode LRCK 0 1 2 3 20 21 22 23 24 25 33 34 0 1 2 3 20 21 22 23 24 25 33 34 0 1 SCLK FSYNC SDATA 23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 23 23:MSB, 0:LSB Left Channel Data Right Channel Data Figure 7. Serial Data TimingNMaster Mode (DFS = Low) 12 M0038-E-01/00 1/1999 ASAHI KASEI AK5393 LRCK 0 1 2 3 19 20 21 22 23 24 0 1 2 3 19 20 21 22 23 24 0 1 SCLK SDATA 23 22 6 5 4 3 2 1 0 23 22 6 5 4 3 2 1 0 23 23:MSB, 0:LSB Left Channel Data Right Channel Data Figure 8. Serial Data TimingNI2S Slave Mode LRCK 0 1 2 3 20 21 22 23 24 25 33 34 0 1 2 3 20 21 22 23 24 25 33 34 0 1 SCLK FSYNC SDATA 23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 23 23:MSB, 0:LSB Left Channel Data Figure 9. Serial Data Right Channel Data TimingNI2S Offset Calibration When the RST pin goes Low, the digital section of the AK5393 is powered down. When this pin returns to High, an offset calibration cycle is started. Such cycle should always be initiated after power-up. During the offset calibration cycle, the digital section of the AK5393 measures and store the calibration values of each channel into the registers. These calibration values are subtracted from all future outputs. Calibration values may be obtained from the analog input pins (AINL-, AINL+, AINR-, and AINR+) or from the common voltage pins (VCOML and VCOMR) depending on the 1/1999 Master Mode (DFS = Low) state of the ZCAL pin. When ZCAL is High, voltages from the analog input pins are measured. When ZCAL is Low, the common voltage pins are measured. The CAL pin is High during calibration. Digital High Pass Filter The AK5393 includes a digital High Pass Filter (HPF) used for DC offset cancellation. The cut-off frequency, fc, for the HPF is 1Hz at fs = 48kHz. This frequency also scales with the sampling rate, fs. The cut-off frequency can be calculated by fc = fs/48k. M0038-E-01/00 13 AK5393 ASAHI KASEI Design Considerations Figure 10 shows a system connection diagram. An evaluation board for this device is available, the AKD5393 (see the Ordering Information section). This board demonstrates the applications circuits, an optimum layout, power supply arrangements, and measurement results. 28 1 10 + 0.1 VREFL VREFR GNDL GNDR 27 2 Left Channel + Left Channel Reset and Calibration Control 25 AINL- AINR- ZCAL VA 0.1 22 AK5393 8 0.1 + 10 AGND VD - Analog +5V 21 BGND DGND 20 9 CAL TEST RST HPFE 19 10 18 11 Mode Select Right Channel 23 7 10 Right Channel + 24 6 + 10 0.22 AINR+ 5 Digital +3.3V to 5.0V VCOMR VCOML 4 AINL+ - + 26 3 0.22 0.1 SMODE2 DFS SMODE1 MCLK Mode Select 17 12 16 13 LRCK FSYNC SCLK SDATA 15 14 System Controller 256fs at DFS = L fs Figure 10. Typical Connection Diagram for Crystal Mode Grounding and Power Supply Decoupling Careful attention should be observed for the power supply and grounding of the AK5393. The system's analog and digital grounds are kept separate, but they should be connected together close to where the supplies are brought together into the printed circuit board. The decoupling capacitors should be as close to the AK5393 as possible, with the smaller valued ceramic capacitor being the one nearest to the device. Voltage Reference and Common Voltage The AK5393 reference voltage is a differential voltage between the output voltage reference pins (VREFL and 14 VREFR) and the ground pins (GNDL and GNDR). The GNDL and GNDR pins are connected to AGND. In addition, 10F electrolytic capacitor in parallel with a 0.1F ceramic capacitor should be connected between the VREFL and GNDL, and between the VREFR and GNDR pins to eliminate the effects of high-frequency noise. It is especially important to place the ceramic capacitors as close to the pins as possible. All digital signals, especially the clocks, should be kept away from the VREFL and VREFR pins to avoid unwanted coupling with the AK5393. No load current may be drawn from these pins. M0038-E-01/00 1/1999 ASAHI KASEI AK5393 The VCOML and VCOMR pins are the common voltages of the analog signals. To eliminate the effects of highfrequency noise, a 0.22F ceramic capacitor should be connected as close to each of these pins as possible. All signals, especially the clocks, should be kept away from the VCOML and VCOMR pins to avoid unwanted noise coupled into the AK5393. No load current may be drawn from these pins. Analog Inputs The AK5393 receives analog signals differentially into the modulator through the analog input pins (AINL-, AINL+, AINR-, and AINR+). Each pin full scale is typically 2.45VP-P. The AK5393 can accept input voltages from AGND to VA (that is, from 0V to 5V). The ADC output data is 2's complement. The 24-bit output code is 7FFFFFH for an input signal above a positive full scale, and 800000H for an input signal below a negative full scale. With no input signal, the ideal 24-bit code is 000000H. The DC offset is removed during the offset calibration, or by the HPF in the AK5393. Internally, the AK5393 samples the analog input signal at 128fs (that is, 6.144MHz at fs = 48kHz when the DFS pin is Low). The digital filter rejects noise above the stop band, except for multiples of 128fs. A simple RC filter may be used to attenuate any noise around 128fs so that most audio signals do not have significant energy at 128fs. The AK5393 accepts +5V voltage supply. The following conditions should be avoided: * Any voltage above VA + 0.3V * Any voltage below AGND - 0.3V * Any current beyond 10mA for the analog input pins. Caution: Excessive currents to the input pins may damage the device. Protect input pins from signals at or beyond the limits stated above, especially if using 15V in other analog circuits. ! Figure 11 shows a fully differential input buffer circuit example with an inverted amplifier (gain = -10dB). The 22nF capacitor between AINL-/AINR- and AINL+/AINR+ decreases the feed through noise of the modulator. The 51 resistor has been inserted to stabilize the op-amps before the ADC. This circuit acts also as a LPF with a cut-off frequency of about 140kHz. In this example, the internal offset is removed by self calibration. Refer to the evaluation board data sheet for complete details. 4.7k1/2 9101/2 7.8VP-P 2.5VP-P 100pF 4.7k1/2 Analog In AK5393 VP+ - 10F -VP+ 3k1/2 + 511/2 AINL+ or AINR+ + VPVPTo Bias NJM5532 9101/2 22nF 100pF VA+ 10F 10k1/2 -VP+ 3k1/2 Bias 10F AINL- or AINR- VPTo Bias + 10k1/2 511/2 + VA = +5V VP = 15V 2.5VP-P 0.1F CAL Low at self calibration ZCAL Figure 11. Example of a Differential Input Buffer Circuit 1/1999 M0038-E-01/00 15 AK5393 ASAHI KASEI Notes: 16 M0038-E-01/00 1/1999 ASAHI KASEI AK5393 Notes: 1/1999 M0038-E-01/00 17 AK5393 ASAHI KASEI Notes: 18 M0038-E-01/00 1/1999 ASAHI KASEI AK5393 Package Dimensions 28-Pin SOP Units: mm 1.095 Typical 10.4 0.3 7.5 0.2 Detail A 0u ~ 10u 0.75 0.2 2.2 0.1 18.7 0.3 0.1 + 0.1 or 0.1 - 0.05 0.10 1.27 + A 0.15 0.05 0.10 M 0.4 0.1 Material and Lead Frame Material: Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder Plate Package Markings 1/1999 AKM XXXBYYYYC: Data Code Identifier AK5393VS XXXBYYYYC XXXB: Lot Number (X: Digit Number, B: Alpha Character) YYYYC: Assembly Date (YYYY: Digit Number, C: Alpha Character) M0038-E-01/00 19 AK5393 ASAHI KASEI Ordering Information Part Number Temperature Range Package AK5393VS -10uC to +70uC 28-Pin SOP AKD5393 Evaluation Board Important Notice These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonable be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. It is the responsibility of the buyer or distributor of an AKM product who contributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. M0038-E-01/00 1/1999