AK5393VSP - AKM Semiconductor

M0038-E-01/00

1/1999

AK5393

24-Bit, 96kHz

Analog-to-Digital Converter

Features

• Proprietary dual-bit delta-sigma (

∆Σ

) architecture

• Sampling rate from 1kHz to 108kHz

• Full differential inputs

• Dynamic range = 117dB

• Signal-to-noise = 117dB

• Signal-to-(Noise + Distortion) = 105dB

• On-chip linear phase digital anti-alias ﬁlter

Passband from 0 to 21.768kHz at fs = 48kHz

Ripple = 0.001dB

Stopband attenuation = 110dB

• Selectable digital HPF or offset calibration

• Power supplies

Analog: 5V ± 5%

Digital: from 3V to 5.25V

• Low power dissipation: 470mW

• Small 28-pin SOP package

• Pin compatible with the AK5391, AK5392, and

AK5383

Description

The AK5393 is a 24-bit, 96kHz stereo Analog-to-

Digital Converter (ADC) that offers up to 117dB of

dynamic range and a 105dB Signal-to-(Noise +

Distortion) Ratio. The improved dynamic range and

lowered distortion are achieved using an innovative

dual-bit

Σ∆

architecture that reduces power

consumption and improves reliability.

The AK5393 include full differential inputs for

maximum signal range and performance. It also

includes a reference ﬁlter and a digital decimation

ﬁlter to minimize application requirements for

anti-aliasing ﬁltering. The user can select an internal

HPF to eliminate DC inputs or offset calibration. The

AK5393 outputs data at up to 108kHz, in several

selectable formats.

The AK5393 is available in a space-saving 28-pin

SOP package, and it operates over the full

commercial temperature range: –10˚C to 70˚C.

Block Diagram

VREFL

GNDL

VCOML

AINL+

AINL-

AINR+

AINR-

ZCAL

VCOMR

VREFR

GNDR

VA AGND BGND CAL RST VD DGND

Voltage

Reference

Æ· Modulator

Decimation

Filter

Controller Calibration

SRAM

Decimation

Filter

HPF

Voltage

Reference

Serial Output

Interface

SMODE1 SMODE2 SCLK LRCK FSYNC

SDATA

HPF

Enable

MCLK

Double

Speed

Select

AK5393 ASAHI KASEI

M0038-E-01/00

1/1999

Performance SpeciÞcations

Analog Characteristics

Ta = 25ûC, VA = 5.0V, VD = 3.3V, AGND= SGND = DGND = 0V, fs = 48kHz, Signal Frequency = 1kHz,

24-bit output, and measurement frequency = 10Hz to 20kHz, unless otherwise specified.

Parameter Conditions/Comments Min. Typ. Max. Units

Resolution 24 Bits

Analog Input Characteristics

Dynamic Range -60dBFS, A-Weighted 112 117 dB

Signal-to-Noise Ratio A-Weighted 112 117 dB

Signal-to-(Noise + Distortion) Ratio -1dBFS 98 105 dB

-20dBFS 94

-60dBFS 54

-1dBFS, fs = 96kHz

96 103

-20dBFS, fs = 96kHz

-60dBFS, fs = 96kHz

Interchannel Isolation 110 120 dB

Interchannel Gain Mismatch 0.1 0.5 dB

Gain Drift 150 ppm/ûC

Offset Error After Calibration HPF = Off ±200 ±1000 LSB

HPF = On ±1

Offset Drift HPF = Off ±10 LSB/ûC

Offset Calibration Range HPF = Off ±50 mV

Input Voltage (AIN+) - (AIN-) ±2.3 ±2.45 ±2.6 V

Input Impedance 2.4 4 k

Ω

Power Supplies

Analog Power Supply Current 90 130 mA

Digital Power Supply Current 6 9 mA

fs = 96kHz 9 14

Power Dissipation 470 680 mW

Power Supply Rejection

70 dB

Digital Characteristics

Ta = 25ûC, VA = 5.0V ± 5%, VD = 3.0V to 5.25V

Parameter Conditions/Comments Min. Typ. Max. Units

Input

High-Level Input Voltage 0.7VD V

Low-Level Input Voltage 0.3VD V

Input Leakage Current ±10 µA

Output

High-Level Output Voltage Iout = -20µA VD - 0.1 V

Low-Level Output Voltage Iout = 20µA 0.1 V

ASAHI KASEI AK5393

1/1999

M0038-E-01/00

Notes:

1. When fs = 96kHz, a measurement bandwidth of 40kHz is used.

2. The LSB refers to the Least Significant Bit of the 24-bit output data.

3. The Power Supply Rejection ratio is measured with a 1kHz, 20mV

P-P

input to VA and VD. VREFH is held at a constant

voltage.

4. The passband and stopband frequencies are proportional to fs.

5. The analog modulator samples the input at 6.144MHz for 48kHz output. There is no rejection of input signals which

are multiples of the sampling frequency. That is, there is no rejection for signals of the following frequencies:

n x 6.144MHz ± 21.768kHz, where n = 1, 2, 3, 4, ...

6. The Group Delay is the calculated delay time which takes place due to the digital filtering process. This time is taken

from when the analog signal is input, to the time of setting the 24-bit data (from both channels) to the output register.

When the HPF is on, this time is typically 40.7/fs if the DFS pin is Low, and 40.8/fs if the DFS pin is High.

7. The analog modulator samples the input at 6.144MHz for 96kHz output. There is no rejection of input signals which

are multiples of the sampling frequency. That is, there is no rejection for signals of the following frequencies:

n x 6.144MHz ± 43.536kHz, where n = 1, 2, 3, 4, ...

Filter CharacteristicsÑfs = 48kHz

fs = 48kHz,

Ta = 25ûC, VA = 5.0V ± 5%, VD = 3.0V to 5.25V, DFS = Low.

Parameter Conditions/Comments Min. Typ. Max. Units

ADC Digital Filter (Decimation LPF)

PB Passband

0 21.768 kHz

SB Stopband

26.232 kHz

PR Passband Ripple ±0.001 dB

SA Stopband Attenuation

110 dB

GD Group Delay

38.7 1/fs

∆

GD Group Delay Distortion 0 µs

ADC Digital Filter (HPF)

FR Frequency Response

-3dB 1.0 Hz

-0.1dB 6.5

Filter CharacteristicsÑfs = 96kHz

fs = 96kHz,

Ta = 25ûC, VA = 5.0V ± 5%, VD = 3.0V to 5.25V, DFS = High.

Parameter Conditions/Comments Min. Typ. Max. Units

ADC Digital Filter (Decimation LPF)

PB Passband

0 43.536 kHz

SB Stopband

52.464 kHz

PR Passband Ripple ±0.003 dB

SA Stopband Attenuation

110 dB

GD Group Delay

38.8 1/fs

∆

GD Group Delay Distortion 0 µs

ADC Digital Filter (HPF)

FR Frequency Response

-3dB 2.0 Hz

-0.1dB 13.0

Performance SpeciÞcation

(Continued)

AK5393 ASAHI KASEI

M0038-E-01/00

1/1999

Typical Performance Curves

-120

-80

-115

-110

-105

-100

-95

-90

-85

20 20k50 100 200 500 1k 2k 5k 10k

THD + N vs. Frequency

-160

-140

-120

-100

-80

-60

-40

-20

16384 Points, 8 Averages, 48kHz Sampling

20k50 100 200 500 1k 2k 5k 10k

0dB FFT

dBFS

-140

-120

-100

-80

-60

-40

-20

-140 0-120 -100 -80 -60 -40 -20

dBr

Linearity

dBFS

-160

-140

-120

-100

-80

-60

-40

-20

16384 Points, 8 Averages, 48kHz Sampling

20k50 100 200 500 1k 2k 5k 10k

-60dB FFT

dBFS

ASAHI KASEI AK5393

1/1999

M0038-E-01/00

Absolute Maximum Ratings

Note:

1. AGND and SGND must be at the same voltage.

Recommended Operating Conditions

Note:

1. The VA and VD power-up sequences are not critical.

AGND, SGND, and DGND = 0V. All voltages are with respect to ground.

Parameter

Min. Max. Units

Power Supplies

VA Analog Power Supply -0.3 6.0 V

VD Digital Power Supply -0.3 6.0 V

∆

GND

|SGND - DGND| 0.3 V

IIN Input CurrentÑAll pins except supply pins ±10 mA

VINA Analog Input Voltage -0.3 VA + 0.3 V

VIND Digital Input Voltage -0.3 VD + 0.3 V

Temperature

Ta Ambient Operating Temperature (Power Applied) -10 70 ¡C

Tstg Storage Temperature -65 150 ¡C

AGND, SGND, and DGND = 0V. All voltages are with respect to ground.

Parameter

Min. Typ. Max. Units

Power Supplies

VA Analog Power Supply 4.75 5.0 5.25 V

VD Digital Power Supply 3.0 3.3 5.25 V

Caution:

Exceeding minimum and maximum ratings may result in damage to the device.

AK5393 ASAHI KASEI

M0038-E-01/00

1/1999

Pin Layout

Pin Descriptions

No. Pin Name I/O Pin Function and Description

1 VREFL O

Left Channel Reference Voltage.

VREFL = 3.75V. This pin is normally connected

to the GNDL pin through a 10µF electrolytic capacitor and a 0.1µF ceramic capacitor

in parallel. Refer to the Design Considerations section for additional information.

2 GNDL -

Left Channel Reference Ground.

GNDL = 0V.

3 VCOML O

Left Common Voltage.

VCOML = 2.75V.

4 AINL+ I

Left Channel Analog Positive Input.

5 AINL- I

Left Channel Analog Negative Input.

6 ZCAL I

Zero Calibration Control.

This pin controls the calibration reference signal. When

ZCAL is Low, the VCOML and VCOMR are selected. When High, the analog inputs

(AINL+, AINL-, AINR+, and AINR-) are used for the reference level.

7VD -

Digital Power Supply.

VD = 3.3V.

8 DGND -

Digital Ground.

DGND = 0V.

9 CAL O

Calibration Active Signal.

When this pin outputs a High signal, it shows that the

offset calibration cycle is in progress. The offset calibration cycle starts when the RST

pin goes High. The CAL pin goes Low after 8704 clock cycles when DFS is Low or

after 17408 cycles when DFS is High.

10 RST I

Reset.

When this pin is Low, the digital section is powered down. When this pin

returns to High, an offset calibration cycle starts. An offset calibration cycle should

always be initiated upon powering up the device.

11 SMODE2 I

Serial Interface Mode Select.

The serial interface mode data should always be MSB

first, 2Õs complement formatted. See Table 3 for these pin definitions.

12 SMODE1 I

13 LRCK I/O

Left Channel and Right Channel Select Clock.

During resetÑwhen the SMODE1

pin is HighÑthe LRCK pin goes High when the SMODE2 pin is Low, and the LRCK

pin goes Low when the SMODE2 pin is High.

14 SCLK I/O

Serial Data Clock.

Data is clocked on the falling edge of SCLK. In the slave mode,

the SCLK pin requires a clock greater than 48fs. In the master mode, this pin outputs

a 128fs (when DFS is Low) clock or a 64fs clock. SCLK is Low during reset.

15 SDATA O

Serial Data Output.

Serial data output is MSB first and 2Õs complement formatted.

This pin is low during reset.

16 FSYNC I/O

Frame Synchronization Signal.

In slave mode, when FSYNC is High, the data bits

are clocked on SDATA. In the master mode, FSYNC outputs a 2fs clock and it is Low

during reset.

VREFL

GNDL

VCOML

AINL+

AINL-

ZCAL

DGND

CAL

RST

SMODE2

SMODE1

LRCK

SCLK

VREFR

GNDR

VCOMR

AINR+

AINR-

AGND

SGND

TEST

HPFE

DFS

MCLK Note:

See Table 1 for compatibility with

other AKM devices.

FSYNC

SDATA

Pin Descriptions

ASAHI KASEI AK5393

1/1999

M0038-E-01/00

Note:

1. All input pins, except pull-down pins, should not be left floating.

Table 1. AK5393 Compatibility with the AK5392

17 MCLK I

Master Clock Input.

Set the DFS pin Low for a 256fs input clock. Set the DFS pin

High for a 128fs clock.

18 DFS I

Double Speed Sampling Mode.

When this pin is Low, the chip is in normal speed

mode. When High, the double speed mode is selected.

19 HPFE I

High Pass Filter Enable.

When this pin is High, the high pass filter is enabled. When

Low, this pin is disabled.

20 TEST I

Test.

This pin should be connected to ground.

21 SGND -

Substrate Ground.

SGND = 0V.

22 AGND -

Analog Ground.

AGND = 0V.

23 VA -

Analog Power Supply.

VA = 5V.

24 AINR- I

Right Channel Analog Negative Input.

25 AINR+ I

Right Channel Analog Positive Input.

26 VCOMR O

Right Common Voltage Pin.

VCOMR = 2.75V.

27 GNDR -

Right Channel Reference Ground

. GNDR = 0V.

28 VREFR O

Right Channel Reference Voltage.

VREFR = 3.75V. This pin is normally connected

to the GNDR pin through a 10µF electrolytic capacitor and a 0.1µF ceramic capacitor

in parallel. Refer to the Design Considerations section for additional information.

AK5393 AK5392 AK5391 AK5383

Pin 2 GNDL GNDL VREFL- GNDL

Pin 18 DFS CMODE CMODE DFS

Pin 19 HPFE HPFE SEL24 HPFE

Pin 27 GNDR GNDR VREFR- GNDR

Maximum fs 108kHz 54kHz 54kHz 108kHz

Master Clock at 48kHz 256fs 256fs or 384fs 256fs or 384fs 256fs

Master Clock at 96kHz 128fs N/A N/A 128fs

No. Pin Name I/O Pin Function and Description

Pin Descriptions

(Continued)

AK5393 ASAHI KASEI

M0038-E-01/00

1/1999

Swithching Characteristics

Notes:

1. Refer to the Serial Data Interface section.

2. The specified LRCK edges do not coincide with the rising edges of SCLK.

3. tRCF and tRTV specify the number of LRCK rising edges after RST is brought High. This value is given for when the

device is operated in master mode. In slave mode, this value is one LRCK clock (1/fs) longer. When the DFS is High,

the number of cycles, 1/fs, is doubled.

Ta = 25ûC, VA = 5.0V ± 5%, VD = 3.0V to 5.25V, CL = 20pF.

Parameter Conditions/Comments Min. Typ. Max. Units

Control Clock Frequency

fCLK Master Clock Frequency 256fs 0.256 12.288 13.824 MHz

tCLKL Clock Pulse Width Low 29 ns

tCLKH Clock Pulse Width High 29 ns

fSLK Serial Data Output Clock (SCLK)

Frequency

6.144 6.912 MHz

fs Channel Select Clock (LRCK)

Frequency

1 48 108 kHz

Duty Cycle 25 75 %

Serial Interface TimingÑSlave Mode1 (SMODE = Low)

tSLK SCLK Period 144.7 ns

tSLKL SCLK Pulse Width Low 65 ns

tSLKH SCLK Pulse Width High 65 ns

tSLR SCLK Falling Edge to LRCK Edge Note 2 -45 45 ns

tDLR LRCK Edge to SDATA MSB Valid 45 ns

tDSS SCLK Falling Edge to SDATA Valid 45 ns

tSF SCLK Falling Edge to FSYNC Edge -45 45 ns

Serial Interface TimingÑMaster Mode (SMODE = High)

tSCLK SCLK Frequency DFS = Low 128fs Hz

DFS = High 64fs

SCLK Frequency Duty Cycle 50 %

fFSYNC FSYNC Frequency 2fs Hz

FSYNC Frequency Duty Cycle 50 %

tSLR SCLK Falling Edge to LRCK Edge -20 20 ns

tLRF LRCK Edge to FSYNC Rising Edge 1 tSLK

tDSS SCLK Falling Edge to SDATA Valid 45 ns

tSF SCLK Falling Edge to FSYNC Edge -20 20 ns

Reset and Calibration Timing

tRTW RST Pulse Width 150 ns

tRCR RST Falling to CAL Rising Edge 50 ns

tRCF RST Rising to CAL Falling Edge Note 3 8704 1/fs

tRTV RST Rising Edge to SDATA Valid Note 3 8960 1/fs

ASAHI KASEI AK5393

1/1999 M0038-E-01/00 9

Timing Diagrams

Figure 1. Serial Data Timing (Slave Mode, FSYNC = High)

Figure 2. Serial Data Timing (Slave Mode)

Figure 3. Serial Data Timing (I2S Slave Mode, FSYNC = DonÕt Care)

SCLK

LRCK

SDATA MSB MSB - 1 MSB - 2

tSLK

tSLKL tSLKH

tDSStDLR

tSLR

SCLK

FSYNC

LRCK

SDATA MSB D1 D0

tDSStDLR

tSF tSF

tSLR

SCLK

LRCK

SDATA MSB MSB - 1

tSLK

tSLKL tSLKH

tDSS

tSLR

tDSS

AK5393 ASAHI KASEI

10 M0038-E-01/00 1/1999

Timing Diagrams (Continued)

Figure 4. Serial Data Timing (Master Mode and I2S Master Mode, DFS = Low)

Figure 5. Reset and Calibration Timing

SCLK

FSYNC

LRCK

SDATA MSB MSB - 1

tDSS

tLRF

tSF tSF

tSLR

RST

CAL

SDATA

tRCR

tRTW

tRCF

tRTV

ASAHI KASEI AK5393

1/1999 M0038-E-01/00 11

Device Operation

System Clock Input

Three clocks are required to operate the AK5393: the

Master Clock (MCLK), the Left/Right Channels Select

Clock (LRCK), and the Serial Data Clock (SCLK). Refer

to Table 1. The MCLK should be synchronized with the

LRCK, but the phase is not critical. MCLK should be

256fs when in the normal sampling mode (i.e. DFS =

Low), and should be 128fs when in the double sampling

mode. Table 2 shows the standard audio word rates and

their corresponding frequencies.

Table 1. System Clocks

Table 2. System Clocks

The AK5393 includes a phase detect circuit for the

LRCK; thus, by changing the clock frequencies, the

device is reset automatically when synchronization of

MCLK on LRCK is not maintained. With this feature,

resetting the AK5393 is only needed during power-up.

Ideally, all e xternal clocks—MCLK, BICK, and LRCK—

should always be present whenever the AK5393 is in

normal operation (that is, when RST is High). In real

applications, however, one or more of these clocks may

not be present for a short amount of time. When this

occurs, the AK5393 should be reset by setting the RST

pin Low, which resets and powers do wn the de vice. Once

all the clocks hav e been reinstated, the RST pin can again

be set High for normal operation, completing the reset

procedure.

Serial Data Interface

The AK5393 supports four serial data formats which can

be selected using the SMODE1 and SMODE2 pins.

Refer to Table 3. The data format is MSB ﬁrst and

2’s complement. Figures 6 through 9 show the timing

diagrams for the four different types of serial data

formats.

Table 3. Serial Interface Formats

Normal Speed

(DFS = Low)

Double Speed

(DFS = High)

LRCK (maximum) 54kHz 108kHz

BICK Up to 128fs Up to 64fs

MCLK 256fs 128fs

fs MCLK SCLK

32.0kHz 8.1920MHz 4.0960MHz

44.1kHz 11.2896MHz 5.6448MHz

48.0kHz 12.2880MHz 6.1440MHz

96.0kHz 12.2880MHz 6.1440MHz

Caution:

Due to its internal dynamic refresh logic,

prolonged periods of time without external clock

input may result in damage to the device.

Timing Diagram SMODE2 SMODE1 Mode

LRCK

Left Channel Right Channel

Figure 6 L L Slave Mode H L

Figure 7 L H Master Mode H L

Figure 8 H L I2S Slave Mode L H

Figure 9 H H I2S Master Mode L H

AK5393 ASAHI KASEI

12 M0038-E-01/00 1/1999

Figure 6. Serial Data TimingÑSlave Mode

Figure 7. Serial Data TimingÑMaster Mode (DFS = Low)

SCLK

LRCK

FSYNC

0123 2019 21 22 23 24 0 1 2 3 2019 21 22 23 24 0 1

SDATA

FSYNC

23 22 21 23 22 23 2221453210 543210

2223 2223453210 543210 23

SDTA

Left Channel Data Right Channel Data

23:MSB, 0:LSB

SCLK

LRCK

FSYNC

0 1 2 3 20 21 22 23 24 25 3433

SDATA 23 22 23 22 23453210 543210

Left Channel Data Right Channel Data

23:MSB, 0:LSB

01 012 3 20 21 22 23 24 25 3433

ASAHI KASEI AK5393

1/1999 M0038-E-01/00 13

Figure 8. Serial Data TimingÑI2S Slave Mode

Figure 9. Serial Data TimingÑI2S Master Mode (DFS = Low)

Offset Calibration

When the RST pin goes Low, the digital section of the

AK5393 is powered down. When this pin returns to

High, an offset calibration cycle is started. Such cycle

should always be initiated after power-up.

During the offset calibration cycle, the digital section of

the AK5393 measures and store the calibration values of

each channel into the registers. These calibration values

are subtracted from all future outputs. Calibration v alues

may be obtained from the analog input pins (AINL-,

AINL+, AINR-, and AINR+) or from the common

voltage pins (VCOML and VCOMR) depending on the

state of the ZCAL pin. When ZCAL is High, voltages

from the analog input pins are measured. When ZCAL is

Low, the common voltage pins are measured. The CAL

pin is High during calibration.

Digital High Pass Filter

The AK5393 includes a digital High Pass Filter (HPF)

used for DC offset cancellation. The cut-off frequency,

fc, for the HPF is 1Hz at fs = 48kHz. This frequenc y also

scales with the sampling rate, fs. The cut-off frequency

can be calculated by fc = fs/48k.

SCLK

LRCK

SDATA

0123 2019 21 22 23 24 0 1 2 3 2019 21 22 23 24 0 1

23 22 6 23 22 236453210 543210

Left Channel Data Right Channel Data

23:MSB, 0:LSB

SCLK

LRCK

FSYNC

0 1 2 3 20 21 22 23 24 25 3433

SDATA 23 22 23 22 23453210 543210

Left Channel Data Right Channel Data

23:MSB, 0:LSB

01 012 3 20 21 22 23 24 25 3433

AK5393 ASAHI KASEI

14 M0038-E-01/00 1/1999

Design Considerations

Figure 10 shows a system connection diagram. An

evaluation board for this device is available, the

AKD5393 (see the Ordering Information section). This

board demonstrates the applications circuits, an optimum

layout, power supply arrangements, and measurement

results.

Figure 10. Typical Connection Diagram for Crystal Mode

Grounding and Power Supply Decoupling

Careful attention should be observed for the po wer supply

and grounding of the AK5393. The system’s analog and

digital grounds are kept separate, but they should be

connected together close to where the supplies are

brought together into the printed circuit board. The

decoupling capacitors should be as close to the AK5393

as possible, with the smaller valued ceramic capacitor

being the one nearest to the device.

Voltage Reference and Common Voltage

The AK5393 reference voltage is a differential voltage

between the output voltage reference pins (VREFL and

VREFR) and the ground pins (GNDL and GNDR). The

GNDL and GNDR pins are connected to AGND. In

addition, 10µF electrolytic capacitor in parallel with a

0.1µF ceramic capacitor should be connected between the

VREFL and GNDL, and between the VREFR and GNDR

pins to eliminate the effects of high-frequenc y noise. It is

especially important to place the ceramic capacitors as

close to the pins as possible.

All digital signals, especially the clocks, should be kept

away from the VREFL and VREFR pins to avoid

unwanted coupling with the AK5393. No load current

may be drawn from these pins.

Digital

+3.3V to 5.0V

Left Channel +

Left Channel -

Reset

and

Calibration

Control

Mode

Select

System

Controller

AK5393

Analog

+5V

VREFL

GNDL

VCOML

AINL+

AINL-

ZCAL

DGND

CAL

RST

SMODE2

SMODE1

LRCK

SCLK

VREFR

GNDR

VCOMR

AINR+

AINR-

AGND

BGND

TEST

HPFE

DFS

MCLK

FSYNC

SDATA

256fs at

DFS = L

10µ 0.1µ

0.22µ 0.22µ

10µ

0.1µ +

10µ 0.1µ

10µ

0.1µ +

Right Channel +

Right Channel -

Mode

Select

ASAHI KASEI AK5393

1/1999 M0038-E-01/00 15

The VCOML and VCOMR pins are the common voltages

of the analog signals. To eliminate the effects of high-

frequency noise, a 0.22µF ceramic capacitor should be

connected as close to each of these pins as possible. All

signals, especially the clocks, should be kept away from

the VCOML and VCOMR pins to avoid unwanted noise

coupled into the AK5393. No load current may be drawn

from these pins.

Analog Inputs

The AK5393 receives analog signals differentially into

the modulator through the analog input pins (AINL-,

AINL+, AINR-, and AINR+). Each pin full scale is

typically ±2.45VP-P. The AK5393 can accept input

voltages from A GND to VA (that is, from 0V to 5V). The

ADC output data is 2’s complement. The 24-bit output

code is 7FFFFFH for an input signal abov e a positive full

scale, and 800000H for an input signal below a negative

full scale. With no input signal, the ideal 24-bit code is

000000H. The DC offset is removed during the offset

calibration, or by the HPF in the AK5393.

Internally, the AK5393 samples the analog input signal at

128fs (that is, 6.144MHz at fs = 48kHz when the DFS pin

is Low). The digital ﬁlter rejects noise above the stop

band, except for multiples of 128fs. A simple RC ﬁlter

may be used to attenuate any noise around 128fs so that

most audio signals do not have signiﬁcant energy at

128fs.

The AK5393 accepts +5V voltage supply. The following

conditions should be avoided:

• Any voltage above VA + 0.3V

• Any voltage below AGND - 0.3V

• Any current beyond 10mA for the analog input pins.

Figure 11 shows a fully differential input buffer circuit

example with an inverted ampliﬁer (gain = -10dB). The

22nF capacitor between AINL-/AINR- and

AINL+/AINR+ decreases the feed through noise of the

modulator . The 51Ω resistor has been inserted to stabilize

the op-amps before the ADC. This circuit acts also as a

LPF with a cut-off frequency of about 140kHz. In this

example, the internal offset is removed by self calibration.

Refer to the evaluation board data sheet for complete

details.

Figure 11. Example of a Differential Input Buffer Circuit

Caution:

Excessive currents to the input pins may

damage the device. Protect input pins from

signals at or beyond the limits stated above,

especially if using ±15V in other analog circuits.

VP-

VP+

4.7k½

Analog In

7.8VP-P

NJM5532

VA = +5V

VP = ±15V

Bias

VA+

10k½

2.5VP-P

VP-

VP+

910½

AK5393

51½

100pF

VP-

VP+

910½

51½

To Bias

3k½

10µF

10µF 0.1µF

100pF

22nF

AINL+ or AINR+

AINL- or AINR-

CAL

ZCALLow at self calibration

AK5393 ASAHI KASEI

16 M0038-E-01/00 1/1999

Notes:

ASAHI KASEI AK5393

1/1999 M0038-E-01/00 17

Notes:

AK5393 ASAHI KASEI

18 M0038-E-01/00 1/1999

Notes:

ASAHI KASEI AK5393

1/1999 M0038-E-01/00 19

Package Dimensions

28-Pin SOP

Units: mm

Package Markings

1.095 Typical

7.5 ± 0.2

2.2 ± 0.1 10.4 ± 0.3

0.75 ± 0.2

18.7 ± 0.3

0.10

1.27

0.4 ± 0.1

0.1 + 0.1

0.1 - 0.05

0.15 ± 0.05

Detail A

0û ~ 10û

0.10

Material and Lead Frame Material:

Package molding compound:

Lead frame material:

Lead frame surface treatment:

Epoxy

Solder Plate

AK5393VS

XXXBYYYYC

XXXBYYYYC: Data Code Identifier

XXXB: Lot Number (X: Digit Number, B: Alpha Character)

YYYYC: Assembly Date (YYYY: Digit Number, C: Alpha Character)

AK5393 ASAHI KASEI

M0038-E-01/00

1/1999

Important Notice

These products and their speciﬁcations are subject to change without notice. Before considering any use or application, consult the

Asahi Kasei Microsystems Co., Ltd. (AKM) sales ofﬁce or authorized distributor concerning their current status.

AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any informa-

tion contained herein.

Any export of these products, or devices or systems containing them, may require an export license or other ofﬁcial approval under

the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.

AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related

device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Repre-

sentative Director of AKM. As used here:

a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in med-

icine, aerospace, nuclear energy, or other ﬁelds, in which its failure to function or perform may reasonable be expected to result in

loss of life or in signiﬁcant injury or damage to person or property.

b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indi-

rectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high

standards of performance and reliability.

It is the responsibility of the buyer or distributor of an AKM product who contributes, disposes of, or otherwise places the product

with a third party to notify that party in advance of the abo ve content and conditions, and the b uyer or distrib utor agrees to assume any

and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the

absence of such notiﬁcation.

Ordering Information

Part Number Temperature Range Package

AK5393VS -10ûC to +70ûC 28-Pin SOP

AKD5393 Evaluation Board