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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DThree Differential Transceivers in One
Package
DSignaling Rates† Up to 30 Mbps
DLow Power and High Speed
DDesigned for TIA/EIA-485, TIA/EIA-422, ISO
8482, and ANSI X3.277 (HVD SCSI Fast−20)
Applications
DCommon-Mode Bus Voltage Range
–7 V to 12 V
DESD Protection on Bus Terminals
Exceeds 12 kV
DDriver Output Current up to ±60 mA
DThermal Shutdown Protection
DDriver Positive and Negative Current
Limiting
DPower-Up, Power-Down Glitch-Free
Operation
DPin-Compatible With the SN75ALS170
DAvailable in Shrink Small-Outline Package
description
The SN65LBC170 and SN75LBC170 are
monolithic integrated circuits designed for
bidirectional data communication on multipoint
bus-transmission lines. Potential applications
include serial or parallel data transmission, cabled
peripheral buses with twin axial, ribbon, or
twisted-pair cabling. These devices are suitable
for FAST-20 SCSI and can transmit or receive
data pulses as short as 25 ns, with skew less
than 3 ns.
These devices combine three 3-state differential
line drivers and three differential input line
receivers, all of which operate from a single 5-V
power supply.
The driver differential outputs and the receiver
differential inputs are connected internally to form
three differential input/output (I/O) bus ports that
are designed to offer minimum loading to the bus
whenever the driver is disabled or VCC = 0. These
ports feature a wide common-mode voltage range
making the device suitable for party-line
applications over long cable runs.
Copyright 2002, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
logic diagram
1A
1DIR
1B
2A
2B
3A
3B
1D
2DIR
2D
3DIR
3D
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1D
1DIR
NC
GND
NC
2D
2DIR
NC
3D
3DIR
1B
1A
NC
NC
VCC
2B
2A
3B
3A
NC
SN65LBC170DW (marked as 65LBC170)
SN75LBC170DW (marked as 75LBC170)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1D
1DIR
NC
GND
2D
2DIR
3D
3DIR
1B
1A
NC
VCC
2B
2A
3B
3A
SN65LBC170DB (marked as BL170)
SN75LBC170DB (marked as BL170)
(TOP VIEW)
NC − No internal connection
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2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The driver’s active-high enable and the receiver’s active-low enable are tied together internally and provide a
direction input for each driver/receiver pair.
The SN75LBC170 is characterized for operation over the temperature range of 0°C to 70°C. The SN65LBC170
is characterized for operation over the temperature range of −40°C to 85°C.
AVAILABLE OPTIONS†
PACKAGE
TAPLASTIC SHRINK SMALL-OUTLINE
(JEDEC MO-150) PLASTIC SMALL-OUTLINE
(JEDEC MS-013)
0°C to 70°C SN75LBC170DB SN75LBC170DW
−40°C to 85°C SN65LBC170DB SN65LBC170DW
†Add R suffix for taped and reel
†For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
INPUT
DOUTPUTS
H
L
OPEN
X
X
EACH DRIVER
A
H
L
L
Z
X
L
H
H
Z
X
B
ENABLE DIFFERENTIAL INPUT
(VA−VB)OUTPUT
D
ENABLE
DIR
VID ≥ 0.2 V L H
−0.2 V < VID < 0.2 V L ?
VID ≤ − 0.2 V L L
XHZ
EACH RECEIVER
Function Tables
DIR
H
H
H
L
OPEN OPEN LH
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
VCC
VCC
DIR INPUTS
1 kΩ
8 V
Input
100 kΩ
D I/O
VCC
VCC
A INPUT
16 V
16 V
100 kΩ
18 kΩ
4 kΩ
4 kΩ
Input
VCC
B INPUT
16 V
16 V 100 kΩ
18 kΩ
4 kΩ
4 kΩ
Input
16 V
16 V
18 kΩ
4 kΩ
4 kΩ
VCC
Output
A AND B OUTPUT
40 Ω
8 V 100 kΩ
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absolute maximum ratings† over operating free−air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus I/O terminal (steady state) −10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage input range, A and B, (transient pulse through 100 Ω, see Figure 12) −30 V to 30 V. . . . . . . . . . . . . .
Voltage range at any D or DIR terminal − 0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver output current, IO ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: Human body model (A, B, GND) (see Note 2) 12 kV. . . . . . . . . . . . . . . . . . . . . . . . . .
All pins 5 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged-device model (all pins) (see Note 3) 1 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Power Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114−A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
POWER DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR}
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
DB 995 mW 8.0 mW/°C635 mW 515 mW
DW 1480 mW 11.8 mW/°C950 mW 770 mW
‡This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus I/O terminal A, B −7 12 V
High-level input voltage, VIH
D, DIR
2 VCC
V
Low-level input voltage, VIL D, DIR 0 0.8 V
Differential input voltage, VID A with respect to B −12 12 V
Output current
Driver −60 60
mA
Output current Receiver −8 8 mA
Operating free-air temperature, TA
SN75LBC170 0 70
°C
Operating free-air temperature, TASN65LBC170 −40 85 °C
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DRIVER SECTION
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage D and DIR II = 18 mA −1.5 −0.7 V
VOOpen-circuit output voltage (single-ended) A or B, No load 0 VCC V
Steady-state differential output voltage
No load 3.8 4.3 VCC
|V
OD(SS)|
Steady-state differential output voltage
magnitude‡
RL = 54 Ω,See Figure 1 1 1.6 2.4 V
|VOD(SS)|
magnitude‡
With common-mode loading, See Figure 2 1 1.6 2.4
V
∆VOD Change in differential output voltage
magnitude, | VOD(H) | – |VOD(L) |
RL = 54 Ω,
−0.2 0.2
V
VOC(SS) Steady-state common-mode output voltage RL = 54 Ω,
CL = 50 pF
See Figure 1 2 2.4 2.8
V
∆VOC(SS) Change in steady-state common-mode output
voltage (VOC(H) – VOC(L))
CL = 50 pF
See Figure 1
−0.2 0.2 V
IIInput current D, DIR −100 100 µA
IOOutput current with power off VCC = 0 V, VO = −7 V to 12 V −700 900 µA
IOS Short-circuit output current VO = −7 V to 12 V, See Figure 7 −250 250 mA
ICC Supply current (driver enabled) D at 0 V or VCC,DIR at VCC, No load 14 20 mA
†All typical values are at VCC = 5 V and TA = 25°C.
‡The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
lower output signal into account in determining the maximum signal-transmission distance.
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Differential output propagation delay, low-to high 4 8.5 12
tPHL Differential output propagation delay, high-to-low 4 8.5 11
trDifferential output rise time 3 7.5 11
tfDifferential output fall time R
L
= 54 Ω, C
L
= 50 pF, See Figure 3 3 7.5 11 ns
tsk(p) Pulse skew | (tPLH – tPHL) |
RL = 54 Ω, CL = 50 pF, See Figure 3
2
ns
tsk(o) Output skew§1.5
tsk(pp) Part-to-part skew¶2
tPLH Differential output propagation delay, low-to high 3 7 10
tPHL Differential output propagation delay, high-to-low 3 7.5 10
trDifferential output rise time
See Figure 4,
3 7.5 12
tfDifferential output fall time See Figure 4,
(HVD SCSI double-terminated load)
3 7.5 12 ns
tsk(p) Pulse skew | (tPLH – tPHL) |
(HVD SCSI double-terminated load)
3
ns
tsk(o) Output skew§1.5
tsk(pp) Part-to-part skew¶2.5
tPZH Output enable time to high level
See Figure 5
15 25
ns
tPHZ Output disable time from high level
See Figure 5
18 25
ns
tPZL Output enable time to low level
See Figure 6
10 25
ns
tPLZ Output disable time from low level See Figure 6 17 25 ns
§Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
¶Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
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RECEIVER SECTION
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+ Positive-going differential input voltage threshold 0.2
V
VIT− Negative-going differential input voltage threshold See Figure 8 −0.2 V
Vhys Hysteresis voltage (VIT+ − VIT−)
See Figure 8
40 mV
VOH High-level output voltage VID = 200 mV, I OH = −8 m A, See Fi gure 8 4 4.7 VCC
V
VOL Low-level output voltage VID = −200 mV, IOL = −8 mA , See Figur e 8 0 0.2 0.4 V
II
Line input current
Other input = 0 V
VI = 12 V 0.9
mA
IILine input current Other input = 0 V VI = −7 V −0.7 mA
RIInput resistance A, B 12 kΩ
ICC Supply current (receiver enabled) A, B, D, and DIR open 16 mA
†All typical values are at VCC = 5 V and TA = 25°C.
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high level output 7 16 ns
tPHL Propagation delay time, high-to-low level output
See Figure 9
7 16 ns
trReceiver output rise time See Figure 9 1.3 3 ns
tfReceiver output fall time 1.3 3 ns
tPZH Receiver output enable time to high level
See Figure 10
26 40
ns
tPHZ Receiver output disable time from high level See Figure 10 40 ns
tPZL Receiver output enable time to low level
See Figure 11
29 40
ns
tPLZ Receiver output enable time to high level See Figure 11 40 ns
tsk(p) Pulse skew (| tPLH – tPHL |) 2 ns
tsk(o) Output skew‡1.5 ns
tsk(pp) Part-to-part skew§3 ns
‡Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
§Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
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PARAMETER MEASUREMENT INFORMATION
IO
IO
VOD
VOC
II
VO
27 Ω
VO50 pF†
27 Ω
0 V or 3 V
† Includes probe and jig capacitance
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
VTEST = −7 V to 12 V
VOD
Input 60 Ω375 Ω
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
VOD
RL = 54 Ω
50 Ω
Signal
Generator{
CL = 50 pF}
90%
Output 0 V
10%
tf
tr
Input
0 V
3 V
tPHL
1.5 V
tPLH
90% 10%
VOD(H
)
VOD(L
)
1.5 V
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 3. Driver Switching Test Circuit and Waveforms, 485-Loading
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PARAMETER MEASUREMENT INFORMATION
VOD
75 Ω
50 Ω
Signal
Generator{
90%
Output 0 V
10%
tf
tr
Input
0 V
3 V
tPHL
1.5 V
tPLH
90% 10%
VOD(H
)
VOD(L)
1.5 V
S1
0 V
5 V
375 Ω
165 Ω
165 Ω375 Ω
S2
0 V
5 V
60 pF‡
60 pF‡
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 4. Driver Switching Test Circuit and Waveforms, HVD SCSI-Loading (double terminated)
Output 2.3 V
Input
0 V
3 V
1.5 V
tPZH 0.5 V
0 V
VOH
tPHZ
S1
50 Ω
Generator}
0
V or 3 V{
Input
RL = 110 Ω
Output
CL = 50 pF§
1.5 V
A
B
† 3 V if testing A output, 0 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
w Includes probe and jig capacitance
Figure 5. Driver Enable/Disable Test, High Output
Output 2.3 V
Input
0 V
3 V
1.5 V
tPZL
0.5 V
5 V
VOL
tPLZ
S1
50 Ω
Generator‡
Input
RL = 110 Ω
Output
CL = 50 pF§
1.5 V
5 V
B
A
† 0 V if testing A output, 3 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
w Includes probe and jig capacitance
0 V or 3 V{
Figure 6. Driver Enable/Disable Test, Low Output
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PARAMETER MEASUREMENT INFORMATION
Voltage
Source
VO
IOS
Figure 7. Driver Short-Circuit Test
VID VO
IO
Figure 8. Receiver DC Parameters
VID
IO
50 Ω
Generator{
Generator{
50 Ω
A
B
D
VO
1.5 V
1.5 V1.5 V
trtf
90% 90%
10%10%
tPLH tPHL
3 V
0 V
VOH
VOL
Input B
Input A
Output
CL = 15 pF}
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 9. Receiver Switching Test Circuit and Waveforms
50 Ω
Generator{
A
B
D1.5 V
1.5 V
tPZH tPHZ
3 V
0 V
VOH
GND
CL = 15 pF}
1.5 V 1 kΩ
DIR
VCC
1.5 V
VOH −0.5 V
DIR
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 10. Receiver Enable/Disable Test, High Output
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PARAMETER MEASUREMENT INFORMATION
50 Ω
Generator{
A
B
D1.5 V
1.5 V
tPZL tPLZ
3 V
0 V
VCC
CL = 15 pF}
−1.5 V 1 kΩ
DIR
V
CC
1.5 V
VOL + 0.5 V
VOL
DIR
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 11. Receiver Enable/Disable Test, Low Output
100 Ω
Pulse
Generator,
15-µs Duration,
1% Duty Cycle
VTEST
−VTEST
15 µs1.5 ms
0 V
Figure 12. Test Circuit and Waveform, Transient Over Voltage Test
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TYPICAL CHARACTERISTICS
Figure 13
0
0.5
1
1.5
2
2.5
3
3.5
4
0 20406080100
VCC = 5.25 V VCC = 5 V
VCC = 4.75 V
− Differential Output Voltage − V
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
IO − Output Current − mA
VOD
Figure 14
0
0.5
1
1.5
2
2.5
−60 −40 −20 0 20 40 60 80 100
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
− Differential Output Voltage − V
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOD
TA − Free-Air Temperature − °C
Figure 15
4
5
6
7
8
9
10
11
12
−40 −20 0 20 40 60 80
SCSI Load
RS−485 Load
TA − Free-Air Temperature − °C
Driver Propagation Delay − ns
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
Figure 16
135
140
145
150
155
160
165
0.1 1 10 100
− Supply Current − mA
Signaling Rate − Mbps
SUPPLY CURRENT
vs
SIGNALING RATE
ICC
All 3 Channels Driving
RL = 54 Ω,
CL = 50 pF (Each Channel),
Pseudorandom NRZ Data
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TYPICAL CHARACTERISTICS
Figure 17
−600
−400
−200
0
200
400
600
800
−10 −5 0 5 10 15
VCC = 0 V
VCC = 5 V
Bus Input Current −
Bus Input Voltage − V
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
Aµ
Figure 18
4
5
6
7
8
9
10
11
12
−40 −20 0 20 40 60 80
tPLH
tPHL
− Receiver Propagation Delay Time − ns
RECEIVER PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature°C
tpd
Signal
Generator
SN65LBC170
(as Driver)
100 Ω
15 pF
SN65LBC170
(as Receiver)
15 Meters, Cat. 5
Twisted-Pair Cable
Figure 19. Circuit Diagram for Signaling Characteristics
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TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
Receiver Output
(5 V/div)
25 ns
Figure 20. Signal Waveforms at 30 Mbps
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
Receiver Output
(5 V/div)
12.5 ns
Figure 21. Eye Patterns, Pseudorandom Data at 30 Mbps
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TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
Receiver Output
(5 V/div)
25 ns
Figure 22. Signal Waveforms at 50 Mbps
12.5 ns
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
Receiver Output
(5 V/div)
Figure 23. Eye Patterns, Pseudorandom Data at 50 Mbps
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LBC170DB ACTIVE SSOP DB 16 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC170DBG4 ACTIVE SSOP DB 16 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC170DBR ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC170DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC170DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC170DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC170DB ACTIVE SSOP DB 16 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC170DBG4 ACTIVE SSOP DB 16 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC170DBR ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC170DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC170DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN75LBC170DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC170DBR SSOP DB 16 2000 367.0 367.0 38.0
SN75LBC170DBR SSOP DB 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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