OUT
NR
GND
EN
IN
3
2
4
1
5
2.2 µF 2.2 µF
10 nF
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TPS72301
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TPS723xx 200mA Low-Noise, High-PSRR
Negative Output Low-Dropout Linear Regulators
1 Features 3 Description
The TPS723xx family of low-dropout (LDO) negative
1• Ultralow Noise: 60 μVRMS Typical voltage regulators offers an ideal combination of
• High PSRR: 65 dB Typical at 1 kHz features to support low noise applications. These
• Low Dropout Voltage: 280 mV Typical at 200 mA, devices are capable of operating with input voltages
2.5 V from –10 V to –2.7 V, and support outputs from –10 V
to –1.2 V. These regulators are stable with small, low-
• Available in –2.5-V and Adjustable (–1.2 V to cost ceramic capacitors, and include enable (EN) and
–10 V) Versions noise reduction (NR) functions. Thermal short-circuit
• Stable With a 2.2-μF Ceramic Output Capacitor and over-current protections are provided by internal
• Less Than 2-μA Typical Quiescent Current in detection and shutdown logic. High PSRR (65 dB at
Shutdown Mode 1 kHz) and low noise (60 μVRMS) make the TPS723xx
ideal for low-noise applications.
• 2% Overall Accuracy
(Line, Load, Temperature) The TPS723xx uses a precision voltage reference to
achieve 2% overall accuracy over load, line, and
• Thermal and Over-Current Protection temperature variations. Available in a small SOT23-5
• SOT23-5 (DBV) Package package, the TPS723xx family is fully specified over
• SOT-5 (DDC) Package a temperature range of –40°C to 125°C.
• Operating Junction Temperature Range: –40°C to Device Information(1)
125°C PART NUMBER PACKAGE(2) BODY SIZE (NOM)
2 Applications SOT-23 (5) 2.90 mm x 1.60 mm
TPS723xx SOT (5) 2.90 mm x 1.60 mm
• Optical Drives (1) For all available packages, see the orderable addendum at
• Optical Networking the end of the datasheet.
• Noise Sensitive Circuitry (2) The two SOT23 packages are identical in size, but the SOT
• GaAs FET Gate Bias package is thinner.
• Video Amplifiers
Typical Application Circuit
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS72301
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Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 13
8.1 Application Information............................................ 13
2 Applications ........................................................... 18.2 Typical Application.................................................. 13
3 Description............................................................. 18.3 Do's and Don'ts....................................................... 14
4 Revision History..................................................... 29 Power-Supply Recommendations...................... 15
5 Pin Configuration and Functions......................... 310 Layout................................................................... 15
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 15
6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Example .................................................... 15
6.2 Handling Ratings....................................................... 410.3 Power Dissipation ................................................. 15
6.3 Recommended Operating Conditions....................... 410.4 Thermal Protection................................................ 15
6.4 Thermal Information.................................................. 411 Device and Documentation Support................. 16
6.5 Electrical Characteristics........................................... 511.1 Device Support...................................................... 16
6.6 Typical Characteristics.............................................. 611.2 Related Links ........................................................ 16
7 Detailed Description............................................ 11 11.3 Trademarks........................................................... 16
7.1 Overview................................................................. 11 11.4 Electrostatic Discharge Caution............................ 16
7.2 Functional Block Diagrams ..................................... 11 11.5 Glossary................................................................ 16
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 12 Information ........................................................... 16
4 Revision History
Changes from Revision B (July 2007) to Revision C Page
• Changed format to meet latest data sheet standards; added new sections, and moved existing sections .......................... 1
• Added bullet item for DDC package to Features list ............................................................................................................. 1
• Revised Device Information table to include SOT-5 package................................................................................................ 1
• Updated Typical Application Circuit to show SOT-5 (DDC) package pin configuration......................................................... 1
• Added pin configuration drawings ......................................................................................................................................... 3
• Deleted Dissipation Ratings table; see Thermal Information ................................................................................................ 4
• Changed y-axis title in Figure 11 to Feedback Current from Supply Current ....................................................................... 6
• Reworded second paragraph in Current Limit subsection. .................................................................................................. 12
Changes from Revision A (June 2007) to Revision B Page
• Added second paragraph in Current Limit subsection ........................................................................................................ 12
• Changed equation shown in Figure 27 ................................................................................................................................ 13
Changes from Original (September 2003) to Revision A Page
• Changed document format to correspond to current product line standards......................................................................... 1
• Removed Output Voltage vs Output Current graph (original Fig 2) ...................................................................................... 6
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3
2
4
5
1
NR/FB
OUT
GND
IN
EN
3
2
4
5
1
NR/FB
OUT
GND
IN
EN
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SLVS346C –SEPTEMBER 2003–REVISED SEPTEMBER 2014
5 Pin Configuration and Functions
DBV PACKAGE DDC PACKAGE
SOT23-5 SOT-5
Top View Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
GND 1 — Ground
IN 2 I Input supply
Bipolar enable pin. Driving this pin above the positive enable threshold or below the negative enable
EN 3 I threshold turns on the regulator. Driving this pin below the positive disable threshold and above the
negative disable threshold puts the regulator into shutdown mode.
Fixed voltage versions only. Connecting an external capacitor between this pin and ground, bypasses
NR 4 — noise generated by the internal bandgap. This configuration allows output noise to be reduced to very
low levels.
Adjustable voltage version only. This pin is the input to the control loop error amplifier. It is used to set
FB 4 I the output voltage of the device.
Regulated output voltage. A small, 2.2-μF ceramic capacitor is needed from this pin to GND to ensure
OUT 5 O stability.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
IN –11 +0.3 V
NR –11 +5.5 V
Voltage EN –VI+5.5 V
OUT –11 +0.3 V
Current OUT Internally limited A
Output short-circuit duration Indefinite
See Thermal Information
Continuous total power dissipation table
Operating junction temperature, TJ–65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –1000 1000
pins
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification –500 500
JESD22-C101, all pins
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIInput supply voltage range –10 –2.7 V
IOOutput current 0 200 mA
TJOperating junction temperature –40 125 °C
6.4 Thermal Information TPS723xx
THERMAL METRIC(1) DBV DDC UNIT
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 206.9 194.8
RθJC(top) Junction-to-case (top) thermal resistance 120.5 41.4
RθJB Junction-to-board thermal resistance 35.9 35.9 °C/W
ψJT Junction-to-top characterization parameter 13.3 1.0
ψJB Junction-to-board characterization parameter 35.0 35.7
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Over operating junction temperature range, VI= VO(NOM) – 0.5 V, IO= 1 mA, VEN = 1.5 V, CO= 2.2 μF, and CNR = 0.01 μF,
unless otherwise noted. Typical values are at TJ= 25°C. TPS723xx
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIInput voltage range(1) –10 –2.7 V
VFB Feedback reference voltage TPS72301 TJ= 25°C –1.210 –1.186 –1.162 V
Output voltage range TPS72301 –10 + VDO VFB V
Nominal TJ= 25°C –1% 1%
TPS72325 vs
VO–2% ±1% 2%
Accuracy VI/IO/T –10 V ≤VI≤VO– 0.5 V,
10 μA≤IO≤200 mA
TPS72301 vs –3% ±1 3%
VI/IO/T
ΔVO(ΔVI) Line regulation –10 V ≤VI≤VO(NOM) – 0.5 V 0.04 %/V
ΔVO(ΔIO) Load regulation 0 mA ≤IO≤200 mA 0.002 %/mA
Dropout voltage at
VDO TPS72325 IO= 200 mA 280 500 mV
VO= 0.96 × VO(NOM)
I(LIM) Current limit VO= 0.85 × VO(NOM) 300 550 800 mA
IO= 0 mA (IQ), 130 200
–10 V ≤VI≤VO– 0.5 V
I(GND) Ground pin current μA
IO= 200 mA, 350 500
–10 V ≤VI≤VO– 0.5 V
–0.4 V ≤VEN ≤0.4 V,
I(SHDN) Shutdown ground pin current 0.1 2.0 μA
–10 V ≤VI≤VO– 0.5 V
I(FB) Feedback pin current –10 V ≤VI≤VO– 0.5 V 0.05 1.0 μA
IO= 200 mA, 1 kHz, 65
CI= CO= 10 μF
PSRR Power-supply rejection ratio TPS72325 dB
IO= 200 mA, 10 kHz, 48
CI= CO= 10 μF
CO= 10 μF, 10 Hz to 100 kHz,
VnOutput noise voltage TPS72325 60 μVRMS
IO= 200 mA
VO= –2.5 V, CO= 1 μF,
tSTR Startup time 1 ms
RL= 25 Ω
VEN(HI) Enable threshold positive 1.5 V
VEN(LO) Enable threshold negative –1.5 V
VDIS(HI) Disable threshold positive 0.4 V
VDIS(LO) Disable threshold negative –0.4 V
–10 V ≤VI≤VO– 0.5 V,
I(EN) Enable pin current 0.1 2.0 μA
–10 V ≤VEN ≤±3.5 V
Shutdown, temperature increasing 165
Tsd Thermal shutdown temperature °C
Reset, temperature decreasing 145
TJOperating junction temperature –40 125 °C
(1) Maximum VI= (VO– VDO) or – 2.7 V, whichever is more negative.
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350
300
250
200
150
100
50
0
JunctionTemperature( C)°
-40 -20 0 20 40 60 80 100 120 140
DropoutVoltage(mV)
500
450
400
350
300
250
200
150
100
50
0
InputVoltage(V)
-10 -9-8-7-6-5-4-3-2-1 0
GroundCurrent( A)m
NoLoad
R =12.5W
L
350
300
250
200
150
100
50
0
OutputCurrent(mA)
0 25 50 75 100 125 150 175 200
DropoutVoltage(mV)
T =+25 C
J°
T = 40°
JC
-
T =+125 C
J°
-2.475
-2.488
-2.500
-2.513
-2.525
InputVoltage(V)
-10 -9-8-7-2
OutputVoltage(V)
T =+25 C
J°
T =+125 C
J°
T =+85°
JC
-6-5-4-3
T = 40- °
JC
-2.475
-2.488
-2.500
-2.513
-2.525
AmbientTemperature (°C)
-40 -20 0 20 40 60 80 100 120 140
OutputVoltage,V (V)
OUT
VIN OUT
=3V,I =200mA
VIN OUT
=10V,I =200mA
VIN =10V,IOUT =0mA
VIN OUT
=3V,I =0mA
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,
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6.6 Typical Characteristics
TPS72325 at VI= VO(NOM) – 0.5 V, IO= 1 mA, VEN = 1.5 V, CO= 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
Figure 1. Output Voltage vs Input Voltage Figure 2. Output Voltage vs Ambient Temperature
Figure 3. TPS72301 Dropout Voltage vs Input Voltage Figure 4. Dropout Voltage vs Output Current
Figure 5. TPS72325 Dropout Voltage vs Junction Figure 6. Ground Current vs Input Voltage
Temperature
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1000
800
600
400
200
0
-200
-400
-600
-800
-1000
AmbientTemperature( C)°
-40 -20 0 20 40 60 80 100 120 140
EnablePinCurrent(nA)
V = 10V,V-
IN EN = 0.5V-
V = 10V,V-
IN EN = 10V-
V = 10V,V-
IN EN =3.5V
200
0
-200
-400
-600
-800
-1000
-1200
-1400
-1600
-1800
-2000
Junction Temperature ( C)°
-40 -20 0 20 40 60 80 100 120 140
V = 2.5V-
OUT
V = 1.2V-
OUT
Feedback Current (nA)
800
750
700
650
600
550
500
450
400
350
300
JunctionTemperature( C)°
-40 -20 0 20 40 60 80 100 120 140
CurrentLimit(mA)
250
200
150
100
50
0
JunctionTemperature( C)°
-40 -20 0 20 40 60 80 100 120 140
StandbyCurrent(nA)
V = 3V
IN -
V = 10V
IN -
400
350
300
250
200
150
100
50
0
OutputCurrent(mA)
0 50 100 150 200
GroundCurrent( A)m
T =+25 C
J°
T =+125 C
J°
T = 40- °
JC
500
450
400
350
300
250
200
150
100
50
0
JunctionTemperature( C)°
-40 -20 0 20 40 60 80 100 120 140
GroundCurrent( A)m
V =3V,I =0mA
IN OUT
V =10V,I =0mA
IN OUT
V =10V,I =200mA
IN OUT
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Typical Characteristics (continued)
TPS72325 at VI= VO(NOM) – 0.5 V, IO= 1 mA, VEN = 1.5 V, CO= 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
Figure 7. Ground Current vs Output Current Figure 8. Ground Current vs Junction Temperature
Figure 9. TPS72325 Current Limit vs Junction Temperature Figure 10. Standby Current vs Junction Temperature
Figure 11. TPS72301 Feedback Pin Current vs Junction Figure 12. Enable Pin Current vs Junction Temperature
Temperature
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100
0
0
-100
-200
Time( s)m
0 20 40 60 80 100 120 140 160 180 200
CurrentLoad(mA)
DV ,ChangeIn
OUT
OutputVoltage(mV)
C =2.2 F
IN m
C =2.2 F
OUT m
C =0 F
NR m
Time(ms)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OutputVoltage(mV)
InputVoltage(V)
CIN =2.2mF
COUT =2.2mF
I =50mA
OUT
CNR =0mF
100
50
0
-50
0
-3.0
-3.5
-4.0
-4.5
Time( s)m
0 20 40 60 80 100 120 140 160 180 200
OutputVoltage(mV)
InputVoltage(V)
C =2.2 F
IN m
C =2.2 F
OUT m
C =0 F
NR m
100
0
0
-100
-200
Time( s)m
0 20 40 60 80 100 120 140 160 180 200
DV ,ChangeIn
OUT
OutputVoltage(mV)
CurrentLoad(mA)
C =2.2 F
IN m
C =2.2 F
OUT m
C =0 F
NR m
0.25
0.13
0
-0.13
-0.25
JunctionTemperature( C)°
-40 -20 0 20 40 60 80 100 120 140
LineRegulation(%/V)
LoadRegulation(%/mA)
Load
Line
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Typical Characteristics (continued)
TPS72325 at VI= VO(NOM) – 0.5 V, IO= 1 mA, VEN = 1.5 V, CO= 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
Figure 13. Line And Load Regulation vs Junction Figure 14. TPS72301 Minimum Required Input Voltage vs
Temperature Output Voltage
Figure 15. TPS72325 Line Transient Response Figure 16. TPS72325 Load Transient Response
Figure 18. TPS72325 Start-Up Response
Figure 17. TPS72325 Load Transient Response
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10m
1m
100n
10n
Frequency(Hz)
100 1k 10k 100k
NoiseSpectralDensity(V / )ÖHz
RMS
C =0.01 F
IN m
C =2.2 F
OUT m
C =0.01 F
NR m
I =100mA
OUT
I =25 A
OUT m
10m
1m
100n
10n
Frequency(Hz)
100 1k 10k 100k
NoiseSpectralDensity(V / )ÖHz
RMS
C =0 F
IN m
C =2.2 F
OUT m
C =0.01 F
NR m
I =100mA
OUT
I =25 A
OUT m
250
200
150
100
50
0
C (pF)
NR
1 10 100 1k 10k 100k
TotalNoise( V )mRMS
C =2.2
OUT OUT
mF,I =100mA
C =10
OUT OUT
mF,I =100mA
C =2.2 F,Im
OUT OUT =25mA
C =10 F,Im
OUT OUT =25mA
C =2.2m
IN F
Time(1ms/div)
OutputNoise(100 V/div)m
C 2.2m
IN =-F,C m
OUT =2.2 F
I =0.01m
OUT =100mA,CNR F
Time(ms)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OutputVoltage(mV)
InputVoltage(V)
CIN =2.2mF
COUT =2.2mF
I =50mA
OUT
CNR =0.01mF
0
1
2
0
1
2
3
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Typical Characteristics (continued)
TPS72325 at VI= VO(NOM) – 0.5 V, IO= 1 mA, VEN = 1.5 V, CO= 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
Figure 19. TPS72325 Start-Up Response Figure 20. TPS72325 Power-Up/Power-Down
Figure 22. TPS72325 Output Noise vs Time
Figure 21. TPS72325 Total Noise vs CNR (10 Hz to 100 kHz)
Figure 23. TPS72325 Noise Spectral Density vs Frequency Figure 24. TPS72325 Noise Spectral Density vs Frequency
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90
80
70
60
50
40
30
20
10
0
-10
Frequency(Hz)
10 100 1k 10k 100k 1M 10M
Power-SupplyRejectionRatio(dB)
V-
IN = 5V
Cm
IN =10 F
Cm
OUT =10 F
C =0
NR mF
I =1mA
OUT
I =200mA
OUT
I =100mA
OUT
90
80
70
60
50
40
30
20
10
0
-10
Frequency(Hz)
10 100 1k 10k 100k 1M 10M
Power-SupplyRejectionRatio(dB)
VIN =-5V
CIN =10mF
COUT =10mF
C =0.01
NR mF
I =1mA
OUT
I =200mA
OUT
I =100mA
OUT
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Typical Characteristics (continued)
TPS72325 at VI= VO(NOM) – 0.5 V, IO= 1 mA, VEN = 1.5 V, CO= 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
Figure 25. PSRR vs Frequency Figure 26. PSRR vs Frequency
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TPS72325
OUT
IN
EN
CurrentLimit
/Thermal
Protection
NR
VREF
1.186V
5pF
R1
R1+R2=97kW
R2
100kW
GND
TPS72301
OUT
IN
EN
CurrentLimit
/Thermal
Protection
FB
VREF
1.186V
5pF
R1
R1+R2 100k@ W
R2
100kW
GND
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7 Detailed Description
7.1 Overview
The TPS723xx is a low-dropout, negative linear voltage regulator with a rated current of 200 mA. It is offered in
trimmed output voltages between –1.5 V and –5.2 V and as an adjustable regulator from –1.2 V to –10 V. It
features very low noise and high power-supply rejection ratio (PSRR), making it ideal for high-sensitivity analog
and RF applications. A shutdown mode is available, reducing ground current to 2 μA maximum over temperature
and process.
7.2 Functional Block Diagrams
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7.3 Feature Description
7.3.1 Current Limit
The TPS723xx has internal circuitry that monitors and limits output current to protect the regulator from damage
under all load conditions. When output current reaches the output current limit (550 mA typical), protection
circuitry turns on, reducing output voltage to ensure that current does not increase. See Figure 9 in the Typical
Characteristics section.
Do not drive the output more than 0.3 V above the input. An output voltage more than 0.3 V above the input
voltage biases the body diode in the pass FET, and allows current to flow from the output to the input. This
current is not limited by the device. If this condition is expected, make sure to externally limit the reverse current.
7.3.2 Enable
The enable pin is active above +1.5 V and below –1.5 V, allowing it to be controlled by a standard TTL signal or
by connection to VIif not used. When driven to GND most internal circuitry is turned off, putting the TPS723xx
into shutdown mode, drawing 2-μA maximum ground current.
7.4 Device Functional Modes
Driving EN over 1.5 V or below –1.5 V turns on the regulator. Driving EN between –1.5 V and +1.5 V puts the
regulator into shutdown mode, thus reducing the operating current to 100 nA, nominal.
12 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: TPS72301 TPS72325
OUT
FB
GND
EN
IN
R1
1
2
34
5
R2
V = 1.186–
OUT 1+ R1
R2
R1+R2 ≈100kΩ
TPS72301
,
TPS72325
www.ti.com
SLVS346C –SEPTEMBER 2003–REVISED SEPTEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS723xx family of LDO regulators provides high PSRR and low noise. These features make the family a
good fit for high-sensitivity analog and RF applications.
8.2 Typical Application
The TPS72301 allows designers to specify any output voltage from –10 V to –1.2 V. As shown in the application
circuit in Figure 27, an external resistor divider is used to scale the output voltage (VO) to the reference voltage.
For best accuracy, use precision resistors for R1 and R2. Use the equations in Figure 27 to determine the values
for the resistor divider.
Figure 27. TPS72301 Adjustable LDO Regulator Programming
8.2.1 Design Requirements
8.2.1.1 Capacitor Selection for Stability
Appropriate input and output capacitors should be used for the intended application. The TPS723xx only requires
a 2.2-μF ceramic output capacitor to be used for stable operation. Both the capacitor value and equivalent series
resistance (ESR) affect stability, output noise, PSRR, and transient response. For typical applications, a 2.2-μF
ceramic output capacitor located close to the regulator is sufficient.
8.2.1.2 Output Noise
Without external bypassing, output noise of the TPS723xx from 10 Hz to 100 kHz is 200 μVRMS typical. The
dominant contributor to output noise is the internal bandgap reference. Adding an external 0.01-μF capacitor to
ground reduces noise to 60 μVRMS. Best noise performance is achieved using appropriate low ESR capacitors for
bypassing noise at the NR and OUT pins. See Figure 21 in the Typical Characteristics section.
8.2.1.3 Power-Supply Rejection
The TPS723xx offers a very high PSRR for applications with noisy input sources or highly sensitive output supply
lines. For best PSRR, use high-quality input and output capacitors.
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND terminal current, and power the load.
Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS72301 TPS72325
90
80
70
60
50
40
30
20
10
0
-10
Frequency(Hz)
10 100 1k 10k 100k 1M 10M
Power-SupplyRejectionRatio(dB)
VIN =-5V
CIN =10mF
COUT =10mF
C =0.01
NR mF
I =1mA
OUT
I =200mA
OUT
I =100mA
OUT
Time(ms)
0 1 2 3 4 5 6 7 8 9 10
Voltage(V)
CIN =2.2mF
COUT =2.2mF
I =50mA
OUT
CNR =0mF
0
0.5
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
VOUT
VIN
Time(1ms/div)
OutputNoise(100 V/div)m
C 2.2m
IN =-F,C m
OUT =2.2 F
I =0.01m
OUT =100mA,CNR F
TPS72301
,
TPS72325
SLVS346C –SEPTEMBER 2003–REVISED SEPTEMBER 2014
www.ti.com
Typical Application (continued)
8.2.3 Application Curves
Figure 29. TPS72325 Output Noise vs Time
Figure 28. TPS72325 Power-Up/Power-Down
Figure 30. PSRR vs Frequency
8.3 Do's and Don'ts
Do place at least one 2.2-µF ceramic capacitor as close as possible to the OUT terminal of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Do connect a 0.1-μF to 2.2-μF low ESR capacitor across the IN terminal and GND input of the regulator.
Do not exceed the absolute maximum ratings.
14 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: TPS72301 TPS72325
PD+ǒVIN*VOUTǓ@IOUT
Ground
Plane
Ground
Plane
VIR2
R1
CI
COVO
EN
TPS723
TPS72301
,
TPS72325
www.ti.com
SLVS346C –SEPTEMBER 2003–REVISED SEPTEMBER 2014
9 Power-Supply Recommendations
These devices are designed to operate from an input voltage supply range between –10 V and –2.7 V. The input
voltage range must provide adequate headroom in order for the device to have a regulated output. This input
supply must be well-regulated and stable. If the input supply is noisy, additional input capacitors with low ESR
can help improve the output noise performance.
10 Layout
10.1 Layout Guidelines
To improve ac performance (such as PSRR, output noise, and transient response), design the board with
separate ground planes for VIand VO, with each ground plane connected only at the GND pin of the device. In
addition, connect the bypass capacitor directly to the GND pin of the device.
10.2 Layout Example
Figure 31. Example Layout
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the head from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in
the Thermal Information table near the front of this data sheet. Using heavier copper increases the effectiveness
in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves
heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation is
equal to the product of the output current times the voltage drop across the output pass element, as shown in
Equation 1:
(1)
10.4 Thermal Protection
As protection from damage due to excessive junction temperatures, the TPS723xx has internal protection
circuitry. When junction temperature reaches approximately 165°C, the output device is turned off. After the
device has cooled to 145°C, the output device is enabled, allowing normal operation. For reliable operation,
design is for worst-case junction temperature of ≤125°C taking into account worst-case ambient temperature
and load conditions.
Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS72301 TPS72325
TPS72301
,
TPS72325
SLVS346C –SEPTEMBER 2003–REVISED SEPTEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS723xx is available through the product folders under
Simulation Models.
11.1.2 Device Nomenclature
Table 1. Device Nomenclature(1)
PRODUCT VOUT
TPS723xx yyy z XX is nominal output voltage (for example, 25 = 2.5 V, 01 = Adjustable).
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TPS72301 Click here Click here Click here Click here Click here
TPS72325 Click here Click here Click here Click here Click here
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated
Product Folder Links: TPS72301 TPS72325
PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS72301DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T08I
TPS72301DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T08I
TPS72301DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T08I
TPS72301DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T08I
TPS72301DDCR ACTIVE SOT-23-THIN DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T08I
TPS72301DDCT ACTIVE SOT-23-THIN DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T08I
TPS72325DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T02I
TPS72325DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T02I
TPS72325DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T02I
TPS72325DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 T02I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2017
Addendum-Page 2
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS723 :
•Automotive: TPS723-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS72301DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS72301DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS72301DDCR SOT-
23-THIN DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS72301DDCT SOT-
23-THIN DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS72325DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS72325DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS72301DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS72301DBVT SOT-23 DBV 5 250 203.0 203.0 35.0
TPS72301DDCR SOT-23-THIN DDC 5 3000 195.0 200.0 45.0
TPS72301DDCT SOT-23-THIN DDC 5 250 195.0 200.0 45.0
TPS72325DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS72325DBVT SOT-23 DBV 5 250 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2018
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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Copyright © 2018, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
TPS72301DBVR TPS72301DBVRG4 TPS72301DBVT TPS72301DBVTG4 TPS7230QDR TPS72325DBVR
TPS72325DBVRG4 TPS72325DBVT TPS72325DBVTG4 TPS72301DDCT TPS72301DDCR