LM4549B
SNAS598B –JULY 2012–REVISED JULY 2015
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Pin Functions (continued)
PIN I/O DESCRIPTION
NAME NO.
Mono Input
This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix
signal at MIX2 under the control of the PC_Beep Volume control register, 0Ah. The PC_BEEP level
can be muted or adjusted from 0 dB to -45 dB in 3 dB steps. The Stereo Mix signal feeds both the
PC_BEEP 12 I Line Out and Line Level Out analog outputs and is also selectable at the Record Select Mux.
During Initialization or Cold Reset, (reset pin held active low), PC_BEEP is switched directly to both
channels of the Line Out stereo output, bypassing all volume controls. This allows signals such as
PC power-on self-test tones to be heard through the audio system of the PC before the codec
registers are configured.
Mono Input
This line level (1 Vrms nominal) mono input is selectable at the Record Select Mux for conversion
by either channel of the stereo ADC. It can also be mixed equally into both channels of the Stereo
PHONE 13 I Mix signal at MIX2 under the control of the Phone Volume register, 0Ch. The PHONE level can be
muted or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. The Stereo Mix signal feeds both the
Line Out and Line Level Out analog stereo outputs and is also selectable at the Record Select Mux.
Left Stereo Channel Input
This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select
Mux for conversion by the left channel ADC. It can also be mixed into the left channel of the Stereo
VIDEO_L 16 I Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_L level can
be muted (along with VIDEO_R) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps. Stereo Mix
3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line Out and
Line Level Out.
Right Stereo Channel Input
This line level input (1 Vrms nominal) is selectable at the right channel of the stereo Record Select
Mux for conversion by the right channel ADC. It can also be mixed into the right channel of the
VIDEO_R 17 I Stereo Mix 3D signal at MIX1 under the control of the Video Volume register, 14h. The VIDEO_R
level can be muted (along with VIDEO_L) or adjusted from +12 dB to -34.5 dB in 1.5-dB steps.
Stereo Mix 3D is combined into the Stereo Mix signal at MIX2 for access to the stereo outputs Line
Out and Line Level Out.
DIGITAL I/O AND CLOCKING
AC Link clock
An OUTPUT when in Primary Codec mode. This pin provides a 12.288 MHz clock for the AC Link.
The clock is derived (internally divided by two) from the 24.576 MHz signal at the crystal input
BIT_CLK 6 I/O (XTL_IN).
This pin is an INPUT when the codec is configured in any of the Secondary Codec modes and
would normally use the AC Link clock generated by a Primary Codec.
External Amplifier Power Down control signal
This output is set by the EAPD bit (bit D15) in the Powerdown Control/ Status register, 26h. As with
EAPD 47 O the other logic outputs, the output voltage is set by DVDD. This pin is intended to be connected to
the shutdown pin on an external power amplifier. For normal operation the default value of EAPD =
0 will enable the external amplifier allowing an input on PC_BEEP to be heard during Cold Reset.
Codec Identity
ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures
the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of
ID0# 45 I inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only
Extended Audio ID register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit
(D14, reg 28h) will be set to “1”. Similarly, connection to DVDD will set the ID0 bit to “0”. If left open
(NC), ID0# is pulled high by an internal pull-up resistor.
Codec Identity
ID1# and ID0# determine the codec address for multiple codec use. The Codec Identity configures
the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of
ID1# 46 I inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only
Extended Audio ID register, 28h. If the ID1# pin (pin 46) is connected to ground then the ID1 bit
(D15, reg 28h) will be set to “1”. Similarly, connection to DVDD will set the ID1 bit to “0”. If left open
(NC), ID1# is pulled high by an internal pull-up resistor.
Cold Reset
This active low signal causes a hardware reset which returns the control registers and all internal
circuits to their default conditions. RESET# MUST be used to initialize the LM4549B after Power On
RESET# 11 I when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor
test modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels
of the LINE_OUT stereo output.
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