MK2059-01 P R E L I M I N A RY I N F O R M AT I O N Low Phase Noise Communications Clock Description Features The MK2059-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock synthesizer designed to be used in communications network applications. It accepts an 8kHz network reference clock and generates one of eight selectable output clock frequencies. * Generates T1, E1 and other common telecom clock * * * By controlling the VCXO frequency within a phase-locked loop (PLL), the output clock is phase and frequency locked to the 8kHz input reference clock. The low loop bandwidth provides high jitter attenuation of the 8kHz reference input, assuring low jitter transfer to the clock output. The crystal-based VCXO clock source generates an output clock with very low phase noise. * * * * * * frequencies 2:1 Input MUX for 8kHz input reference clocks VCXO-based clock generation offers very low jitter and phase noise generation Output clock is phase and frequency locked to the selected 8kHz input reference clock Fixed input to output phase relationship Locks to 8kHz input over +/-32ppm error range (using recommended external pullable crystal) Industrial temperature range Low power CMOS technology 20 pin SOIC package Single 3.3V power supply Block Diagram P ullable x tal X1 RES 8kH z R ef In p ut 8kH z R ef In p ut IC L K 2 1 IC L K 1 0 P h ase D etecto r X2 VD D VDD 3 O u tpu t D ivid er V C XO CLK C harg e P um p ISE L F eedb ack D ivid er S EL 2:0 3 CHGP MDS 2059-01 A 1 VIN GND 4 Revision 020601 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com P R E L I M I N A RY I N FO R M ATI O N MK2059-01 Low Phase Noise Communications Clock Pin Assignment X1 VDD VDD VDD VIN GND GND GND CHGP RES Output Clock Selection Table 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 X2 GND ISEL ICLK1 ICLK2 SEL0 CLK NC SEL1 SEL2 Input SEL2 SEL1 SEL0 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 0 0 0 0 M M M M 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Clock (MHz) 1.544 2.048 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576 Crystal Used (MHz) 24.704 24.576 16.384 17.664 18.528 20.00 25.00 25.92 19.44 20.48 24.704 24.576 Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 X1 - 2 3 VDD VDD Power Power Crystal Input. Connect this pin to the specified crystal. Power Supply. Connect to +3.3V. Power Supply. Connect to +3.3V. 4 5 VDD VIN Power Input Power Supply. Connect to +3.3V. VCXO Control Voltage Input. Connect this pin to pin CHGP and the external loop filter as shown in this data sheet. 6 7 GND GND Power Power Ground Ground 8 9 GND CHGP Power Output Ground Charge Pump Output. Connect this pin to the external loop filter and to pin VIN. Connection for Charge Pump Current Setting Resistor. 10 RES - 11 SEL2 Input Output Frequency Selection Pin 2. Determines output frequency as per table above. Internally biased to VDD/2. 12 SEL1 Input 13 NC Input Output Frequency Selection Pin 1. Determines output frequency as per table above. Internal pull-up. No Internal Connection. 14 15 CLK SEL0 Output Input 16 ICLK2 Input 17 18 ICLK1 ISEL Input Input 19 GND Power 20 X2 - MDS 2059-01 A Clock Output Output Frequency Selection Pin 0. Determines output frequency as per table above. Internal pull-up. Input Clock Connection 2. Connect an 8kHz input reference clock to this pin. Input Clock Connection 1. Connect an 8kHz input reference clock to this pin. Input Selection. Used to select which 8kHz reference input clock is active. Low input level selects ICLK1, high input level selects ICLK2. Internal pull-up. Ground Crystal Output. Connect this pin to the specified crystal. 2 Revision 020601 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com P R E L I M I N A RY I N FO R M ATI O N MK2059-01 Low Phase Noise Communications Clock Functional Description External Component Schematic The MK2059-01 is a clock generator IC that generates an output clock directly from an internal VCXO circuit. The VCXO is controlled by an internal PLL (Phase Locked Loop) circuit, enabling the device to perform clock regeneration from an input reference clock. The MK2059-01 is configured to generate a popular selection of telecommunication and other frequencies from an 8kHz input reference clock. Please refer to the Output Clock Selection Table on page 2. Most PLL clock devices use a VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO, the MK2059-01 is able to generate a low jitter, low phase-noise output clock from a low frequency reference source. In addition, the PLL loop bandwidth can be very low (down to 10Hz or lower) providing clock jitter attenuation. The VCXO circuit requires an external pullable crystal for operation. External loop filter components are used to obtain the low loop bandwidth needed for the low frequency input reference frequency, and for jitter attenuation. External Component Selection CL CL X tal X1 1 2 3 4 5 6 7 8 9 10 VDD VDD VDD V IN C2 R C1 GND GND GND CHGP RES 20 19 18 17 16 15 14 13 12 11 X2 GND IS EL IC L K 1 IC L K 2 S EL 0 CLK NC S EL 1 S EL 2 R S ET Loop Filter Components The MK2059-01 requires a minimum number of external components for proper operation. Please refer to the External Component Schematic on this page. Referring the External Component Schematic, the external loop filter is made up of components R, C1 and C2. RSET, which establishes PLL charge pump current, also affects loop filter dynamics. Decoupling Capacitors For optimum stability and jitter attenuation characteristics the following component values are recommended: Decoupling capacitors of 0.01F must be connected between each VDD and GND, as close to the VDD pin as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. (Decoupling capacitors are not shown in the External Component Schematic.) Series Termination Resistor Clock traces over 1 inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. (The optional series termination resistors is not shown.) MDS 2059-01 A 3 RSET = 11.8 k R = 1.3 M C1 = 0.2 F (may use two 0.1 F caps in parallel) C2 = 5.6 nF For questions or changes regarding loop filter characteristics, please contact ICS, MicroClock Applications. Loop filter components (including RSET) should be mounted as close to the device as possible. C1 and C2 should be high quality ceramic capacitors. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Another alternative is the Panasonic PPS polymer dielectric series. The Panasonic part number for the 0.1 F cap is ECHU1C104JB5. Avoid high-K dielectrics like Z5U and Revision 020601 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com P R E L I M I N A RY I N FO R M ATI O N MK2059-01 Low Phase Noise Communications Clock X7R. These and other ceramics which have piezoelectric properties allow mechanical vibration in the system to increase the output jitter, because the mechanical energy is converted directly to voltage noise on the VCXO input. Quartz Crystal The MK2059-01 operates by phase-locking the VCXO circuit to the input signal at the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The MK2059-01 incorporates variable load capacitors on-chip which "pull", or change, the frequency of the crystal. The crystals specified for use with the MK2059-01 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. To achieve this, the layout should use short traces between the MK2059-01 and the crystal. A complete description of the recommended crystal parameters is shown below. Recommended Crystal Parameters: Operating Temperature Range Commercial Applications Industrial Applications Initial Accuracy at 25C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0 C0/C1 Ratio Equivalent Series Resistance 0 to 70C -40 to 85C 20 ppm 30 ppm 20 ppm Note 1 7 pF Max 250 Max 35 Max Note 1: Nominal crystal load capacitance specification varies with frequency. Contact the ICS MicroClock applications department at (408)297-1201. To obtain a list of qualified crystal devices that meet these requirements, please contact ICS, MicroClock Applications. Crystal Load Capacitors The crystal traces should include pads for small capacitors from X1 and X2 to ground, shown as C L in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is accurate to much less than 1 ppm, so the MK2059-01 may lock and run properly even if the board capacitance is not adjusted with these fixed capacitors. However, ICS MicroClock recommends that the adjustment capacitors be included to minimize the effects of variation in individual crystals, included those induced by temperature and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout, using the procedure described in the section titled "Optimization of Crystal Load Capacitors". PCB Layout Recommendation A proper board layout is critical to the successful use of the MK2059-01. In particular, the loop filter network is very sensitive to noise and leakage. Because of leaking sensitivity, the PCB must be cleaned and well dried prior to testing. Traces must be as short as possible and the R, C1 and C2 must be mounted next to the device. The output clock should have a series termination of 33 connected close to the pin, particularly if the clock trace is over 1 inch. Additional improvements will come from keeping all components on the same side of the board, minimizing vias through other signal layers, and routing other signals away from the MK2059-01. You may also refer to MAN05 for additional suggestions on layout of the crystal section. Optimization of Crystal Load Capacitors To determine the crystal adjustment capacitor values, you will need a PC board of your final layout, a frequency counter capable of less than 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors: MDS 2059-01 A 4 Revision 020601 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com P R E L I M I N A RY I N FO R M ATI O N MK2059-01 Low Phase Noise Communications Clock 1. Connect VDD of the MK2059-01 to 3.3V. Connect pin 5 of the MK2059-01 to the second power supply. Adjust the voltage on pin 5 to 0V. Measure and record the frequency of the CLK output. 2. Adjust the voltage on pin 5 to 3.3V. Measure and record the frequency of the same output. To calculate the centering error: stray capacitance and will need to be redone with a new layout to reduce stray capacitance. (The crystal may be re-specified to a lower load capacitance instead. Contact ICS MicroClock for details.) If the centering error is more than 15 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: External Capacitor = 2 x (centering error)/(trim sensitivity) 6 ( f 3.0V - f t arg et ) + ( f 0V - f t arg et ) Error = 10 x ------------------------------------------------------------------------------ - error xtal f t arg et Where: ftarget = nominal crystal frequency errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than 15 ppm, no adjustment is needed. If the centering error is more than 15 ppm negative, the PC board has too much Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (less than 15ppm). The MicroClock Applications department can perform this procedure on your board. Call us at 408-295-9800, and we will arrange for you to send us a PC board (stuffed or unstuffed) and one of your crystals. We will calculate the value of capacitors needed. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2059-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature -40 to +85C Storage Temperature -65 to +150C Junction Temperature 175C Soldering Temperature 260C MDS 2059-01 A 5 Revision 020601 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com P R E L I M I N A RY I N FO R M ATI O N MK2059-01 Low Phase Noise Communications Clock Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. Typ. Max. Units -40 - +85 C +3.15 +3.3 +3.45 V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85C Parameter Symbol Conditions Min. Typ. Max. Units 3.15 3.3 3.45 V 23 30 mA Operating Voltage VDD Supply Current IDD Clock outputs unloaded, VDD = 3.3V Input High Voltage, SEL2 VIH - VDD-0.5 - - V Input Low Voltage, SEL2 VIL - - - 0.5 V Input High Voltage, ISEL. SEL1:0 VIH - 2 - - V Input Low Voltage, ISEL, SEL1:0 VIL - - - 0.8 V Input High Voltage, ICLK1/2 VIH - VDD/2+1 - - V Input Low Voltage, ICLK1/2 VIL - - - VDD/2 -1 V Input High Current IIH VIH = VDD -10 - +10 A Input Low Current IIL VIL = 0 -10 - +10 A Input Capacitance, except X1 CIN - 7 - pF Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -8 mA 2.4 V Output Low Voltage VOL IOL = 8 mA - Short Circuit Current IOS VIN, VCXO Control Voltage VXC - - 0.4 50 0 V mA VDD V AC Electrical Characteristics MDS 2059-01 A 6 Revision 020601 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com P R E L I M I N A RY I N FO R M ATI O N MK2059-01 Low Phase Noise Communications Clock Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85C Parameter Symbol VCXO Crystal Pull Range Conditions fXP Using Recommended Crystal FOUT ICLK = exactly 8kHz Output Duty Cycle (% high time) tOD Measured at VDD/2, CL=15pF Output Rise Time tOR Output Fall Time tOF Output Frequency Error Nominal Output Impedance Min. Typ. -100 Max. Units +100 ppm 0 0 ppm - 60 % 0.8 to 2.0V, CL=15pF 1.5 ns 2.0 to 0.8V, CL=15pF 1.5 ns 40 20 ZOUT Package Outline and Package Dimensions (20 pin SOIC, 300 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Symbol A A1 A2 B C D E e H h L Index A rea E H 1 2 Min Inches Max -2.65 1.10 -2.05 2.55 0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 Basic 10.00 10.65 0.25 0.75 0.40 1.27 0 8 Min Max -0.104 0.0040 -0.081 0.100 0.013 0.020 0.007 0.013 0.496 0.512 0.291 0.299 0.050 Basic 0.394 0.419 0.010 0.029 0.016 0.050 0 8 h x 45 o D A2 A A1 e L C B Ordering Information Part / Order Number MDS 2059-01 A Marking Shipping packaging 7 Package Temperature Revision 020601 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 www.icst.com