5962-8866203YA - Integrated Device Technology, Inc.

OCTOBER 1999

DSC-3067/04

PowerPC is a trademark of International Business Machines, Inc.

Features

◆16K x 15 Configuration

– 12 TAG Bits

– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)

◆Match output uses Valid bit to qualify MATCH output

◆High-Speed Address-to-Match comparison times

– 8/9/10/12ns over commercial temperature range

◆TATA

TATA

TA circuitry included inside the Cache-Tag for highest

speed operation

◆Asynchronous Read/Match operation with Synchronous

Write and Reset operation

◆Separate WEWE

WEWE

WE for the TAG bits and the Status bits

◆Separate OEOE

OEOE

OE for the TAG bits, the Status bits, and TATA

TATA

◆Synchronous RESETRESET

RESETRESET

RESET pin for invalidation of all Tag

entries

◆Dual Chip selects for easy depth expansion with no

performance degredation

◆I/O pins both 5V TTL and 3.3V LVTTL compatible with

VCCQ pins

◆PWRDNPWRDN

PWRDNPWRDN

PWRDN pin to place device in low-power mode

◆Packaged in a 80-pin plastic Thin Quad Flat Pack (TQFP).

Description

The IDT71216 is a 245,760-bit Cache Tag Static RAM, orga-

nized 16K x 15 and designed to support PowerPC and other RISC

processors at bus speeds up to 66MHz. There are twelve common

I/O TAG bits, with the remaining three bits used as status bits. A 12-

bit comparator is on-chip to allow fast comparison of the twelve

stored TAG bits and the current Tag input data. An active HIGH

MATCH output is generated when these two groups of data are the

same for a given address. This high-speed MATCH signal, with tADM

as fast as 8ns, provides the fastest possible enabling of secondary

cache accesses.

The three separate I/O status bits (VLD, DTY, and WT) can be

configured for either dedicated or generic functionality, depending on

the SFUNC input pin. With SFUNC LOW, the status bits are defined

and used internally by the device, allowing easier determination of

the validity and use of the given Tag data. SFUNC HIGH releases the

defined internal status bit usage and control, allowing the user to

configure the status bit information to fit his system needs. A synchro-

nous RESET pin, when held LOW at a rising clock edge, will reset all

status bits in the array for easy invalidation of all Tag addresses.

The IDT71216 also provides the option for Transfer Acknowledge

(TA) generation within the cache tag itself, based upon MATCH, VLD

bit, WT bit, and external inputs provided by the user. This can

significantly simplify cache controller logic and minimize cache

decision time. Match and Read operations are both asynchronous

in order to provide the fastest access times possible, while Write

operations are synchronous for ease of system timing.

The IDT71216 uses a 5V power supply on Vcc, with separate

VCCQ pins provided for the outputs to offer compliance with both 5V

TTL and 3.3V LVTTL Logic levels. The PWRDN pin offers a low-

power standby mode to reduce power consumption by 90%, provid-

ing significant system power savings.

The IDT71216 is fabricated using IDT’s high-performance, high-

reliability BiCMOS technology and is offered in a space-saving 80-

pin plastic Thin Quad Flat Pack (TQFP) package.

Pin Descriptions

A0 – A13 Address Input s Input CLK Sy stem Clock Input

CS1, CS2 Chip Select s I nput TAH TA Force H igh Input

WET Writ e Enable – Tag Bits Input TAOE TA Output Enable Input

WES Write Enable – Status Bit s Input TAIN Additional TA Input Input

OET Out put Enable – Tag Bits Input TA Transfer Acknow ledge Out put

OES O utp ut Enable – St atus Bit s Input TAG 0 – TAG11 Tag Data Input/Outputs I/O

RESET Status Bit Reset Input VLDOUT/S1OUT Valid B it / S 1 Bit Output Out put

PWRDN Powerdow n M ode C ontrol Pin Input DTYOUT/S2OUT Dirty Bit/S2 Bit Output O utput

SFUNC St at us Bit Function Cont rol Pin Input WT OUT/S3OUT Writ e Through Bit/ S3 Bit Out put Out put

TT1 Read/ Writ e I nput f rom Processor Input M AT CH Mat ch Out put

VLDIN/S1IN Va lid B it / S 1 Bit Input Input VCC +5V Power Pwr

DTYIN/S2IN Dirty Bit/ S2 Bit Input Input VCCQ Output Buffer Pow er QPw r

WTIN/S3IN Write Through Bit/ S3 Bit I nput Input VSS Ground Gnd

3067 t bl 01

BiCMOS Static RAM

240K (16K x 15-Bit)

Cache-Tag RAM

for PowerPC™ and RISC Processors

IDT71216

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Pin Configuration

TQFP

Top View

3067 drw 01

PN80-1

VSS

VSS 80

TAG1

DTY

OUT

TAIN

TAH

TT1

SFUNCVLD

TAG9

TAG10

TAG11

TAOE

OET

OES

CLK

RESET

WES

WET

CS1

CS2

PWRDN

VSS

TAG4

TAG5

WTOUT /S3

OUT

VSS

MATCH

VSS

VLDOUT /S1

OUT

TAG6

TAG7

TAG8

VSS

VCC

WTIN /S3

DTYIN /S2

VSS

VCCQ

CCQ

TAG0

TAG2

TAG3

A10

A11

A12

A13

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Functional Block Diagram

CLK

SFUNC

ADDR (0:13)

VLD/S1OUT

DTY/S2OUT

WT/S3OUT

RESET

WET

WES

16K x 12

MEMORY

TAG BITS

TAG (0:11)

OET

16K x 3

MEMORY

STATUS

BITS

MATCH

TAH

TT1

TAOE

TAIN

VLD/S1IN

DTY/S2IN

WT/S3IN

CS2

CS1

RESET

(neg) PULSE

GENERATOR

PWRDN

DataIN

WRITE

(pos) PULSE

GENERATOR

COMPARE

Reg

OES

Reg

3067 drw 02

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Truth Tables  Chip Select, Reset, and Power-Down Functions(1,2)

NOTES:

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2. OET, OES, TT1, TAH, TAIN and SFUNC are "X" for this table.

3. OES is LOW.

NOTES:

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2. This table applies when CS1 is LOW and CS2, RESET, and PWRDN are HIGH. TAOE, TAH, TAIN and SFUNC are "X" for this table.

3. DOUT in this case is the same as DIN; that is, the input data is written through to the outputs during the write operation.

CS1

CS2

RESET PWRDN

CLK

WET WES TAOE

TAG

VLD

OUT

DTY

OUT

MATCH

OPERATION

POWER

CHIP SELECT FUNCTION

H X X H X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Deselected Active

X L X H X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Deselected Active

L H X H X X X X — — — — — — Selected Active

RESET FUNCTION

LH L H ↑HH L Hi-ZL

(3) L(3) L(3) L(3) H Reset Status Active

LH L H ↑HH H Hi-ZL

(3) L(3) L(3) L(3) Hi-Z Reset Status Active

HX L H ↑H H X Hi-Z H i-Z Hi-Z Hi-Z H i-Z Hi-Z Reset St atus Act iv e

XL L H ↑H H X Hi-Z H i-Z Hi-Z Hi-Z H i-Z Hi-Z Reset St atus Act iv e

XX L H ↑LX X — — — — — —Not Allowed —

XX L H ↑XL X — — — — — —Not Allowed —

POWE R-DOWN FUNCTION

X X X L X H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Power-down Standby

3067 t bl 02

OET OES WET WES

CLK

TT1

TAG

VLD

DTY

VLD

OUT

DTY

OUT

MATCH

OPERATION

READ FUNCTION

LXH XXX D

OUT ——— — — —D

OUT Read TAG I /O

XLX XXX ——— —D

OUT DOUT DOUT DOUT Read Status Bits

HXX XXX Hi-Z— — — — — —D

OUT TAG I/O Disable

X H X X X X — — — — Hi-Z Hi-Z Hi-Z DOUT St atus Disabled

WRITE FUNCTION

HX L X↑XD

IN ———D

OUT DOUT DOUT L Write TAG I/O

LX L X↑X ————————Not Allowed

XLX L↑X—D

IN DIN DIN DOUT(3) DOUT(3) DOUT(3) L Write Status Bits

XHX L↑X—D

IN DIN DIN Hi-Z Hi-Z H i-Z L Write Sta tus Bit s

3067 tbl 03

Truth Tables  Read and Write Functions(1,2)

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Truth Table  Match Function(1,2,3)

NOTES:

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.

3. PWRDN and RESET are HIGH for this table. CLK and OES are "X".

4. This column represents the stored memory cell data for the given Status bit at the selected address.

5. CS1 is LOW, CS2 is HIGH for this table.

6. TAIN is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge.

7. TAIN will be a factor in determining the TA output in all cases except when TAH is HIGH and there is a valid MATCH. In that case, TA will be LOW(Valid).

NOTES:

1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.

2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.

3. PWRDN and RESET are HIGH for this table. TT1, TAH, TAOE, TAIN, OES, and CLK are "X".

4. This column represents the stored memory cell data for the given Status bit at the selected address.

CS1

CS2

SFUNC

OET WET WES

TAG

VLD

(4)

DTY

(4)

MATCH

OPERATION

H X X X X X Hi-Z — — — Hi-Z Deselected

X L X X X X Hi-Z — — — Hi-Z Deselected

LHX X XX — — — — D

OUT Selected

LHX L HX D

OUT — — — L Read Tag I /O

LHX H LX D

IN — — — L Writ e Tag I /O

LHX X XL — D

IN DIN DIN L Write St atus Bits

LH L HHH TAG

IN L — — L Inv alid Dat a — Dedicat ed St atus Bits

LH L HHH TAG

IN H — — M M at ch — Dedicat ed Stat us Bits

LHH HHH TAG

IN X — — M M atch — Generic Status Bits

3067 t bl 04

TAOE TAIN

(6)

OET WET WES

TAH

TT1

SFUNC

VLD

(4)

DTY

(4)

TAG

MATCH

OPERATION

HXXXXXXX X—X——Hi-Z

TA Disabled

L L X X X X X X X — X — X L External TA I nput(7)

LHLXXXXX X—XD

OUT L H Read TAG

LHXLXXXX X—XD

IN LH Write TAG

LHXXLXXXD

IN DIN DIN —L HWrite Status

LHXXXHXX X—X—XHForce TA HIGH

LHXXXXXL L—X—LHInvalid TAG

L H X X X X L L X — H — X H Writ e Through

LHHHHLXL H—LTAG

IN MMCompare

LHHHHLHL H—XTAG

IN MMCompare

LHHHHLXL H—XTAG

IN MMCompare

LHHHHLXH X—XTAG

IN MMCompare

3067 t bl 05

Truth Table  TA Function(1,2,3,5)

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Symbol Parameter(1) Condition Max. Unit

CIN Input Capacitance VIN = 0V 5 pF

CTAG TAG Input /Ouput C apacitance VI/O = 0V 7 pF

COUT Output Capacitance VOUT = 0V 7 pF

3067 tbl 07

Symbol

Parameter

Min.

Typ.

Max.

Unit

VCC Supply Vo ltage 4. 75 5. 0 5.25 V

VCCQ 5V Out put Buf fers 4. 75 5.0 5.25 V

VCCQ 3.3V Out put Buffers 3.0 3.3 3.6 V

VSS Supply Ground 0 0 0 V

VIH Input High Voltage 2.2 3.0 VCC+0.3 V

VIHQ I/ O H igh Voltage 2. 2 3. 0 VCCQ+0.3 V

VIL Input Low Voltage –0.5(1) —0.8V

3067 t bl 06

DC Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range (VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V)

Absolute Maximum Ratings(1)

NOTE:

1. VIL (min.) = –1.5V for pulse width of less than 10ns, once per cycle.

DC Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range(1,2) (VCC = 5.0V ± 5%)

Recommended DC Operating

Conditions

Capacitance

(TA = +25°C, f = 1.0MHz)

NOTE:

1. This parameter is determined by device characterization but is not production tested.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliabilty.

2. VIN should not exceed Vcc+0.5V. All pins should not exceed 7.0V.

VCCQ should never exceed VCC, and VCC should never exceed VCCQ + 4.0V.

Symbol

Rating

Value

Unit

VTERM Term in al Volt age w ith Resp ect t o GND –0. 5 to + 7. 0(2) V

TAOperating Tem perature 0 to +70 °C

TBIAS Temperat ure Under Bias –65 to + 135 ° C

TSTG St orage Tem p erat ure –65 t o +150 °C

PTPow er Dissipation 1.7 W

IOUT DC Output Current 20 m A

3067 t bl 08

Symbol Par ame ter Tes t C on ditio n M in. M ax . U ni t

|ILI| I nput Leakage Current VCC = M ax., VIN = 0V to VCC —5

|ILO| Out put Leakage Current CS1 ≥ VIH, CS2 ≤ VIL, OE ≥ VIH, VCC = M ax.

VOUT = 0V to VCCQ, VCCQ = M ax. —5µA

VOL Out put Low Volt age IOL = 4m A, VCC = M in. — 0.4 V

VOH Out put H igh Voltage IOH = –4m A, VCC = Min. 2.4 — V

3067 t bl 09

NOTES:

1. All values are maximum guaranteed values.

2. CS1 ≤ VIL, CS2 ≥ VIH.

3. fMAX =1/tCYC (all address inputs are cycling at fMAX). f = 0 means no address input lines are changing.

4. VHC = VCC - 0.2V, VLC = 0.2V

Symbol Parameter Test Condition

71216S8 71216S9 71216S10 71216S12

UnitCom'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil.

ICC O perat ing Pow er

Supply Current PWRDN ≥ VIH

Out puts Open, V CC = Max., f = fMAX

(3)

330 — 300 — 290 — 280 — mA

ISB St andby Pow er

Supply Current PWRDN ≤ VIL, VIN ≥ VIH or ≤ VIL

VCC = M ax., f = fMAX

(3)

30 — 30 — 30 — 30 — mA

ISB1 Full St andby Pow er

Supply Current PWRDN ≤ VIL, VIN ≥ VHC or ≤ VLC

(4)

VCC = M ax., f = 0

(3)

25 — 25 — 25 — 25 — mA

306 7 tb l 1 0

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

AC Electrical Characteristics

(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)

NOTE:

1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.

Symbol

Parameter

IDT71216S8

IDT71216S9

IDT71216S10

IDT71216S12

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

READ CYCLE

tAAT Address Access Tim e Tag Bits — 10 — 11 — 12 — 14 ns

tACST Chip Select Access Tim e Tag Bits — 8 — 9 — 10 — 12 ns

tCLZ(1) Chip Select to Tag an d Status Bits in Low -Z 1 — 1 — 1 — 1 — ns

tCHZ(1) Chip Select to Tag and Status Bits in High-Z 1 5 1 6 1 6 1 7 ns

tOET Out put Enable to Tag Bits Valid — 5 — 6 — 6 — 7 ns

tOTLZ(1) Output Enabl e to Tag Bits in Low -Z 0 — 0 — 0 — 0 — ns

tOTHZ(1) Output Enable to Tag Bits in High-Z 1 5 1 6 1 6 1 7 ns

tTOH Tag Bit Hold from Address Change 2 — 2 — 2 — 2 — ns

tOES Out put Enab le to St atus Bits Valid — 5 — 6 — 6 — 7 ns

tOSLZ(1) Out put Enable t o Status Bits in Low -Z 0 — 0 — 0 — 0 — ns

tOSHZ(1) Output Enable to Status Bits in High-Z 1 5 1 6 1 6 1 7 ns

tAAS Address Ac cess Tim e Stat us Bits — 8 — 9 — 10 — 12 ns

tACSS Chip Select Ac cess Tim e Sta tus Bits — 6 — 7 — 8 — 10 ns

tSOH Stat us Bit Hold from Address Change 2 — 2 — 2 — 2 — ns

3067 tbl 11

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Symbol

Parameter

IDT71216S8

IDT71216S9

IDT71216S10

IDT71216S12

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

RESET AND POWER DO WN CYCLES

tSR RESET Set-up Tim e 4—4—4—4—ns

tHR RESET Hold Tim e 1— 1— 1— 1—ns

tSRST S tat us Bit Reset Time — 50 — 60 — 60 — 70 ns

tSHRS Status Bit Hold from RESET LOW 2—2—2—2—ns

tRSMI RESET L OW to M ATCH and TA Invalid —9—10—10—12ns

tRSMV RESET H I GH t o M ATCH and TA Va lid —110—120—120—130ns

tRSHZ(2) RESET LOW to TAG High-Z —9—10—10—12ns

tRSLZ(2) RESET HIGH to TAG Low-Z — 90 — 100 — 100 — 110 ns

tPDSR PWRDN Set-up to RESET LO W 30 — 30 — 30 — 30 — ns

tRHPL RESET HIGH to PWDRN LOW 1— 1— 1— 1—CLK

tRHWL RESET HIGH to WET and WES LOW 90 — 95 — 95 — 105 — ns

tPD(2) PWRDN LO W to Low Pow er M ode — 50 — 50 — 50 — 50 ns

tPU(2) PWRDN HIGH to Activ e Power M ode 0—0—0—0—ns

tPDHZ(2) PWRDN LOW to O utput s in High-Z —9—10—10—12ns

tPDLZ(2) PWRDN HI GH t o Out puts in Low -Z 0—0—0—0—ns

tPUV PWRDN H IGH to Outputs Valid — 50 — 50 — 50 — 50 ns

tWHPL(2) WET and WES HIGH to PWRDN LOW 5—5—5—5—ns

tPUWL PWRDN HIGH to WET and WES Active 50 — 50 — 50 — 50 — ns

3067 t bl 12

AC Electrical Characteristics(1)

(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)

NOTES:

1. Power-down mode is intended to be used during extended time periods of device inactivity.

2. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

AC Electrical Characteristics(1)

(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)

NOTES:

1. All Write cycles are synchronous and referenced from rising CLK.

2. This parameter is measured as a HIGH time above 2.0V and a LOW time below 0.8V.

3. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.

4. Addresses are stable prior to CLK transition HIGH.

Symbol

Parameter

IDT71216S8

IDT71216S9

IDT71216S10

IDT71216S12

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

WRITE CYCLE AN D CLOCK PARAMETERS

tCYC Clock Cy cle Tim e 15 — 15 — 15 — 16. 6 — ns

tCH(2,3) Clock Pulse HIGH 4.5 — 4. 5 — 4.5 — 5 — ns

tCL(2,3) Clock Pulse LOW 4.5 — 4.5 — 4.5 — 5 — ns

tSWET, WES, Chip Select , a nd I nput Dat a Set-up Tim e 3—3—3—3—ns

tHWET, WES, Chip Select , and Input Data Hold Time 1— 1— 1— 1—ns

tSA Address Set-up Time 3—3— 3—3—ns

tHA Address Hold Time 1— 1— 1— 1—ns

tWMI CLK H IG H Writ e to M ATCH and TA Invalid —6—7— 7—8ns

tCKLZ(3) CLK HI GH Read to O utput s in Low -Z 1. 5 — 1. 5 — 1. 5 — 1. 5 — ns

tCTV(4) CLK H I GH R ead to Tag Bit s Valid — 9 — 10 — 10 — 12 ns

tCSV(4) CLK HIGH W rit e to St atus Outputs Valid — 8 — 9 — 9 — 10 ns

tCSH(3) Stat us Output Hold from CLK HIGH Write 0 — 0 — 0 — 0 — ns

tWHPL WET and WES HIGH to PWRDN LOW 5—5—5—5—ns

tPUWL PWRDN HIGH to WET and WES Act ive 50 — 50 — 50 — 50 — ns

3067 t bl 14

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Symbol

Parameter

IDT71216S8

IDT71216S9

IDT71216S10

IDT71216S12

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

MATCH AND

CYCLES

tADM Address to M ATCH Valid — 8 — 9 — 10 — 12 ns

tDAM Dat a Input to M ATCH Valid — 8 — 9 — 10 — 12 ns

tCSM Ch ip S e lec t t o M AT C H Va lid — 8 — 9 — 10 — 1 2 n s

tCMLZ(1) Chip Select to M ATCH in Low-Z 1 — 1 — 1 — 1 — ns

tCMHZ(1) Chip Select to M ATCH in High-Z 1 5 1 6 1 6 1 7 ns

tMHA MATCH Va lid Hold f rom A ddress 2 — 2 — 2 — 2 — ns

tMHD M ATCH Valid Hold from Data 2 — 2 — 2 — 2 — ns

tBHA TA Valid Hold from Address 2—2—2—2—ns

tBHD TA Valid Hold f rom Data 2—2—2—2—ns

tADB Address to TA Valid — 9 — 10 — 11 — 13 ns

tDAB Data Input to TA Valid — 9 — 10 — 11 — 13 ns

tCSB Chip Selec t LO W t o TA Valid — 9 — 10 — 11 — 13 ns

tOEBV TAOE LOW to TA Valid —6—6—7—8ns

tOBLZ(1) TAOE LOW to TA in Low -Z 0—0—0—0—ns

tOBHZ(1) TAOE HIGH to TA in High-Z 15161617ns

tBYFH TAH HI GH to Force TA HIGH —5—5—5—6ns

tBYHV TA H LO W t o TA Valid —5—5—5—6ns

tSB TAIN Set -up Tim e 4—4—4—4—ns

tHB TAIN Hold Tim e 1.5 — 1.5 — 1.5 — 1.5 — ns

tBIBL CLK HI GH TAIN LOW to TA LOW —6— 6—7— 8ns

tBIBV CLK HIGH TAIN HIGH to TA Valid —6—6—7—8ns

tOEMI OET LOW t o MATCH and TA Inv alid —6—7—7—8ns

tOEMV OET HIGH to MATCH and TA Valid —7—8—8—10ns

tWRBH(2) W/R HIGH to TA HIGH —6—7—7—8ns

tWRBV(2) W/R LOW to TA Valid —6—7—7—8ns

tWMI CLK HIGH Write to M ATCH and TA Invalid — 7—7— 7— 8ns

tWMV(3) CLK H IGH Read to M ATCH and TA Valid — 8 — 9 — 10 — 12 ns

3067 t bl 15

AC Electrical Characteristics

(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)

NOTES:

1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.

2. These parameters only apply when SFUNC is LOW and the internal WT bit is HIGH.

3. tADM, tDAM, tCSM and tADB, tDAB, tCSB must also be satisfied.

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Tag I/O

VCCQ

50pF *

3067 drw 04

893Ω

347Ω

Outputs

VCCQ

30pF *

3067 drw 03

893 Ω

347 Ω

Input Pulse Levels GND to 3.0V

Input Rise/Fall Tim es 3ns

Input Tim in g Ref erence Levels 1. 5V

Out put Tim ing Reference Levels 1.5V

AC Test Load See Figures 1, 2, 3, & 4

3067 tbl 16

AC Test Loads

AC Test Conditions

Figure 4. Lumped Capacitance Load, Typical Derating

Figure 1. AC Test Load

Figure 3. AC Test Load

(for tHZ and tLZ parameters )

* Including scope and jig capacitance

Figure 2. Tag I/O AC Test Load

VCCQ

5pF*

3067 drw 05

Tag I/O

and

Outputs

893Ω

347Ω

20 30 50 100

3067 drw 06

∆t

(Typical, ns)

∆Capacitance (pF)

* Including scope and jig capacitance

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Timing Waveforms of Write and Read Cycles

NOTE:

1. Transition is measured ±200mV from steady state.

CLK

A(0:13)

TAG(0:11)

VLD

DTY

VLD

OUT

DTY

OUT

WES

WET

OET

CS1

CS2

OUT

AAT

Valid Input

Valid

Valid Output

CSV

CTV

AAT

ACSS

CLZ

(1)

CKLZ

(1)

OTHZ

(1)

OET

OTLZ

(1)

CHZ

(1)

VALID VALID

Valid

Output

VALID

ACST

CLZ

(1)

CHZ

(1)

SOH

Valid

Output

AAS

TOH

STATUSWRITE

TAGWRITETAG

READ

SOH

AAS

Valid Valid

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CSH

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Timing Waveforms of Match and TA Functions

NOTE:

1. Transition is measured ±200mV from steady state.

Valid

Valid TA

CLK

A(0:13)

TAG(0:11)

WES

WET

OET

TAH

TAOE

MATCH

CS1

CS2

MATCHValid

MHA

DAM

TAFH

TAHV

WMI

WMV

OEMI

OEMV

CMHZ

(1)

CMLZ

(1)

WMI

WMV

ADM

MHD

Valid

OTLZ

(1)

OETV

Valid

DAT

ADT

CSM

Valid

OTHZ

(1)

CST

Valid Valid

Valid

Valid Address

Valid Match Data

Valid

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THD

THA

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Timing Waveforms of RESET Function

NOTE:

1. Transition is measured ±200mV from steady state.

Clock Timing Waveform

Timing Waveforms of TA and TT1 Signals

VLDOUT

DTYOUT

WES

WET

MATCH

RESET

PWRDN

WTOUT

CLK

TAG (0:11)

tRSMV

tPDSR

tSR

tRSMI

tRHWL

tHR

VALID

tRSLZ(1)

tRSHZ(1)

tSHRS

tSRST

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tCYC

tCH tCL

CLK 0.8V

2.0V 2.0V 0.8V

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TT1

TAIN

CLK

Applies when SFUNC is LOW, and the internal WT bit is HIGH

tTHTH tTHTV

TA Valid TA Valid

tTITL tTITV

tSTI tHTI

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6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Timing Waveforms of OES Function

NOTE:

1. Transition is measured ±200mV from steady state.

Timing Waveforms of POWER DOWN Function

NOTE:

1. Transition is measured ±200mV from steady state.

Ordering Information

TAG (0:10)

VLDOUT

DTYOUT

RESET

WET,WES

MATCH

PWRDN

WTOUT

CLK

ICC

ISB

tWHPL tPUWL

tPUV

tPD tPU

Valid TAG out

Valid Status out

TA Valid

MATCH Valid

tStS

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tPDLZ(1)

tPDHZ(1)

tRHPL

IDT 71216 PFXX

Speed in nanoseconds

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Device Type Package

PF Plastic Thin Quad Flatpack (PN80-1)

Power Speed

VLDOUT

DTYOUT

WTOUT

OES

tOSHZ(1) tOES

tOSLZ(1)

Valid Output Valid Output

3067 drw 12

6.42

IDT71216 BiCMOS Static RAM

240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors Commercial Temperature Range

Datasheet Document History

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726, x4033

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

10/19/99 Updated to new format

Pg. 16 Added Datasheet Document History