HUF76131SK8 Data Sheet December 2001 10A, 30V, 0.013 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Features * Logic Level Gate Drive This N-Channel power MOSFET is (R) manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. * 10A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.013 * Temperature Compensating PSPICE(R) Model * Thermal Impedance SPICE Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol Formerly developmental type TA76131. Ordering Information PART NUMBER HUF76131SK8 PACKAGE MS-012AA SOURCE(1) DRAIN(8) SOURCE(2) DRAIN(7) SOURCE(3) DRAIN(6) GATE(4) DRAIN(5) BRAND 76131SK8 NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76131SK8T. Packaging JEDEC MS-012AA BRANDING DASH 5 1 2 3 (c)2001 Fairchild Semiconductor Corporation 4 HUF76131SK8 Rev. B HUF76131SK8 Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2) (Notes 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg HUF76131SK8 30 30 16 UNITS V V V 10 Figure 5 Figure 6 2.5 0.02 -55 to 150 A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250A, VGS = 0V (Figure 11) 30 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 10) 1 - - V VDS = 25V, VGS = 0V - - 1 A Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance VDS = 25V, VGS = 0V, TA = 150oC - - 250 A VGS = 16V - - 100 nA ID = 10A, VGS = 4.5V (Figures 9,14) - 0.017 0.018 ID = 10A, VGS = 5V - 0.015 0.017 ID = 10A, VGS = 10V - 0.011 0.013 VDD = 15V, ID 10A, RL = 1.5, VGS = 5V, RGS = 6.8 (Figure 15) - - 115 ns - 15 - ns - 61 - ns td(OFF) - 33 - ns tf - 36 - ns tOFF - - 105 ns IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Turn-Off Time TEST CONDITIONS Total Gate Charge Qg(TOT) Gate Charge at 5V Qg(5) VGS = 0V to 10V VDD = 15V, ID 10A, VGS = 0V to 5V RL = 1.5, Ig(REF) = 1.0mA (Figure 13) VGS = 0V to 1V - 39 47 nC - 22 26 nC - 1.53 1.85 nC Gate to Source Gate Charge Qgs - 4.00 - nC Gate to Drain "Miller" Charge Qgd - 9.50 - nC - 1605 - pF - 685 - pF - 115 - pF Pad Area = 0.76 in2 (Note 2) - - 50 oC/W Pad Area = 0.054 in2 (See TB377) - - 143.4 oC/W Pad Area = 0.0115 in2 (See TB377) - - 177.3 oC/W Threshold Gate Charge Qg(TH) Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Ambient RJA VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD MIN TYP MAX UNITS ISD = 10A TEST CONDITIONS - - 1.25 V ISD = 2.3A - - 1.1 V trr ISD = 2.3A, dISD/dt = 100A/s - - 57 ns QRR ISD = 2.3A, dISD/dt = 100A/s - - 81 nC NOTES: 2. 50oC/W measured using FR-4 board with 0.76 in2 footprint at 10 seconds. 3. 177.3oC/W measured using FR-4 board with 0.0115 in2 footprint at 1000 seconds. (c)2001 Fairchild Semiconductor Corporation HUF76131SK8 Rev. B HUF76131SK8 1.2 12 1.0 10 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 8 6 4 2 0 0 0 25 50 75 125 100 150 25 50 TA , AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE THERMAL IMPEDANCE ZJA, NORMALIZED 10 1 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 10-1 100 101 102 103 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TJ = MAX RATED TA = 25oC 100 100s 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1000 IDM, PEAK CURRENT (A) ID, DRAIN CURRENT (A) 500 10ms TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION VGS = 5V 100 10 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 125 VDSS(MAX) = 30V 1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2001 Fairchild Semiconductor Corporation 150 - TA 100 1 10-5 10-4 TA = 25oC 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 5. PEAK CURRENT CAPABILITY HUF76131SK8 Rev. B HUF76131SK8 Typical Performance Curves (Continued) 50 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC VGS = 10V VGS = 5V VGS = 4.5V VGS = 4V VGS = 3.5V 40 30 VGS = 3V 20 10 1 0.1 1 10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 100 0 0.5 1.0 1.5 2.0 VDS, DRAIN TO SOURCE VOLTAGE (V) tAV , TIME IN AVALANCHE (ms) 2.5 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS 50 1.75 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 30 20 150oC 10 25oC 0 0.5 0 -55oC 1.0 1.5 2.0 2.5 3.0 VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 10A 1.5 1.25 1.0 VDD = 15V 3.5 0.75 -80 4.0 40 80 120 160 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 0 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. TRANSFER CHARACTERISTICS 1.0 0.8 0.6 0.4 -80 -40 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE (c)2001 Fairchild Semiconductor Corporation ID = 250A 1.1 1.0 0.9 0.8 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE HUF76131SK8 Rev. B HUF76131SK8 Typical Performance Curves (Continued) 10 2500 C, CAPACITANCE (pF) 2000 CISS VGS , GATE TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 1500 1000 COSS 500 CRSS 0 0 5 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 20A ID = 10A ID = 5A ID = 2.5A 2 VDD = 15V 0 30 10 15 20 25 VDS , DRAIN TO SOURCE VOLTAGE (V) 8 10 0 30 20 Qg, GATE CHARGE (nC) 40 50 NOTE: Refer to Fairchild Application Notes 7254 and 7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 200 VDD = 15V, ID = 10A, RL= 1.5 ID = 10A 60 ID = 5A 40 SWITCHING TIME (ns) rDS(ON), ON-STATE RESISTANCE (m) 80 ID = 20A ID = 2.5A 20 150 tr td(OFF) 100 tf 50 td(ON) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 4 2 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 0 0 10 FIGURE 14. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50 FIGURE 15. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 17. UNCLAMPED ENERGY WAVEFORMS HUF76131SK8 Rev. B HUF76131SK8 Test Circuits and Waveforms (Continued) VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS - VDD 10% 10% 0 DUT 90% RGS VGS VGS 0 50% 10% FIGURE 18. SWITCHING TIME TEST CIRCUIT 50% PULSE WIDTH FIGURE 19. SWITCHING TIME WAVEFORM VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT Ig(REF) VGS = 5V VGS - VGS = 1V 0 Qg(TH) Ig(REF) 0 FIGURE 20. GATE CHARGE TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 21. GATE CHARGE WAVEFORMS HUF76131SK8 Rev. B HUF76131SK8 Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature TJMAX constrains the maximum allowable device power dissipation PDmax in an application. The application ambient temperature TA (oC) and thermal impedance ZJA (oC/W) must be reviewed to ensure that TJMAX (oC) is never exceeded. Equation 1 mathematically represents the relationship. R JA = 79.3 - 21.8 x ln ( Area ) (EQ. 2) 250 (EQ. 1) Fairchild provides thermal information to assist the designer's preliminary application evaluation. Precise determination of PDMAX is complex and influenced by many factors: 1. PC heat sink area and location (top and bottom), copper leads and mounting pad area. RJA = 79.3 - 21.8*ln(AREA) 200 RJA (oC/W) ( T JMAX - T A ) P DMAX = ---------------------------------------Z JA Thermal resistance values corresponding to other component side copper areas can be obtained from Figure 22 or by calculation using Equation 2. Area in Equation 2 is the top copper area including the gate and source pads. 177.3oC/W - 0.0115in2 143.4oC/W - 0.054in2 150 100 2. Air Flow, board orientation and type. 3. Power pulse width and duty factor. Figure 22 addresses these points by depicting RJA values vs. top copper (component side) heat sink area. The measurements were performed in still air using a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power. Figure 22 also displays the two RJA values listed in the Electrical Specifications table. The two points were chosen to graphically depict the compromise between copper board area, thermal resistance and ultimately power dissipation. (c)2001 Fairchild Semiconductor Corporation 50 0.001 0.01 0.1 AREA, TOP COPPER AREA (in2) 1.0 FIGURE 22. THERMAL RESISTANCE vs MOUNTING PAD AREA Figure 22 provides the necessary information for steady state junction temperature or power dissipation calculations. Transient pulse applications are best studied using the Fairchild device SPICE thermal model. HUF76131SK8 Rev. B HUF76131SK8 PSPICE Electrical Model SUBCKT HUF76131 2 1 3 ; rev 12/31/97 CA 12 8 2.22-9 CB 15 14 2.13e-9 CIN 6 8 1.52e-9 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD ESLC 11 - EBREAK 11 7 17 18 37.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 + 17 EBREAK 18 50 - LDRAIN 2 5 1e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 1.29e-10 EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RLSOURCE S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.94e-3 RGATE 9 20 2.20 RLDRAIN 2 5 10 RLGATE 1 9 10.4 RLSOURCE 3 7 1.29 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 8.75e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBREAK + RSLC2 5 51 IT 8 17 1 RLDRAIN RSLC1 51 S2A 13 8 14 13 S1B 17 18 RVTEMP S2B 13 CA RBREAK 15 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),3))} .MODEL DBODYMOD D (IS = 2.25e-12 RS = 6.05e-3 IKF=16.00 TRS1 = 1.14e-4 TRS2 = 1.23e-6 CJO = 2.35e-9 TT = 2.71e-8 M = 0.44) .MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 1.01e-4 TRS2 = 1.11e-7) .MODEL DPLCAPMOD D (CJO = 1.08e-9 IS = 1e-30 N = 10 M = 0.69) .MODEL MMEDMOD NMOS (VTO = 1.89 KP = 5.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.20) .MODEL MSTROMOD NMOS (VTO = 2.22 KP = 125.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22.0 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.54e-4 TC2 = 1.07e-7) .MODEL RDRAINMOD RES (TC1 = 1.61e-2 TC2 = 5.17e-5) .MODEL RSLCMOD RES (TC1 = 1.03e-5 TC2 = 7.67e-7) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -2.81e-3 TC2 = -8.75e-6) .MODEL RVTEMPMOD RES (TC1 = -6.68e-4 TC2 = 8.80e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.80 VOFF= -1.50) VON = -1.50 VOFF= -5.80) VON = -0.50 VOFF= -0.00) VON = 0.00 VOFF= -0.50) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2001 Fairchild Semiconductor Corporation HUF76131SK8 Rev. B HUF76131SK8 SPICE Thermal Model 7 JUNCTION REV 20 Feb 98 HUF76131 CTHERM1 7 6 3.75e-4 CTHERM2 6 5 3.05e-3 CTHERM3 5 4 3.70e-2 CTHERM4 4 3 2.52e-2 CTHERM5 3 2 8.50e-2 CTHERM6 2 1 7.95e-1 RTHERM1 RTHERM1 7 6 3.95e-2 RTHERM2 6 5 2.50e-1 RTHERM3 5 4 4.00e-1 RTHERM4 4 3 6.35 RTHERM5 3 2 2.02e1 RTHERM6 2 1 4.80e1 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 1 (c)2001 Fairchild Semiconductor Corporation CASE HUF76131SK8 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET VCXTM STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4