FQA19N60 - Fairchild - Datasheet.Live

April 2000

Rev. A, April 2000

FQA19N60

QFET

QFETQFET

QFETTM

FQA19N60

600V N-Ch annel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for high efficiency switch mode power supply.

Features

• 18.5A, 600V, RDS(on) = 0.38 Ω @ VGS = 10 V

• Low gate charge ( typical 70 nC)

• Low Crss ( typical 35 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratin gs

 TC = 25°C unless otherwise noted

Thermal Characteri stics

Symbol Parameter FQA19N60 Units

VDSS Drain-Source Voltage 600 V

IDDrain Current - Continuous (TC = 25°C) 18.5 A

- Continuous (TC = 100°C) 11.7 A

IDM Drain Current - Pulsed (Note 1) 74 A

VGSS Gate-Source Voltage ±30 V

EAS Single Pulsed Avalanche Energy (Note 2) 1150 mJ

IAR Avalanche Current (Note 1) 18.5 A

EAR Repetitive Avalanche Energy (Note 1) 30 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 Vns

PDPower Dissipation (TC = 25°C) 300 W

- Derate above 25°C 2.38 W/°C

TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C

TLMaximum lead temperature for soldering purposes,

1/8 from case for 5 seconds 300 °C

Symbol Parameter Typ Max Units

RθJC Thermal Resistance, Junction-to-Case -- 0.42 °CW

RθCS Thermal Resistance, Case-to-Sink 0.24 -- °CW

RθJA Thermal Resistance, Junction-to-Ambient -- 40 °CW

TO-3PN

FQA Series

GSD

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FQA19N60

(Note 4)

(Note 4, 5)

(Note 4)

Rev. A, April 2000

Electrical CharacteristicsTC = 25°C unless otherwise noted

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 6.2mH, IAS = 18.5A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD  18.5A, di/dt  200A/µs, VDD  BVDSS, Starting TJ = 25°C

4. Pulse Test : Pulse width 300µs, Duty cycle 2%

5. Essentially independent of operating temperature

Symbol Parame ter Test Condit ions Min Typ Max Units

Off Characteristics

BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA600 -- -- V

∆BVDSS

/ ∆TJ

Breakdown Voltage Temperature

Coefficient ID = 250 µA, Referenced to 25°C -- 0.65 -- V/°C

IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V -- -- 10 µA

VDS = 480 V, TC = 125°C -- -- 100 µA

IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA

IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteri st ics

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA3.0 -- 5.0 V

RDS(on) Static Drain-Source

On-Resistance VGS = 10 V, ID = 9.3 A -- 0.3 0.38 Ω

gFS Forward Transconduct ance VDS = 50 V, ID = 9.3 A -- 16 -- S

Dynamic Characteristics

Ciss Input Capacitance VDS = 25 V, VGS = 0 V,

f = 1.0 MHz

-- 2800 3600 pF

Coss Output Capacitance -- 350 450 pF

Crss Reverse Transfer Capacitance -- 35 45 pF

Switching Characteristics

td(on) Turn-On Delay Time VDD = 300 V, ID = 18.5 A,

RG = 25 Ω

-- 65 140 ns

trTurn-On Rise Time -- 210 430 ns

td(off) Turn-Off D e l a y Time -- 15 0 310 n s

tfTurn-Off F a ll Time -- 1 3 5 280 n s

QgTotal Gate Ch a rge VDS = 480 V, ID = 18.5 A,

VGS = 10 V

-- 70 90 nC

Qgs Gate-Source Charge -- 17 -- nC

Qgd Gate-Drain Charge -- 33 -- nC

Drain-Sourc e Diode Characteristics and Maximum R atings

ISMaximum Continuous Drain-Source Diode Forward Current -- -- 18.5 A

ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 74 A

VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 18.5 A -- -- 1.4 V

trr Reverse Recovery Time VGS = 0 V, I S = 18.5 A,

dIF / dt = 100 A/µs -- 420 -- ns

Qrr Reverse Recovery Charge -- 4.7 - - µC

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FQA19N60

Rev. A, April 2000

01530456075

VDS = 300V

VDS = 120V

VDS = 480V

 N ote : ID = 18.5 A

VGS, Gate-Source Voltage [V]

QG, T ota l Ga t e Ch arge [n C]

10-1 100101

1000

2000

3000

4000

5000 Ciss = Cgs + C gd (C ds = shorted)

Coss = Cds + Cgd

Crss = Cgd



N o te s :

1. V GS = 0 V

2. f = 1 MHz

Crss

Coss

Ciss

Capacitance [pF]

VDS, Drain-Source Voltage [V]

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

10-1

100

101

25

150

 N o te s :

1. VGS = 0V

2. 250

s Pu lse Te st

IDR , Reverse Drain Current [A]

VSD , Source-Drain Voltage [V]

0 10203040506070

0.0

0.2

0.4

0.6

0.8

1.0

1.2

VGS = 20V

VGS = 10V

 Note : TJ = 25

RDS(ON) [],

Drain-Source On-Resistance

ID, Dr a i n Curren t [A]

246810

10-1

100

101



No te s :

1. V DS = 50V

2. 250

s Pulse Test

-55

150

25

ID , Drain Current [A]

VGS , G a te- S ou rc e V o ltag e [V ]

10-1 100101

100

101



N o te s :

1. 250

s Pu lse T es t

2. T C = 25

VGS

T op : 1 5 V

10 V

8.0 V

7.0 V

6.5 V

6.0 V

B otto m : 5.5 V

ID , D ra in C u rr en t [A ]

VDS , Drain-S o u rc e V olta g e [V ]

Typical Characteristics

Figure 5. C apacitance C h a racteristi cs Figure 6. Ga te Ch arge Chara ct eri stics

Figu re 3. On-Resi stan ce Variation vs.

Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage

Variation vs. Source Curre n t an d

Temperature

Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character i st ics

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FQA19N60

Rev. A, April 2000

10-5 10-4 10-3 10-2 10-1 100101

10-2

10-1  Note s :

1 . Z JC(t) = 0.42 /W Max .

2 . D u ty Fa c to r , D=t1/t2

3 . T JM - T C = P DM * Z JC(t)

single p ulse

D=0.5

0.02

0.2

0.05

0.1

0.01

ZJC

(t), T herm al R esponse

t1, S qu a re W a ve P u lse D u ra tio n [se c ]

25 50 75 100 125 150

ID, D rain Current [A]

TC, Case Temperature [

]

100101102103

10-1

100

101

102

10 µs

DC 10 ms

1 ms

100 µs

Operation in This Area

is Limited by R DS(on)

 Notes :

1. TC = 25 oC

2. TJ = 150 oC

3. Single Pulse

ID, D rain Curr e nt [A]

VDS, Drain-Source Voltage [V]

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0



Notes :

1. V GS = 10 V

2. ID = 9.3 A

RDS(ON) , (Normalized)

Drain-Source O n-Resistance

TJ, Junction Tem perature [oC]

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2



N o te s :

1. V GS = 0 V

2. ID = 250 

BV DSS , (No r ma liz e d )

D rain-S ource B reakdow n V oltage

TJ, Junction T em perature [oC]

Typical Characteristics (Continued)

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

Figu re 7. Breakdown Voltage Variati o n

vs. Temperature Figure 8. On-Resistance Variation

vs. Temperature

Figure 11. Transient Thermal Res pons e Cur ve

PDM

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FQA19N60

Rev. A, April 2000

Gate Charge Test Circuit & W aveform

Resistive Switching Test Circuit & Waveforms

Unclamped Inductive Switching Test Circuit & Waveforms

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K

200nF

12V

Same Type

as DUT

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K

200nF

12V

Same Type

as DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

EAS =LI

AS2

----

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

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FQA19N60

Rev. A, April 2000

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD controlled by pulse period

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD controlled by pulse period

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

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FQA19N60

Rev. A, April 2000

Mechanical Dimensions

Dimensions in Millimeters

TO-3PN

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TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

ACEx™

Bottomless™

CoolFET™

CROSSVOLT™

E2CMOS™

FACT™

FACT Quiet Series™

FAST®

FASTr™

GTO™

HiSeC™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench®

QFET™

QS™

Quiet Series™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic™

UHC™

VCX™

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

INTERNATIONAL.

As used herein:

1. Life support devices or systems are devic es or syst em s

which, (a) ar e intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary First Production T his datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconduct or reserv es the right to make

changes at any time without notice in order to improve

design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconduct or reserv es the right to make changes at

any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

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