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PC16550D
SNLS378C –JUNE 1995–REVISED MAY 2015
PC16550D Universal Asynchronous Receiver/Transmitter With FIFOs
1 Features 3 Description
The PC16550D device is an improved version of the
1• Capable of Running All Existing 16450 Software. original 16450 Universal Asynchronous
• Pin for Pin Compatible With the Existing 16450 Receiver/Transmitter (UART). Functionally identical to
Except for CSOUT (24) and NC (29). The Former the 16450 on powerup (CHARACTER mode: can also
CSOUT and NC Pins Are TXRDY and RXRDY, be reset to 16450 Mode under software control) the
Respectively. PC16550D can be put into an alternate mode (FIFO
mode) to relieve the CPU of excessive software
• After Reset, All Registers Are Identical to the overhead.
16450 Register Set.
• In the FIFO(1) Mode Transmitter and Receiver Are In this mode internal FIFOs are activated allowing 16
bytes (plus 3 bits of error data per byte in the RCVR
Each Buffered With 16 Byte FIFO’s to Reduce the FIFO) to be stored in both receive and transmit
Number of Interrupts Presented to the CPU. modes. All the logic is on chip to minimize system
• Adds or Deletes Standard Asynchronous overhead and maximize system efficiency. Two pin
Communication Bits (Start, Stop, and Parity) to or functions have been changed to allow signalling of
From the Serial Data. DMA transfers.
• Holding and Shift Registers in the 16450 Mode The UART performs serial-to-parallel conversion on
Eliminate the Need for Precise Synchronization data characters received from a peripheral device or
Between the CPU and Serial Data. a MODEM, and parallel-to-serial conversion on data
• Independently Controlled Transmit, Receive, Line characters received from the CPU. The CPU can
Status, and Data Set Interrupts. read the complete status of the UART at any time
during the functional operation. Status information
• Programmable Baud Generator Divides Any Input reported includes the type and condition of the
Clock by 1 to (216 – 1) and Generates the 16 × transfer operations being performed by the UART, as
Clock. well as any error conditions (parity, overrun, framing,
• Independent Receiver Clock Input. or break interrupt).
• MODEM Control Functions (CTS, RTS, DSR, Device Information(1)
DTR, RI, and DCD). PART NUMBER PACKAGE BODY SIZE (NOM)
• Fully Programmable Serial-Interface PLCC (44) 17.53 mm x 17.53 mm
Characteristics PC16550D PDIP (40) 52.58 mm x 13.97 mm
– 5-, 6-, 7-, or 8-Bit Characters (1) For all available packages, see the orderable addendum at
– Even, Odd, or No-Parity Bit Generation and the end of the datasheet.
Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation Basic Configuration
– Baud Generation (DC to 1.5 M Baud).
• False Start Bit Detection.
• Complete Status Reporting Capabilities.
• TRI-STATE TTL Drive for the Data and Control
Buses.
• Line Break Generation and Detection.
• Internal Diagnostic Capabilities
– Loopback Controls for Communications Link
Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation.
• Full Prioritized Interrupt System Controls.
2 Applications
Modems or Generic UART Communication
(1) This part is patented
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PC16550D
SNLS378C –JUNE 1995–REVISED MAY 2015
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Table of Contents
8.4 Device Functional Modes........................................ 16
1 Features.................................................................. 18.5 Programming .......................................................... 17
2 Applications ........................................................... 18.6 Register Maps ........................................................ 17
3 Description............................................................. 19 Application and Implementation ........................ 25
4 Revision History..................................................... 29.1 Application Information............................................ 25
5 Description (continued)......................................... 39.2 Typical Applications ................................................ 25
6 Pin Configuration and Functions......................... 39.3 System Examples ................................................... 27
7 Specifications......................................................... 810 Power Supply Recommendations ..................... 27
7.1 Absolute Maximum Ratings ...................................... 811 Layout................................................................... 27
7.2 ESD Ratings.............................................................. 811.1 Layout Guidelines ................................................. 27
7.3 Recommended Operating Conditions....................... 812 Device and Documentation Support................. 28
7.4 Electrical Characteristics........................................... 812.1 Community Resources.......................................... 28
7.5 Timing Requirements................................................ 912.2 Trademarks........................................................... 28
8 Detailed Description............................................ 15 12.3 Electrostatic Discharge Caution............................ 28
8.1 Overview................................................................. 15 12.4 Glossary................................................................ 28
8.2 Functional Block Diagram....................................... 15 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 16 Information ........................................................... 28
4 Revision History
Changes from Revision B (June 1995) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
• Deleted the TQFP Package drawing...................................................................................................................................... 3
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5 Description (continued)
The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock
input by divisors of 1 to (216–1), and producing a 16 × clock for driving the internal transmitter logic. Provisions
are also included to use this 16 × clock to drive the receiver logic. The UART has complete MODEM-control
capability, and a processor-interrupt system. Interrupts can be programmed to the user’s requirements,
minimizing the computing required to handle the communications link.
The UART is fabricated using Texas Instruments advanced M2CMOS process.
6 Pin Configuration and Functions
NFJ Package
44-Pin PDIP
Top View
FN Package
44-Pin PLCC
Top View
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Pin Functions
PIN I/O DESCRIPTION(1)
NAME PDIP PLCC
A0 28 31 I Register Select. Address signals connected to these 3 inputs select a UART register for the CPU
to read from or write to during data transfer. A table of registers and their addresses is shown
A1 27 30 I below. Note that the state of the Divisor Latch Access Bit (DLAB), which is the most significant
bit of the Line Control Register, affects the selection of certain UART registers. The DLAB must
A2 26 29 I be set high by the system software to access the Baud Generator Divisor Latches.
Address Strobe. The positive edge of an active Address Strobe (ADS) signal latches the
Register Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) signals.
NOTE
An active ADS input is required when the Register
ADS 25 28 I Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2)
signals are not stable for the duration of a read or
write operation. If not required, tie the ADS input
permanently low.
Baud Out. This is the 16 × clock signal from the transmitter section of the UART. The clock rate
is equal to the main reference oscillator frequency divided by the specified divisor in the Baud
BAUDOUT 15 17 O Generator Divisor Latches. The BAUDOUT may also be used for the receiver section by tying
this output to the RCLK input of the chip.
CS0 12 14 I Chip Select. When CS0 and CS1 are high and CS2 is low, the chip is selected. This enables
communication between the UART and the CPU. The positive edge of an active Address Strobe
CS1 13 15 I signal latches the decoded chip select signals, completing chip selection. If ADS is always low,
CS2 14 16 I valid chip selects should stabilize according to the tCSW parameter.
D01 2 I/O
D12 3 I/O
D23 4 I/O Data Bus. This bus comprises eight TRISTATE input/output lines. The bus provides bidirectional
D34 5 I/O communications between the UART and the CPU. Data, control words, and status information
D45 6 I/O are transferred through the D7–D0Data Bus.
D56 7 I/O
D67 8 I/O
D78 9 I/O Clear to Send. When low, this indicates that the MODEM or data set is ready to exchange data.
The CTS signal is a MODEM status input whose conditions can be tested by the CPU reading
bit 4 (CTS) of the MODEM Status Register. Bit 4 is the complement of the CTS signal. Bit 0
(DCTS) of the MODEM Status Register indicates whether the CTS input has changed state
since the previous reading of the MODEM Status Register. CTS has no effect on the
Transmitter.
CTS 36 40 I NOTE
Whenever the CTS bit of the MODEM Status Register
changes state, an interrupt is generated if the MODEM
Status Interrupt is enabled.
(1) The following describes the function of all UART pins. Some of these descriptions reference internal circuits. In the following
descriptions, a low represents a logic 0 (0 V nominal) and a high represents a logic 1 (2.4 V nominal).
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Pin Functions (continued)
PIN I/O DESCRIPTION(1)
NAME PDIP PLCC
Data Carrier Detect. When low, indicates that the data carrier has been detected by the MODEM
or data set. The DCD signal is a MODEM status input whose condition can be tested by the
CPU reading bit 7 (DCD) of the MODEM Status Register. Bit 7 is the complement of the DCD
signal. Bit 3 (DDCD) of the MODEM Status Register indicates whether the DCD input has
changed state since the previous reading of the MODEM Status Register. DCD has no effect on
the receiver.
DCD 38 42 I NOTE
Whenever the DCD bit of the MODEM Status Register
changes state, an interrupt is generated if the MODEM
Status Interrupt is enabled.
Driver Disable. This goes low whenever the CPU is reading data from the UART. It can disable
DDIS 23 26 O or control the direction of a data bus transceiver between the CPU and the UART.
Data Set Ready. When low, this indicates that the MODEM or data set is ready to establish the
communications link with the UART. The DSR signal is a MODEM status input whose condition
can be tested by the CPU reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the
complement of the DSR signal. Bit 1 (DDSR) of the MODEM Status Register indicates whether
the DSR input has changed state since the previous reading of the MODEM Status Register.
DSR 37 41 I NOTE
Whenever the DDSR bit of the MODEM Status
Register changes state, an interrupt is generated if the
MODEM Status Interrupt is enabled.
Data Terminal Ready. When low, this informs the MODEM or data set that the UART is ready to
establish a communications link. The DTR output signal can be set to an active low by
DTR 33 37 O programming bit 0 (DTR) of the MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its
inactive state.
Interrupt. This pin goes high whenever any one of the following interrupt types has an active high
condition and is enabled through the IER Receiver Error Flag; Received Data Available timeout
INTR 30 33 O (FIFO Mode only); Transmitter Holding Register Empty; and MODEM Status. The INTR signal is
reset low upon the appropriate interrupt service or a Master Reset operation.
Master Reset. When this input is high, it clears all the registers (except the Receiver Buffer,
Transmitter Holding, and Divisor Latches), and the control logic of the UART. The states of
MR 35 39 I various output signals (SOUT, INTR, OUT 1, OUT 2, RTS, DTR) are affected by an active MR
input (Refer to Table 3) This input is buffered with a TTL-compatible Schmitt Trigger with 0.5-V
typical hysteresis.
Output 1. This user-designated output can be set to an active low by programming bit 2 (OUT 1)
of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its
OUT 1 34 38 O inactive (high) state. Loop mode operation holds this signal in its inactive state. In the XMOS
parts this will achieve TTL levels.
Output 2. This user-designated output that can be set to an active low by programming bit 3
(OUT 2) of the MODEM Control Register to a high level. A Master Reset operation sets this
OUT 2 31 35 O signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. In
the XMOS parts this will achieve TTL levels.
RCLK 9 10 I Receiver Clock. This input is the 16 x baud rate clock for the receiver section of the chip.
RD 22 25 I Read. When RD is high or RD is low while the chip is selected, the CPU can read status
information or data from the selected UART register.
NOTE
Only an active RD or RD input is required to transfer
RD 21 24 I data from the UART during a read operation.
Therefore, tie either the RD input permanently low or
the RD input permanently high, when it is not used.
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Pin Functions (continued)
PIN I/O DESCRIPTION(1)
NAME PDIP PLCC
Ring Indicator. When low, this indicates that a telephone ringing signal has been received by the
MODEM or data set. The RI signal is a MODEM status input whose condition can be tested by
the CPU reading bit 6 (RI) of the MODEM Status Register. Bit 6 is the complement of the RI
signal. Bit 2 (TERI) of the MODEM Status Register indicates whether the RI input signal has
changed from a low to a high state since the previous reading of the MODEM Status Register.
RI 39 43 I NOTE
Whenever the RI bit of the MODEM Status Register
changes from a high to a low state, an interrupt is
generated if the MODEM Status Interrupt is enabled.
Request to Send. When low, this informs the MODEM or data set that the UART is ready to
exchange data. The RTS output signal can be set to an active low by programming bit 1 (RTS)
RTS 32 36 O of the MODEM Control Register. A Master Reset operation sets this signal to its inactive (high)
state. Loop mode operation holds this signal in its inactive state.
Receiver. DMA signaling is available through two pins (24 and 29). When operating in the FIFO
mode, one of two types of DMA signaling per pin can be selected through FCR3. When
operating as in the 16450 Mode, only DMA mode 0 is allowed. Mode 0 supports single transfer
DMA where a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA
where multiple transfers are made continuously until the RCVR FIFO has been emptied or the
XMIT FIFO has been filled.
RXRDY 29 32 O Mode 0: When in the 16450 Mode (FCR0e0) or in the FIFO Mode (FCR0=1, FCR3=0) and there
is at least 1 character in the RCVR FIFO or RCVR holding register, the RXRDY pin (29) will be
low active. Once it is activated the RXRDY pin will go inactive when there are no more
characters in the FIFO or holding register.
Mode 1: In the FIFO Mode (FCR0=1) when the FCR3=1 and the trigger level or the timeout has
been reached, the RXRDY pin will go low active. Once it is activated it will go inactive when
there are no more characters in the FIFO or holding register.
Serial Input. Serial data input from the communications link (peripheral device, MODEM, or data
SIN 10 11 I set).
Serial Output. Composite serial data output to the communications link (peripheral, MODEM or
SOUT 11 13 O data set). The SOUT signal is set to the Marking (logic 1) state upon a Master Reset operation.
Transmitter. DMA signaling is available through two pins (24 and 29). When operating in the
FIFO mode, one of two types of DMA signaling per pin can be selected through FCR3. When
operating as in the 16450 Mode, only DMA mode 0 is allowed. Mode 0 supports single transfer
DMA where a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA
where multiple transfers are made continuously until the RCVR FIFO has been emptied or the
XMIT FIFO has been filled.
TXRDY 24 27 O Mode 0: In the 16450 Mode (FCR0=0) or in the FIFO Mode (FCR0=1, FCR3=0) and there are
no characters in the XMIT FIFO or XMIT holding register, the TXRDY pin (24) will be low active.
Once it is activated the TXRDY pin will go inactive after the first character is loaded into the
XMIT FIFO or holding register.
Mode 1: In the FIFO Mode (FCR0=1) when FCR3=1 and there are no characters in the XMIT
FIFO, the TXRDY pin will go low active. This pin will become inactive when the XMIT FIFO is
completely full.
VDD 40 44 — 5-V supply.
VSS 20 22 — Ground (0 V) reference.
WR 19 21 I Write. When WR is high or WR is low while the chip is selected, the CPU can write control words
or data into the selected UART register.
NOTE
Only an active WR or WR input is required to transfer
WR 18 20 I data to the UART during a write operation. Therefore,
tie either the WR input permanently low or the WR
input permanently high, when it is not used.
(External Crystal Input). This signal input is used in conjunction with XOUT to form a feedback
XIN 16 18 I circuit for the baud rate generator’s oscillator. If a clock signal will be generated off-chip, then it
should drive the baud rate generator through this pin.
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Pin Functions (continued)
PIN I/O DESCRIPTION(1)
NAME PDIP PLCC
(External Crystal Output). This signal output is used in conjunction with XIN to form a feedback
XOUT 17 19 O circuit for the baud rate generator’s oscillator. If the clock signal will be generated off-chip, then
this pin is unused.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
All input or output voltages with respect to VSS –0.5 7 V
Power Dissipation 1 W
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
TAAmbient Temperature 0 25 70 °C
VDD Supply Voltage 4.5 5 5.5 V
7.4 Electrical Characteristics
TA= 0°C to 70°C, VDD = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VILX Clock input low voltage –0.5 0.8 V
VIHX Clock input high voltage 2.0 VDD V
VIL Input low voltage –0.5 0.8 V
VIH Input high voltage 2 VDD V
VOL Output low voltage IOL = 1.6 mA on all(1) 0.4 V
VOH Output high voltage IOH = –1.0 mA(1) 2.4 V
VDD = 5.5 V, TA= 25°C, No Loads on output,
ICC(AV) Average power supply current SIN, DSR, DCD, CTS, RI = 2.0 V, 15 mA
All other inputs = 0.8 V
IIL Input leakage ±10 mA
VDD = 5.5 V, VSS = 0 V, All other pins floating,
VIN = 0 V, 5.5 V
ICL Clock leakage ±10 mA
VDD = 5.5 V, VSS = 0 V, VOUT = 0 V, 5.25 V
IOZ TRI-STATE leakage 1) Chip deselected ±20 mA
2) WRITE mode, chip selected
VILMR MR Schmitt VIL 0.8 V
VIHMR MR Schmitt VIH 2 V
CAPACITANCE: TA= 25°C, VDD = VSS = 0 V
CXIN Clock input capacitance 7 9 pF
CXOUT Clock output capacitance 7 9 pF
CIN Input capacitance fc= 1 MHz, Unmeasured pins returned to VSS 5 7 pF
COUT Output capacitance 6 8 pF
CI/O Input/Output capacitance 10 12 pF
(1) Does not apply to XOUT.
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7.5 Timing Requirements
TA= 0°C to 70C, VDD = 5 V ± 10% MIN MAX UNIT
tADS Address strobe width 60 ns
tAH Address hold time 0 ns
tAR RD, RD delay from address See (1) 30 ns
tAS Address setup time 60 ns
tAW WR, WR delay from address See (1) 30 ns
tCH Chip select hold time 0 ns
tCS Chip select setup time 60 ns
tCSR RD, RD delay from chip select See (1) 30 ns
tCSW WR, WR delay from select See (1) 30 ns
tDH Data hold time 30 ns
tDS Data setup time 30 ns
tHZ RD, RD to floating data delay At 100 pF loading (2) 0 100 ns
tMR Master reset pulse width 5000 ns
tRA Address hold time from RD, RD See (1) 20 ns
tRC Read cycle delay 125 ns
tRCS Chip select hold time from RD, RD See (1) 20 ns
tRD RD, RD strobe width 125 ns
tRDD RD, RD to driver enable/disable At 100 pF loading (2) 60 ns
tRVD Delay from RD, RD to data At 100 pF loading 60 ns
tWA Address hold time from WR, WR See (1) 20 ns
tWC Write cycle delay 150 ns
tWCS Chip select hold time from WR, WR See (1) 20 ns
tWR WR, WR strobe width 100 ns
tXH Duration of clock high pulse External Clock (8, Max.) 55 ns
tXL Duration of clock low pulse External Clock (8, Max.) 55 ns
RC Read cycle = tAR + tRD + tRC 280 ns
WC Write cycle = tAW + tWR + tWC 280 ns
BAUD GENERATOR
N Baud divisor 1 216–1
tBHD Baud output positive edge delay 100-pF Load 175 ns
tBLD Baud output negative edge delay 100-pF Load 175 ns
tHW Baud output up time fX= 8, ÷2, 100-pF Load 75 ns
tLW Baud output down time fX= 8, ÷2, 100-pF Load 100 ns
RECEIVER
Delay from active edge of RD to Reset
tRAI Interrupt – ns
Delay from RD, RD (RD RBR/or RD LSR) to
tRINT 100-pF Load 1000 ns
Reset Interrupt
tRXI Delay from RD RBR to RXRDY Inactive 290 ns
tSCD Delay from RCLK to sample time 2000 ns
RCLK
tSINT Delay from Stop to Set Interrupt See (3) 1Cycles
(1) Applicable only when ADS is tied low.
(2) Charge and discharge time is determined by VOL, VOH and the external loading.
(3) In the FIFO mode (FCR0=1) the trigger level interrupts, the receiver data available indication, the active RXRDY indication and the
overrun error indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been
received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt is
delayed 8 RCLKs.
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Timing Requirements (continued)
TA= 0°C to 70C, VDD = 5 V ± 10% MIN MAX UNIT
TRANSMITTER
Delay from WR, WR (WR THR) to Reset
tHR 100-pF Load 175 ns
Interrupt
Delay from RD, RD (RD IIR) to Reset Interrupt
tIR 100-pF Load 250 ns
(THRE) BAUDOUT
tIRS Delay from Initial INTR Reset to Transmit Start 8 24 Cycles
BAUDOUT
tSI Delay from Initial Write to Interrupt See (4) 16 24 Cycles
BAUDOUT
tSTI Delay from Stop to Interrupt (THRE) See (2) 8 8 Cycles
BAUDOUT
tSXA Delay from Start to TXRDY active 100-pF Load 8 Cycles
tWXI Delay from Write to TXRDY inactive 100-pF Load 195 ns
MODEM CONTROL
tMDO Delay from WR, WR (WR MCR) to Output 100-pF Load 200 ns
Delay from RD, RD to Reset Interrupt (RD
tRIM 100-pF Load 250 ns
MSR)
tSIM Delay from MODEM input to set interrupt 100-pF Load 250 ns
(4) This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active. (See FIFO
Interrupt Mode Operation).
All timings are referenced to valid 0 and valid 1.
Figure 1. External Clock Input (24 MHz Max) Figure 2. AC Test Points
Figure 3. BAUDOUT Timing
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All timings are referenced to valid 0 and valid 1.
Figure 4. Write Cycle
Figure 5. Read Cycle
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All timings are referenced to valid 0 and valid 1.
Figure 6. Receiver Timing
Figure 7. Transmitter Timing
(1) See Write Cycle Timing
(2) See Read Cycle Timing
Figure 8. MODEM Control Timing
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All timings are referenced to valid 0 and valid 1.
Figure 9. RCVR FIFO First Byte (This Sets RDR)
Figure 10. RCVR FIFO Bytes Other Than the First Byte (RDR is Already Set)
(1) This is the reading of the last byte in the FIFO.
(2) If FCR0 = 1, then tSINT = 3 RCLKs. For a timeout interrupt, tSINT = 8 RCLKs.
Figure 11. Receiver Ready (Pin 29) FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
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All timings are referenced to valid 0 and valid 1.
(1) This is the reading of the last byte in the FIFO.
(2) If FCR0 = 1, tSINT = 3 RCLKs.
Figure 12. Receiver Ready (Pin 29) FCR0=1 and FCR3=1 (Mode 1)
Figure 13. Transmitter Ready (Pin 24) FCR0=0 or FCR0=1 and FCR3=0 (Mode 0)
Figure 14. Transmitter Ready (Pin 24) FCR0=1 and FCR3=1 (Mode 1)
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8 Detailed Description
8.1 Overview
The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter
(UART). This device performs serilization/deserialization (ser/des) on data between a peripheral device, such as
a modem, and the central processing unit (CPU). The PC16550D provides several status indicators to allow the
cpu to monitor the type and status of data transfers.
8.2 Functional Block Diagram
NOTE: Applicable pinout numbers are included within parenthesis.
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8.3 Feature Description
The PC16550D contains the full feature set and functionality of the 16450, but also features integrated transmit
and receive FIFOs to relieve the CPU of excessive software overhead. Configuration of the modem status,
modem control, interrupt enable, interrupt I/O, transmitter, receiver, line control registers are discussed in the
Registers section. The PC16550D can be configured to support baud rates from DC to 1.5 M baud.
8.4 Device Functional Modes
8.4.1 FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR0=1, IER0=1) RCVR interrupts will occur as
follows
1. The receive data available interrupt will be issued to the CPU when the FIFO has reached its programmed
trigger level; it will be cleared as soon as the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR=06), as before, has higher priority than the received data available
(IIR=04) interrupt.
4. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the RCVR
FIFO. It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts will occur as follows:
1. A FIFO timeout interrupt will occur, if the following conditions exist
– at least one character is in the FIFO
– the most recent serial character received was longer than 4 continuous character times ago (if 2 stop bits
are programmed the second one is included in this time delay).
– the most recent CPU read of the FIFO was longer than 4 continuous character times ago.
The maximum time between a received character and a timeout interrupt will be 160 ms at 300 baud with a
12-bit receive character (that is, 1 Start, 8 Data, 1 Parity and 2 Stop Bits).
2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional
to the baudrate).
3. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character
from the RCVR FIFO.
4. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after
the CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR0=1, IER1=1), XMIT interrupts will occur as
follows:
1. The transmitter holding register interrupt (02) occurs when the XMIT FIFO is empty; it is cleared as soon as
the transmitter holding register is written to (1 to 16 characters may be written to the XMIT FIFO while
servicing this interrupt) or the IIR is read.
2. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time
whenever the following occurs THRE=1 and there have not been at least two bytes at the same time in the
transmit FIFO, since the last THRE=1. The first transmitter interrupt after changing FCR0 will be immediate,
if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data
available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty
interrupt.
8.4.2 FIFO Polled Mode Operation
With FCR0=1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART in the FIFO Polled Mode of
operation. Since the RCVR and XMITTER are controlled separately either one or both can be in the polled mode
of operation.
In this mode the user’s program will check RCVR and XMITTER status through the LSR. As stated previously:
• LSR0 will be set as long as there is one byte in the RCVR FIFO.
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Device Functional Modes (continued)
• LSR1 to LSR4 will specify which error(s) has occurred. Character error status is handled the same way as
when in the interrupt mode, the IIR is not affected since IER2=0.
• LSR5 will indicate when the XMIT FIFO is empty.
• LSR6 will indicate that both the XMIT FIFO and shift register are empty.
• LSR7 will indicate whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR
and XMIT FIFOs are still fully capable of holding characters.
8.5 Programming
8.5.1 Programmable Baud Generator
The UART contains a programmable Baud Generator that is capable of taking any clock input from DC to 24
MHz and dividing it by any divisor from 2 to 216–1. The output frequency of the Baud Generator is 16 × the Baud
[divisor # = (frequency input) ÷ (baud rate × 16)]. Two 8-bit latches store the divisor in a 16-bit binary format.
These Divisor Latches must be loaded during initialization to ensure proper operation of the Baud Generator.
Upon loading either of the Divisor Latches, a 16-bit Baud counter is immediately loaded.
Table 4 provides decimal divisors to use with crystal frequencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz,
respectively. For baud rates of 38400 and below, the error obtained is minimal. The accuracy of the desired baud
rate is dependent on the crystal frequency chosen. Using a divisor of zero is not recommended.
8.6 Register Maps
Table 1. Summary of Registers
REGISTER ADDRESS
0 1
0 DLAB=0 0 DLAB=0 1 DLAB=0 2 2 3 4 5 6 7 DLAB=1 DLAB=1
Transmitter
Receiver Interrupt FIFO Divisor Divisor
Holding
Bit Buffer Interrupt Ident. Control Line MODEM Scratch
Line Status MODEM Status
Register
No. Register Enable Register Register Control Control Latch Latch
Register Register Register
(Read Register (Read (Write Register Register
(Write (LS) (MS)
Only) Only) Only)
Only)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
0 Data Bit 0(1) Data Bit 0 Enable ‘‘0’’ if FIFO Word Data Data Ready Delta Clear to Bit 0 Bit 0 Bit 8
Received Data Interrupt Enable Length Terminal (DR) Send (DCTS)
Available Pending Select Bit 0 Ready
Interrupt (WLS0) (DTR)
(ERBFI)
1 Data Bit 1 Data Bit 1 Enable Interrupt ID RCVR FIFO Word Request to Overrun Delta Data Set Bit 1 Bit 1 Bit 9
Transmitter Bit (0) Reset Length Send (RTS) Error (OE) Ready (DDSR)
Holding Select Bit 1
Register Empty (WLS1)
Interrupt
(ETBEI)
2 Data Bit 2 Data Bit 2 Enable Interrupt ID XMIT FIFO Number of Out 1 Parity Error Trailing Edge Bit 2 Bit 2 Bit 10
Receiver Line Bit (1) Reset Stop Bits (PE) Ring Indicator
Status Interrupt (STB) (TERI)
(ELSI)
3 Data Bit 3 Data Bit 3 Enable Interrupt ID DMA Mode Parity Out 2 Framing Delta Data Bit 3 Bit 3 Bit 11
MODEM Status Select Enable Error (FE) Carrier Detect
Bit (2) (2)
Interrupt (PEN) (DDCD)
(EDSSI)
4 Data Bit 4 Data Bit 4 0 0 Reserved Even Parity Loop Break Clear to Send Bit 4 Bit 4 Bit 12
Select Interrupt (CTS)
(EPS) (BI)
5 Data Bit 5 Data Bit 5 0 0 Reserved Stick Parity 0 Transmitter Data Set Ready Bit 5 Bit 5 Bit 13
Holding (DSR)
Register
(THRE)
6 Data Bit 6 Data Bit 6 0 FIFOs RCVR Set Break 0 Transmitter Ring Indicator Bit 6 Bit 6 Bit 14
Trigger Empty (RI)
Enabled (2) (LSB) (TEMT)
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the 16450 Mode.
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Table 1. Summary of Registers (continued)
REGISTER ADDRESS
0 1
0 DLAB=0 0 DLAB=0 1 DLAB=0 2 2 3 4 5 6 7 DLAB=1 DLAB=1
Transmitter
Receiver Interrupt FIFO Divisor Divisor
Holding
Bit Buffer Interrupt Ident. Control Line MODEM Scratch
Line Status MODEM Status
Register
No. Register Enable Register Register Control Control Latch Latch
Register Register Register
(Read Register (Read (Write Register Register
(Write (LS) (MS)
Only) Only) Only)
Only)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
7 Data Bit 7 Data Bit 7 0 FIFOs RCVR Divisor 0 Error in Data Carrier Bit 7 Bit 7 Bit 15
Trigger Latch RCVR Detect (DCD)
Enabled(2) (MSB) Access Bit FIFO(2)
(DLAB)
8.6.1 Registers
The system programmer may access any of the UART registers summarized in Table 1 through the CPU. These
registers control UART operations including transmission and reception of data. Each register bit in Table 1 has
its name and reset state shown.
Table 2. Register Addresses
DLAB A2A1A0REGISTER
0 0 0 0 Receiver Buffer (read),
Transmitter Holding
Register (write)
0 0 0 1 Interrupt Enable
X 0 1 0 Interrupt Identification (read)
X 0 1 0 FIFO Control (write)
X 0 1 1 Line Control
X 0 0 0 MODEM Control
X 1 0 1 Line Status
X 1 1 0 MODEM Status
X 1 1 1 Scratch
1 0 0 0 Divisor Latch (least significant byte)
1 0 0 1 Divisor Latch (most significant byte)
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Table 3. UART Reset Configuration
REGISTER/SIGNAL RESET CONTROL RESET STATE(1)
Interrupt Enable Register Master Reset 0000 0000
Interrupt Identification Register Master Reset 0000 0001
FIFO Control Master Reset 0000 0000
Line Control Register Master Reset 0000 0000
MODEM Control Register Master Reset 0000 0000
Line Status Register Master Reset 0110 0000
MODEM Status Register Master Reset XXXX 0000(2)
SOUT Master Reset High
INTR (RCVR Errs) Read LSR/MR Low
INTR (RCVR Data Ready) Read RBR/MR Low
INTR (THRE) Read IIR/Write THR/MR Low
INTR (Modem Status Changes) Read MSR/MR Low
OUT 2 Master Reset High
RTS Master Reset High
DTR Master Reset High
OUT 1 Master Reset High
RCVR FIFO MR/FCR1●FCR0/DFCR0 All Bits Low
XMIT FIFO MR/FCR1●FCR0/DFCR0 All Bits Low
(1) Boldface bits are permanently low.
(2) Bits 7 – 4 are driven by the input signals.
Table 4. Baud Rates, Divisors and Crystals
1.8432 MHz CRYSTAL 3.072 MHz CRYSTAL 18.432 MHz CRYSTAL
BAUD DECIMAL DECIMAL
DECIMAL DIVISOR for PERCENT PERCENT PERCENT
RATE DIVISOR for DIVISOR for
ERROR ERROR ERROR
16 × Clock 16 × Clock 16 × Clock
50 2304 – 3840 – 23040 –
75 1536 – 2560 – 15360 –
110 1047 0.026 1745 0.026 10473 –
134.5 857 0.058 1428 0.034 8565 –
150 768 – 1280 – 7680 –
300 384 – 640 – 3840 –
600 192 – 320 – 1920 –
1200 96 – 160 – 920 –
1800 64 – 107 0.312 640 –
2000 58 0.69 96 – 576 –
2400 48 – 80 – 480 –
3600 32 – 53 0.628 320 –
4800 24 – 40 – 240 –
7200 16 – 27 1.23 160 –
9600 12 – 20 – 120 –
19200 6 – 10 – 60 –
38400 3 – 5 – 30 –
56000 2 2.86 – – 21 2.04
128000 – – – – 9 –
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8.6.2 Line Control Register
The system programmer specifies the format of the asynchronous data communications exchange and set the
Divisor Latch Access bit through the Line Control Register (LCR). The programmer can also read the contents of
the Line Control Register. The read capability simplifies system programming and eliminates the need for
separate storage in system memory of the line characteristics. Table 1 shows the contents of the LCR. Details on
each bit follow.
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. The
encoding of bits 0 and 1 is as follows:
Bit 1 Bit 0 Character Length
0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits
Bit 2: This bit specifies the number of Stop bits transmitted and received in each serial character. If bit 2 is a
logic 0, one Stop bit is generated in the transmitted data. If bit 2 is a logic 1 when a 5-bit word length is selected
through bits 0 and 1, one and a half Stop bits are generated. If bit 2 is a logic 1 when either a 6-, 7-, or 8-bit word
length is selected, two Stop bits are generated. The Receiver checks the first Stop-bit only, regardless of the
number of Stop bits selected.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is generated (transmit data) or checked
(receive data) between the last data word bit and Stop bit of the serial data. (The Parity bit is used to produce an
even or odd number of 1s when the data word bits and the Parity bit are summed.)
Bit 4: This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of logic
1s is transmitted or checked in the data word bits and Parity bit. When bit 3 is a logic 1 and bit 4 is a logic 1, an
even number of logic 1s is transmitted or checked.
Bit 5: This bit is the Stick Parity bit. When bits 3, 4 and 5 are logic 1 the Parity bit is transmitted and checked as
a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic 0 then the Parity bit is transmitted and checked as a logic 1. If
bit 5 is a logic 0 Stick Parity is disabled.
Bit 6: This bit is the Break Control bit. It causes a break condition to be transmitted to the receiving UART. When
it is set to a logic 1, the serial output (SOUT) is forced to the Spacing (logic 0) state. The break is disabled by
setting bit 6 to a logic 0. The Break Control bit acts only on SOUT and has no effect on the transmitter logic.
Note: This feature enables the CPU to alert a terminal in a computer communications system. If the following
sequence is followed, no erroneous or extraneous characters will be transmitted because of the break.
1. Load an all 0s, pad character, in response to THRE.
2. Set break after the next THRE
3. Wait for the transmitter to be idle, (TEMT=1), and clear break when normal transmission has to be restored.
During the break, the Transmitter can be used as a character timer to accurately establish the break duration.
Bit 7: This bit is the Divisor Latch Access Bit (DLAB). It must be set high (logic 1) to access the Divisor Latches
of the Baud Generator during a Read or Write operation. It must be set low (logic 0) to access the Receiver
Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.
8.6.3 Line Status Register
This register provides status information to the CPU concerning the data transfer. Table 1 shows the contents of
the Line Status Register. Details on each bit follow.
Bit 0: This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to a logic 1 whenever a complete incoming
character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a
logic 0 by reading all of the data in the Receiver Buffer Register or the FIFO.
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Bit 1: This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was
not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby
destroying the previous character. The OE indicator is set to a logic 1 upon detection of an overrun condition and
reset whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data continues to fill
the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next character
has been completely received in the shift register. OE is indicated to the CPU as soon as it happens. The
character in the shift register is overwritten, but it is not transferred to the FIFO.
Bit 2: This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have the
correct even or odd parity, as selected by the even-parityselect bit. The PE bit is set to a logic 1 upon detection
of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. In the
FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is revealed to
the CPU when its associated character is at the top of the FIFO.
Bit 3: This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not have a valid
Stop bit. Bit 3 is set to a logic 1 whenever the Stop bit following the last data bit or parity bit is detected as a logic
0 bit (Spacing level). The FE indicator is reset whenever the CPU reads the contents of the Line Status Register.
In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is
revealed to the CPU when its associated character is at the top of the FIFO. The UART will try to resynchronize
after a framing error. To do this it assumes that the framing error was due to the next start bit, so it samples this
‘‘start’’ bit twice and then takes in the ‘‘data’’.
Bit 4: This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic 1 whenever the received data input is
held in the Spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit +
data bits + Parity + Stop bits). The BI indicator is reset whenever the CPU reads the contents of the Line Status
Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This
error is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs only one
zero character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state
and receives the next valid start bit.
NOTE
Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt
whenever any of the corresponding conditions are detected and the interrupt is enabled.
Table 5. Interrupt Control Functions
FIFO Interrupt
Mode Identification Interrupt Set and Reset Functions
Only Register
Priority
Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Type Interrupt Source Interrupt Reset Control
Level
0 0 0 1 – None None –
0 1 1 0 Highest Receiver Line Overrun Error or Parity Error or Reading the Line Status Register
Status Framing Error or Break Interrupt
0 1 0 0 Second Received Data Receiver Data Available or Trigger Reading the Receiver Buffer Register
Available Level Reached or the FIFO Drops Below the Trigger
Level
1 1 0 0 Second Character Timeout No Characters Have Been Reading the Receiver
Indication Removed From or Input to the
RCVR FIFO During the Last 4
Char. Times and There Is at Least
1 Char. in It During This Time
0 0 1 0 Third Transmitter Transmitter Holding Register Empty Reading the IIR Register (if source of
Holding Register interrupt) or Writing into the
Empty Transmitter Holding Register
0 0 0 0 Fourth MODEM Status Clear to Send or Data Set Ready or Reading the MODEM Status Register
Ring Indicator or Data Carrier
Detect
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Bit 5: This bit is the Transmitter Holding Register Empty (THRE) indicator. Bit 5 indicates that the UART is ready
to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the CPU
when the Transmit Holding Register Empty Interrupt enable is set high. The THRE bit is set to a logic 1 when a
character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset
to logic 0 concur- rently with the loading of the Transmitter Holding Register by the CPU. In the FIFO mode this
bit is set when the XMIT FIFO is empty; it is cleared when at least 1 byte is written to the XMIT FIFO.
Bit 6: This bit is the Transmitter Empty (TEMT) indicator. Bit 6 is set to a logic 1 whenever the Transmitter
Holding Regis- ter (THR) and the Transmitter Shift Register (TSR) are both empty. It is reset to a logic 0
whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the
transmitter FIFO and shift register are both empty.
Bit 7: In the 16450 Mode this is a 0. In the FIFO mode LSR7 is set when there is at least one parity error,
framing error or break indication in the FIFO. LSR7 is cleared when the CPU reads the LSR, if there are no
subsequent errors in the FIFO.
NOTE
The Line Status Register is intended for read operations only. Writing to this register is not
recommended as this operation is only used for factory testing. In the FIFO mode the
software must load a data byte in the Rx FIFO through Loopback Mode in order to write to
LSR2–LSR4. LSR0 and LSR7 can’t be written to in FIFO mode.
8.6.4 FIFO Control Register
This is a write only register at the same location as the IIR (the IIR is a read only register). This register is used
to en- able the FIFOs, clear the FIFOs, set the RCVR FIFO trigger level, and select the type of DMA signalling.
Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR FIFOs. Resetting FCR0 will clear all bytes in both
FIFOs. When changing from the FIFO Mode to the 16450 Mode and vice versa, data is automatically cleared
from the FIFOs. This bit must be a 1 when other FCR bits are written to or they will not be programmed.
Bit 1: Writing a1 to FCR1 clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is
not cleared. The 1 that is written to this bit position is self-clearing.
Bit 2: Writing a 1 to FCR2 clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is
not cleared. The 1 that is written to this bit position is self-clearing.
Bit 3: Setting FCR3 to a 1 will cause the RXRDY and TXRDY pins to change from mode 0 to mode 1 if FCR0=1
(see description of RXRDY and TXRDY pins).
Bit 4, 5: FCR4 to FCR5 are reserved for future use.
Bit 6, 7: FCR6 and FCR7 are used to set the trigger level for the RCVR FIFO interrupt.
7 6 RCVR FIFO Trigger Level (Bytes)
0 0 01
0 1 04
1 0 08
1 1 14
8.6.5 Interrupt Identification Register
In order to provide minimum software overhead during data character transfers, the UART prioritizes interrupts
into four levels and records these in the interrupt Identification Register. The four levels of interrupt conditions in
order of priority are Receiver Line Status; Received Data Ready; Transmitter Holding Register Empty; and
MODEM Status.
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending
interrupt to the CPU. While this CPU access is occurring, the UART records new interrupts, but does not change
its current indication until the access is complete. Table 1 shows the contents of the IIR. Details on each bit
follow.
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Bit 0: This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending. When
bit 0 is a logic 0, an interrupt is pending and the IIR contents may be used as a pointer to the appropriate
interrupt service routine. When bit 0 is a logic 1, no interrupt is pending.
Bits 1 and 2: These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in
Table 5.
Bit 3: In the 16450 Mode this bit is 0. In the FIFO mode this bit is set along with bit 2 when a timeout interrupt is
pending.
Bits 4 and 5: These two bits of the IIR are always logic 0.
Bits 6 and 7: These two bits are set when FCR0=1.
8.6.6 Interrupt Enable Register
This register enables the five types of UART interrupts. Each interrupt can individually activate the interrupt
(INTR) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the
Interrupt Enable Register (IER). Similarly, setting bits of the IER register to a logic 1, enables the selected
interrupt(s). Disabling an interrupt prevents it from being indicated as active in the IIR and from activating the
INTR output signal. All other system functions operate in their normal manner, including the set- ting of the Line
Status and MODEM Status Registers. Table 1 shows the contents of the IER. Details on each bit follow.
Bit 0: This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set
to logic 1.
Bit 1: This bit enables the Transmitter Holding Register Empty Interrupt when set to logic 1.
Bit 2: This bit enables the Receiver Line Status Interrupt when set to logic 1.
Bit 3: This bit enables the MODEM Status Interrupt when set to logic 1.
Bits 4 through 7: These four bits are always logic 0.
8.6.7 Modem Control Register
This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).
The contents of the MODEM Control Register are indicated in Table 1 and are described below.
Bit 0: This bit controls the Data Terminal Ready (DTR) output. When bit 0 is set to a logic 1, the DTR output is
forced to a logic 0. When bit 0 is reset to a logic 0, the DTR output is forced to a logic 1.
NOTE
The DTR output of the UART may be applied to an EIA inverting line driver (such as the
DS1488) to obtain the proper polarity input at the succeeding MODEM or data set.
Bit 1: This bit controls the Request to Send (RTS) output. Bit 1 affects the RTS output in a manner identical to
that described above for bit 0.
Bit 2: This bit controls the Output 1 (OUT 1) signal, which is an auxiliary user-designated output. Bit 2 affects the
OUT 1 output in a manner identical to that described above for bit 0.
Bit 3: This bit controls the Output 2 (OUT 2) signal, which is an auxiliary user-designated output. Bit 3 affects the
OUT 2 output in a manner identical to that described above for bit 0.
Bit 4: This bit provides a local loopback feature for diagnostic testing of the UART. When bit 4 is set to logic 1,
the following occur the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state; the receiver Serial
Input (SIN) is disconnected; the output of the Transmitter Shift Register is ‘‘looped back’’ into the Receiver Shift
Register input; the four MODEM Control inputs (DSR, CTS, RI, and DCD) are disconnected; and the four
MODEM Control outputs (DTR, RTS, OUT 1, and OUT 2) are internally connected to the four MODEM Control
inputs, and the MODEM Control output pins are forced to their inactive state (high). In the loopback mode, data
that is transmitted is immediately received. This feature allows the processor to verify the transmit-and received-
data paths of the UART.
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In the loopback mode, the receiver and transmitter interrupts are fully operational. Their sources are external to
the part. The MODEM Control Interrupts are also operational, but the interrupts’ sources are now the lower four
bits of the MODEM Control Register instead of the four MODEM Control inputs. The interrupts are still controlled
by the Interrupt Enable Register.
Bits 5 through 7: These bits are permanently set to logic 0.
8.6.8 Modem Status Register
This register provides the current state of the control lines from the MODEM (or peripheral device) to the CPU. In
addition to this current-state information, four bits of the MODEM Status Register provide change information.
These bits are set to a logic 1 whenever a control input from the MODEM changes state. They are reset to logic
0 whenever the CPU reads the MODEM Status Register.
The contents of the MODEM Status Register are indicated in Table 1 and described below.
Bit 0: This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input to the chip has
changed state since the last time it was read by the CPU.
Bit 1: This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the DSR input to the chip has
changed state since the last time it was read by the CPU.
Bit 2: This bit is the Trailing Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the RI input to the chip
has changed from a low to a high state.
Bit 3: This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip
has changed state.
NOTE
Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status Interrupt is generated.
Bit 4: This bit is the complement of the Clear to Send (CTS) input. If bit 4 (loop) of the MCR is set to a 1, this bit
is equivalent to RTS in the MCR.
Bit 5: This bit is the complement of the Data Set Ready (DSR) input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to DTR in the MCR.
Bit 6: This bit is the complement of the Ring Indicator (RI) input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to OUT 1 in the MCR.
Bit 7: This bit is the complement of the Data Carrier Detect (DCD) input. If bit 4 of the MCR is set to a 1, this bit
is equivalent to OUT 2 in the MCR.
8.6.9 Scratchpad Register
This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a scratchpad register to be
used by the programmer to hold data temporarily.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The PC16550D is a Universal Asynchronous Receiver/Transmitter (UART) with integrated transmit and receive
FIFOs.
9.2 Typical Applications
The following sections describe the typical use cases and common implementation practices for this device.
9.2.1 Typical Interface for a High-Capacity Data Bus
Figure 15. Typical Application Schematic
9.2.1.1 Design Requirements
This section lists some critical areas for printed circuit board design consideration and study.
• Be sure to provide adequate power supply decoupling and filtering. These components should be placed as
close to the power pins as possible.
• Ensure that signals fed to the PC1550D do not violate datasheet input min and max specs. To avoid
excursion (over-shoot, or under-shoot), consider implementing series termination resistors. These are
typically on the order of 10 Ωto 33 Ω.
9.2.1.2 Detailed Design Procedure
To begin the design process determine the following:
• Maximum power draw for PCB regulator selection.
• Determine a clocking scheme for the baud rate generator. Either apply a system reference clock or implement
a crystal based clock solution.
• Review datasheet descriptions for each register and plan for the desired device configuration and operating
mode.
Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: PC16550D
TL_C_8652_ 20
TL_C_8652_ 19
PC16550D
www.ti.com
SNLS378C –JUNE 1995–REVISED MAY 2015
9.3 System Examples
9.3.1 Typical Clock Circuits
Table 6. Typical Crystal Oscillator Network(1)
CRYSTAL RP RX2 C1 C2
3.1 MHz 1 MX 1.5k 10-30 pF 40-60 pF
1.8 MHz 1 MX 1.5k 10-30 pF 40-60 pF
(1) These R and C values are approximate and may vary 2x depending on the crystal characteristics. All
crystal circuits should be designed specifically for the system.
10 Power Supply Recommendations
Power supply filtering typically consists of a bulk 22-μF capacitor with an array of 0.1-μF capacitors all placed
near the device. Additional bypass capacitors or capacitors of different values may be required depending on
system conditions.
11 Layout
11.1 Layout Guidelines
For a successful PCB layout, be sure to connect the power pins to power planes. Avoid long, skinny power
traces. Route the parallel data lines and RCLK line as a phased match bus. Use controlled impedance traces for
the serial data nets.
Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: PC16550D
PC16550D
SNLS378C –JUNE 1995–REVISED MAY 2015
www.ti.com
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: PC16550D
PACKAGE OPTION ADDENDUM
www.ti.com 8-Feb-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
PC16550DN LIFEBUY PDIP NFJ 40 9 TBD Call TI Call TI 0 to 70 PC16550DN
PATENTED
PC16550DN/NOPB LIFEBUY PDIP NFJ 40 9 Green (RoHS
& no Sb/Br) Call TI Level-1-NA-UNLIM 0 to 70 PC16550DN
PATENTED
PC16550DV LIFEBUY PLCC FN 44 25 TBD Call TI Call TI 0 to 70 PC16550DV
PATENTED
PC16550DV/NOPB ACTIVE PLCC FN 44 25 Green (RoHS
& no Sb/Br) CU SN Level-3-245C-168 HR 0 to 70 PC16550DV
PATENTED
PC16550DVX LIFEBUY PLCC FN 44 500 TBD Call TI Call TI 0 to 70 PC16550DV
PATENTED
PC16550DVX/NOPB ACTIVE PLCC FN 44 500 Green (RoHS
& no Sb/Br) CU SN Level-3-245C-168 HR 0 to 70 PC16550DV
PATENTED
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Feb-2018
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
N0040A
www.ti.com
N40A (Rev E)
NFJ0040A
www.ti.com
PACKAGE OUTLINE
C
44X -.021.013 -0.530.33[ ]
44X -.032.026 -0.810.66[ ]
TYP
-.695.685 -17.6517.40[ ]
40X .050
[1.27]
-.638.582 -16.2014.79[ ]
.020 MIN
[0.51]
TYP-.120.090 -3.042.29[ ]
.180 MAX
[4.57]
B
NOTE 3
-.656.650 -16.6616.51[ ]
A
NOTE 3
-.656.650 -16.6616.51[ ]
(.008)
[0.2]
4215154/A 04/2017
4215154/A 04/2017
PLCC - 4.57 mm max heightFN0044A
PLASTIC CHIP CARRIER
NOTES:
1. All linear dimensions are in inches. Any dimensions in brackets are in millimeters. Any dimensions in parenthesis are for reference only.
Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension does not include mold protrusion. Maximum allowable mold protrusion .01 in [0.25 mm] per side.
4. Reference JEDEC registration MS-018.
PIN 1 ID
(OPTIONAL)
144
6
18 28
29
39
40
7
17
.004 [0.1] C
.007 [0.18] C A B
SEATING PLANE
SCALE 0.800
www.ti.com
EXAMPLE BOARD LAYOUT
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
44X (.093 )
[2.35]
44X (.030 )
[0.75]
40X (.050 )
[1.27]
(.64 )
[16.2]
(.64 )
[16.2]
(R.002 ) TYP
[0.05]
4215154/A 04/2017
4215154/A 04/2017
PLCC - 4.57 mm max heightFN0044A
PLASTIC CHIP CARRIER
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
SYMM
SYMM
144
6
18 28
29
39
40
7
17
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED) SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
44X (.030 )
[0.75]
44X (.093 )
[2.35]
(.64 )
[16.2]
(.64 )
[16.2]
40X (.050 )
[1.27]
(R.002 ) TYP
[0.05]
PLCC - 4.57 mm max heightFN0044A
PLASTIC CHIP CARRIER
4215154/A 04/2017
PLCC - 4.57 mm max heightFN0044A
PLASTIC CHIP CARRIER
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
SYMM
SYMM
144
6
18 28
29
39
40
7
17
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