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PRELIMINARY DATA
April 2003
STP4NB50
STP4NB50FP
N-CHANNEL 500V - 2.5Ω - 3.8A - TO-220/TO-220FP
PowerMesh™ MOSFET
(1)ISD ≤4A,di/dt≤200A/µs, VDD ≤V(BR)DSS,T
j≤T
JMAX
■TYPICAL RDS(on) = 2.5 Ω
■EXTREMELY HIGH dv/dt CAPABILITY
■100% AVALANCHE TESTED
■VERY LOW INTRINSIC CAPACITANCES
■GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstanding
performances. The new patent pending strip layout
coupled with the Company’s proprieraty edge termi-
nation structure, gives the lowest RDS(on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteris-
tics.
APPLICATIONS
■HIGH CURRENT, HIGH SPEED SWITCHING
■SWITH MODE POWER SUPPLIES (SMPS)
■DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
(•)Pulse width limited by safe operating area
TYPE VDSS RDS(on) ID
STP4NB50
STP4NB50FP 500 V
500 V < 2.8 Ω
< 2.8 Ω3.8 A
2.5 A
Symbol Parameter Value Unit
STP4NB50 STP4NB50FP
VDS Drain-source Voltage (VGS =0) 500 V
VDGR Drain-gate Voltage (RGS =20kΩ)500 V
VGS Gate- source Voltage ±30 V
IDDrain Current (continuous) at TC= 25°C 3.8 2.5 A
IDDrain Current (continuous) at TC= 100°C 2.4 1.6 A
IDM(
)Drain Current (pulsed) 15.2 15.2 A
PTOT Total Dissipation at TC= 25°C 80 35 W
Derating Factor 0.64 0.28 W/°C
dv/dt Peak Diode Recovery voltage slope 4.5 V/ns
VISO Insulation Withstand Voltage (DC) - 2500 V
Tstg Storage Temperature –65 to 150 °C
TjMax. Operating Junction Temperature 150 °C
TO-220
123
123
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
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THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
ON (1)
DYNAMIC
TO-220 TO-220FP
Rthj-case Thermal Resistance Junction-case Max 1.56 3.57 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
TlMaximum Lead Temperature For Soldering Purpose 300 °C
Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tjmax) 3.8 A
EAS Single Pulse Avalanche Energy
(starting Tj= 25 °C, ID=I
AR,V
DD =50V) 220 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source
Breakdown Voltage ID= 250 µA, VGS = 0 500 V
IDSS Zero Gate Voltage
Drain Current (VGS =0) V
DS = Max Rating 1µA
V
DS = Max Rating, TC= 125 °C 50 µA
IGSS Gate-body Leakage
Current (VDS =0) V
GS = ±30V ±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS =V
GS,I
D= 250µA 234V
R
DS(on) Static Drain-source On
Resistance VGS =10V,I
D= 1.9 A 2.5 2.8 Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (1) Forward Transconductance VDS >I
D(on) xR
DS(on)max,
ID= 1.9 A 2.3 S
Ciss Input Capacitance VDS =25V,f=1MHz,V
GS =0 400 pF
Coss Output Capacitance 62 pF
Crss Reverse Transfer
Capacitance 7.5 pF
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ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Delay Time VDD = 250V, ID= 1.9 A
RG=4.7ΩV
GS = 10V
(see test circuit, Figure 3)
11 ns
trRise Time 8 ns
QgTotal Gate Charge VDD = 400V, ID= 3.8 A,
VGS = 10V 15 21 nC
Qgs Gate-Source Charge 6.5 nC
Qgd Gate-Drain Charge 5 nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
tr(Voff) Off-voltage Rise Time VDD = 400V, ID= 3.8 A,
RG= 4.7Ω, VGS =10V
(see test circuit, Figure 5)
8ns
t
f
Fall Time 5 ns
tcCross-over Time 14 ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 3.8 A
ISDM (2) Source-drain Current (pulsed) 15.2 A
VSD (1) Forward On Voltage ISD = 3.8 A, VGS =0 1.6 V
trr Reverse Recovery Time ISD = 3.8 A, di/dt = 100A/µs,
VDD = 100V, Tj= 150°C
(see test circuit, Figure 5)
245 ns
Qrr Reverse Recovery Charge 980 nC
IRRM Reverse Recovery Current 9 A
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Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
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STP4NB50 - STP4NB50FP
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
b 0.61 0.88 0.024 0.034
b1 1.15 1.70 0.045 0.066
c 0.49 0.70 0.019 0.027
D 15.25 15.75 0.60 0.620
E 10 10.40 0.393 0.409
e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F 1.23 1.32 0.048 0.052
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
L 13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154
L20 16.40 0.645
L30 28.90 1.137
øP 3.75 3.85 0.147 0.151
Q 2.65 2.95 0.104 0.116
TO-220 MECHANICAL DATA
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L2
A
B
D
E
H
G
L6
F
L3
G1
123
F2
F1
L7
L4
L5
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
TO-220FP MECHANICA L DATA
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequen ces of u se of such inform ation nor for any in fringeme nt of p atents or o ther righ ts of th ird pa rties which may r esult from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2003 STMicroelectronics - Printed in Italy - All Rights Reserved
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