ESMT Preliminary M53D128168A Mobile DDR SDRAM 2M x 16 Bit x 4 Banks Mobile DDR SDRAM Features z z z z z z z z z z JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. z Differential clock inputs (CLK and CLK ) Quad bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 Special function support PASR (Partial Array Self Refresh) Internal TCSR (Temperature Compensated Self Refresh) DS (Driver Strength) z z z z z z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for READ; center-aligned with data for WRITE Data mask (DM) for write masking only VDD/VDDQ = 1.7V ~ 1.9V Auto & Self refresh 15.6us refresh interval (64ms refresh period, 4K cycle) 1.8V LVCMOS-compatible inputs 60 ball BGA package z z Ordering information : Part NO. MAX FREQ M53D128168A -7.5BG 133MHz M53D128168A -10BG 100MHz M53D128168A -7.5BAG 133MHz M53D128168A -10BAG 100MHz VDD 1.8V PACKAGE COMMENTS 8x10 mm Pb-free BGA Pb-free 8x13 mm Pb-free BGA Pb-free Functional Block Diagram Clock Generator Bank D Bank C Bank B Address Mode Register & Extended Mode Register Row Address Buffer & Refresh Counter Row Decoder CLK CLK CKE Bank A DQS DM WE Elite Semiconductor Memory Technology Inc. Data Control Circuit Input & Output Buffer CAS Column Decoder Latch Circuit RAS Control Logic CS Command Decoder Sense Amplifier Column Address Buffer & Refresh Counter DQ Publication Date : Sep. 2008 Revision : 1.4 1/47 ESMT Preliminary M53D128168A Pin Arrangement 60 Ball BGA (8x10mm) 60 Ball BGA (8x13mm) TOP View TOP View 1 2 3 7 8 9 A VSSQ DQ15 VSS VDD DQ0 VDDQ B DQ14 VDDQ DQ13 DQ2 VSSQ DQ1 1 2 3 7 8 9 A VSS DQ15 VSSQ VDDQ DQ0 VDD B VDDQ DQ13 DQ14 DQ1 DQ2 VSSQ C DQ12 VSSQ DQ11 DQ4 VDDQ DQ3 C VSSQ DQ11 DQ12 DQ3 DQ4 VDDQ D DQ10 VDDQ DQ9 DQ6 VSSQ DQ5 D VDDQ DQ9 DQ10 DQ5 DQ6 VSS E DQ8 VSSQ UDQS LDQS VDDQ DQ7 E VSSQ UDQS DQ8 DQ7 LDQS VDDQ F NC VSS UDM LDM VDD NC F WE CAS LDM VDD CLK NC NC CLK UDM G VSS G H NC CKE CS CLK CLK WE CAS RAS RAS CKE J A11 A9 BA1 BA0 K A8 A7 A0 A10/AP L A6 A5 A2 A1 M A4 VSS VDD A3 H A9 J K A6 VSS A11 A7 A4 NC CS A10/AP A8 A2 A5 BA0 A0 A3 BA1 A1 VDD Pin Description Pin Name A0~A11, BA0,BA1 DQ0~DQ15 Function Pin Name Function Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) LDM, UDM DM is an input mask signal for write data. LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8~DQ15. Data-in/Data-out CLK, CLK RAS Row address strobe CAS Column address strobe WE Write enable VDDQ Supply Voltage for DQ VSS Ground VSSQ Ground for DQ VDD Power NC No connection LDQS, UDQS CKE Clock input CS Clock enable Chip select Bi-directional Data Strobe. LDQS corresponds to the data on DQ0~DQ7; UDQS correspond to the data on DQ8~DQ15. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 2/47 ESMT Preliminary M53D128168A Absolute Maximum Rating Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 2.7 V Voltage on VDD supply relative to VSS VDD -0.5 ~ 2.7 V Voltage on VDDQ supply relative to VSS VDDQ -0.5 ~ 2.7 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operation Condition & Specifications DC Operation Condition Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 C ) Parameter Symbol Min Max Unit Supply voltage VDD 1.7 1.9 V I/O Supply voltage VDDQ 1.7 1.9 V Input logic high voltage VIH (DC) 0.7 x VDDQ VDDQ + 0.3 V Input logic low voltage VIL (DC) -0.3 0.3 x VDDQ V Output logic high voltage VOH (DC) 0.9 x VDDQ - V IOH = -0.1mA Output logic low voltage VOL (DC) - 0.1 x VDDQ V IOL = 0.1mA Input Voltage Level, CLK and CLK inputs VIN (DC) -0.3 VDDQ + 0.3 V Input Differential Voltage, CLK and CLK inputs VID (DC) 0.4 x VDDQ VDDQ + 0.3 V II -2 2 A IOZ -5 5 A Input leakage current Output leakage current Note 1 Notes: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK . . Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 3/47 ESMT Preliminary M53D128168A DC CHARACTERISTICS Recommended operating condition unless otherwise notedTA = 0 to 70 C Parameter Operating Current (One Bank Active) Symbol ICC0 ICC2P Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode ICC2PS ICC2N ICC2NS ICC3P Active Standby Current in power-down mode ICC3PS Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Test Condition tRC= tRC (min), tCK = tCK (min), CKE = High, /CS = High between valid commands, address inputs are switching, data input signals are stable Version -7.5 -10 60 50 All banks idle, CKE = Low, /CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable 0.5 All banks idle, CKE = Low, /CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable 0.5 All banks idle, CKE = Low, /CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable All banks idle, CKE = Low, CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable Unit mA mA mA 28 22 28 22 One bank active, CKE = Low, CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable 5 One bank active, CKE = Low, CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable 2 mA mA mA ICC3N One bank active, CKE = Low, CS = High, tCK = tCK (min), address & control inputs are switching, data input signals are stable 45 35 mA ICC3NS One bank active, CKE = Low, CS = High, tCK = Low, /tCK (min) =High, address & control inputs are switching, data input signals are stable 25 20 mA ICC4R One bank active, BL=4, tCK = tCK (min), continuous read bursts, IOUT = 0 mA, address inputs are switching, 50% data changing each burst 90 75 mA 90 75 mA 75 60 mA One bank active, ICC4W BL=4, tCK = tCK (min), continuous write bursts, IOUT = 0 mA, address inputs are switching, 50% data changing each burst Burst refresh, Refresh Current ICC5 tRC= tRC (min), tCK = tCK (min), CKE = High, address inputs are switching, data input signals are stable Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 4/47 ESMT Self Refresh Current Preliminary ICC6 CKE = Low, CS = High, tck = tck (min), address & control & data inputs are stable Deep Power Down Current ICC7 M53D128168A TCSR range 15 45 70 85 4 Banks 340 360 380 400 2 Bank 290 310 320 350 1 Bank 240 260 280 300 address & control & data inputs are stable 10 C uA uA Note: 1. It has +/- 5 C tolerance. 2. ICC specifications are tested after the device is properly intialized. 3. Definitions for ICC: LOW is defined as V IN 0.1 * V DDQ ; HIGH is defined as V IN 0.9 * V DDQ ; STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. AC Operation Conditions & Timing Specification AC Operation Conditions Parameter Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) 0.8 x VDDQ VDDQ+0.3 V Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) -0.3 0.2 x VDDQ V Input Different Voltage, CLK and CLK inputs VID(AC) 0.6 x VDDQ VDDQ+0.3 V 1 Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.4 x VDDQ 0.6 x VDDQ V 2 Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Input / Output Capacitance (VDD = 1.8V, VDDQ =1.8V, TA = 25 C , f = 1MHz) Parameter Symbol Min Max Unit CIN1 1.5 3.0 pF Input capacitance (CLK, CLK ) CIN2 1.5 3.5 pF Data & DQS input/output capacitance COUT 2.0 4.5 pF Input capacitance (DM) CIN3 2.0 4.5 pF Input capacitance (A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 5/47 ESMT Preliminary M53D128168A AC Operating Test Conditions (VDD = 1.7V~ 1.9V, TA = 0 C to 70 C ) (VDD = 1.8V, VDDQ =1.8V, TA = 25 C , f = 1MHz) Parameter Value Unit 1.0 V/ns 0.8 x VDDQ / 0.2 x VDDQ V Input timing measurement reference level 0.5 x VDDQ V Output timing measurement reference level 0.5 x VDDQ V Input signal minimum slew rate Input levels (VIH/VIL) AC Timing Parameter & Specifications (VDD = 1.7V~1.9V, VDDQ=1.7V~1.9V, TA =0 C to 70 C ) Parameter Symbol CL3 Clock Period CL2 tCK -7.5 -10 min max min max 7.5 - 10 - 12 - 15 - ns Access time from CLK/ CLK tAC 2 7 2 9 ns CLK high-level width tCH 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 tCK Data strobe edge to clock edge tDQSCK 2 7 2 9 ns Clock to first rising edge of DQS delay tDQSS 0.75 1.25 0.75 1.25 tCK Data-in and DM setup time (to DQS) tDS 0.75 - 1.1 - ns Data-in and DM hold time (to DQS) tDH 0.75 - 1.1 - ns DQ and DM input pulse width (for each input) tDS + tDH tDIPW tDS + tDH ns Input setup time (fast slew rate) tIS 2.0 - 2.0 - ns Input hold time (fast slew rate) tIH 1.3 - 1.5 - ns Input setup time (slow slew rate) tIS 2.0 - 2.0 - ns Input hold time (slow slew rate) tIH 1.5 - 1.7 - ns tIPW 3.0 - 3.4 - ns DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 tCK DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 tCK DQS falling edge to CLK rising-setup time tDSS 0.2 - 0.2 - tCK DQS falling edge from CLK rising-hold time tDSH 0.2 - 0.2 - tCK Data strobe edge to output data edge tDQSQ - 0.6 - 0.7 ns tHZ - 6.0 - 7.0 ns tLZ 1.0 - 1.0 - ns Control and Address input pulse width Data-out high-impedance window from CLK/ CLK Data-out low-impedance window from CLK/ CLK Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 6/47 ESMT Preliminary M53D128168A AC Timing Parameter & Specifications-continued Parameter -7.5 Symbol -10 min max min max Half Clock Period tHP tCLmin or tCHmin - tCLmin or tCHmin - ns DQ-DQS output hold time tQH tHPmin-tQHS - tHPmin-tQHS - ns Data hold skew factor tQHS - 0.75 - 1.0 ns ACTIVE to PRECHARGE command tRAS 45 70K 50 70K ns Row Cycle Time tRC 67.5 - 80 - ns AUTO REFRESH Row Cycle Time tRFC 80 - 90 - ns ACTIVE to READ,WRITE delay tRCD 22.5 - 30 - ns PRECHARGE command period tRP 22.5 - 30 - ns Minimum tCKE High/Low time tCKE 2 ACTIVE bank A to ACTIVE bank B command tRRD 15 - 15 - ns Write recovery time tWR 15 - 15 - tCK Write data in to READ command delay tWTR 1 - 1 - tCK Col. Address to Col. Address delay tCCD 1 - 1 - tCK Average periodic refresh interval tREFI - 15.6 - 15.6 us Write preamble tWPRE 0.25 - 0.25 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK tWPRES 0 - 0 - ns Load Mode Register / Extended Mode register cycle time tMRD 2 - 2 - tCK Exit self refresh to first valid command tXSR 120 - 120 - ns Exit power-down mode to first valid command tXP 25 - 25 - ns Autoprecharge write recovery+Precharge time tDAL (tWR/tCK) + (tRP/tCK) - (tWR/tCK) + (tRP/tCK) - ns Clock to DQS write preamble setup time Elite Semiconductor Memory Technology Inc. 2 tCK Publication Date : Sep. 2008 Revision : 1.4 7/47 ESMT Preliminary M53D128168A Command Truth Table COMMAND CKEn-1 CKEn CS RAS CAS WE DM BA0,1 A10/AP A11, A9~A0 Note Register Extended MRS H X L L L L X OP CODE 1,2 Register Mode Register Set H X L L L L X OP CODE 1,2 L L L H X X L H H H H X X X X X Auto Refresh Refresh Entry Self Refresh H Exit Bank Active & Row Addr. H L L H H X L L H H X V H X L H L H X V Read & Column Address Auto Precharge Disable Write & Column Address Auto Precharge Disable Deep Power Down Entry H L L H H L X Exit L H H X X X X H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H Auto Precharge Enable L H L L X V Auto Precharge Enable Burst Stop Precharge X Bank Selection All Banks Active Power Down Precharge Power Down Mode L L H Entry H L Exit L H DM H No Operation Command H X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H X 3 3 3 Row Address H H 3 Column Address Column Address 4 4 4 4,6 X X V L X H 7 X 5 X X X X X V X X X 8 (V = Valid, X = Don't Care, H = Logic High, L = Logic Low) 1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto".. Auto/self refresh can be issued only at all banks precharge state. 4. BA0~BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 8/47 ESMT Preliminary M53D128168A Basic Functionality Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. 2. Start clock and maintain stable condition for a minimum. 3. The minimum of 200us after stable power and clock (CLK, CLK ),apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. 5. Issue 2 or more auto-refresh commands. 6. Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLOCK CKE High level is necessary CS tRFC tRP tRFC tMRD tMRD RAS CAS ADDR Key Key RA BA1 BS BA0 BS A10 /AP RA DQ High-Z WE DQM High level is necessary Precharge Auto Refresh (All Banks) Auto Re fresh Mode Register Set Row Active Extended Mode Register Set : Don't care Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 9/47 ESMT Preliminary M53D128168A Mode Register Definition Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS latency, addressing mode, burst length and various vendor specific options to make Mobile DDR SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written in the power up sequence of Mobile DDR SDRAM. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7~A11 is used for test mode. A7~A11 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A11~ A7 0 0 RFU* A6 A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length A3 Burst Type 0 Sequential 1 Interleave Address Bus Mode Register Burst Length CAS Latency BA1 BA0 0 0 1 0 Operating Mode MRS Cycle EMRS Cycle A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 Reserve Reserve Reserve Reserve A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Latency Sequential Interleave Reserve Reserve 2 2 4 4 8 8 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve * RFU should stay "0" during MRS cycle Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 10/47 ESMT Preliminary M53D128168A Burst Address Ordering for Burst Length Burst Length 2 4 8 Starting Address (A2, A1,A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 Elite Semiconductor Memory Technology Inc. Sequential Mode Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Publication Date : Sep. 2008 Revision : 1.4 11/47 ESMT Preliminary M53D128168A Extended Mode Register Set (EMRS) The extended mode register stores for selecting PASR and DS. The extended mode register set must be done before any active command after the power up sequence. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA1,low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more register). The state of address pins A0~An in the same cycle as CS , RAS , CAS , WE going low is written in the extended mode register. Refer to the table for specific codes. The extended mode register can be changed by using the same command and clock cycle requirements during operations as long as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks refreshed. Internal Temperature Compensated Self Refresh (TCSR) 1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the three temperature range : 15C, 45C, 70C and 85C. 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. 3. It has +/-5C tolerance BA1 BA0 1 0 A11 A10 A9 A8 A7 0 0 0 0 0 A6 A5 A4 A3 DS RFU* A2 A1 A0 PASR Address bus Extended Mode Register Set A2-A0 000 001 PASR 010 011 100 101 111 Self Refresh Coverage 4Bank 2 Bank (BankA& BankB) or (BA1=0) 1 Bank (BankA) or (BA0=BA1=0) R R R R Internal TCSR DS A6-A5 00 01 10 11 Driver Strength Full Strength 1/2 Strength 1/4 Strength R Remark R : Reserved * RFU should stay "0" during EMRS cycle Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 12/47 ESMT Preliminary M53D128168A Precharge The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Burst Selection for Precharge by Bank address bits A10/AP BA1 BA0 Precharge 0 0 0 Bank A Only 0 0 1 Bank B Only 0 1 0 Bank C Only 0 1 1 Bank D Only 1 X X All Banks NOP & Device Deselect The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile DDR SDRAM is put in NOP mode when CS is actived and by deactivating RAS , CAS and WE . For both Deselect and NOP, the device should finish the current operation when this command is issued. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 13/47 ESMT Preliminary M53D128168A Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The Mobile DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Activation Command Cycle ( CAS Latency = 3) 0 1 2 3 4 5 6 CLK CLK Address Bank A Col. Addr. Bank A Row Addr. RAS-CAS delay (tRCD) Command Bank A Activate NOP NOP Bank A Row. Ad dr. Bank B Row Addr. RAS-RAS delay (tRRD) Write A with Auto Prec harge Bank B Activate NOP Bank A Activate ROW Cycle Time (tRC) : Don't Care Read Bank This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command. Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 14/47 ESMT Preliminary M53D128168A Essential Functionality for Mobile DDR SDRAM Burst Read Operation Burst Read operation in Mobile DDR SDRAM is in the same manner as the current Mobile DDR SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by Mobile DDR SDRAM until the burst length is completed. <Burst Length = 4, CAS Latency = 3> 0 CLK 1 2 3 4 5 6 7 8 CLK COMMAND NOP READ A NOP NOP NOP NOP NOP NOP NOP tDQSCK tRPST tRPRE DQS CAS Latency=3 tAC Dout0 Dout1 Dout2 Dout3 DQ's Burst Write Operation The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. <Burst Length = 4> 0 1 2 3 4 5 6 7 8 CLK CLK CO MMA ND NOP W RITEA NOP WRITEB NOP NOP NOP NOP NOP tWR tDQSS(max) DQS tWPREH tWPRES DQ's Din0 Din1 Din2 Din3 Din0 Din1 Din2 Din3 tWR tDQSS(min) DQS tWPREH tWPRES DQ's Din0 D in1 Din2 Din3 Din0 D in1 Din2 Din3 tDS tDH Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 15/47 ESMT Preliminary M53D128168A Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. <Burst Length = 4, CAS Latency = 3> 0 1 2 3 4 5 6 7 8 CLK CLK tCCD(min) COMMAND DQS READ A RE AD B NOP NOP NOP NOP NOP tDQSCK Hi-Z tRPST tRPRE DQ's NOP NOP Hi-Z D o u t A 0 D o u t A 1 D ou t B 0 D o u t B 1 D o u t B 2 D o u t B 3 Read Interrupted by a Write & Burst Stop To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ's(Output drivers) in a high impedance state. To insure the DQ's are tri-stated one cycle before the beginning the write operation, Burt stop command must be applied at least RU(CL) clocks RU means round up to the nearest integer before the Write command. <Burst Length = 4, CAS Latency = 3> CLK 0 1 2 3 4 5 6 7 8 CLK COMMAND READ Burst Stop NOP NOP NOP tRPRE tRPST tWPREH tWPST tW PRES tAC DQ's NOP NOP tDQSS tDQSCK DQS NOP W RITE D ou t 0 D o u t 1 Din 0 Din 1 Din 2 Din 3 tWPRE The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 16/47 ESMT Preliminary M53D128168A Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. <Burst Length = 8, CAS Latency = 3> CLK 0 1 2 3 4 5 6 7 8 CLK 1tCK COMMAND READ Precha rge NOP NOP NOP NOP NOP NOP NOP tDQSCK DQS tRPRE tAC DQ's D ou t 0 D ou t 1 D o ut 2 D o ut 3 D ou t 4 D ou t 5 Do ut 6 D o ut 7 Interrupted by precharge When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 17/47 ESMT Preliminary M53D128168A Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. <Burst Length = 4> 0 CLK 1 2 3 4 5 6 7 8 CL K 1tCK C OMM AN D N OP WR IT E A WR IT E B N OP NO P N OP NO P N OP N OP D QS D Q's D in A 0 D in A 1 Di n B 0 D in B 1 Di n B 2 D in B 3 tCCD Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 18/47 ESMT Preliminary M53D128168A Write Interrupted by a Read & DM A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. <Burst Length = 8, CAS Latency = 3> 0 CLK 1 2 3 4 5 6 7 8 CLK COMMAND NOP NOP W RITE tDQSS(max) DQS NOP NOP READ NOP NOP NOP tCDLR Hi-Z 5) tWPRES DQ's H i- Z Dina0 Dina1 Dina2 Dina3 Dina4 D ina5 Dina6 Dina7 Dout0 Dout1 DM tDQSS(min) DQS tCDLR Hi-Z 5) tWPRES DQ's Hi-Z Dina0 Dina1 D ina2 Dina3 Dina4 Dina5 Dina6 D ina7 Dout0 Dout1 DM The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation. 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM. 5. It is illegal for a Read command interrupt a Write with autoprecharge command. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 19/47 ESMT Preliminary M53D128168A Write Interrupted by a Precharge & DM A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. <Burst Length = 8> 0 CLK 1 2 3 4 5 6 7 8 CLK CO MMAND W RITE A NOP NOP NOP NOP t DQ SS(max) DQS Hi-Z DQ's H i- Z NOP tWR PrechargeA NOP W RITE B tDQSS(max) tWPREH tWPREH tWPRES tWPRES Dina0 Dina1 Dina2 Dina3 Dinb0 DM tDQS S(min) DQS tWR tWPRES tWPREH DQ's t DQSS(min) Hi-Z Hi-Z Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 tWPRES tWPREH Dinb0 Dinb1 DM Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow "Write recovery" which is the time required by a Mobile DDR SDRAM core to properly store a full "0" or "1" level before a Precharge operation. For Mobile DDR SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the Mobile DDR SDRAM, the data path is eventually synchronizes with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that strobes in the precharge command. 1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 20/47 ESMT Preliminary M53D128168A Burst Stop The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation. <Burst Length = 4, CAS Latency = 3 > 0 1 2 3 4 5 6 7 8 CLK CLK CO MMAND READ A Burst Stop NOP NOP NOP NOP NOP NOP NOP The burst read ends after a deley equal to the CAS lantency. DQS Hi-Z DQ's Hi-Z D out 0 Dout 1 The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required. 1. 2. 3. 4. 5. 6. The BST command may only be issued on the rising edge of the input clock, CLK. BST is only a valid command during Read burst. BST during a Write burst is undefined and shall not be used. BST applies to all burst lengths. BST is an undefined command during Read with autoprecharge and shall not be used. When terminating a burst Read command, the BST command must be issued LBST ( "BST Latency") clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s). Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 21/47 ESMT Preliminary M53D128168A DM masking The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe. <Burst Length = 8> 0 CLK 1 2 3 4 5 6 7 8 CLK CO MMAND NOP NOP WRITE NOP NOP NOP NOP NOP NOP tDQSS DQS Hi-Z tWPRES tWPREH DQ's Hi-Z D ina0 D ina1 D ina2 Dina3 Dina4 Dina5 D ina6 Dina7 DM masked by DM=H Read With Auto Precharge If a read with auto-precharge command is initiated, the Mobile DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (tRP) has been satisfied <Burst Length = 4, CAS Latency = 3> CLK 0 1 2 3 4 5 6 7 9 8 10 CLK CO MMAND Bank A ACTIVE NOP NOP NOP Read A Aut o Precharge NOP NOP NOP NOP tRP DQS DQ's NOP NOP Bank can be reactivated at completion of tRP 1) Hi-Z Dout 0 Dout 1 Dout 2 Dout 3 Hi-Z Auto-Precharge starts Note : At burst read / write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 22/47 ESMT Preliminary M53D128168A Write with Auto Precharge If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). <Burst Length = 4> 0 1 2 3 4 5 6 7 8 CLK CLK COMMAND Bank A ACTIVE NOP W rite A A uto Pr echar ge NOP NOP NOP NOP NOP NOP DQS *Bank can be reactivated at completion of tRP DQ's D IN 0 DIN 1 DIN 2 D IN 3 tWR tRP Internal precharge s tar t Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). A maximum of eight consecutive AUTO REFRSH commands (with tRFCmin) can be posted to any given Mobile DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6 m. CLK CLK CO MMA ND Auto Refr esh PRE CMD CKE = High tRP Elite Semiconductor Memory Technology Inc. tRFC Publication Date : Sep. 2008 Revision : 1.4 23/47 ESMT Preliminary M53D128168A Self Refresh A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSRD for locking of DLL. CLK CLK COMMAND NOP Self Ref resh NOP NOP NOP NOP Active NOP tXSR(min) CKE tIS tIS Power Down The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set in high for at least tPDEX prior to Row active command. Refresh operations cannot be performed during power down mode, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device. CLK CLK tPDEX CKE tIS CO MMAND tIS Precharge tIS tIS Active E n t e r P re c h a rg e p o w e r- d o wn mode Elite Semiconductor Memory Technology Inc. Enter Precharge p o w e r -d o wn mode Read E n t e r Ac ti v e p o we r- d o wn mode Enter Active p o w e r -d o wn mo de Publication Date : Sep. 2008 Revision : 1.4 24/47 ESMT Preliminary M53D128168A Functional Truth Table. Current IDLE ROW ACTIVE Address Command Action CS RAS CAS WE H X X X X DESEL NOP L H H H X NOP NOP L H H L BA Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A10 PRE / PREA NOP*4 L L L H X Refresh AUTO-Refresh*5 L L L L Op-Code Mode-Add MRS Mode Register Set*5 H X X X X DESEL NOP L H H H X NOP NOP L H H L BA Burst Stop NOP L H L H BA, CA, A10 READ / READA Begin Read, Latch CA, Determine Auto -precharge L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA, Determine Auto -precharge L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE / PREA Precharge/Precharge All L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA Burst Stop Terminate Burst L H L H BA, CA, A10 READ / READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminate Burst, Precharge L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL READ Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 25/47 ESMT Current State WRITE READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE Preliminary Address M53D128168A Command Action CS RAS CAS WE H X X X X DESEL NOP (Continue Burst to end) L H H H X NOP NOP (Continue Burst to end) L H H L BA Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge*3 L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminal Burst Precharge L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to end) L H H H X NOP NOP (Continue Burst to end) L H H L BA Burst Stop ILLEGAL L H L H BA, CA, A10 READ READ*7 L H L L BA, CA, A10 WRITE ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA Burst Stop ILLEGAL L H L H BA, CA, A10 READ ILLEGAL L H L L BA, CA, A10 WRITE Write L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL Elite Semiconductor Memory Technology Inc. With DM=High, Publication Date : Sep. 2008 Revision : 1.4 26/47 ESMT Current State PRE-CHARGIN G ROW ACTIVATING WRITE RECOVERING Preliminary Address M53D128168A Command Action CS RAS CAS WE H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L BA Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP) L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL H X X X X DESEL NOP (ROW Active after tRCD) L H H H X NOP NOP (ROW Active after tRCD) L H H L BA Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL H X X X X DESEL NOP L H H H X NOP NOP L H H L BA Burst Stop ILLEGAL*2 L H L H BA, CA, A10 READ ILLEGAL*2 L H L L BA, CA, A10 WRITE WRITE L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 27/47 ESMT Current State RE-FRESHING MODE REGISTER SETTING Preliminary Address M53D128168A Command Action CS RAS CAS WE H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L BA Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L BA Burst Stop ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code Mode-Add MRS ILLEGAL ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don't Care BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL of any bank is not idle. 6. Same bank's previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be performed. 7. Refer to "Read with Auto Precharge: for more detailed information. ILLEGAL = Device operation and / or data integrity are not guaranteed. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 28/47 ESMT Current State SELF-REFRESHING* 1 POWER DOWN DEEP POWER DOWN ALL BANKS IDLE*2 Preliminary M53D128168A CKE n-1 CKE n CS RAS CAS WE Add H X X X X X X INVALID L H H X X X X Exit Self-Refresh L H L H H H X Exit Self-Refresh L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X H X X X X X X INVALID L H X X X X X Exit Power Down L L X X X X X NOP (Maintain Power Down) H X X X X X X INVALID L H H X X X X Exit Deep Power Down *3 L L X X X X X NOP (Maintain Deep Power Down) H H X X X X X Refer to Function True Table H L L L L H X Enter Self-Refresh H L H X X X X Exit Power Down H L L H H H X Exit Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L L L X X X X Refer to Current State = Power Down H H X X X X X Refer to Function True Table X Action NOP (Maintain Self-Refresh) ANY STATE other than listed above ABBREVIATIONS : H = High Level, L = Low level, V = Valid, X = Don't Care Note : 1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from All Bank Idle state. 3. The Deep Power Down mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down mode. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 29/47 ESMT Preliminary M53D128168A Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3) tCH tCL tCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK CLK HIGH CKE tIS CS tIH RAS CAS BA0,BA1 BAa A1 0/AP Ra ADDR (A0~An) Ra BAb BAa tDQSS Ca Cb WE tDQSS tRPST tRPRE Hi-Z DQS tWPRES tDQSCK DQ Hi-Z Qa0 tAC tDSC tDQSL tWPST Hi-Z Qa1 Qa2 Qa3 Db0 H i-Z Hi-Z tDQSH tWPREH Db1 Db2 Db3 H i-Z t D St D H tQHS DM CO MMA ND Active READ WRITE Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 30/47 ESMT Preliminary M53D128168A Multi Bank Interleaving READ (@BL=4, CL=3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAb A 10/AP Ra Rb ADDR (A0~An) Ra Rb BAa BAb Ca Cb WE tRRD tCCD DQS Hi-Z DQs Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 DM tRCD CO MMA ND ACTIVE ACTIVE Elite Semiconductor Memory Technology Inc. READ READ Publication Date : Sep. 2008 Revision : 1.4 31/47 ESMT Preliminary M53D128168A Multi Bank Interleaving WRITE (@BL=4) 0 1 2 3 4 5 6 7 8 9 10 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAb A10/AP Ra Rb ADDR (A0~An) Ra BAa BAb tRCD tRRD Rb Ca Cb WE DQS DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM tRCD CO MMAND ACTIVE ACTIVE Elite Semiconductor Memory Technology Inc. READ READ Publication Date : Sep. 2008 Revision : 1.4 32/47 ESMT Preliminary M53D128168A Read with Auto Precharge (@BL=8) 0 1 2 3 4 5 6 7 8 9 10 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAa A10/AP Ra ADDR (A 0~A n) Ca Ra WE Auto prechar ge start tRP 1) No te DQS(CL=3) DQ(CL=3) Hi-Z Qa0 H i-Z Qa1 Qa2 Qa3 Qa4 Qa 5 Qa6 Qa7 DM CO MMAND Note 1. ACTIVE READ The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 33/47 ESMT Preliminary M53D128168A Write with Auto Precharge (@BL=8) CLK 0 1 2 3 4 5 6 7 8 9 10 CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAa A10/AP ADDR (A0~An) Ra Ca Ra WE tD AL Auto prechar ge s tart tWR Note1 tRP DQS DQ Da0 Da1 Da2 Da3 Da 4 Da5 Da6 Da7 DM CO MMAND Note 1. ACTIVE WRITE The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 34/47 ESMT Preliminary M53D128168A Read Interrupted by Precharge (@BL=8) . 0 1 2 3 4 5 6 7 8 9 10 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAa A10/AP ADDR (A0~An) Ca WE DQS Hi-Z DQs Hi-Z 2 Qa 0 Qa1 Qa2 tCK Qa3 Valid Qa4 Qa5 DM COMMAND READ Elite Semiconductor Memory Technology Inc. PRE CHARGE Publication Date : Sep. 2008 Revision : 1.4 35/47 ESMT Preliminary M53D128168A Read Interrupted by a Read (@BL=8, CL=3) 0 1 2 3 4 5 6 7 8 9 10 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAb Ca Cb A10/AP ADDR (A0~An) WE DQS Hi-Z DQs Hi-Z Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 DM CO MMAND READ READ Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 36/47 ESMT Preliminary M53D128168A Read Interrupted by a Write & Burst stop (@BL=8, CL=3) 0 1 2 3 4 5 6 7 8 9 10 CLK CLK H IGH CKE CS RAS CAS BA0,BA1 BAa BAb Ca Cb A10/AP ADDR (A0~An) WE DQS Hi-Z DQs Hi-Z Qa0 Db0 Qa1 Db1 Db2 Db3 Db4 Db5 Db6 Db7 DM CO MMAND READ Elite Semiconductor Memory Technology Inc. Burst Stop WRITE Publication Date : Sep. 2008 Revision : 1.4 37/47 ESMT Preliminary M53D128168A Write followed by Precharge (@BL=4) 0 1 2 3 4 5 6 7 8 9 10 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAa A1 0 / A P ADDR (A0~ An) Ca WE tWR DQS Da0 DQ Da1 Da2 Da3 DM COMMAND WRITE Elite Semiconductor Memory Technology Inc. PRE CHARGE Publication Date : Sep. 2008 Revision : 1.4 38/47 ESMT Preliminary M53D128168A Write Interrupted by Precharge & DM (@BL=8) 0 1 2 3 4 0 1 2 3 4 5 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAa BAb BAc Cb Cc A10/AP ADDR (A0~An) Ca WE DQS Da0 DQ Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Dc0 Dc1 Dc2 Dc3 DM tWR CO MMAND WRITE Elite Semiconductor Memory Technology Inc. tCCD PRE CHARGE WRITE WRITE Publication Date : Sep. 2008 Revision : 1.4 39/47 ESMT Preliminary M53D128168A Write Interrupted by a Read (@BL=8, CL=3) 0 1 2 3 4 5 6 7 8 9 10 CLK CLK HIGH CKE CS RAS CAS BA0,BA1 BAa BAb Ca Cb A10/AP ADDR (A0~An) WE DQS DQ Hi- Z Hi-Z Da0 Da1 Da2 Da3 Da4 Da5 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Maskecd by DM DM tCDLR CO MMAND WRITE Elite Semiconductor Memory Technology Inc. READ Publication Date : Sep. 2008 Revision : 1.4 40/47 ESMT Preliminary M53D128168A DM Function (@BL=8) only for write 0 1 2 3 4 5 6 7 8 9 10 CLK CLK HIG H CKE CS RAS CAS BA0,BA1 BAa A10/AP ADDR (A0~An) Ca WE DQS(CL=3) DQ(CL=3) Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 DM CO MMAND WRITE Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 41/47 ESMT Preliminary M53D128168A Deep Power Down Mode Entry & Exit Cycle Note : DEFINITION OF DEEP POWER MODE FOR Mobile DDR SDRAM : Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the device exits from Deep Power Down Mode. TO ENTER DEEP POWER DOWN MODE 1) 2) 3) The deep power down mode is entered by having CS and held low with RAS and CAS high at the rising edge of the clock. While CKE is low. Clock must be stable before exited deep power down mode. Device must be in the all banks idle state prior to entering Deep Power Down mode. TO EXIT DEEP POWER DOWN MODE 4) The deep power down mode is exited by asserting CKE high. 5) In case of 2/CS, 2CKE device with 2/CS & 2CKE, 200s wait tine is required even if only 1 device exits from Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 42/47 ESMT Preliminary M53D128168A Mode Register Set 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CLK HIGH CKE CS RAS CAS WE BA0,BA1 KEY A10/AP KEY ADDRESS KEY KEY ADDR (A0~An) Hi-Z DQS tRP tMRD DQs Hi-Z DM CO MMA ND Precharge Command All Bank Any Command MRS Co mmand Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 43/47 ESMT Preliminary PACKING DIMENSIONS 60-BALL DDR SDRAM Symbol ( 8x10 mm ) Dimension in mm Min Norm Max A 1.00 A1 0.25 0.30 0.35 A2 0.66 b 0.35 0.40 0.45 D 7.95 8.00 8.05 E 9.95 10.00 10.05 D1 6.40 BSC E1 7.20 BSC e 0.80 BSC Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. M53D128168A Dimension in inch Min Norm Max 0.039 0.010 0.012 0.014 0.026 0.014 0.016 0.018 0.313 0.315 0.317 0.392 0.394 0.396 0.252 BSC 0.283 BSC 0.031 BSC Publication Date : Sep. 2008 Revision : 1.4 44/47 ESMT Preliminary PACKING DIMENSIONS 60-BALL DDR SDRAM Symbol A A1 A2 b D E D1 E1 e e1 M53D128168A ( 8x13 mm ) Dimension in mm Min Norm Max 1.20 0.30 0.35 0.40 0.80 0.40 0.45 0.50 7.90 8.00 8.10 12.90 13.00 13.10 6.40 11.0 0.80 1.00 Dimension in inch Min Norm Max 0.047 0.012 0.014 0.016 0.031 0.016 0.018 0.020 0.311 0.315 0.319 0.508 0.512 0.516 0.252 0.433 0.031 0.039 Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 45/47 ESMT Preliminary M53D128168A Revision History Revision Date 1.0 2007.11.16 Original 1.1 2008.01.02 1. Change BGA package 2. Modify tIS 1.2 2008.01.16 Add 8x10mm BGA package 1.3 2008.06.13 1. Move Revision History to the last 2. Modify tIS 1.4 2008.09.01 Modify the arrangement of 60 Ball BGA (ball F1 : VREF => NC) Elite Semiconductor Memory Technology Inc. Description Publication Date : Sep. 2008 Revision : 1.4 46/47 ESMT Preliminary M53D128168A Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008 Revision : 1.4 47/47