ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 1/47
Control Logic
DM
DQ
Mode Register &
Extended Mode
Register
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Sense Amplifier
Column Decoder
Data Control Circuit
Input & Output
Buffer
Address
Clock
Generator
CLK
CLK
CKE
CS
RAS
CAS
WE
DQS
Mobile DDR SDRAM 2M x 16 Bit x 4 Banks
Mobile DDR SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data
access per clock cycle
z Bi-directional data strobe (DQS)
z No DLL; CLK to DQS is not synchronized.
z Differential clock inputs (CLK and CLK )
z Quad bank operation
z CAS Latency : 2, 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z Special function support
- PASR (Partial Array Self Refresh)
- Internal TCSR (Temperature Compensated Self
Refresh)
- DS (Driver Strength)
z All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
z Data mask (DM) for write masking only
z VDD/VDDQ = 1.7V ~ 1.9V
z Auto & Self refresh
z 15.6us refresh interval (64ms refresh period, 4K cycle)
z 1.8V LVCMOS-compatible inputs
z 60 ball BGA package
Ordering information :
Part NO. MAX FREQ VDD PACKAGE COMMENTS
M53D128168A -7.5BG 133MHz Pb-free
M53D128168A -10BG 100MHz
8x10 mm
BGA Pb-free
M53D128168A -7.5BAG 133MHz Pb-free
M53D128168A -10BAG 100MHz
1.8V
8x13 mm
BGA Pb-free
Functional Block Diagram
Bank A
Command Decoder
Bank D
Latch Circuit
Bank B
Bank C
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 2/47
Pin Arrangement
60 Ball BGA (8x10mm) 60 Ball BGA (8x13mm)
TOP View TOP View
VSS
VSS
A
B
C
D
E
F
G
H
J
K
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CLK
A11
A7
A4
VSSQ
DQ14
DQ12
DQ10
NC
CLK
NC
A8
A5
VDD
VDDQ
DQ1
DQ3
DQ5
NC
WE
CS
A10/AP
A2
DQ0
LDQS
CAS
BA0
A3
123 789
VDDQ
VSSQ
VDDQ
VSSQ
A6
CKE
A9
VSS
DQ7
DQ2
DQ4
DQ6
LDM
A0
VSSQ
VDDQ
VSS
VDDQ
VDD
RAS
BA1
A1
VDD
DQ8
VSSQ
DQ14
DQ12
DQ10
DQ8
NC
A
B
C
D
E
F
G
H
J
K
L
M
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
NC
A11
A8
A6
A4
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CLK
CKE
A9
A7
A5
VSS
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
VDD
DQ2
DQ4
DQ6
LDQS
LDM
WE
RAS
BA1
A0
A2
VDD
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
123 789
Pin Description
Pin Name Function Pin Name Function
A0~A11,
BA0,BA1
Address inputs
- Row address A0~A11
- Column address A0~A8
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
LDM, UDM
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
DQ0~DQ15 Data-in/Data-out CLK, CLK Clock input
RAS Row address strobe CKE Clock enable
CAS Column address strobe CS Chip select
WE Write enable VDDQ Supply Voltage for DQ
VSS Ground VSSQ Ground for DQ
VDD Power NC No connection
LDQS, UDQS
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 3/47
Absolute Maximum Rating
Parameter Symbol Value Unit
Voltage on any pin relative to VSS V
IN, VOUT -0.5 ~ 2.7 V
Voltage on VDD supply relative to VSS V
DD -0.5 ~ 2.7 V
Voltage on VDDQ supply relative to VSS V
DDQ -0.5 ~ 2.7 V
Storage temperature TSTG -55 ~ +150 C°
Power dissipation PD 1.0 W
Short circuit current IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 C°)
Parameter Symbol Min Max Unit Note
Supply voltage VDD 1.7 1.9 V
I/O Supply voltage VDDQ 1.7 1.9 V
Input logic high voltage VIH (DC) 0.7 x VDDQ VDDQ + 0.3 V
Input logic low voltage VIL (DC) -0.3 0.3 x VDDQ V
Output logic high voltage VOH (DC) 0.9 x VDDQ - V IOH = -0.1mA
Output logic low voltage VOL (DC) - 0.1 x VDDQ V IOL = 0.1mA
Input Voltage Level, CLK and CLK inputs VIN (DC) -0.3 VDDQ + 0.3 V
Input Differential Voltage, CLK and CLK inputs VID (DC) 0.4 x VDDQ V
DDQ + 0.3 V 1
Input leakage current II -2 2
μA
Output leakage current IOZ -5 5
μA
Notes:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 4/47
DC CHARACTERISTICS
Recommended operating condition unless otherwise notedTA = 0 to 70 C°
Version
Parameter Symbol Test Condition -7.5 -10 Unit
Operating Current
(One Bank Active) ICC0
tRC= tRC (min), tCK = tCK (min), CKE = High,
/CS = High between valid commands, address
inputs are switching, data input signals are stable
60 50 mA
ICC2P All banks idle,
CKE = Low, /CS = High, tCK = tCK (min), address &
control inputs are switching, data input signals are
stable
0.5
mA
Precharge Standby
Current in power-down
mode ICC2PS All banks idle,
CKE = Low, /CS = High, tCK = Low,
/tCK (min) =High, address & control inputs are
switching, data input signals are stable
0.5 mA
ICC2N
All banks idle,
CKE = Low, /CS = High, tCK = tCK (min), address &
control inputs are switching, data input signals are
stable
28 22
mA
Precharge Standby
Current in non
power-down mode
ICC2NS
All banks idle,
CKE = Low, CS = High, tCK = Low,
/tCK (min) =High, address & control inputs are
switching, data input signals are stable
28 22
mA
ICC3P One bank active,
CKE = Low, CS = High, tCK = tCK (min), address &
control inputs are switching, data input signals are
stable
5
Active Standby Current
in power-down mode
ICC3PS One bank active,
CKE = Low, CS = High, tCK = Low,
/tCK (min) =High, address & control inputs are
switching, data input signals are stable
2
mA
ICC3N
One bank active,
CKE = Low, CS = High, tCK = tCK (min), address &
control inputs are switching, data input signals are
stable
45 35 mA
Active Standby Current
in non power-down
mode
(One Bank Active)
ICC3NS
One bank active,
CKE = Low, CS = High, tCK = Low,
/tCK (min) =High, address & control inputs are
switching, data input signals are stable
25 20 mA
ICC4R
One bank active,
BL=4, tCK = tCK (min), continuous read bursts,
IOUT = 0 mA, address inputs are switching, 50%
data changing each burst
90 75 mA
Operating Current
(Burst Mode)
ICC4W
One bank active,
BL=4, tCK = tCK (min), continuous write bursts,
IOUT = 0 mA, address inputs are switching, 50%
data changing each burst
90 75 mA
Refresh Current ICC5
Burst refresh,
tRC= tRC (min), tCK = tCK (min), CKE = High,
address inputs are switching, data input signals
are stable
75 60 mA
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 5/47
TCSR range 15 45 70 85 C°
4 Banks 340 360 380 400
2 Bank 290 310 320 350
Self Refresh Current ICC6 CKE = Low, CS = High,
tck = tck (min), address &
control & data inputs are
stable
1 Bank 240 260 280 300
uA
Deep Power Down
Current ICC7 address & control & data inputs are stable 10 uA
Note: 1. It has +/- 5 °C tolerance.
2. ICC specifications are tested after the device is properly intialized.
3. Definitions for ICC: LOW is defined as V IN 0.1 * V DDQ ;
HIGH is defined as V
IN 0.9 * V DDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once
per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock
cycle; DM and DQS are STABLE.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter Symbol Min Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) 0.8 x VDDQ V
DDQ+0.3 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) -0.3 0.2 x VDDQ V
Input Different Voltage, CLK and CLK inputs VID(AC) 0.6 x VDDQ V
DDQ+0.3 V 1
Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.4 x VDDQ 0.6 x VDDQ V 2
Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(VDD = 1.8V, VDDQ =1.8V, TA = 25 C° , f = 1MHz)
Parameter Symbol Min Max Unit
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) CIN1 1.5 3.0 pF
Input capacitance (CLK, CLK ) CIN2 1.5 3.5 pF
Data & DQS input/output capacitance COUT 2.0 4.5 pF
Input capacitance (DM) CIN3 2.0 4.5 pF
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 6/47
AC Operating Test Conditions (VDD = 1.7V~ 1.9V, TA = 0 C° to 70 C°)
(VDD = 1.8V, VDDQ =1.8V, TA = 25 C° , f = 1MHz)
Parameter Value Unit
Input signal minimum slew rate 1.0 V/ns
Input levels (VIH/VIL) 0.8 x VDDQ / 0.2 x VDDQ V
Input timing measurement reference level 0.5 x VDDQ V
Output timing measurement reference level 0.5 x VDDQ V
AC Timing Parameter & Specifications
(VDD = 1.7V~1.9V, VDDQ=1.7V~1.9V, TA =0 C° to 70 C°)
-7.5 -10
Parameter Symbol
min max min max
CL3 7.5 - 10 -
Clock Period
CL2
tCK
12 - 15 -
ns
Access time from CLK/ CLK tAC 2 7 2 9 ns
CLK high-level width tCH 0.45 0.55 0.45 0.55 tCK
CLK low-level width tCL 0.45 0.55 0.45 0.55 tCK
Data strobe edge to clock edge tDQSCK 2 7 2 9 ns
Clock to first rising edge of DQS delay tDQSS 0.75 1.25 0.75 1.25
tCK
Data-in and DM setup time (to DQS) tDS 0.75 - 1.1 -
ns
Data-in and DM hold time (to DQS) tDH 0.75 - 1.1 -
ns
DQ and DM input pulse width (for each
input) tDIPW tDS + tDH t
DS + tDH ns
Input setup time (fast slew rate) tIS 2.0 - 2.0 -
ns
Input hold time (fast slew rate) tIH 1.3 - 1.5 -
ns
Input setup time (slow slew rate) tIS 2.0 - 2.0 -
ns
Input hold time (slow slew rate) tIH 1.5 - 1.7 -
ns
Control and Address input pulse width tIPW 3.0 - 3.4 -
ns
DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6
tCK
DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6
tCK
DQS falling edge to CLK rising-setup
time tDSS 0.2 - 0.2 -
tCK
DQS falling edge from CLK rising-hold
time tDSH 0.2 - 0.2 -
tCK
Data strobe edge to output data edge tDQSQ - 0.6 - 0.7 ns
Data-out high-impedance window from
CLK/ CLK tHZ - 6.0 - 7.0 ns
Data-out low-impedance window from
CLK/ CLK tLZ 1.0 - 1.0 - ns
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 7/47
AC Timing Parameter & Specifications-continued
-7.5 -10
Parameter Symbol
min max min max
Half Clock Period tHP tCLmin or tCHmin - tCLmin or tCHmin - ns
DQ-DQS output hold time tQH tHPmin-tQHS - tHPmin-tQHS - ns
Data hold skew factor tQHS - 0.75 - 1.0 ns
ACTIVE to PRECHARGE
command tRAS 45 70K 50 70K ns
Row Cycle Time tRC 67.5 - 80 - ns
AUTO REFRESH Row Cycle
Time tRFC 80 - 90 - ns
ACTIVE to READ,WRITE
delay tRCD 22.5 - 30 - ns
PRECHARGE command
period tRP 22.5 - 30 - ns
Minimum tCKE High/Low time tCKE 2 2 tCK
ACTIVE bank A to ACTIVE
bank B command tRRD 15 - 15 - ns
Write recovery time tWR 15 - 15 - tCK
Write data in to READ
command delay tWTR 1 - 1 - tCK
Col. Address to Col. Address
delay tCCD 1 - 1 - tCK
Average periodic refresh
interval tREFI - 15.6 - 15.6 us
Write preamble tWPRE 0.25 - 0.25 - tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK
Clock to DQS write preamble
setup time tWPRES 0 - 0 - ns
Load Mode Register /
Extended Mode register
cycle time
tMRD 2 - 2 - tCK
Exit self refresh to first valid
command tXSR 120 - 120 - ns
Exit power-down mode to
first valid command tXP 25 - 25 - ns
Autoprecharge write
recovery+Precharge time tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
- ns
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 8/47
Command Truth Table
COMMAND CKEn-1 CKEn CS RAS CAS WE DM BA0,1 A10/AP A11,
A9~A0 Note
Register Extended MRS H X L L L L X OP CODE 1,2
Register Mode Register Set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry
H
L
L L L H X X 3
L H H H 3
Refresh Self
Refresh Exit L H
H X X X
XX 3
Bank Active & Row Addr. H X L L H H X V Row Address
Auto Precharge Disable L 4
Read &
Column
Address Auto Precharge Enable
H X L H L H X V
H
Column
Address 4
Auto Precharge Disable L 4
Write &
Column
Address Auto Precharge Enable
H X L H L L X V
H
Column
Address 4,6
Entry H L L H H L X
Deep Power
Down Exit L H H X X X X
X
Burst Stop H X L H H L X X 7
Bank Selection V L
Precharge All Banks H X L L H L X X H
X
5
H X X X
Entry H L
L V V V
X
Active Power Down
Exit L H X X X X X
X
H X X X
Entry H L
L H H H
X
H X X X
Precharge Power Down
Mode
Exit L H
L V V V
X
X
DM H X V X 8
H X X X
No Operation Command H X L H H H
XX
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 9/47
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK, CLK ),apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
0123456789
CLOCK
CKE
CS
RAS
CAS
ADDR
WE
DQ
DQM
A10/AP
t
RP
Key Key
BA1
BA0
High-Z
Precharge
(All Banks)
Auto Refresh Auto Refresh Mode Register Set
Extended Mode
Register Set
:Don'tcare
t
RFC
t
RFC
High level is necessary
High level is necessary
10 11 12 13 14 15 16 17 18 19 20
RA
BS
BS
RA
Row Active
t
MRD
t
MRD
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 10/47
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS
latency, addressing mode, burst length and various vendor specific options to make Mobile DDR SDRAM useful for variety of
different applications. The default value of the register is not defined, therefore the mode register must be written in the power up
sequence of Mobile DDR SDRAM. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0 (The
Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of
address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7~A11 is used for test mode. A7~A11 must be set to low for normal MRS operation.
Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1 BA0 A11~ A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0 0 RFU* CAS Latency BT Burst Length Mode Register
A3Burst Type
0 Sequential
1 Interleave
Burst Length
CAS Latency Latency
A6 A5 A4 Latency
A2 A1 A0
Sequential Interleave
BA1 BA0 Operating Mode 0 0 0 Reserve 0 0 0 Reserve Reserve
0 0 MRS Cycle 0 0 1 Reserve 0 0 1 2 2
1 0 EMRS Cycle 0 1 0 2 0 1 0 4 4
0 1 1 3 0 1 1 8 8
1 0 0 Reserve 1 0 0 Reserve Reserve
1 0 1 Reserve 1 0 1 Reserve Reserve
1 1 0 Reserve 1 1 0 Reserve Reserve
1 1 1 Reserve 1 1 1 Reserve Reserve
* RFU should stay “0” during MRS cycle
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 11/47
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address (A2, A1,A0) Sequential Mode Interleave Mode
xx0 0, 1 0, 1
2 xx1 1, 0 1, 0
x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
4
x11 3, 0, 1, 2 3, 2, 1, 0
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
8
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 12/47
Extended Mode Register Set (EMRS)
The extended mode register stores for selecting PASR and DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS , RAS , CAS , WE and
high on BA1,low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the
extended more register). The state of address pins A0~An in the same cycle as CS , RAS , CAS , WE going low is written in
the extended mode register. Refer to the table for specific codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as long
as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks
refreshed.
Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control
the self refresh cycle automatically according to the three temperature range : 15°C, 45°C, 70°C and 85°C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
3. It has +/-5°C tolerance
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1 0 0 0 0 0 0 DS RFU* PASR Extended Mode Register Set
A2-A0 Self Refresh Coverage
000 4Bank
001 2 Bank
(BankA& BankB) or (BA1=0)
010 1 Bank
(BankA) or (BA0=BA1=0)
011 R
100 R
101 R
PASR
111 R
Internal TCSR
A6-A5 Driver Strength
00 Full Strength
01 1/2 Strength
10 1/4 Strength
DS
11 R
Remark R : Reserved
* RFU should stay “0” during EMRS cycle
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 13/47
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued.
After tRP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by Bank address bits
A10/AP BA1 BA0 Precharge
0 0 0 Bank A Only
0 0 1 Bank B Only
0 1 0 Bank C Only
0 1 1 Bank D Only
1 X X All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the
control inputs. The Mobile DDR SDRAM is put in NOP mode when CS is actived and by deactivating RAS , CAS and WE .
For both Deselect and NOP, the device should finish the current operation when this command is issued.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 14/47
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock (CLK). The Mobile DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The
Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time
(tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the
same bank. The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the
Bank to Bank delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
Address
01 23 456
Command
Bank A
Row Addr.
Bank A
Row. Addr.
Bank B
Row Addr.
Bank A
Activate NOP Bank B
Activate NOP Bank A
Activate
RAS-CAS delay (
t
RCD
)RAS-RAS delay (
t
RRD
)
ROW Cycle Time (
t
RC
)
:Don'tCare
CLK
CLK
Bank A
Col. Addr.
Write A
with Auto
Precharge
NOP
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 15/47
Essential Functionality for Mobile DDR SDRAM
Burst Read Operation
Burst Read operation in Mobile DDR SDRAM is in the same manner as the current Mobile DDR SDRAM such that the Burst
read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK)
after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of
burst (Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by Mobile DDR
SDRAM until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
01 234 5678
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP
CLK
CLK
CAS Latency=3
DQS
DQ's
Dout0 Dout1 Dout2 Dout3
tRPRE
tDQSCK
tRPST
tAC
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge
enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
WRITEA NOP NOP NOP NOP NOP NOP
t
DQSS(
max)
t
WR
Din0 Din1 Din2 Din3
t
WPRES
CLK
CLK
t
WPREH
NOP
Din0 Din1 Din2 Din3
DQS
DQ's
t
DQSS(
min)
Din0 Din1 Din2 Din3
t
WPRES
t
WPREH
Din0 Din1 Din2 Din3
t
WR
t
DS
t
DH
WRITEB
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 16/47
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4, CAS Latency = 3>
01 234 5678
COMMAND
DQS
DQ's
READ A NOP NOP NOP NOP NOP NOP NOP
Dout A
0
READ B
Dout A
1
Dout B
2
Dout B
3
Dout B
0
Dout B
1
CLK
CLK
t
CCD(min)
t
RPRE
t
DQSCK
Hi-Z
Hi-Z
t
RPST
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks RU means round up to the nearest integer before
the Write command.
<Burst Length = 4, CAS Latency = 3>
01 234 5678
COMMAND
DQS
DQ's
READ NOP NOP NOP NOP NOP
Dout 0
Burst Stop
Din 0
Dout 1
Din 1 Din 2 Din 3
CLK
CLK
NOP WRITE
t
DQSCK
t
RPRE
t
RPST
t
AC
t
WPRE
t
WPRES
t
WPREH
t
DQSS
t
WPST
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write
command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 17/47
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
01 234 5678
COMMAND
DQS
DQ's
READ NOP NOP NOP NOP NOP NOP
Dout 0
Precharge
Dout 1
1t
CK
NOP
Interrupted by precharge
CLK
CLK
Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
t
RPRE
t
DQSCK
t
AC
When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank
before the Read burst is complete. The following functionality determines when a Precharge command may be given during a
Read burst and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after tRP.
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with
autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 18/47
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
NOP NO P NOP NO P NOP NOP
Din A0
WRITE A
Din A1Di n B0Din B1Di n B2Din B3
1tCK
NOP WRITE B
CLK
CLK
tCCD
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 19/47
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered,
any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is
required to avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read
command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock
edge of that of write command.
<Burst Length = 8, CAS Latency = 3>
01 234 5678
COMMAND
DQS
DQ's
DQS
DQ's
NOP NOP NOP NOP READ NOP
t
DQSS(max
)
Dina0 Dina1
WRITE
Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
t
DQSS(min)
DM
Dout0
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
CLK
CLK
DM
NOP NOP
Hi-Z
Hi-Z
t
WPRES
t
CDLR
5)
Hi-Z
Hi-Z
t
CDLR
t
WPRES
5)
Dout1
Dout0 Dout1
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into
the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM.
5. It is illegal for a Read command interrupt a Write with autoprecharge command.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 20/47
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column
access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
01 234 5678
COMMAND
DQS
DQ's
DQS
DQ's
NOP NOP NOP NOP NOP
t
DQSS(max
)
Dina0 Dina1
WRITE A
Dina2 Dina3
t
DQSS(min)
DM
Dinb0
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1
CLK
CLK
DM
PrechargeA
Hi-Z
Hi-Z
t
WPRES
t
WR
Hi-Z
Hi-Z
t
WR
NOP WRITE B
t
WPREH
t
DQSS(max
)
t
WPRES
t
WPREH
t
DQSS(min)
t
WPRES
t
WPREH
t
WPRES
t
WPREH
Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow “Write recovery” which is the time
required by a Mobile DDR SDRAM core to properly store a full “0” or “1” level before a Precharge operation. For Mobile DDR
SDRAM, a timing parameter, tWR, is used to indicate the required of time between the last valid write operation and a Precharge
command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is
sampled by the input clock. Inside the Mobile DDR SDRAM, the data path is eventually synchronizes with the address path by
switching clock domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery
parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock
edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the
time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the
DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where
tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as
the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with
autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command
which does not interrupt the burst.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 21/47
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst
stop command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
01 234 5678
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP
Burst Stop
CLK
CLK
DQS
DQ's
Dout 0 Dout 1
Hi-Z
Hi-Z
The burst read ends after a deley equal to the CAS lantency.
The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST ( “BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 22/47
DM masking
The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When
the data mask is activated (DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data. (DM to
data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
01 234 5678
COMMAND WRITE NOP NOP NOP NOP NOP NOP NOP
CLK
CLK
NOP
DQS
DQ's
tDQSS
DM
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
tWPRES tWPREH
Hi-Z
Hi-Z
mas
k
ed b
y
D
M
=H
Read With Auto Precharge
If a read with auto-precharge command is initiated, the Mobile DDR SDRAM automatically enters the precharge operation BL/2
clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will
be delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
01 234 5678
COMMAND
Bank A
ACTIVE
NOP NOP NOP NOP NOP NOP NOP
Read A
Aut o P rec harge
CLK
CLK
DQS
DQ's
Dout 0 Dout 1 Dout 2 Dout 3
t
RP
910
NOP NOP
Bank can be reactivated at
completion of tRP 1)
Auto-Precharge starts
Hi-Z
Hi-Z
Note : At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 23/47
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
Bank A
ACTIVE NOP NOP NOP NOP NOP NOP NOP
D
IN
0D
IN
1
Write A
Auto Precharge
D
IN
2D
IN
3
*Bank can be reactivated at
completion of t
RP
t
WR
t
RP
Internal precharge start
CLK
CLK
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of
the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the tRFC(min).
A maximum of eight consecutive AUTO REFRSH commands (with tRFCmin) can be posted to any given Mobile DDR SDRAM,
and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6
μm.
COMMAND
CKE = High
t
RP
PRE
Auto
Refresh
CMD
t
RFC
CLK
CLK
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 24/47
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the
self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce
power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than tXSRD for locking of DLL.
COMMAND
CKE
t
XSR(min)
Self
Refresh
Active NOP
t
IS
CLK
CLK
NOP NOP NOP NOP NOP
t
IS
Power Down
The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of
the receiver circuits except CLK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to
entering the precharge power down mode and CKE should be set in high for at least tPDEX prior to Row active command. Refresh
operations cannot be performed during power down mode, therefore the device cannot remain in power down mode longer than
the refresh period(tREF) of the device.
COMMAND
CKE
CLK
CLK
Precharge Read
Enter Precharge
power-down
mode
t
IS
t
IS
t
IS
t
IS
t
PDEX
Active
Enter Precharge
power-down
mode
Enter Active
power-down
mode
Enter Active
power-down
mode
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 25/47
Functional Truth Table.
Current CS RAS CAS WE Address Command Action
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA Active Bank Active, Latch RA
L L H L BA, A10 PRE / PREA NOP*4
L L L H X Refresh AUTO-Refresh*5
IDLE
L L L L Op-Code Mode-Add MRS Mode Register Set*5
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop NOP
L H L H BA, CA, A10 READ / READA Begin Read, Latch CA,
Determine Auto -precharge
L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA,
Determine Auto -precharge
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Precharge/Precharge All
L L L H X Refresh ILLEGAL
ROW ACTIVE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA Burst Stop Terminate Burst
L H L H BA, CA, A10 READ / READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X Refresh ILLEGAL
READ
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 26/47
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Continue Burst to end)
L H H H X NOP NOP (Continue Burst to end)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ/READA
Terminate Burst With DM=High,
Latch CA, Begin Read, Determine
Auto-Precharge*3
L H L L BA, CA, A10 WRITE/WRITEA
Terminate Burst, Latch CA,
Begin new Write, Determine
Auto-Precharge*3
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminal Burst With DM=High,
Precharge
L L L H X Refresh ILLEGAL
WRITE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to end)
L H H H X NOP NOP (Continue Burst to end)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ READ*7
L H L L BA, CA, A10 WRITE ILLEGAL
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
READ with
AUTO
PRECHARGE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ ILLEGAL
L H L L BA, CA, A10 WRITE Write
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
WRITE with
AUTO
PRECHARGE
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 27/47
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ/WRITE ILLEGAL*2
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP)
L L L H X Refresh ILLEGAL
PRE-CHARGIN
G
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (ROW Active after tRCD)
L H H H X NOP NOP (ROW Active after tRCD)
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
ROW
ACTIVATING
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop ILLEGAL*2
L H L H BA, CA, A10 READ ILLEGAL*2
L H L L BA, CA, A10 WRITE WRITE
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
WRITE
RECOVERING
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 28/47
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL
L H L X BA, CA, A10 READ/WRITE ILLEGAL
L L H H BA, RA Active ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X Refresh ILLEGAL
RE-FRESHING
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA Active ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X Refresh ILLEGAL
MODE
REGISTER
SETTING
L L L L Op-Code Mode-Add MRS ILLEGAL
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL of any bank is not idle.
6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be
performed.
7. Refer to “Read with Auto Precharge: for more detailed information.
ILLEGAL = Device operation and / or data integrity are not guaranteed.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 29/47
Current State CKE
n-1
CKE
n CS RAS CAS WE Add Action
H X X X X X X INVALID
L H H X X X X Exit Self-Refresh
L H L H H H X Exit Self-Refresh
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
SELF-REFRESHING*
1
L L X X X X X NOP (Maintain Self-Refresh)
H X X X X X X INVALID
L H X X X X X Exit Power Down
POWER DOWN
L L X X X X X NOP (Maintain Power Down)
H X X X X X X INVALID
L H H X X X X Exit Deep Power Down *3
DEEP POWER
DOWN
L L X X X X X NOP (Maintain Deep Power Down)
H H X X X X X Refer to Function True Table
H L L L L H X Enter Self-Refresh
H L H X X X X Exit Power Down
H L L H H H X Exit Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
ALL BANKS IDLE*2
L L L X X X X Refer to Current State = Power Down
H H X X X X X Refer to Function True Table
ANY STATE other
than listed above
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
Note :
1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be
satisfied before issuing any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
3. The Deep Power Down mode is exited by asserting CKE high and full initialization is required after exiting Deep Power
Down mode.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 30/47
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
ADDR
(A0~An)
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
10
/AP
BAa BAb
t
CK
t
IS
t
IH
t
WPREH
t
DQSS
Qa0 Qa1 Qa2 Qa3
t
DQSS
t
RPST
t
DQSH
t
DQSL
t
WPST
Hi-Z
Hi-Z
READ WRITE
CLK
CLK
t
CL
t
RPRE
t
AC
t
QHS
11 12 13
t
CH
BAa
Ra
Ra Cb
Ca
Hi-Z
Hi-Z
t
DQSCK
Hi-Z
t
DSC
t
WPRES
Db0 Db1 Db3
Db2
Active
Hi-Z
t
DS
t
DH
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 31/47
Multi Bank Interleaving READ (@BL=4, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQs
01 234 5678910
HIGH
DM
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Qb0 Qb1 Qb3
Qb2
ACTIVE
BAb BAa BAb
Ra Rb
Ra
Qa0 Qa1 Qa3
Qa2
ACTIVE READ
t
RCD
READ
t
RRD
t
CCD
Rb
CLK
CLK
11 12 13
Ca Cb
Hi-Z
Hi-Z
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 32/47
Multi Bank Interleaving WRITE (@BL=4)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Db0 Db1 Db3
Db2
ACTIVE
BAb BAa BAb
Ra Rb
Ra Ca Cb
Da0 Da1 Da3
Da2
ACTIVE READ
t
RCD
READ
t
RRD
t
RCD
Rb
CLK
CLK
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 33/47
Read with Auto Precharge (@BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=3)
DQ(CL=3)
01 234 5678910
HIGH
DM
A
10
/AP
ADDR
(A0~An)
BAa
Qa4 Qa5 Qa7
Qa6
BAa
t
RP
Qa0 Qa1 Qa3
Qa2
Ca
Auto precharge start
Note
CLK
CLK
Ra
Ra
Hi-Z
Hi-Z
1)
READ
ACTIVE
COMMAND
Note 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 34/47
Write with Auto Precharge (@BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Da4 Da5 Da7
Da6
t
RP
Da0 Da1 Da3
Da2
ACTIVE
WRITE
Ca
Auto precharge start
Note1
BAa
Ra
Ra
t
WR
CLK
CLK
t
DAL
Note 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 35/47
Read Interrupted by Precharge (@BL=8)
.
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQs
01 234 5678910
HIGH
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Qa0 Qa1
READ
BAa
Ca
PRE
CHARGE
CLK
CLK
Qa2 Qa3 Qa4 Qa5
DM
Hi-Z
Hi-Z
2
t
CK
Valid
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 36/47
Read Interrupted by a Read (@BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQs
01 234 5678910
HIGH
DM
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Qa0 Qa1 Qb1Qb0
READ
Ca
BAb
Cb
Qb2 Qb3 Qb5
Qb4 Qb7
Qb6
READ
CLK
CLK
Hi-Z
Hi-Z
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 37/47
Read Interrupted by a Write & Burst stop (@BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQs
01 234 5678910
HIGH
DM
COMMAND
BAa
Qa0 Qa1
READ
Db0 Db5
Db1 Db4
Db3Db2 Db6
BAb
Cb
Burst
Stop WRITE
Db7
CLK
CLK
A
10
/AP
ADDR
(A0~An) Ca
Hi-Z
Hi-Z
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 38/47
Write followed by Precharge (@BL=4)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa BAa
tWR
Da0 Da1 Da3
Da2
PRE
CHARGE
WRITE
Ca
CLK
CLK
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 39/47
Write Interrupted by Precharge & DM (@BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 012345
HIGH
DM
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa BAa
Da0 Da1 Da3
Da2
PRE
CHARGE
WRITE WRITE WRITE
Ca
CLK
CLK
BAb BAc
Cb Cc
Da4 Da5 Da6 Da7 Db0 Db1 Dc1Dc0 Dc3
Dc2
t
WR
t
CCD
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 40/47
Write Interrupted by a Read (@BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
BAa
t
CDLR
Da0 Da1 Da3
Da2
WRITE READ
Ca
CLK
CLK
BAb
Cb
Da5
Da4 Qb0 Qb1 Qb3
Qb2 Qb4 Qb5
Maskecd by DM
A
10
/AP
ADDR
(A0~An)
Hi-Z
Hi-Z
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 41/47
DM Function (@BL=8) only for write
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=3)
DQ(CL=3)
01 234 5678910
HIGH
DM
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Da4 Da5 Da7
Da6
Da0 Da1 Da3
Da2
WRITE
Ca
CLK
CLK
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 42/47
Deep Power Down Mode Entry & Exit Cycle
Note :
DEFINITION OF DEEP POWER MODE FOR Mobile DDR SDRAM :
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of
the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the
device exits from Deep Power Down Mode.
TO ENTER DEEP POWER DOWN MODE
1) The deep power down mode is entered by having CS and held low with RAS and CAS high at the rising edge of the
clock. While CKE is low.
2) Clock must be stable before exited deep power down mode.
3) Device must be in the all banks idle state prior to entering Deep Power Down mode.
TO EXIT DEEP POWER DOWN MODE
4) The deep power down mode is exited by asserting CKE high.
5) In case of 2/CS, 2CKE device with 2/CS & 2CKE, 200μs wait tine is required even if only 1 device exits from Deep Power
Down.
6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands
and a load mode register sequence.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 43/47
Mode Register Set
CKE
CS
RAS
CAS
ADDR
(A0~An)
Precharge
Command
All Bank
DQS
DQs
MRS
Command
Any
Command
BA0,BA1
A10/AP
WE
DM
ADDRESS KEY
t
RP
CLK
CLK
t
MRD
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
HIGH
KEY
KEY
KEY
Hi-Z
Hi-Z
COMMAND
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 44/47
PACKING DIMENSIONS
60-BALL DDR SDRAM ( 8x10 mm )
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A
1.00
0.039
A1 0.25 0.30 0.35 0.010 0.012 0.014
A2
0.66
0.026
Φb 0.35 0.40 0.45 0.014 0.016 0.018
D 7.95 8.00 8.05 0.313 0.315 0.317
E 9.95 10.00 10.05 0.392 0.394 0.396
D1 6.40 BSC 0.252 BSC
E1 7.20 BSC 0.283 BSC
e 0.80 BSC 0.031 BSC
Controlling dimension : Millimeter.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 45/47
PACKING DIMENSIONS
60-BALL DDR SDRAM ( 8x13 mm )
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A
1.20
0.047
A1 0.30 0.35 0.40 0.012 0.014 0.016
A2
0.80
0.031
Φb 0.40 0.45 0.50 0.016 0.018 0.020
D 7.90 8.00 8.10 0.311 0.315 0.319
E 12.90 13.00 13.10 0.508 0.512 0.516
D1
6.40
0.252
E1
11.0
0.433
e
0.80
0.031
e1
1.00
0.039
Controlling dimension : Millimeter.
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 46/47
Revision History
Revision Date Description
1.0 2007.11.16 Original
1.1 2008.01.02
1. Change BGA package
2. Modify tIS
1.2 2008.01.16 Add 8x10mm BGA package
1.3 2008.06.13
1. Move Revision History to the last
2. Modify tIS
1.4 2008.09.01
Modify the arrangement of 60 Ball BGA (ball F1 : VREF =>
NC)
ESMT
Preliminary M53D128168A
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2008
Revision : 1.4 47/47
Important Notice
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No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time
of publication. ESMT assumes no responsibility for any error in this document,
and reserves the right to change the products or specification in this document
without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
A
ny semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but
not limited to, life support devices or system, where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage. If
products described here are to be used for such kinds of application, purchaser
must do its own quality assurance testing appropriate to such applications.