NS Memory/Clock Drivers MH0026/MHO0O26C 5 MHz two phase MOS clock driver general description The MHO0026/MHOO26C is a low cost. monolithic high speed two phase MOS clock driver and inter- face circuit. Unique circuit design along with advanced processing provide both very high speed operation and the ability to drive large capacitive loads. The device accepts standard TTL/DTL out- puts and converts them to MOS logic levels. It may be driven from standard 54/74 series gates and flip-flops or from drivers such as the DM8830 or DM7440. The MH0026 is intended for applications in which the output pulse width is logically con- trolled: i.e., the output pulse width is equal to the input pulse width, features Fast rise and fall times20 ns with 1000 pF load High output swing20V High output current drive+1.5 amps TTL/DTL compatible inputs High rep rate5 to 10 MHz depending on load = Low power consumption in MOS 0 state 2 mw Drives to 0.4V of GND for RAM address drive The MH0026 is intended to fulfill a wide variety of MOS interface requirements. As a MOS clock driver for long silicon gate shift registers, a single device can drive over 10k bits at 5 MHz. Six devices pro- vide input address and precharge drive for a 8k by 16 bit MM1103 RAM memory system. Information on the correct usage of the MHQ026 in these as well as other systems is included in the application sec- tion starting on page 5. A thorough understanding of its usage will insure optimum performance of the device. The device is available in 8-lead TO-5, one watt copper lead frame 8-pin mini-DIP, and one and a half watt TO-8 packages. connection diagrams Matai Can Package Dual-In-Line Package wi U tNPUT A >+_D--_}? OUTPUT A =a p A nc voi rs. TOP VIEW INPUTB 5 OUTPUT B 7 Note: Pin 4 connected to case. Tor VIEW Order Number MHO026H or MHO026CH See Package 11 Order Number MHO026CN See Package 20 schematic diagram INPUT A, Sy a INPUT B Order Number MH0026G Metal Can Package Flat Package INPUT A LI ne enc WUT A, 3 -_ ourPUT A vey Loy INPUT 4 > I OUTPUT B Nema Ee wc INPUT 8 TOP view Order Number MHO0O26F or MHOO26CF See Package 3 or MHOO26CG See Package 6 eov (1/2 of Circuit Shown} 4 ] < $ R? $ AS 3 RG EXTERNAL 4 a3 Cin a? , DB re eo o 05 q ag INPUT DY RZ Ww to = s R3 02 Wy > fa: x 03 o-0 sutrut 06 08 > | =H ys Ra VW Ny 4 for 05 09 > 2 ns Ag oN 2 oOo 3-31 I9Z00HW/SZ00HWMH0026/MHO0026C absolute maximum ratings V*_V" Differential Voltage 22vV Input Current 100 mA Input Voltage (Vin Vo} 5.5V Peak Output Current 1.5A Power Dissipation See curves Operating Temperature Range MHO0026 -55C to +125C MHO026C 0C to 85C Storage Temperature Range -65C to +150C Lead Temperature (Soldering, 10 sec) 300C de electrical characteristics (Notes 1 & 2) LIMITS PARAMETER CONDITIONS UNITS MIN TYP MAX Logic 1 Input Voltage Vout = V+ 1.0V 2.5 1.5 v Logic 1 Input Current Vin V7 = 2.5V, Vout = V+ 1,0V 10 15 mA Logic 0 Input Voltage Vout = V - 1.0V 0.6 0.4 Vv Logic 0 Input Current Vin - VV = OV, Vour = V* - 1.0V -0.005 -10 HA Logic 0 Output Voltage V* = +5.0V, V = -12.0V Vin = ~-11.6 4.0 4.3 v Logic 0 Output Voltage | Viy - V7 =0.4V vt -1.0| v*-0.7 v Logic 1 Output Voltage Vt =4+5.0V, V7 = -12.0V Vin = -9.5V -11.5 -11.0 v Logic 1' Output Voltage Vin - Vo = 2.5V vo +05 vo +10 Vv ON Supply Current Vt - V7 = 20V, Vin - VO = 2.5V 30 40 mA OFF Supply Current V* - V7 = 20V, Vin - V7 =0.0V 10 100 LA ac electrical characteristics (notes 1 & 2. AC test circuit, T, = 25C) Turn-On Delay (ton) 5.0 75 12 ns Turn-Off Delay (tore) 5.0 12 15 ns Rise time (t,) Note 3 vt VW" =17V, CL = 250 pF 12 ns vt = V7 =17V, C, = 500 pF 15 18 ns C. = 1000 pF 20 35 ns Falltime (t,} Note 3 V* ~V" =17V, C, = 250 pF 10 ns V* - V7 = 17V, CL = 500 pF 12 16 ns C_ = 1000 pF 17 25 ns Note 1: These specifications apply for vt v~ = 10V to 20V, CL = 1000 pF, over the temperature range ~55C to +128C for the MH0026 and 0C to +85C for the MHOOZE6C, unless otherwise specified. Note 2: All typical values for the Ta = 25C. Note 3: Rise and fal! time are given for MOS logic levels; i.e., rise time is transistion from lagic 0"' to lagic 1"' which is voltage fall. See waveforms on the following pages. ac test circuit oureur INPUT Vin = 5V PRE = 1 MHz = | sngens PW = O.8u5 Gq te S10 ns Lom _t 1000 pF a1 uF vr=-2009 > switching time waveformsRISE TIME (ns) TRANSIENT POWER (mW) POWER DISSIPATION (Wy TURN-ON & TURN-OFF TIMES {ns} typical performance characteristics a4 62 800 700 600 500 400 300 200 100 TO-5 & DIP Power Ratings y T y y MHQOZECN SOLDERED TO PL BOARD WITH 8 CU. CONDUCTORS AC 202., 03 1N, WIDE 4 MHOO26H AND MHOOZ6CH 1N STILL AVR WITH CLIP nog ON HEAT SINK NA NL ungz6H & mHoozECH A [SS N IN STILL AIR 25 50 75 100 125 150 AMBIENT TEMPERATURE (C) Transient Power (Pac) vs Frequency =2000 10 2.0 3.0 FREQUENCY (MHz) 40 6.0 Rise Time vs Load Capacitance Vo-Ww=1Vv Ro= 50:2 Ta = 25C Q 200 400 600 800 1000 LDAD CAPACITANCE (pF) 1200 Turn-On & Turn-Off Time vs Temperature view = 20 Cuy = C, = 1000 pF Ro = 5082 ton -75 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 FALL TIME (ns) SUPPLY CURRENT (mA) POWER DISSIPATION (W) RISE TIME (ns) 3.0 25 20 6.5 25 20 25 20 -75 ~50 TO-8 Package Power Rating MH0026G AND MHOOZ6CG IN STILL AIR WITH CLIP-ON HEAT SINK (THERMALLOY TYPE 215-1.9 OR EQUIV.) NO KIN MH0026G AND S MHOO26C6 IN STILL AIR | 25 50 675100 125 150 AMBIENT TEMPERATURE ( C) Supply Current vs Temperature = 20% viv" = 20V vi-v"=17V TEMPERATURE (C) 0 -75 -50 -25 0 25 50 75 100 125 Fall Time vs Load Capacitance vi V7 = 15V to 20V Ro= 5082 Ty = 25C Q 200 400 600 LOAD CAPACITANCE (pF) Rise Time vs Temperature 1000 vi -vo=20V C= 1000 pF ~25 0 TEMPERATURE (C) 25 50 75 100 125 POWER (mW) QUTPUT PULSE WIDTH (ns) INPUT CURRENT (mA) FALE TIME {ns} 400 360 320 280 240 200 160 120 80 40 900 700 600 600 400 300 200 100 -75 -0 -25 @ TEMPERATURE (C) DC Power (Ppc) vs Duty Cycie Ta 28 C C=0 vi~Vvo=20V ve-w=1V Ve -vs12V _ wavy? DEK (DC) Poc 10 20 30 40 50 60 DUTY CYCLE (%) 70 80 Input Current vs Input Voltage Ta=25C vt = 20v vieav 05 1.0 16 2.0 INPUT VOLTAGE (V) 2.5 Optimum Input Capacitance vs Output Pulse Width ve =v" =20V Cy = 1000 pF Ty = 28C 200 400 600 800 1000 1200 ENPUT CAPACITANCE, Cin (PF) Fall Time vs Temperature vi -vo=20V C,. 1000 oF C, = 500 pF 25 50 75 100 125 3-33 I9ZTOOHW/S9Z00HWMH0026/MHO026C typical applications (cont.) AC Coupled MOS Clock Driver +5 o i. 1000 pF 2 7 TWO PHASE mHGO26CN clock To Cy" SHIFT REGISTERS 1006 pF ot }-}+ po 54/74 SERIES GATES AND FLOPS E 17 *See applications section for detailed information on input/output design criterion. DC Coupled RAM Memory Address or Precharge Driver (Positive Supply Onty) HIV 100 pF 6 t 7 mK F TO ADDRESS we MHOO26CN LINES ON Nt} 103 TYPE MEMORY SYSTEM 4 , 1K 1/2 DM7400 i Precharge Driver for MOS RAM Memories ADORESS wet omeoume cOUKTER meut ADDRESS weut aw counreR CONTROL REFRESH A omer2a PaECHARGE MEMORY SELEY areRESH 3-34typical applications OC Coupled MOS Clock Driver eat 1 OUTPUT wet oureuT MH9026CN DHoOsac 4 O.1uF -12V Transistor Coupled MOS Clock Driver TTL INPUTS: { +50 150 150 = 100 9F [>> + TO SHIFT 100 pF REGISTERS > > > < giu g 510 0026 4 = j ~2V Logically Controtled AC Coupled Clock Driver +5V * ln [Rene 4 T C2 400 pF ~ tl SCH TTL cLotk ro \ wneUT = ey etipron tte at 2to 6 a 03.400 pF SHIFT +t +! f 4 5 REGISTER tr iltl . Cy = JIL pMags noozECH 3 TO ADDITIONAL SHIFT REGISTERS 14 zt M0601 I ONE + I SHOT - 3 - | LT AA +. CLOCK INPUT ~ 2 fo -f a E2-f l J l ONE SHOT OUTPUT - ADJ PULSE WIDTH LIL PHASE ONE OUTPUT | a PHASE TWO OUTPUT Lg O1uF >_0 -1v 3-35 IIZTOOHW/S9ZOOHWMH0026/MHO0026C application information 1.0 Introduction The MHOQ026 is capable of delivering 30 watts peak power (1.5 amps at 20V needed to rapidly charge large capacitative loads) while its package is limited to the watt range. This section describes the operation of the circuit and how to obtain optimum system performance. If additional design information is required, please contact your local National field application engineer. 2.0 Theory of Operation Conventional MOS clock drivers like the MHO0013 and similar devices have relied on the circuit configuration in Figure 1. The AC coupling of an input pulse allows the device to work over a wide range of supplies while the output pulse width may be controlled by the time constant R; X C,. Co > EXTERNAL Con 1 a tee FIGURE 1. Convantional MOS Clock Drive D2 provides 0.7V of dead-zone thus preventing Q, and Q, from conducting at the same time. In order to drive large capacitive loads, Q, and Q, are large geometry devices but C,, now limits useful output rise time. A high voltage TTL output stage (Figure 2) could be used; however, during switching until the stored charge is removed from Q,, both output devices conduct at the same time. This is familiar in TTL with supply line glitches in the order of 60 to 100 mA. A clock driver built this way would introduce 1.5 amp spikes into the supply lines. EXTERNAL C1 FIGURE 2, Alternate MOS Clock Drive Unique circuit design and advanced semiconductor processing overcome these clasic problems allow- ing the high volume manufacture of a device, the MH0026, that delivers 1.5A peak output currents with 20ns rise and fall times into TOOOpF loads. In a simplified diagram, 0, (Figure 3) provides 0.7V dead zone so that Qj is turned ON for a rising input pulse and Q, OFF prior to Q, turning ON a few nanoseconds later. Dz prevents zenering of the emitter-base junction of Q2 and provides an initial discharge path for the load via Q3. During a falling input, the stored charge in Q3 is used beneficially to keep Q3 ON thus preventing Q, from conduct- ing until Qy is OFF. Q, stored charge is quickly discharged by means of common-base transistor Q,. The complete circuit of the MHO026 (see sche- matic on page 1) basically makes Darlingtons out of each of the transistors in Figure 3. ve > < 2 he 2 4q a2 EXTERNAL ct Rt our IN + Jo o4 03 ot q > a Re O--0 v- FIGURE 3. Simplified MHO026 When the output of the TTL input element (not shown) goes to the logic 1 state, current is supplied through Ciy to the base of Q, and Q, turning them ON, and Q; and Q, OFF when the input voltages reaches 0.7V. Initial discharge of the load as well as E-B protection for Q3; and Qy are provided by 0, and Dz. When the input voltage reaches about 1.5V, Q, and Q, begin to conduct and the load is rapidly discharged by Q,. As the input goes low, the input side of C,,, goes negative with respect to V~ causing Qg and Qy to conduct momentarily to assure rapid turn-off of Q, and Q, respectively. When Q, and Q, turn OFF, Darlington connected Q3; and Qy, rapidly charge the load toward vt volts. Re assures that the output will reach to within one Veg of the vt supply. The real secret of the device's performance is proper selection of transistor geometries and resis- tor values so that Q, and Q, do not conduct at the same time while minimizing delay from input to output. 3.0 Power Dissipation Considerations There are four considerations power dissipations. 1. Average DC power 2. Average AC power 3. Package and heat sink selection 4, Remember2 drivers per package in determining 3-36application information (cont.) The total average power dissipated by the MH0026 is the sum of the DC power and AC transient power. The total must be less than given package power ratings. P PrcotPoe <P oiss~ ac pc "max Since the device dissipates only 2mMW with output voltage high (MOS logic 0), the dominating factor in average DC power is duty cycle or the percent of time in output voltage low state (MOS logic '1). Percent of total power contributed by Pog is usually neglible in shift register applications where duty cycle is less than 25%. P,,,. dominates in RAM address line driver applications where duty cycle can exceed 50%. 3.1 DC Power (per driver) DC Power is given by: Pog = (VT -V)X (Ig(row)) X ON time (OFF timeON time or P= (Output Low Power) X (Duty Cycle) where: IsrLow) = Ig @ (V7 - V7) Example 1; (V =+5V, V=-12V) a) Duty cycle = 25%, therefore Poco = 17V X 40mA X 17/20 X 25% Pog = 145mW worst-case, each side Poe = 109mW typically b) Duty cycle = 5% Poe = 2imw c) See graph on page 3 The above illustrates that for shift register applica- tions, the minimum clock width allowable for the given type of shift register should be used in order to drive the largest number of registers per clack driver. Example 2: (V = +17V, V7 = GND): a) Duty cycle = 50% Pog = 290mW worst-case D Poco = 218mW typically b) Duty cycle = 100% Pog = S80mW Thus for RAM address line applications, package type and heat sink technique will limit drive capability rather than AC power. 3.2 AC Transient Power (per driver) AC Transient power is given by: =(yt -\2 Pao =(VE-V)EX EXC, where: f = frequency of operation C, = Load capacitance (inciuding all strays and wiring) Example 3: (V* = 45V, V7 =-12V) Pag =17X 17 X (MHz) X 10 X C, (nF) X 107 Ac = 290mW per MHz per 1000pF Thus at SMHz, a 1000pF load will cause any driver to dissipate one and one half watts. For long shift registers, a driver with the highest package power rating will drive the largest number of bits for the towest cost per bit. 3.3 Package Selection Power ratings are based on a maximum junction rating of 175C. The following guidelines are suggested for package selection. Graphs on page 3 illustrate derating for various operating tempera- tures. 3.31 TO-5 (H) Package: Rated at 600mW stil! air (derate at 4.0mW/C above 25C) and 900mW with clip on heat sink (derate at 6.0mW/C above 25C). This popular hermetic package is recom- mended for small systems. Low cost (about 10) clip-on-heat sink increases driving capability by 50%. 3.32 8-Pin (N) Motded Mini-DIP: Rated at GOOmW still air (derate at 4.0mW/C above 25C} and 1.0 watt soldered to PC board (derate at 6.6mW/C). Constructed with a special copper lead frame, this package is recommended for medium size commercial systems particularly where automatic insertion is used. (Please note for prototype work, that this package is only rated at 600mMW when mounted in a socket and not one watt until it is soldered down.) 3.33 TO-8 ("G") Package: Rated at 1.5 watts still air (derate at 10mW/C above 25C) and 2.3 watts with clip on heat sink (Wakefield type 215-1.9 or equivalentderate at 15mW/C), Selected for its power handling capability and moderate cost, this hermetic package will drive very large systems at the towest cost per bit. IIZOOHW/9ZOOHWMH0026/MHOO026C application information (cont.) 3.4 SummaryPackage Power Considerations The maximum capacitative load that the MHO026 can drive is thus determined by package type, heat sink technique, ambient temperature, AC power (which is proportional to frequency and capacitive load) and DC power {which is principally deter- mined by duty cycle}. Combining equations pre- viously given, the following formula is valid for any clock driver with negligible input power and negligible power in output high state: 3 Cy (max in pF) = o x Pnaximw)(Ta-Pkg) X Raq ~ (Wt ~ V7)? X (De) X 109 (VT -V7)? X Reg X f(MHz) or: Cy (max in pF) = .5 X 1073 x Pinax(MW} X 500 - Vg? X De X 10 Vg X S00 X f(MHz) Where: n = number of drivers per pkg. (2 for the MH0026) Prax(mw)'la, Pkg) = Package power rating in milliwatts for given package, heat sink, and max, ambient tempera- ture (See graphs) R eq W equivalent internal resistance R " eq 7 (VT - VV lecy ow) = 500 ohms (worst case over temperature for the MH0026 or 660 ohms typically} Vs = (vt ~ V7) = total supply voltage across device Dc = Duty Cycle = Time in output iow state Time in output low + Time in output high state Table | illustrates MHO026 drive capability under various system conditions, 4.0 Pulse Width Control The MHO026 is intended for applications in which the input pulse width sets the output pulse width; i.e., the output pulse width is logically controtled by the input pulse. The output pulse width is given by: tt (PW) gut = (PWhiyt = PW... +25ns Two external input coupting capacitors are re- quired to perform the level translation between TTL/DTL and MOS logic levels. Selection of the capacitor size is determined by the desired output pulse width. Minimum delay and optimum per- formance is attained when the voltage at the input of the MHOO26 discharges to just above the devices threshold {about 1.5V). If the input is allowed to discharge below the threshold, tor, and t; will be degraded. The graph on page 3 shows optimum values for Cy, vs desired output pulse width. The value for Ciy may be roughly predicted by: Ciy = (2X 1073) (PW yr For an output pulse width of 500ns, the optimum value for Cy is: Ciy = (2X 10-7)(500 X 10-%) = 1000pF TABLE 1. Worst Case Maximum Drive Capability for MHO026* TO-8 WITH MINI- DIP TO-5 AND MINI-DIP PACKAGE TYPE HEAT SINK FREE AIR SOLDERED DOWN FREE AIR Max, Max, Ambient Operating | Temp. 60C 85C 60C a6C 60C a5C 60C 85C Frequency | 4 > Duty cycie~ 100kHz 5% 30 k 24 k 19 k 15 k 13k 10k 7.5k 5.8k 500kHz 10% 6.5k 5.1k 4.1k 3.2k 2.7k 2k 1.5k 1.1k IMHz 20% 2.9k 2.2k 1.8k 1.4k 1.1k 840 600 430 2MHz 25% 1.4 ik 850 650 550 400 280 190 5MH2z 25% 620 470 380 290 240 170 120 80 1OMHz 25% 280 220 170 130 110 79 - - *Note: Valuesin pF and assume both sides in use as non-overtaping 2 phase driver; each side Operating at same frequency and duty cycle with (vt - v7) = 17. For toads greater than 1200 pF, cise and fall times will be limited by output current; see Section 5 0. 3-38application information (cont.) 5.0 Rise & Fail Time Considerations(Note 3) The MH0026's peak output current is limited to 1.5A. The peak current limitation restricts the maximum load capacitance which the device is capable of driving and is given by: i=c, #<15a The rise time, t,, for various loads may be predicted by: t, = (AV)(250 X 1071 a4 cy) Where: AV = The change in voltage across C. =vteve C. = The load capacitance For Vt - V7 = 20V, C, = 1000pF, 1, is: t, = (20V}(250 X 1071? + 1071?) = 25ns For smatl values of C,_, equation above predicts optimistic values for t,. The graph on page 3 shows typical rise times for various load capaci- tances. The output fall time (see Graph} may be predicted by: t, = 2.2R(Cg + C ) Are +4 6.0 Clock Overshoot The output waveform of the MHO026 can over- shoot. The overshoot is due to finite inductance of the clock lines, It occurs on the negative going edge when Q, saturates, and on the positive edge when Q3 turns OFF as the output goes through vt-v,. The problem can be eliminated by placing a small series resistor in the ouput of the MHO026. The critical valve for R,= 2\/L/C2 where L is the self-inductance of the clock line. In practice, determination of a value for L is rather difficult. However,R, is readily determined emper- ically, and values typically range between 10 and 51 ohms. R, does reduce rise and fall times as iven by: g y ty = ty = 2.2RgCL 7.0 Clock Line Cross Talk At the system level,voitage spikes from ; may be transmitted to $2 (and vice-versa) during the transition of , to MOS logic 1. The spike is due to mutual capacitance between clock lines and is, in general, aggravated by long clock lines when numerous registers are being driven. Transistors Q3; and Q, on the @2 side of the MHOO26 are essentially OFF when @, is in the MOS logic Q" state since only micro-amperes are drawn from the device. When the spike is coupled to 2, the output has to drop at least 2 V,,_ before Q3 and Q,g come on and pull the output back to V7. A simple method for eliminating or minimizing this effect is to add bleed resistors between the MH0026 outputs and ground causing a current of a few milliamps to flow in Q4. When a spike is coupled to the clock line Q, is already ON with a finite h,,. The spike is quickly clamped by Qq. Values for R depend on layout and the number of registers being driven and vary typically between 2k and 10k ohms. 8.0 Power Supply Decoupling Power supply decoupling is a widespread and accepted practice. Decoupling of Vt to V7 supply tines with at least 0.1 uF noninductive capacitors as close as possible to each MHOO26 is strongly recommended. This decoupling is necessary because otherwise 1.5 ampere currents flow during logic transition in order to rapidly charge clock lines. 3-39 IIZOOHIN/9ZOOHW