GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: June 2004 Document No. 522 - 28 - 05
DATA SHEET
GS1545
FEATURES
• SMPTE 292M compliant
• 1.485 and 1.485/1.001Gb/s operation
• integrated adaptive cable equalizer
• integrated adjustment-free reclocker
• 1:20 serial to parallel conver sion
• selectable reclocked serial output
• analog/digita l input MUX
• carrier detect
• LOCK detect
• input jitter indicator (IJI)
• cable length indication
• maximum cable length adjust
• 20 bit output
• 74.25MHz or 74.25/1.001MHz clock output
• Pb-free an d Gr ee n
• single +5.0V power supply
• minimal component count for HD SDI receive
solutions
APPLICATIONS
SMPTE 292M Serial Digital Interfaces for Video Cameras,
Camcorders, VTRs, Signal Generators, Portable Equipment,
and NLEs.
DESCRIPTION
The GS1545 is a high performance integrated Equalizing
Receiver designed for HDTV component signals,
conforming to the SMPTE 292M standard. The GS1545
includes adjustment free adaptive cable equalization, clock
and data recovery, and serial to parallel conversion.
The Equalizer stage features DC restoration for immunity to
the DC content in pathological test patterns.
The Clock and Data Recovery stage was designed to auto-
matically recover the embedded clock signal and re-time
the data from SMPTE 292M compliant digital video signals.
There is also a selectable reclocked serial data output and
the ability to bypass the reclocker stage.
A unique feature, Input Jitter Indicator (IJI), is included for
robust system design. This feature is used to indicate
excessive input jitter before the chip mutes the outputs.
The Serial to Parallel conversion stage provides 1:20 S/P
conversion
The GS1545 uses the GO1515 external VCO connected to
the internal PLL circuitry to achieve ultra low noise PLL
performance.
SIMPLIFIED BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER PACKAGE TEMPERATURE Pb-FREE AND GREEN
GS1545-CQR 128 pin MQFP 0°C to 70°C No
GS1545-CQRE3 128 pin MQFP 0°C to 70°C Yes
RECLOCKER
CORE
EQUALIZER
CORE S/P CONVERTER
BUFFER
DDO_EN
DDO
DDO
DATA_OUT[19:0]
DDI DDI_VTT
(opt) DDI A/D
SDI
SDI
ANALOG-
DIGITAL
MUX &
BUFFER
DDOint
DDOint
PCLK_OUT
HD-LINX
™ GS1545
HDTV Serial Digital
Equalizing Receiver
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GS1545
FUNCTIONAL BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise shown.
PARAMETER VALUE
Supply Voltage (VS)5.5V
Input Voltage Range (any input) VEE – 0.5 < VIN < VCC+ 0.5
Operating Temperature Range 0°C ≤ TA ≤ 70°C
Storage Temperature Range -40°C ≤ TS ≤ 150°C
Power Dissipation (VCC = 5.25V) 2.1W
Lead Temperature (soldering 10 seconds) 260°C
Input ESD Voltage 1000V
Junction Temperature 125°C
PLL_LOCK
RECLOCKER CORE
S/P CONVERTER
CORE
BUFFER
DDO_EN
BYPASS
DDO
DDO
DATA_OUT[19:0]
DDI DDI_VTT
(opt) DDI
PCLK_OUT
MUTE
PHASE
DETECTOR
CHARGE
PUMP PHASE
LOCK LOGIC
GO1515
BYPASS
MUX
LFS LFS PLCAP PLCAP IJI
VCO
LFA
EQUALIZER CORE
AGC
EQ
CORE DC
RESTORE
CABLE LENGTH INDICATOR
MAXIMUM CABLE LENGTH ADJUST
CARRIER DETECT
A/D
ANALOG-
DIGITAL
MUX &
BUFFER
BUFFER
CLICD
MCLADJ
SDI
SDI
DDOint+
DDOint-
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GS1545
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0°C to 70°C unless otherwise shown, Data Rate = 1.485Gb/s.
PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS TEST
LEVEL
Positive Supply Voltage Operating range VCC 4.75 5.00 5.25 V 3
Power Consumption VCC = 5; TA = 25°C PD- 1270 1535 mW 5
Supply Current VCC = 5 IS- 235 295 mA 1
Output CM Voltage (DDO, DDO)V
CM 3.4 3.9 4.30 V 5
Input DC Voltage (DDI, DDI) internal bias voltage 3.7 4.0 4.2 V 1
Input DC Voltage (SDI, SDI) internal bias voltage 2.4 2.65 2.80 V 1
Serial Inputs (DDI, DDI) Differential mode
TA = 25°C
VSID 100 - 800 mV 3
Common mode
TA = 25°C
VCM 2.5+VSID/2 -V
CC-VSID/2 V3
High Level Input Voltage
(A/D, BYPASS)
VCC = 5, TA = 25°C VIH 2.0 - - V 3
Low Level Input Voltage (A/D,
BYPASS)
VCC = 5, TA = 25°C VIL --0.8V3
High Level Output Voltage
(D[19:0], PCLK)
VCC = 5, ISOURCE = 1.0mA VOH 2.4 - 3.0 V 1
Low Level Output Voltage
(D[19:0], PCLK)
VCC = 5, ISINK = 1.0mA VOL --0.4V1
High Level Output Voltage
(PLL_LOCK)
VCC = 5, ISOURCE = 200µA VOH 2.4 3.0 - V 1
Low Level Output Voltage
(PLL_LOCK)
VCC = 5, ISINK = 500µA VOL --0.4V1
Low Level Output Voltage (CD)ISINK = 500µA VOL --0.4V1
CLI DC Voltage 1 meter, 800mV p-p Input
TA = 25°C
2.9 3.2 3.6 V 3
CLI DC Voltage
(max cable length)
120 meters, Belden 1694a
TA = 25°C
1.0 1.4 2.3 V 3
MCLADJ DC Voltage 1 meter, 800mV p-p Input
TA = 25°C
3.4 4.1 4.3 V 3
MCLADJ DC Voltage
(max cable length)
120 meters, 800mV p-p Input
TA = 25°C
2.9 3.1 3.4 V 3
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test.
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GS1545
AC ELECTRICAL CHARACTERISTICS - RECLOCKER STAGE
VCC = 5V, TA = 25°C
PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS TEST
LEVEL
Serial Input – Data Rate SMPTE 292M BRSDI 1.485/1.001 1.485 - Gb/s 3
Serial Input – Jitter Tolerance Sinewave Modulation (p – p) JTOL 0.5 0.6 - UI 9
Phase Lock Time -
Asynchronous
Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
TALOCK - 120 145 ms 7
Phase Lock Time - Synchronous Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
TSLOCK -23.2µs7
Carrier Detect Response Time Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
-1214ms7
Phase Lock/Unlock Time
(1nF PLCAP)
Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
80 - - µs 7
Digital Data Output (DDO) –
Signal Swing
VDDO 355 400 480 mV 1
Digital Data Output (DDO) –
Rise and Fall Time
tR-DDO, tF-DDO - 160 - ps 7
Digital Data Output (DDO) –
Rise and Fall Time Mismatch
-30-ps7
Digital Data Output (DDO) –
Intrinsic Jitter
(RMS Jitter for clean PRN 223 – 1
input on DDI/DDI inputs)
tIJ -10-ps9
Loop bandwidth @ 0.2UI jitter modulation
LBCONT floating
1.2 1.4 1.5 MHz 7
Jitter peaking --0.1dB7
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test.
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GS1545
AC ELECTRICAL CHARACTERISTICS - EQUALIZER STAGE
VCC = 5V, TA = 25°C
PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS TEST
LEVEL
Equalization Belden 1694A - 110 - m 3
Input Resistance (SDI, SDI)-3.2-kΩ7
Input Capacitance (SDI, SDI)C
IN -2.0-pF7
AC ELECTRICAL CHARACTERISTICS - SERIAL TO PARALLEL STAGE
VCC = 5V, TA = 25°C
PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS TEST
LEVEL
Parallel Output Clock Frequency SMPTE 292M PCLK_OUT 74.25/1.001 74.25 - MHz 3
Clock Pulse Width Low 15pF load tPWL 7-6.1ns7
Clock Pulse Width High 15pF load tPWH 6-6.4ns7
Output signal Rise/Fall time 15pF load tr, tf- 2.70 3.60 ns 7
Output Signal Rise/Fall Time
Mismatch
15pF load trfm - 1.00 1.60 ns 7
Output Setup Time 15pF load tOD 55.5-ns7
Output Hold Time 15pF load tOH 6.2 7.1 - ns 7
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
9. Indirect test.
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GS1545
PIN CONNECTIONS
NC
NC
PCLK_VEE
PCLK_VCC
PCLK_OUT
SP_VEE
SP_VEE
SP_VCC
SP_VCC
NC
NC
NC
NC
NC
NC
NC
NC
DDO_VCC
DDO_EN
DDO_VEE
DDO
DDO
EQO_VCC
NC
NC
EQO_VEE
CD
NC
NC
NC
NC
CLI
NC
MCLADJ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LFA_VCC
LFA
LBCONT
LFA_VEE
DFT_VEE
NC
NC
DM
DM
LFS
NC
NC
NC
LFS
IJI
NC
NC
VCO
NC
VCO
NC
PLCAP
NC
NC
PLCAP
NC
PLL_LOCK
NC
NC
NC
NC
DATA_OUT[19]
DATA_OUT[18]
DATA_OUT[17]
DATA_OUT[16]
DATA_OUT[15]
DATA_OUT[14]
NC
NC
DATA_OUT[13]
DATA_OUT[12]
DATA_OUT[11]
DATA_OUT[10]
NC
NC
DATA_OUT[9]
DATA_OUT[8]
DATA_OUT[7]
DATA_OUT[6]
DATA_OUT[5]
DATA_OUT[4]
DATA_OUT[3]
DATA_OUT[2]
DATA_OUT[1]
DATA_OUT[0]
NC
NC
NC
NC
BYPASS
DDI_VTT
NC
DDI
DDI
PD_VCC
A/D
PDSUB_VEE
PD_VEE
NC
NC
NC
EQI_VCC
NC
NC
EQI_VEE
NC
SDI
NC
SDI
NC
EQI_VEE
NC
NC
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
GS1545
TOP
VIEW
NC
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GS1545
PIN DESCRIPTIONS
NUMBER SYMBOL LEVEL TYPE DESCRIPTION
1, 2, 3, 4, 6, 8,
9, 10, 11, 14,
15, 22, 23, 24,
25, 26, 27, 28,
29, 37, 38, 39,
40, 51, 52, 57,
58, 65, 66, 67,
68, 69, 70, 71,
77, 78, 82, 83,
84, 87, 88, 90,
92, 94, 95, 97,
99, 100, 101,
102, 103, 104,
107, 114, 115,
116, 118, 119,
121, 123, 125,
127, 128
NC No Connect. Leave these pins floating.
5 MCLADJ Analog Input Control Signal Input. Adjusts the maximum amount of cable for the
equalizer (from 0m to the maximum cable length). Normally the output
is muted (latched to the last state) when the set maximum cable
length is exceeded. To achieve maximum cable length, this pin should
be left open (floating).
7 CLI Analog Output Status Control Signal. The Cable Length Indication (CLI) signal
provides approximate voltage representation of the amount of cable
being equalized.
12 CD Digital Output Status Signal. The Carrier Detect indicator is used as an output status
signal.
When the CD output is low, the carrier is present and the data output
is active.
When the CD output is high, the carrier is not present and the data
output is muted (latched to the last state). This indicates that the
maximum cable length as set by MCLADJ has been reached.
13 EQO_VEE Power Input Negative Supply. Most negative power supply connection for Equalizer
output buffer stage.
16 EQO_VCC Power Input Positive Supply. Most positive power supply connection for Equalizer
output buffer stage.
17, 18 DDO, DDO ECL/PECL
compatible
Output Digital Data Output. Differential serial outputs. 50Ω pull up resistors are
included on chip. Note that these outputs are not cable drivers.
Ensure that the trace length between the GS1545 and the GS1508
Cable driver is kept to a minimum and that a PCB trace characteristic
impedance of 50Ω is maintained between the GS1508 and the
GS1545. 50Ω end termination is recommended.
19 DDO_VEE Power Input Negative Supply. Most negative power supply connection for serial
data output stage.
20 DDO_EN Power Input Control Signal Input. Used to enable or disable the serial output stage.
If a loop through function is not required, then this pin should be tied
to the most positive power supply voltage.
When DDO_EN is tied to the most negative power supply voltage, the
DDO, DDO outputs are enabled.
When DDO_EN is tied to the most positive power supply voltage, the
DDO, DDO outputs are disabled.
21 DDO_VCC Power Input Positive Supply. Most positive power supply connection for serial data
output stage.
30, 31 SP_VCC Power Input Positive Supply. Most positive power supply connection for serial to
parallel converter stage.
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32, 33 SP_VEE Power Input N egative Supply. Most negative power supply connection for the
parallel output stage.
34 PCLK_OUT TTL Output Output Clock. The device uses PCLK_OUT for clocking the output
data stream from DATA_OUT[19:0]. This clock is also used to clock
the data into the GS1500 HDTV Deformatter or GS1510 Deformatter.
35 PCLK_VCC Power Input Positive Supply. Most positive supply connection for parallel clock
output stage.
36 PCLK_VEE Power Input Negative Supply. Most negative power supply connection for parallel
clock output stage.
41, 42, 43, 44,
45, 46, 47, 48,
49, 50, 53, 54,
55, 56, 59, 60,
61, 62, 63, 64
DATA_OUT[19:0] TTL Output Parallel Data Output Bus. The device outputs a 20 bit parallel data
stream running at 74.25 or 74.25/1.001MHz on DATA_OUT[19:0].
DATA_OUT[19] is the MSB and DATA_OUT[0] is the LSB.
72 LFA_VCC Power Input Positive Supply. Loop filter most positive power supply connection.
73 LFA Analog Output Control Signal Output. Control voltage for GO1515 VCO.
74 LBCONT Analog Input Control Signal Input. Used to provide electronic control of Loop
Bandwidth.
75 LFA_VEE Power Input Negative Supply. Loop filter most negative power supply connection.
76 DFT_VEE Power Input Most negative power supply connection - enables the jitter
demodulator functionality. This pin should be connected to ground. If
left floating, the DM function is disabled resulting in a current saving of
340µA.
79, 80 DM, DM Analog Output Test Signal. Used for manufacturing test only.
These pins must be floating for normal operation.
81, 85 LFS, LFS Analog Input Loop Filter Connections.
86 IJI Analog Output Status Signal Output. Approximates the amount of excessive jitter on
the incoming DDI and DDI input.
89 VCO Analog Input Control Signal Input. Input pin is AC coupled to ground using a 50Ω
transmission line.
91 VCO Analog Input Control Signal Input. Voltage controlled oscillator input. This pin is
connected to the output pin of the GO1515 VCO.
This pin must be connected to the GO1515 VCO output pin via a 50Ω
transmission line.
93, 96 PLCAP, PLCAP Analog Input Control Signal Input. Phase lock detect time constant capacitor.
98 PLL_LOCK TTL Output Status Indicator Sig nal. This signal is a combination (logical AND) of
the carrier detect and phase lock signals.
When input is present and PLL is locked, the PLL_LOCK goes high
and the outputs are valid. When the PLL_LOCK output is low the data
output is muted (latched at the last state).
PLL_LOCK is independent of the BYPASS signal.
105 BYPASS TTL Input Control Signal Input. Selectable input that controls whether the input
signal is reclocked or passed through the chip.
When BYPASS is high; the input signal is reclocked.
When BYPASS is low; the input signal is passed through the chip and
not reclocked. Muting does not effect bypassed signal.
PIN DESCRIPTIONS (Continued)
NUMBER SYMBOL LEVEL TYPE DESCRIPTION
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GS1545
106 DDI_VTT Analog Input Bias Input. Selectable input for interfacing standard ECL outputs
requiring 50Ω pull down to VTT power supply for a seamless interface.
See Typical Application Circuit for recommended circuit application.
108, 109 DDI, DDI Differential
ECL/PECL
Input Digital Data Input Signals. Digital input signals from a GS1504
Equalizer or HD crosspoint switch.
Because of on chip 50Ω termination resistors, a PCB trace
characteristic impedance of 50Ω is recommended.
110 PD_VCC Power Positive Supply. Phase detector most positive power supply
connection.
111 A/D TTL Input Control Signal Input. Used to select between the SDI/SDI input or
DDI/DDI input.
When A/D is HIGH; the SDI/SDI input is selected.
When A/D is LOW; the DDI/DDI input is selected.
112 PDSUB_VEE Power Input Substrate Connection. Connect to phase detector’s most negative
power supply.
113 PD_VEE Power Input Negative Supply. Phase detector most negative power supply
connection.
117 EQI_VCC Power Input Positive Supply. Most positive power supply connection for serial input
stage.
120, 126 EQI_VEE Power Input Negative Supply. Most negative power supply connection for serial
input stage.
122, 124 SDI, SDI Analog Input Serial Data Input Signals. AC coupled termination is recommended.
Single ended to differential conversion is also feasible. The SDI and
SDI input is selected when the A/D signal is high.
Ensure that the trace length between the input connector and the
GS1545 IC is kept to a minimum and that a PCB trace characteristic
impedance of 75Ω is maintained between the connector and the
device.
PIN DESCRIPTIONS (Continued)
NUMBER SYMBOL LEVEL TYPE DESCRIPTION
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GS1545
INPUT/OUTPUT CIRCUITS
Fig. 1 DDI/DDI Input Circuit
Fig. 2 VCO/VCO Input Circuit
Fig. 3 DM/DM Output Circuit
Fig. 4 PLCAP/PLCAP Output Circuit
Fig. 5 LFA Circuit
Fig. 6 LFS Output Circuit
PD_VEE
DDI_VTT
PD_VCC
DDIDDI 50 50
20k
5k
PD_VEE
PD_VCC
VCO VCO
50
10k
5k 5k
10k
31p
DFT_VEE
10k 10k
DM DM
85µA
PD_VCC
PD_V
EE
20k 10k
PLCAP PLCAP
100µA
PD_V
CC
LFA_VEE
LFA_VCC
40 40
500
5mA 100µA
LFA
LFA_VEE
LFA_VCC
25k
400µA
LFS
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GS1545
Fig. 7 LFS Input Circuit
Fig. 8 PLL_LOCK Output Circuit
Fig. 9 IJI Output Circuit
Fig. 10 A/D Input Circuit
Fig. 11 BYPASS Circuit
Fig. 12 LBCONT Circuit
Fig. 13 D[19:0] Output Circuit
Fig. 14 PCLK Output Circuit
LFA_VEE
LFA_VCC
100µA
100µA
100µA
100µA
10k 5k
LFS
PD_VEE
PD_VCC
10k
PLL_LOCK
PD_V
CC
IJI
10k
5k
V
CC
30k A
PD_V
EE
PD_VE
E
20k 16k
100µA
PD_VCC
A/D
+
-2.4V
PD_VEE
PD_VCC
16k
100µA
BYPASS V = 2.4V
+
-
LFA_VEE
LFA_VCC
20k
LBCONT 5k
SP_VEE
SP_VCC
27k
100
0.1uF
D[19:0]
PCLK_VEE
PCLK_VCC
27k
100 PCLK
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GS1545
Fig. 15 DDO_EN Circuit
Fig. 16 Equalizer Input Circuit
Fig. 17 MCLADJ Equivalent Circuit
Fig. 18 Serial (DDO) Output Stage Circuit
Fig. 19 CLI Output Circuit
Fig. 20 CD Circuit
DDO_VEE
DDO_VCC
2k
20k
DDO_EN
EQI_VEE
EQI_VCC
6k
SDI
7k
SDI
6k
7k
RC
EQI_V
CC
MCLADJ
40k
42µ
+
-
EQI_V
EE
50
50
DDO DDO
DDO_VEE
DDO_VCC
10k
10k
EQO_VCC
CLI
-
+
10k
20k
OUTPUT
STAGE
MUTE
CONTROL
EQO_V
CC
CD
EQO_V
EE
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GS1545
DETAILED DESCRIPTION
The GS1545 is a single standard equalizing receiver for
serial digital HDTV signals at 1.485Gb/s and
1.485/1.001Gb/s.
UNIQUE SLEW PHASE LOCK LOOP (S-PLL):
A unique feature of the GS1545 is the innovative slew phase
lock loop (S-PLL). When a step phase change is applied to
the PLL, the output phase gains constant rate of change
with respect to time. This behaviour is termed slew.
Figure 21 shows an example of input and output phase
variation over time for slew and linear (conventional) PLLs.
Since the slewing is a nonlinear behavior, the small signal
analysis cannot be done in the same way as the standard
PLL. However, it is still possible to plot input jitter transfer
characteristics at a constant input jitter modulation.
Fig. 21 PLL Characteristics
Slew PLLs offer several advantages such as excellent noise
immunity. Because of the infinite bandwidth for an infinitely
small input jitter modulation (or jitter introduced by VCO),
the loop corrects for that immediately thus the small signal
noise of the VCO is cancelled. The GS1545 uses a very
clean, external VCO called the GO1515 (refer to the
GO1515 Data Sheet for details). In addition, the bi-level
digital phase detector provides constant loop bandwidth
that is predominantly independent of the data transition
density. The loop bandwidth of a conventional tri-stable
charge pump drops with reducing data transitions. During
pathological signals, the data transition density reduces
from 0.5 to 0.05, but the slew PLLs performance essentially
remains unchanged.
Because most of the PLL circuitry is digital, it is more like
other digital systems which are generally more robust than
their analog counterparts. Additionally, signals like DM/DM
which represent the internal functionality can be generated
without adding additional artifacts. Thus, system debugging
is also possible with these features. The complete slew PLL
is made up of several blocks including the phase detector,
the charge pump and an external Voltage Controlled
Oscillator (VCO).
DIGITAL INPUT BUFFER
The input buffer is a self-biased circuit. On-chip 50Ω
termination resistors provide a seamless interface for other
HD-LINX™ products such as the GS1504 Adaptive Cable
Equalizer. The digital input is selected by applying a logic
low to the A/D pin.
ANALOG INPUT
The HD serial data signal may be connected to the input
pins (SDI/SDI) in either a differential or single ended
configuration. AC coupling of the inputs is recommended,
as the SDI and SDI inputs are internally biased at
approximately 2.7 volts. The input signal passes through a
variable gain equalizing stage whose frequency response
closely matches the inverse cable loss characteristic. In
addition, the variation of the frequency response with
control voltage imitates the variation of the inverse cable
loss characteristic with cable length. The analog input is
selected by applying a logic high to the A/D pin.
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal cor-
responding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an internal AGC filter capacitor providing a
steady control voltage for the gain stage. As the frequency
response of the gain stage is automatically varied by the
application of negative feedback, the edge energy of the
equalized signal is kept at a constant level which is
representative of the original edge energy at the transmitter.
The equalized signal is also DC restored, effectively
restoring the logic threshold of the equalized signal to its
correct level independent of shifts due to AC coupling.
PHASE DETECTOR
The phase detector portion of the slew PLL used in the
GS1545 is a bi-level digital phase detector. It indicates
whether the data transition occurred before or after with
respect to the falling edge of the internal clock. When the
phase detector is locked, the data transition edges are
aligned to the falling edge of the clock. The input data is
then sampled by the rising edge of the clock, as shown in
Figure 22. In this manner, the allowed input jitter is 1UI p-p
in an ideal situation. However, due to setup and hold time,
the GS1545 typically achieves 0.5UI p-p input jitter
tolerance without causing any errors in this block. When the
0.2
0.1
0.0
INPUT
OUTPUT
SLEW PLL RESPONSE
PHASE (UI)
0.2
0.1
0.0
INPUT
OUTPUT
LINEAR (CONVENTIONAL) PLL RESPONSE
PHASE (UI)
GENNUM CORPORATION 522 - 28 - 05
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GS1545
signal is locked to the internal clock, the control output from
the phase detector is refreshed at the transition of each
rising edge of the data input. During this time, the phase of
the clock drifts in one direction.
Fig. 22 Phase Detector Characteristics
During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not very
significant, even for the pathological signals.
CHARGE PUMP
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump. One function is to hold the frequency
information of the input data. This information is held by
CCP1, which is connected between LFS and LFS. The other
capacitor, CCP2 between LFS and LFA_GND is used to
remove common mode noise. Both CCP1 and CCP2 should
be the same value. The second function of the charge
pump is to provide a binary control voltage to the VCO
depending upon the phase detector output. The output pin,
LFA controls the VCO. Internally there is a 500Ω pull-up
resistor, which is driven with a 100µA current called ΙP.
Another analog current ΙF, with 5mA maximum drive
proportional to the voltage across the CCP1, is applied at the
same node. The voltage at the LFA node is
VLFA_VCC - 500(ΙP+ΙF) at any time.
Because of the integrator, ΙF changes very slowly whereas
ΙP could change at the positive edge of the data transition
as often as a clock period. In the locked position, the
average voltage at the LFA (VLFA_VCC – 500(ΙP/2+ΙF) is such
that VCO generates frequency ƒ, equal to the data rate
clock frequency. Since ΙP is changing all the time between
0A and 100µA, there will be two levels generated at the LFA
output.
VCO
The GO1515 is an external hybrid VCO, which has a centre
frequency of 1.485GHz and is also guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V – 4.65V) of
the GS1545 over process, power supply and temperature.
The GO1515 is a very clean frequency source and,
because of the internal high Q resonator, it is an order of
magnitude more immune to external noise as compared to
on-chip VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V. The control
voltage around the average LFA voltage will be 500 x ΙP/2.
This will produce two frequencies off from the centre by
ƒ=Kƒ x 500 x ΙP/2.
LBCONT
The LBCONT pin is used to adjust the loop bandwidth by
externally changing the internal charge pump current. For
maximum loop bandwidth, connect LBCONT to the most
positive power supply. For medium loop bandwidth,
connect LBCONT through a pull-up resistor (RPULL-UP). For
low loop bandwidth, leave LBCONT floating. The formula
below shows the loop bandwidth for various configurations.
where LBW nominal is the loop bandwidth when LBCONT is
left floating.
LOOP BANDWIDTH OPTIMIZATION
Since the feed back loop has only digital circuits, the small
signal analysis does not apply to the system. The effective
loop bandwidth scales with the amount of input jitter
modulation index.
PHASE LOCK
The phase lock circuit is used to determine the phase
locked condition. It is done by generating a quadrature
clock by delaying the in-phase clock (the clock whose
falling edge is aligned to the data transition) by 166ps
(0.25UI at 1.5GHz) with the tolerance of 0.05UI. When the
PLL is locked, the falling edge of the in-phase clock is
aligned with the data edges as shown in Figure 23. The
quadrature clock is in a logic high state in the vicinity of
input data transitions. The quadrature clock is sampled and
latched by positive edges of the data transitions. The
generated signal is low pass filtered with an RC network.
The R is an on-chip 20kΩ resistor and CPL is an external
capacitor (recommended value 10nF). The time constant is
about 67µs, or more than a video line.
IN-PHASE CLOCK
INPUT DATA
WITH JITTER
OUTPUT DATA
0.5UI
RE-TIMING
EDGE
PHASE ALIGNMENT
EDGE
LBW LBWNOMINAL
25kΩRPULL UP–
+()
5kΩRPULL UP–
+()
------------------------------------------------------
×=
GENNUM CORPORATION 522 - 28 - 05
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GS1545
Fig. 23 PLL Circuit Principles
If the signal is not locked, the data transition phase could
be anywhere with respect to the internal clock or the
quadrature clock. In this case, the normalized filtered
sample of the quadrature clock will be 0.5. When VCO is
locked to the incoming data, data will only sample the
quadrature clock when it is logic high. The normalized
filtered sample quadrature clock will be 1.0. We chose a
threshold of 0.66 to generate the phase lock signal.
Because the threshold is lower than 1, it allows jitter to be
greater than 0.5UI before the phase lock circuit reads it as
“not phase locked”.
INPUT JITTER INDICATOR (IJI)
This signal indicates the amount of excessive jitter (beyond
the quadrature clock window 0.5UI), which occurs beyond
the quadrature clock window (see Figure 23). All the input
data transitions occurring outside the quadrature clock
window, will be captured and filtered by the low pass filter
as mentioned in the Phase Lock section. The running time
average of the ratio of the transitions inside the quadrature
clock and outside the quadrature is available at the
PLCAP/PLCAP pins. A signal, IJI, which is the buffered
signal available at the PLCAP is provided so that loading
does not effect the filter circuit. The signal at IJI is
referenced with the power supply such that the factor
VIJI/VCC is a constant over process and power supply for a
given input jitter modulation. The IJI signal has 10kΩ output
impedance. Figure 24 shows the relationship of the IJI
signal with respect to the sine wave modulated input jitter.
Fig. 24 Input Jitter Indicator (Typical at TA = 25°C)
JITTER DEMODULATION (DM)
The differential jitter demodulation (DM) signal is available
at the DM and DM pins. This signal is the phase correction
signal of the PLL loop, which is amplified and buffered. If
the input jitter is modulated, the PLL tracks the jitter if it is
within loop bandwidth. To track the input jitter, the VCO has
to be adjusted by the phase detector via the charge pump.
Thus, the signal which controls the VCO contains the
information of the input jitter modulation. The jitter
demodulation signal is only valid if the input jitter is less
than 0.5UIp-p. The DM/DM signals have 10kΩ output
impedance, which could be low pass filtered with
appropriate capacitors to eliminate high frequency noise.
DFT_VEE should be connected to GND to activate DM/DM
signals.
The DM signals can be used as diagnostic tools. Assume
there is an HDTV SDI source, which contains excessive
noise during the horizontal blanking because of the
transient current flowing in the power supply. In order to
discover the source of the noise, one could probe around
IN-PHASE CLOCK
INPUT DATA
WITH JITTER
0.5UI
RE-TIMING
EDGE
PHASE ALIGNMENT
EDGE
QUADERATURE
CLOCK
PLCAP SIGNAL
PLCAP SIGNAL
0.25UI
P-P SINE WAVE JITTER IN UI IJI VOLTAGE
0.00 4.75
0.15 4.75
0.30 4.75
0.39 4.70
0.45 4.60
0.48 4.50
0.52 4.40
0.55 4.30
0.58 4.20
0.60 4.10
0.63 3.95
IJI SIGNAL (V)
INPUT JITTER (UI)
0.00 0.20 0.40 0.60 0.80
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
GENNUM CORPORATION 522 - 28 - 05
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GS1545
the source board with a low frequency oscilloscope
(Bandwidth < 20MHz) that is triggered with an appropriately
filtered DM/DM signal. The true cause of the modulation will
be synchronous and will appear as a stationary signal with
respect to the DM/DM signal.
Figure 25 shows an example of such a situation. An HDTV
SDI signal is modulated with a modulation signal causing
about 0.2UI jitter in Figure 25 (Channel 1). The GS1545
receives this signal and locks to it. Figure 25 (Channel 2)
shows the DM signal. Notice the wave shape of the DM
signal, which is synchronous to the modulating signal. The
DM/DM signal could also be used to compare the output
jitter of the HDTV signal source.
Fig. 25 Jitter Demodulation Signal
LOCK LOGIC
Logic is used to produce the PLL_LOCK signal which is
based on the LFS signal and phase lock signal. When there
is not any data input, the integrator will charge and
eventually saturate at either end. By sensing the saturation
of the integrator, it is determined that no data is present. If
either data is not present or phase lock is low, the lock
signal is made low. Logic signals are used to acquire the
frequency by sweeping the integrator. Injecting a current
into the summing node of the integrator achieves the
sweep. The sweep is disabled once phase lock is asserted.
The direction of the sweep is also changed once LFS
saturates at either end.
BYPASS
The BYPASS block bypasses the reclocked/mute path of
the data whenever a logic low input is applied to the
BYPASS input. In the bypass mode, the mute does not have
any effect on the parallel outputs. Also, the internal PLL still
locks to a valid HDTV signal and shows PLL_LOCK.
SERIAL OUTPUT STAGE
The serial output signals DDO, DDO have a nominal voltage
of 400mVpp differential, or 200mVpp single ended when
terminated with 50Ω.
DDO_EN
The DDO_EN enables or disables the serial output driver. To
disable the driver, tie DDO_EN to VCC. To enable the driver,
tie DDO_EN to VEE. When disabled, the supply current is
reduced by approximately 10mA.
A/D
A/D is a TTL compatible input pin used to select between
the analog or digital input. When A/D is at logic high, the
analog input is selected. When A/D is low, the digital input
is enabled.
CLI
The voltage output of CLI pin is proportional to the amount
of cable present at the GS1545 analog input. With 0m of
cable (800mV input signal levels), the CLI output voltage is
approximately 3.3V. As the cable length increases, the CLI
voltage decreases providing correlation between the CLI
voltage and cable length. CLI voltage will be a function of
the launch voltage and cable type/quality.
MCLADJ
The outputs of the GS1545 can be muted when the input
signal decreases below a preselected input level. The
MCLADJ pin may be left unconnected for applications
where output muting is not required. The use of a Carrier
Detect function with a fixed internal reference does not
solve this problem since the signal to noise ratio on the
circuit board could be significantly less than the default
signal detection level set by the on chip reference.
CARRIER DETECT
The CD pin is a TTL compatible output signal. When a
carrier is detected at the analog input, the CD pin is pulled
low. When a carrier is not detected, the CD will be pulled
high.
SERIAL TO PARALLEL CONVERTER
The high-speed serial to parallel converter accepts
differential clock and data signals from the reclocker core.
The S/P core converts this serial output into a 20-bit wide
data stream (D[19:0]). Note that this data stream is not word
aligned or descrambled. It also provides a parallel clock,
which is 1/20th the serial clock rate (PCLK_OUT). The
outputs of the S/P block are TTL compatible. When the PLL
loses lock, the parallel clock continues to freewheel. The
parallel clock and data outputs were designed for seamless
interfaces to the GS1500 and GS1510 deformatters.
GENNUM CORPORATION 522 - 28 - 05
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GS1545
0Ω
SECOND PAIR OF BNC SHOWN IS
FOR DUAL FOOTPRINT OPTION ON
INPUT CONNECTORS
J1
nc
nc
nc
nc
MCLAD
nc
CLI
nc
nc
1
2
3
4
5
6
7
8
9
nc
nc
CD
EQO_VEE
nc
nc
EQO_VCC
DDO
DDO
DDO_VEE
DDO_EN
DDO_VCC
nc
nc
nc
nc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
nc
nc
nc
nc
SP_VCC
SP_VCC
SP_VEE
SP_VEE
PCLK_OUT
PCLK_VCC
PCLK_VEE
nc
nc
26
27
28
29
30
31
32
33
34
35
36
37
38 65
66
67
68
69
70
72
73
74
75
76
77
78
79
80
81
82
83
84
nc
nc
nc
nc
nc
nc
LFA_VCC
LFA
LBCONT
LFA_VEE
DM
DM
LFS
nc
DFT_VEE
nc
nc
nc
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
LFS
IJI
nc
nc
VCO
nc
VCO
nc
PLCAP
nc
nc
PLCAP
nc
PLL_LOCK
nc
nc
nc
nc
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
nc
nc
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
nc
nc
D10
D11
D12
D13
D14
D15
nc
nc
D16
D17
D18
D19
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
123
122
124
125
126
127
128
nc
nc
BYPASS
DDI_VTT
nc
DDI
DDI
PD_VCC
A/D
PDSUB_VEE
PD_VEE
nc
nc
EQI_VCC
nc
nc
EQI_VEE
nc
SDI
nc
SDI
nc
EQI_VEE
nc
nc
BYPASS
C25
10n
C33
4µ7
C32
4µ7
VCC
A/D
J5
J6
J3
10nH
R12 75
R15 75
VCC
C17 10n
C18
47p
C20
47p
R13 37.5
BNC_ANCHOR
C19
10n
R8
15k
R17
2k
R6
10k
VCC
VCC
C22
10n
VCC
CD
SDO_EN
C24
4µ7
+
C23
4µ7
+
J7
J4
PCLK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
VCC
C29
10n
C30
10n
C31
10n
(110/112) (19/21) (30-31/32-33)
PLL_LOCK
VCO
LFA
C27
10n
C26
10n
C28
1µ
+C34
1µ
+
C35
10n
VCC
ANALOG POWER PLANE
VCC
C54
100n
C55
10µ
L10
R111
C53
10µ
C56
100n
VCC
MAIN POWER PLANE
VCC
C49
10µ
C51
10µ
C50
100n
C52
100n
VCC
DIGITAL POWER PLANE
VCC
VCC
C64
10µ
C61
100n
R116
0ΩL17
C60
10µ
C59
100n
L8 R19
VCO POWER PLANE
GS1545
L5
nc
71
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
CLI
VCC VCC
(35/36)
C65
10n
VCC
nc
nc
1p5
0Ω
0Ω
Note that these outputs
are not cable drivers
TYPICAL APPLICATION CIRCUIT
GENNUM CORPORATION 522 - 28 - 05
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GS1545
TYPICAL APPLICATION CIRCUIT (continued)
APPLICATION INFORMATION
Please refer to the EBHDRX evaluation board
documentation for more detailed application and circuit
information on using the GS1545 with the GS1500 and
GS1510 Deformatters.
GO1515 VCO
LFA
C43
100n
C42
10µ
1
2
3
VCC
U2
GO1515
4
5
6
7
+
8
VCO
GND
GND
VCC
GND
VCTR
O/P
GND
nc
POWER CONNECT
VCC
C41
+
10µ
C44
100n
GS1545 LOCK DETECT
R26
22k
Q3 LED3
R27
150
VCC
PLL_LOCK
GS1545 CD
VCC
R28
150
LED4
Q1
R25
20k
CD
GS1545 CONFIGURATION JUMPERS
A/D
VCC VCC
VCC
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
DDO_EN
BYPASS
522 - 28 - 05
19 of 19
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku,
Tokyo 160-0023 Japan
Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright May 2000 Gennum Corporation. All rights reserved. Printed in Canada.
GS1545
PACKAGE DIMENSIONS
23.20 ±0.25
20.0 ±0.10
18.50 REF
17.20 ±0.25
14.0 ±0.10
12.50 REF
3.00 MAX
2.80 ±0.25
1.6
REF
0.30 MAX RADIUS
0.13 MIN.
RADIUS 0.88 ±0.15
0.75 MIN
12 TYP
0 - 7
0 -7
0.27 ±0.08
0.50 BSC
128 pin MQFP
All dimensions are in millimetres.
REVISION NOTES:
Added lead-free and green information.
For latest product information, visit www.gennum.com
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change without notice.
