NJW4152
-
1
-
Ver.2013-01-23
Switching Regulator IC for Buck Converter
w/ 40V/1A or 40V/600mA MOSFET
GENERAL DESCRIPTION ■ PACKAGE OUTLINE
FEATURES
Maximum Rating Input Voltage 45V
Wide Operating Voltage Range 4.6V to 40V
Switching Current 1.4A(min.) @A version
0.8A(min.) @B version
PWM Control
Wide Oscillating Frequency 300kHz to 1MHz
Soft Start Function 4ms typ.
UVLO (Under Voltage Lockout)
Over Current Protection / Thermal Shutdown Protection
Standby Function
Package Outline NJW4152GM1: HSOP8
NJW4152R: MSOP8(VSP8)*
*MEET JEDEC MO-187-DA
PRODUCT CLASSIFICATION
Status Part Number Version
Output
Current
Switching
Current Limit
(MIN.)
Operating
Voltage Package Operating
Temperature Range
MP NJW4152GM1-A A 1.0A 1.4A 4.6 to 40V HSOP8 General Spec.
-40 to +85°C
MP NJW4152GM1-A-T A 1.0A 1.4A 4.6 to 40V HSOP8 Automotive T Spec.
-40 to +105°C
MP NJW4152GM1-A-T1 A 1.0A 1.4A 4.6 to 40V HSOP8 Automotive T1 Spec.
-40 to +125°C
MP NJW4152GM1-AB AB 1.0A 1.4A 3.6 to 40V HSOP8 General Spec.
-40 to +85°C
MP NJW4152GM1-AB-T1 AB 1.0A 1.4A 3.6 to 40V HSOP8 Automotive T1 Spec.
-40 to +125°C
MP NJW4152R-B B 600mA 0.8A 4.6 to 40V MSOP8
(VSP8)
General Spec.
-40 to +85°C
U.D. NJW4152R-BA-Z BA 600mA 0.8A 4.4 to 40V MSOP8
(VSP8)
Automotive Z Spec.
-40 to +125°C
This data sheet is applied to "NJW4152GM1-A, NJW4152R-B".
Please refer to each data sheet for other versions.
The NJW4152 is a buck converter with 40V/1A or 40V/600mA MOSFET.
It corresponds to high oscillating frequency, and Low ESR Output Capacitor
(MLCC) within wide input range from 4.6V to 40V. Therefore, the NJW4152
can realize downsizing of an application with a few external parts.
Also, it has a soft start function, an over current protection and a thermal
shutdown circuit. Moreover there is an automotive for extended operating
temperature range version.
It is suitable for logic voltage generation from high voltage that Car
A
ccessor
y
, Office Automation Equipment, Industrial Instrument and so on.
NJW4152GM1-A
(HSOP8)
NJW4152R-B
(MSOP8 (VSP8))
NJW4152
-
2
-Ver.2013-01-23
PIN FUNCTION
1. PV+
2. V+
3. ON/OFF
4. RT
5. IN-
6. FB
7. GND
8. SW
1 8
2 7
3 6
4 5
1
4
3
2
8
5
6
7
Exposed PAD on
backside connect to GND
PIN CONFIGURATION
NJW4152GM1-A NJW4152R-B
BLOCK DIAGRAM
Buffer
Soft Start
0.8V
IN-
PWM
ER⋅AMP
GND
TSD
Standby
ON/OFF
ON/OFF
High: ON
Low : OFF
(Standby)
UVLO
SW
Vref
OSC
FB
RT
PV+ V+
Regulator
OCP
Pulse by Pulse
480kΩ Low Frequency
Control
NJW4152
-
3
-
Ver.2013-01-23
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
PARAMETER SYMBOL MAXIMUM RATINGS UNIT
Supply Voltage
(V+ pin, PV+ pin) V+ +45 V
PV+- SW pin Voltage VPV-SW +45 V
IN- pin Voltage VIN- -0.3 to +6 V
ON/OFF pin Voltage VON/OFF +45 V
790 (*1)
HSOP8
2,500 (*2)
595 (*1)
Power Dissipation PD
MSOP8(VSP8)
805 (*2)
mW
Junction Temperature Range Tj -40 to +150 °C
Operating Temperature Range Topr -40 to +85 °C
Storage Temperature Range Tstg -40 to +150 °C
(*1): Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 2Layers)
(*2): Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 4Layers),
internal Cu area: 74.2×74.2mm
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply Voltage V+ 4.6 – 40 V
A version – – 1.0 A
Output Current (*3) B version IOUT – – 0.6 A
Timing Resistor RT 18 27 68 kΩ
Oscillating Frequency fosc 300 700 1,000 kHz
(*3): At Static Status
NJW4152
-
4
-Ver.2013-01-23
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, V+=VON/OFF=12V, RT=27kΩ, Ta=25°C)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Under Voltage Lockout Block
ON Threshold Voltage VT_ON V
+= L → H 4.3 4.5 4.6 V
OFF Threshold Voltage VT_OFF V
+= H → L 4.2 4.4 4.54 V
Hysteresis Voltage VHYS 60 100 – mV
Soft Start Block
Soft Start Time TSS V
B=0.75V 2 4 8 ms
Oscillator Block
Oscillation Frequency fOSC 630 700 770 kHz
Oscillation Frequency
(Low Frequency Control) fOSC_LOW V
IN-=0.4V, VFB=0.55V – 270 – kHz
RT pin Voltage VRT 0.24 0.275 0.31 V
Oscillation Frequency
deviation (Supply voltage) fDV V
+=4.6 to 40V – 1 – %
Oscillation Frequency
deviation (Temperature) fDT Ta=-40°C to +85°C – 2 – %
Error Amplifier Block
Reference Voltage VB -1.0% 0.8 +1.0% V
Input Bias Current IB -0.1 – +0.1
µA
Open Loop Gain AV – 80 – dB
Gain Bandwidth GB – 0.6 – MHz
Output Source Current IOM+ V
FB=1V, VIN-=0.7V 8 16 24
µA
Output Sink Current IOM- V
FB=1V, VIN-=0.9V 1 2 4 mA
PWM Comparate Block
Maximum Duty Cycle MAXDUTY V
IN-=0.7V 100 – – %
Output Block
A version, ISW=1A – 0.3 0.5
Ω
Output ON Resistance RON B version, ISW=0.6A – 0.28 0.48
Ω
A version 1.4 1.7 2.0 A
Switching Current Limit ILIM B version 0.8 1.0 1.3 A
Switching Leak Current ILEAK V
ON/OFF=0V, V+=45V, VSW=0V – – 1
µA
ON/OFF Block
ON Control Voltage VON V
ON/OFF= L → H 1.6 – V+ V
OFF Control Voltage VOFF V
ON/OFF= H → L 0 – 0.5 V
Pull-down Resistance RPD – 480 – kΩ
General Characteristics
Quiescent Current IDD R
L=no load, VIN-=0.7V, VFB=0.55V – 2.5 2.8 mA
Standby Current IDD_STB V
ON/OFF=0V – – 1
µA
NJW4152
-
5
-
Ver.2013-01-23
TYPICAL APPLICATIONS
C
NF
R
NF
SW
8765
1234
FB GNDIN-
RT V
+
C
FB
R2
C
OUT
L
SBD
NJW4152
V
IN
C
IN1
R1
V
OUT
R
FB
R
T
PV
+
ON/OFF
ON/OFF
High: ON
Low: OFF
(Standby)
C
IN2
NJW4152
-
6
-Ver.2013-01-23
CHARACTERISTICS
100
1000
10 100
Oscillation Frequency fOSC (kHz)
Timing Resistor vs.Oscillation Frequency
(V+=12V, Ta=25oC)
Timing Resistor R
T (kΩ)
690
695
700
705
710
0 10203040
Oscillation Frequency fOSC (kHz)
Supply Voltage V+ (V)
Oscillation Frequency vs. Supply Voltage
(RT=27kΩ, Ta=25oC)
0.79
0.795
0.8
0.805
0.81
0 10203040
Reference Voltage VB (V)
Supply Voltage V+ (V)
Reference Voltage vs. Supply Voltage
(Ta=25oC)
0
1
2
3
4
0 10203040
Quiescent Current IDD (mA)
Supply Voltage V+ (V)
Quiescent Current vs. Supply Voltage
(RL=no load, VIN-=0.5V, Ta=25oC)
0
15
30
45
60
0
45
90
135
180
0.1 1 10 100 1000 10000
Error Amplifier Block
Voltage Gain, Phase vs. Frequency
(V+=12V, Gain=40dB, Ta=25 oC)
Phase Φ (deg)
Frequency f (kHz)
Voltage Gain Av (dB)
Phase
Gain
NJW4152
-
7
-
Ver.2013-01-23
■ CHARACTERISTICS
660
680
700
720
740
-50-250 255075100125150
Ambient Temperature
Ta (oC)
Oscillator Frequency fOSC (kHz)
Oscillator Frequency vs. Temperature
(V+=12V, RT=27kΩ)
0.79
0.795
0.8
0.805
0.81
-50-250 255075100125150
Ambient Temperature
Ta (oC)
Reference Voltage VB (V)
Reference Voltage vs. Temperature
(V+=12V)
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Limited switching Current ILIM (A)
Limited Switching Current vs. Temperature
(A ver.)
V+=12V
V+=40V
V+=4.5V
0.6
0.8
1
1.2
1.4
1.6
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Limited switching Current ILIM (A)
Limited Switching Current vs. Temperature
(B ver.)
V+=12V
V+=40V
V+=4.5V
0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Output ON Resistance RON (Ω)
Output ON Resistance vs.Temperature
(A ver., ISW=1A)
V+=12V,40V
V+=4.5V
0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Output ON Resistance RON (Ω)
Output ON Resistance vs.Temperature
(B ver., ISW=0.6A)
V+=12V,40V
V+=4.5V
NJW4152
-
8
-Ver.2013-01-23
CHARACTERISTICS
4.3
4.35
4.4
4.45
4.5
4.55
4.6
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Threshold Voltage (V)
Under Voltage Lockout Voltage
vs. Temperature
VT_OFF
VT_ON
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Soft Start Time Tss (ms)
Soft Start Time vs. Temperature
(V+=12V, VB=0.75V)
0
0.5
1
1.5
2
2.5
3
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Quiescent Current IDD (mA)
Quiescent Current vs. Temperature
(RT=27kΩ, RL=no load, VIN-=0.5V)
V+=4.5V V+=12V
V+=40V
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Standby Current IDD_STB (µA)
Standby Current vs. Temperature
(VON/OFF=0V)
V+=12V
V+=4.5V
V+=40V
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125 150
Ambient Temperature
Ta (oC)
Switching Leak Current ILEAK (µA)
Switching Leak Current vs. Temperature
(V+=45V,VON/OFF=0V, VSW=0V)
NJW4152
-
9
-
Ver.2013-01-23
PIN DESCRIPTIONS
PIN
NUMBER PIN NAME FUNCTION
1 PV+ Power Supply pin for Power Line
2 V+ Power Supply pin for IC Control
3 ON/OFF
ON/OFF Control pin
The ON/OFF pin internally pulls down with 480kΩ. Normal Operation at the time
of High Level. Standby Mode at the time of Low Level or OPEN.
4 RT
Oscillating Frequency Setting pin by Timing Resistor.
Oscillating Frequency should set between 300kHz and 1MHz.
5 IN-
Output Voltage Detecting pin
Connects output voltage through the resistor divider tap to this pin in order to
voltage of the IN- pin become 0.8V.
6 FB
Feedback Setting pin
The feedback resistor and capacitor are connected between the FB pin and the
IN- pin.
7 GND GND pin
8 SW Switch Output pin of Power MOSFET
– Exposed
PAD Connect to GND (only HSOP8 PKG)
Description of Block Features
1. Basic Functions / Features
Error Amplifier Section (ER⋅AMP)
0.8V±1% precise reference voltage is connected to the non-inverted input of this section.
To set the output voltage, connects converter's output to inverted input of this section (IN- pin). If requires output
voltage over 0.8V, inserts resistor divider.
This AMP section has high gain and external feedback pin (FB pin). It is easy to insert a feedback resistor and a
capacitor between the FB pin and the IN- pin, making possible to set optimum loop compensation for each type of
application.
Oscillation Circuit Section (OSC)
Oscillation frequency can be set by inserting resistor between the RT pin and GND. Referring to the sample
characteristics in "Timing Resistor and Oscillation Frequency", set oscillation between 300kHz and 1MHz.
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
10
-Ver.2013-01-23
Description of Block Features (Continued)
PWM Comparator Section (PWM)
This section controls the switching duty ratio.
PWM comparator receives the signal of the error amplifier and the triangular wave, and controls the duty ratio
between 0% and 100%. The timing chart is shown in Fig.1.
SW pin
FB pin Voltage
ON
OFF
OSC
Wav ef orm
(IC internal)
Maximum duty: 100%
Fig. 1. Timing Chart PWM Comparator and SW pin
Power MOSFET (SW Output Section)
The power is stored in the inductor by the switch operation of built-in power MOSFET. The output current is limited
to 1.4A(min.)@A version and 0.8A(min.)@B version by the overcurrent protection function. In case of step-down
converter, the forward direction bias voltage is generated with inductance current that flows into the external
regenerative diode when MOSFET is turned off.
The SW pin allows voltage between the PV+ pin and the SW pin up to +45V. However, you should use an
Schottky diode that has low saturation voltage.
Power Supply, GND pin (V+, PV+ and GND)
In line with switching element drive, current flows into the IC according to frequency. If the power supply
impedance provided to the power supply circuit is high, it will not be possible to take advantage of IC performance
due to input voltage fluctuation. Therefore insert a bypass capacitor close to the V+ pin – the GND pin connection in
order to lower high frequency impedance.
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
11
-
Ver.2013-01-23
2. Additional and Protection Functions / Features
Under Voltage Lockout (UVLO)
The UVLO circuit operating is released above V+=4.5V(typ.) and IC operation starts. When power supply voltage
is low, IC does not operate because the UVLO circuit operates. There is 100mV width hysteresis voltage at rise and
decay of power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing.
Soft Start Function (Soft Start)
The output voltage of the converter gradually rises to a set value by the soft start function. The soft start time is
4ms (typ). It is defined with the time of the error amplifier reference voltage becoming from 0V to 0.75V. The soft start
circuit operates after the release UVLO and/or recovery from thermal shutdown. The operating frequency is
controlled with a low frequency, approximately 40% of the set value by the timing resistor, until voltage of the IN- pin
becomes approximately 0.4V.
SW pin
0.8V
FB pin Voltage
ON
OFF
Vref,
IN- pin Voltage
OSC Wavef orm
Steady
Operaton
UVLO(4.5V typ.) Release,
Standby,
Recover from Thermal
Shutdow n
Soft Start ef fective period to V
B
=0.8V
Soft Start time: Tss=4ms(typ.) to V
B
=0.75V
Low Frequency
Control
V
IN-
=approx 0.4V
Fig. 2. Startup Timing Chart
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
12
-Ver.2013-01-23
Description of Block Features (Continued)
Over Current Protection Circuit (OCP)
At when the switching current becomes ILIM or more, the overcurrent protection circuit is stopped the MOSFET
output. The switching output holds low level down to next pulse output at OCP operating.
The NJW4152 output returns automatically along with release from the over current condition because the
OCP is pulse-by-pulse type.
Fig.3. shows the timing chart of the over current protection detection.
If voltage of the IN- pin becomes less than 0.4V, the oscillation frequency decreases to approximately 40% and the
energy consumption is suppressed.
SW pin
FB pin Voltage
ON
OFF
OSC
Wav ef orm
Sw itching
Current
ILIM
0
Static Status Detec t
Overcurrent
Static Status
Fig. 3. Timing Chart at Over Current Detection
Thermal Shutdown Function (TSD)
When Junction temperature of the NJW4152 exceeds the 175°C*, internal thermal shutdown circuit function stops
SW function. When junction temperature decreases to 145°C* or less, SW operation returns with soft start operation.
The purpose of this function is to prevent malfunctioning of IC at the high junction temperature. Therefore it is not
something that urges positive use. You should make sure to operate within the junction temperature range rated
(150°C). (* Design value)
ON/OFF Function (Standby Control)
The NJW4152 stops the operating and becomes standby status when the ON/OFF pin becomes less than 0.5V.
The ON/OFF pin internally pulls down with 480kΩ, therefore the NJW4152 becomes standby mode when the
ON/OFF pin is OPEN. You should connect this pin to V+ when you do not use ON/OFF function.
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
13
-
Ver.2013-01-23
Application Information
Inductors
Large currents flow into inductor, therefore you must
provide current capacity that does not saturate.
Reducing L, the size of the inductor can be smaller.
However, peak current increases and adversely
affecting efficiency.
On the other hand, increasing L, peak current can
be reduced at switching time. Therefore conversion
efficiency improves, and output ripple voltage reduces.
Above a certain level, increasing inductance windings
increases loss (copper loss) due to the resistor
element.
Ideally, the value of L is set so that inductance current is in continuous conduction mode. However, as the load
current decreases, the current waveform changes from (1) CCM: Continuous Conduction Mode → (2) Critical Mode
→ (3) DCM: Discontinuous Conduction Mode (Fig. 4.).
In discontinuous mode, peak current increases with respect to output current, and conversion efficiency tend to
decrease. Depending on the situation, increase L to widen the load current area to maintain continuous mode.
If the application needs maximum output current, the inductor ripple current should be set less than 20% to
prevent operating the over current protection circuit at the minimum switching limiting current.
Catch Diode
When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output
capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's
forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a
low forward saturation voltage, is ideal.
An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when
the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such
factors as noise generation.
Input Capacitor
Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply
impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW4152
performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as
possible.
Output Capacitor
An output capacitor stores power from the inductor, and stabilizes voltage provided to the output.
When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple
current, and breakdown voltage.
Also, the ambient temperature affects capacitors, decreasing capacitance and increasing ESR (at low
temperature), and decreasing lifetime (at high temperature). Concerning capacitor rating, it is advisable to allow
sufficient margin.
Output capacitor ESR characteristics have a major influence on output ripple noise. A capacitor with low ESR can
further reduce ripple voltage. Be sure to note the following points; when ceramic capacitor is used, the capacitance
value decreases with DC voltage applied to the capacitor.
0
Inductor
Current ∆IL
tOFF tON
Peak Current Ipk
Frequency
fOSC
Current
(1) Continuous
Conduction Mode
(2) Critical Mode
(3) Continuous
Conduction Mode
Fig. 4. Inductor Current State Transition
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
14
-Ver.2013-01-23
Application Information (Continued)
Board Layout
In the switching regulator application, because the current flow corresponds to the oscillation frequency, the
substrate (PCB) layout becomes an important.
You should attempt the transition voltage decrease by making a current loop area minimize as much as possible.
Therefore, you should make a current flowing line thick and short as much as possible. Fig.5. shows a current loop
at step-down converter. Especially, should lay out high priority the loop of CIN-SW-SBD that occurs rapid current
change in the switching. It is effective in reducing noise spikes caused by parasitic inductance.
NJW4152
Built-in SW
C
OUT
L
SBDC
IN
V
IN
NJW4152
Built-in SW
C
OUT
L
SBDC
IN
V
IN
(a) Buck Converter SW ON (b) Buck Converter SW OFF
Fig. 5. Current Loop at Buck Converter
Concerning the GND line, it is preferred to separate the power system and the signal system, and use single
ground point.
The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has
high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance.
Fig. 6. shows example of wiring at buck converter. Fig. 7 shows the PCB layout example.
To avoid the influence of the voltage
drop, the output voltage should be
detected near the load.
SW
GND
IN-RT
V
+
C
FB
R2
C
OUT
L
SBD
NJW4152
C
IN
R1
V
OUT
R
FB
R
T
PV
+
V
IN
R
L
Because IN- pin is high impedance, the
voltage detection resistance: R1/R2 is
put as much as possible near IC(IN-).
Separate Digital(Signal)
GND f rom Pow er GND
(Bypass Capacitor)
Fig. 6. Board Layout at Buck Converter
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
15
-
Ver.2013-01-23
Application Information (Continued)
R1 R2
CFB
COUT
L
SBD
CIN1
RFB
RT
CNF
RNF
CIN2
ON/OFF
VIN VOUT
Feed back signal
Signal GND Area
Power GND Area
To
Signal GND
GND IN GNDOUT
Connect Signal GND line and Power GND line on backside pattern
Fig. 7 Layout Example (upper view)
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
16
-Ver.2013-01-23
Calculation of Package Power
A lot of the power consumption of buck converter occurs from the internal switching element (Power MOSFET).
Power consumption of NJW4152 is roughly estimated as follows.
Input Power: PIN = VIN × IIN [W]
Output Power: POUT = VOUT × IOUT [W]
Diode Loss: PDIODE = VF × IL(avg) × OFF duty [W]
NJW4152 Power Consumption: PLOSS = PIN − POUT − PDIODE [W]
Where:
VIN : Input Voltage for Converter IIN : Input Current for Converter
VOUT : Output Voltage of Converter IOUT : Output Current of Converter
VF : Diode's Forward Saturation Voltage IL(avg) : Inductor Average Current
OFF duty : Switch OFF Duty
Efficiency (η) is calculated as follows.
η = (POUT ÷ PIN) × 100 [%]
You should consider temperature derating to the calculated power consumption: PD.
You should design power consumption in rated range referring to the power dissipation vs. ambient temperature
characteristics (Fig. 8).
0
500
1000
1500
2000
2500
3000
0 25 50 75 100 125
Ambient Temperature Ta (oC)
Power Dissipation PD (mW)
HSOP8 Package
Power Dissipation vs. Ambient Temperature
(Tj= ~150oC)
At on 4 layer PC Board
At on 2 layer PC Board
Operating Temp
Expand spec
General spec
0
200
400
600
800
1000
0 25 50 75 100 125
Ambient Temperature Ta (oC)
Power Dissipation PD (mW)
MSOP8(VSP8) Package
Power Dissipation vs. Ambient Temperature
(Tj= ~150oC)
At on 4 layer PC Board
At on 2 layer PC Board
Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 2Layers)
Mounted on glass epoxy board. (76.2×114.3×1.6mm:EIA/JDEC standard size, 4Layers),
internal Cu area: 74.2×74.2mm
Fig. 8. Power Dissipation vs. Ambient Temperature Characteristics
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
17
-
Ver.2013-01-23
Application Design Examples
Step-Down Application Circuit
IC
Input Voltage
: NJW4152GM1
: VIN=12V
Output Voltage : VOUT=5V
Output Current : IOUT=1A
Oscillation frequency : fosc=700kHz
Output Ripple Voltage : Vripple(P-P)=less than 20mV
C
NF
4,700pF
R
NF
3.3kΩ
SW
8765
1234
FB GNDIN-
RT V
+
C
FB
220pF R2
27kΩ
C
OUT
4.7µF/6.3V
L 22µH/2.5A
SBD
NJW4152GM1
V
IN
=12V
C
IN1
10µF/50V
R1
5.1kΩ
V
OUT
=5V
R
FB
0
Ω
R
T
27kΩPV
+
ON/OFF
ONOFF
High: ON
Low: OFF
(Standby)
C1
open
C
IN2
0.1µF/50V
Reference Qty. Part Number Description Manufacturer
IC 1 NJW4152GM1 Internal 1A MOSFET SW.REG. IC New JRC
L 1 CDRH8D28HPNP-220N
Inductor 22µH,
2.5A(Ta=20°C) / 1.9A (Ta=100°C) Sumida
D 1 CMS11 Schottky Diode 40V, 2A Toshiba
CIN1 1 UMK325BJ106MM
Ceramic Capacitor 3225 10µF, 50V, X5R Taiyo Yuden
CIN2 1
0.1µF Ceramic Capacitor 1608 0.1µF, 50V, B Std.
COUT 1 JMK212ABJ475KG
Ceramic Capacitor 2012 4.7µF, 6. 3 V, X5R Taiyo Yuden
CNF 1 4,700pF Ceramic Capacitor 1608 4,700pF, 50V, B Std.
CFB 1 220pF Ceramic Capacitor 1608 220pF, 50V, CH Std.
C1 0
⎯ (Optional) Optional ⎯
R1 1
5.1kΩ Resistor 1608 5.1kΩ, ±1%, 0.1W Std.
R2, RT 2
27kΩ Resistor 1608 27kΩ, ±1%, 0.1W Std.
RNF 1
3.3kΩ Resistor 1608 3.3kΩ, ±5%, 0.1W Std.
RFB 1
0Ω (Short) Resistor 1608 0Ω, 0.1W Std.
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
18
-Ver.2013-01-23
Application Design Examples (Continued)
Setting Oscillation Frequency
From the Oscillation frequency vs. Timing Resistor
Characteristic, RT=27 [kΩ], t=1.43[µs] at fosc=700kHz.
Step-down converter duty ratio is shown with the following
equation.
[]
%45100
12 4.05
100 =×
+
=×
+
=
IN
FOUT
V
VV
Duty
Therefore, tON=0.64 [µs], tOFF=0.79 [µs]
Fig. 9. Inductor Current Waveform
Selecting Inductance
To assume maximum output current: 1A, and the inductor ripple current should be set not to exceed the minimum
switching limiting current: ILIM=1.4A (min.).
∆IL is Inductance ripple current. When to ∆IL= output current 20%:
∆IL = 0.2 × IOUT = 0.2 × 1 = 0.2 [A]
This obtains inductance L. VDS_RON is drop voltage by MOSFET on resistance.
ON
L
OUTRONDSIN t
IVVV
L×
∆
−−
=−][8.2064.0
2.0 55.012 H
µµ
=×
−
−
=⇒ 22[µH]
Inductance L is a theoretical value. The optimum value varies according such factors as application specifications
and components. Fine-tuning should be done on the actual device.
This obtains the peak current Ipk at switching time.
][1.1
22.0
1
2A
I
IIpk L
OUT =+=
∆
+=
The current that flows into the inductance provides sufficient margin for peak current at switching time.
In the application circuit, use L=22µH, 2.5A(Ta=20°C) / 1.9A (Ta=100°C).
0
tOFF tON
Period: t
Frequency: fOSC=1/t
Inductance
Current: ∆IL
Output Current: IOUT
Peak Current: Ipk
Technical Information
NJW
41
5
2
A
pplication Manual
NJW4152
-
19
-
Ver.2013-01-23
Application Design Examples (Continued)
Selecting the Input Capacitor
The input capacitor corresponds to the input of the power supply. It is required to adequately reduce the
impedance of the power supply. The input capacitor selection should be determined by the input ripple current and
the maximum input voltage of the capacitor rather than its capacitance value.
The effective input current can be expressed by the following formula.
()
][A
V
VVV
II
IN
OUTINOUT
OUTRMS
−×
×=
In the above formula, the maximum current is obtained when VIN = 2 × VOUT, and the result in this case is
IRMS = IOUT (MAX) ÷ 2.
When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has
adequate margin.
Selecting the Output Capacitor
The output capacitor is an important component that determines output ripple noise. Equivalent Series Resistance
(ESR), ripple current, and capacitor breakdown voltage are important in determining the output capacitor.
The output ripple noise can be expressed by the following formula.
L
ppripple
I
V
ESR ∆
=−)(
When selecting output capacitance, select a capacitor that allows for sufficient ripple current.
The effective ripple current that flows in a capacitor (Irms) is obtained by the following equation.
][58
32
2.0
32 mArms
I
IL
rms ==
∆
=
Consider sufficient margin, and use a capacitor that fulfills the above spec.
In the application circuit, use COUT=4.7µF/6.3V.
Setting Output Voltage
The output voltage VOUT is determined by the relative resistances of R1, R2. The current that flows in R1, R2 must
be a value that can ignore the bias current that flows in ER AMP.
][04.58.01
1.5
27
1
1
2V
k
k
V
R
R
VBOUT =×
⎟
⎠
⎞
⎜
⎝
⎛+=×
⎟
⎠
⎞
⎜
⎝
⎛+=
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
20
-Ver.2013-01-23
Compensation design example
A switching regulator requires a feedback circuit for acquiring a stable
output. Because the frequency characteristics of the application change
according to the inductance, output capacitor, and so on, the compensation
constant should ideally be determined in such a way that the maximum band
is acquired while the necessary phase for stable operation is maintained.
These compensation constants play an important role in the adjustment of
the NJW4152 when mounted in an actual unit. Finally, select the constants
while performing measurement, in consideration of the application
specifications.
Feedback and Stability
Basically, the feedback loop should be designed in such a way that the
open loop phase shift at the point where the loop gain is 0 dB is less than
-180°. It is also important that the loop characteristics have margin in
consideration of ringing and immunity to oscillation during load fluctuations.
With the NJW4152, the feedback circuit can be freely designed, enabling the
arrangement of the poles and zeros which is important for loop compensation,
to be optimized.
The characteristics of the poles and zeros are shown in Fig. 10.
Poles: The gain has a slope of -20 dB/dec, and the phase shifts -90°.
Zeros: The gain has a slope of +20 dB/dec, and the phase shift +90°.
If the number of factors constituting poles is defined as “n”, the change in the gain and phase will be “n”-fold. This
also applies to zeros as well. The poles and zeros are in a reciprocal relationship, so if there is one factor for each
pole and zero, they will cancel each other.
Configuration of the compensation circuit
VOUT
CFB
C1(option)
RESR
COUT
L
Buffer
VIN
PWM
LC Gain
CNF R
NF
Vref
=0.8V
IN-
FB
ER⋅AMP
R2
R1
CFB
RFB
SW
PV+
Fig. 11. Compensation Circuit Configuration
Fig. 10. Characteristics of Pole and Zero
Gain Phase
-20dB/dec
fP/10 10fP
fP
-45°
0°
-90°
Frequency
Gain Phase
+20dB/dec
fZ/10 10fZ
fZ
+45°
0°
+90°
Frequency
Pole
Zero
Pole
Zero
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
21
-
Ver.2013-01-23
Compensation Design (Continued)
Poles and zeros due to the inductance and output capacitor
Double poles fP(LC) are generated by the inductance and output capacitor. Simultaneously, single zeros fZ(ESR) are
generated by the output capacitor and ESR. Each pole and zero is expressed by the following formula.
ESROUT
)ESR(Z RC2
1
fπ
=
OUT
)LC(P LC2
1
fπ
=
If the ESR of the output capacitor is high, fZ(ESR) will be located in the vicinity of fP(LC). In an application such as this,
the zero fZ(ESR) compensates the double poles fP(LC), resulting in a tendency for stability to be readily maintained.
However, if the ESR of the output capacitor is low, fZ(ESR) shifts to the high region, and the phase is shifted -180° by
fP(LC).The NJW4152 compensation circuit enables compensation to be realized by using zeros fZ1 and fZ2.
Poles and zeros due to error amplifier
The single poles and zeros generated by the error amplifier
are obtained using the following formula.
Zero Pole
NFNF
1Z RC2
1
fπ
=
⎟
⎠
⎞
⎜
⎝
⎛
+
π
=
2R1R
2R1R
AC2
1
f
VNF
1P
(Av: Amplifier Open Loop Gain=80dB)
2RC2
1
f
FB
2Z π
= ⎟
⎠
⎞
⎜
⎝
⎛
+
+π
=
2R1R
2R1R
RC2
1
f
FBFB
2P
NF
3P R1C2
1
fπ
=
(Option)
fZ1 and fZ2 are located on both sides of fP(LC).
Because the inductance and output capacitor vary, they are
each set using the following as a rough guide.
fP(LC) × 0.5-fold – 0.9-fold
fP(LC) × 1.1-fold – 2.0-fold
There is also a method in which fZ1 and fZ2 are located at positions lower than even fP(LC). Because there is a
tendency for the phase shift to increase and the gain to rise, it can be expected that the response will improve.
However, there is a tendency for the phase margin to become insufficient, so care is necessary.
fP1 creates poles in the low frequency region due to the Miller effect of the error amplifier. The stability becomes
better as fP1 becomes lower. On the other hand, the frequency characteristics do not improve, so the response is
adversely affected. fP1 is set using a frequency gain of 20 dB for fP(LC) as a rough guide.
If the open loop gain of the error amplifier is made 80 dB, design is carried out using fP1 < fP(LC) ÷ 103 (= 60 dB) as a
rough guide.
Above several 100 kHz, various poles are generated, so the upper limit of the frequency range where the loop
gain is 0 dB is set to fifth (1/5) to tenth (1/10) of oscillation frequency. The fZ(ESR) in the high frequency region
sometimes causes a loop gain to be generated (See Fig.12 Loop Gain “). Using fP2 and fP3, perform adjustment with
the NJW4152 mounted in an actual unit, so as to adequately reduce the loop gain in the high frequency region.
Fig12. Loop Gain examples
fZ1 or fZ2
fP(LC) fP2 f
P3 fZ(ESR)
Gain (dB)
LC Gain
Loop
Gain
Compensation
Gain
-40dB/dec -20dB/dec
0dB frequency
Double
pole
fP1
* Gain increase
due to Zero
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
22
-Ver.2013-01-23
■Application Characteristics :NJW4152GM1-A
● At VOUT=5.0V setting (R1=5.1kΩ, R2=27kΩ, CFB=220pF, RFB=0Ω)
0
10
20
30
40
50
60
70
80
90
100
1101001000
VIN=6V
VIN=12V
VIN=18V
VIN=24V
Output Current I
OUT (mA)
Efficiency η (%)
Efficiency vs. Output Current
(VOUT=5.0V, Ta=25oC)
f=700kHz
L=22µH
4.8
4.85
4.9
4.95
5
5.05
5.1
5.15
5.2
1 10 100 1000
Output Voltage VOUT (V)
Output Voltage vs. Output Current
(Ta=25oC)
Output Current I
OUT (mA)
f=700kHz
L=22µH
VIN=6V,12V, 18V, 24V
● At VOUT=3.3V setting (R1=5.1kΩ, R2=16kΩ, CFB=220pF, RFB=0Ω)
0
10
20
30
40
50
60
70
80
90
100
1101001000
VIN=5V
VIN=12V
VIN=18V
VIN=24V
Output Current I
OUT (mA)
Efficiency η (%)
Efficiency vs. Output Current
(VOUT=3.3V, Ta=25oC)
f=700kHz
L=22µH
3.24
3.26
3.28
3.3
3.32
3.34
3.36
1 10 100 1000
Output Voltage VOUT (V)
Output Voltage vs. Output Current
(Ta=25oC)
Output Current I
OUT (mA)
f=700kHz
L=22µH
VIN=5V,12V, 18V, 24V
● At VOUT=1.5V setting (R1=30kΩ, R2=27kΩ, CFB=220pF, RFB=10kΩ)
0
10
20
30
40
50
60
70
80
90
100
1101001000
VIN=5V
VIN=12V
VIN=18V
VIN=24V
Output Current I
OUT (mA)
Efficiency η (%)
Efficiency vs. Output Current
(VOUT=1.5V, Ta=25oC)
f=700kHz
L=22µH
1.44
1.46
1.48
1.5
1.52
1.54
1.56
1 10 100 1000
Output Voltage VOUT (V)
Output Voltage vs. Output Current
(Ta=25oC)
Output Current I
OUT (mA)
f=700kHz
L=22µH
VIN=5V,12V, 18V, 24V
Technical Information
NJW
41
5
2
Application Manual
NJW4152
-
23
-
Ver.2013-01-23
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
