NAND Flash Memory
MT29F4G08ABADAH4, MT29F4G08ABADAWP, MT29F4G08ABBDAH4,
MT29F4G08ABBDAHC, MT29F4G16ABADAH4, MT29F4G16ABADAWP,
MT29F4G16ABBDAH4, MT29F4G16ABBDAHC, MT29F8G08ADADAH4,
MT29F8G08ADBDAH4, MT29F8G16ADADAH4, MT29F8G16ADBDAH4,
MT29F16G08AJADAWP
Features
Open NAND Flash Interface (ONFI) 1.0-compliant1
Single-level cell (SLC) technology
Organization
Page size x8: 2112 bytes (2048 + 64 bytes)
Page size x16: 1056 words (1024 + 32 words)
Block size: 64 pages (128K + 4K bytes)
Plane size: 2 planes x 2048 blocks per plane
Device size: 4Gb: 4096 blocks; 8Gb: 8192 blocks
16Gb: 16,384 blocks
Asynchronous I/O performance
tRC/tWC: 20ns (3.3V), 25ns (1.8V)
Array performance
Read page: 25µs 3
Program page: 200µs (TYP: 1.8V, 3.3V)3
Erase block: 700µs (TYP)
Command set: ONFI NAND Flash Protocol
Advanced command set
Program page cache mode4
Read page cache mode 4
One-time programmable (OTP) mode
Two-plane commands 4
Interleaved die (LUN) operations
Read unique ID
Block lock (1.8V only)
Internal data move
Operation status byte provides software method for
detecting
Operation completion
Pass/fail condition
Write-protect status
Ready/Busy# (R/B#) signal provides a hardware
method of detecting operation completion
WP# signal: Write protect entire device
First block (block address 00h) is valid when ship-
ped from factory with ECC. For minimum required
ECC, see Error Management.
Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-
cles are less than 1000
RESET (FFh) required as first command after pow-
er-on
Alternate method of device initialization (Nand_In-
it) after power up (contact factory)
Internal data move operations supported within the
plane from which data is read
Quality and reliability
Data retention: 10 years
Endurance: 100,000 PROGRAM/ERASE cycles
Operating voltage range
VCC: 2.7–3.6V
VCC: 1.7–1.95V
Operating temperature:
Commercial: 0°C to +70°C
Industrial (IT): –40ºC to +85ºC
Package
48-pin TSOP type 1, CPL2
63-ball VFBGA
Notes: 1. The ONFI 1.0 specification is available at
www.onfi.org.
2. CPL = Center parting line.
3. See Program and Erase Characteristics for
tR_ECC and tPROG_ECC specifications.
4. These commands supported only with ECC
disabled.
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Products and specifications discussed herein are subject to change by Micron without notice.
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Marketing Part Number Chart
MT 29F 4G 08 A B A D A WP IT ES :D
Micron Technology
Product Family
29F = NAND Flash memory
Density
4G = 4Gb
8G = 8Gb
16G = 16Gb
Device Width
08 = 8-bit
16 = 16-bit
Level
A = SLC
Classification
Mark Die nCE RnB I/O Channels
B 1 1 1 1
D 2 1 1 1
Operating Voltage Range
A = 3.3V (2.7–3.6V)
B = 1.8V (1.7–1.95V)
Feature Set
D = Feature set D
Design Revision (shrink)
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
QS = Qualification sample
Special Options
Blank
X = Product longevity program (PLP)
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade
Blank
Package Code
WP = 48-pin TSOP 1
HC = 63-ball VFBGA (10.5 x 13 x 1.0mm)
H4 = 63-ball VFBGA (9 x 11 x 1.0mm)
Interface
A = Async only
J 4 2 12
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Contents
General Description ......................................................................................................................................... 8
Signal Descriptions ........................................................................................................................................... 8
Signal Assignments ........................................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 12
Architecture ................................................................................................................................................... 15
Device and Array Organization ........................................................................................................................ 16
Asynchronous Interface Bus Operation ........................................................................................................... 20
Asynchronous Enable/Standby ................................................................................................................... 20
Asynchronous Commands .......................................................................................................................... 20
Asynchronous Addresses ............................................................................................................................ 22
Asynchronous Data Input ........................................................................................................................... 23
Asynchronous Data Output ......................................................................................................................... 24
Write Protect# ............................................................................................................................................ 25
Ready/Busy# .............................................................................................................................................. 25
Device Initialization ....................................................................................................................................... 30
Command Definitions .................................................................................................................................... 31
Reset Operations ............................................................................................................................................ 34
RESET (FFh) ............................................................................................................................................... 34
Identification Operations ................................................................................................................................ 35
READ ID (90h) ............................................................................................................................................ 35
READ ID Parameter Tables .............................................................................................................................. 36
READ PARAMETER PAGE (ECh) ...................................................................................................................... 39
Parameter Page Data Structure Tables ............................................................................................................. 40
Bare Die Parameter Page Data Structure Tables ................................................................................................ 45
READ UNIQUE ID (EDh) ................................................................................................................................ 48
Feature Operations ......................................................................................................................................... 49
SET FEATURES (EFh) .................................................................................................................................. 50
GET FEATURES (EEh) ................................................................................................................................. 51
Status Operations ........................................................................................................................................... 54
READ STATUS (70h) ................................................................................................................................... 55
READ STATUS ENHANCED (78h) ................................................................................................................ 55
Column Address Operations ........................................................................................................................... 57
RANDOM DATA READ (05h-E0h) ................................................................................................................ 57
RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ 58
RANDOM DATA INPUT (85h) ...................................................................................................................... 59
PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 60
Read Operations ............................................................................................................................................. 62
READ MODE (00h) ..................................................................................................................................... 64
READ PAGE (00h-30h) ................................................................................................................................ 64
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 65
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 66
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 68
READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 69
Program Operations ....................................................................................................................................... 71
PROGRAM PAGE (80h-10h) ......................................................................................................................... 72
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 72
PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 75
Erase Operations ............................................................................................................................................ 77
ERASE BLOCK (60h-D0h) ............................................................................................................................ 77
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 78
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Internal Data Move Operations ....................................................................................................................... 79
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 80
PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 81
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 82
Block Lock Feature ......................................................................................................................................... 83
WP# and Block Lock ................................................................................................................................... 83
UNLOCK (23h-24h) .................................................................................................................................... 83
LOCK (2Ah) ................................................................................................................................................ 86
LOCK TIGHT (2Ch) ..................................................................................................................................... 87
BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 88
One-Time Programmable (OTP) Operations .................................................................................................... 90
Legacy OTP Commands .............................................................................................................................. 90
OTP DATA PROGRAM (80h-10h) ................................................................................................................. 91
RANDOM DATA INPUT (85h) ...................................................................................................................... 92
OTP DATA PROTECT (80h-10) ..................................................................................................................... 93
OTP DATA READ (00h-30h) ......................................................................................................................... 95
Two-Plane Operations .................................................................................................................................... 97
Two-Plane Addressing ................................................................................................................................ 97
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 106
Error Management ........................................................................................................................................ 107
Internal ECC and Spare Area Mapping for ECC ............................................................................................... 109
Electrical Specifications ................................................................................................................................. 111
Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 113
Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 115
Electrical Specifications – Program/Erase Characteristics ................................................................................ 118
Asynchronous Interface Timing Diagrams ...................................................................................................... 119
Revision History ............................................................................................................................................ 131
Rev. N – 10/12 ............................................................................................................................................ 131
Rev. M – 02/12 ........................................................................................................................................... 131
Rev. L – 1/12 .............................................................................................................................................. 131
Rev. K – 11/11 ............................................................................................................................................ 131
Rev. J – 09/11 ............................................................................................................................................. 131
Rev. I – 07/11 ............................................................................................................................................. 131
Rev. H – 12/10 ............................................................................................................................................ 131
Rev. G – 10/10 ............................................................................................................................................ 131
Rev. F – 06/10 ............................................................................................................................................ 131
Rev. E – 05/10 ............................................................................................................................................ 131
Rev. D – 03/10 ............................................................................................................................................ 132
Rev. C – 01/10 ............................................................................................................................................ 132
Rev. B – 10/09 ............................................................................................................................................ 132
Rev. A – 07/09 ............................................................................................................................................ 132
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List of Tables
Table 1: Signal Definitions ............................................................................................................................... 8
Table 2: Array Addressing – MT29F4G08 (x8) .................................................................................................. 16
Table 3: Array Addressing – MT29F4G16 (x16) ................................................................................................. 17
Table 4: Array Addressing – MT29F8G08 and MT29F16G08 (x8) ....................................................................... 18
Table 5: Array Addressing – MT29F8G16 ( x16) ................................................................................................ 19
Table 6: Asynchronous Interface Mode Selection ............................................................................................ 20
Table 7: Command Set .................................................................................................................................. 31
Table 8: Two-Plane Command Set .................................................................................................................. 33
Table 9: READ ID Parameters for Address 00h ................................................................................................. 36
Table 10: READ ID Parameters for Address 20h ............................................................................................... 38
Table 11: Parameter Page Data Structure ........................................................................................................ 40
Table 12: Parameter Page Data Structure ........................................................................................................ 45
Table 13: Feature Address Definitions ............................................................................................................. 49
Table 14: Feature Address 90h – Array Operation Mode ................................................................................... 50
Table 15: Feature Addresses 01h: Timing Mode ............................................................................................... 52
Table 16: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 53
Table 17: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 53
Table 18: Status Register Definition ................................................................................................................ 54
Table 19: Block Lock Address Cycle Assignments ............................................................................................ 85
Table 20: Block Lock Status Register Bit Definitions ........................................................................................ 88
Table 21: Error Management Details ............................................................................................................. 107
Table 22: Absolute Maximum Ratings ............................................................................................................ 111
Table 23: Recommended Operating Conditions ............................................................................................. 111
Table 24: Valid Blocks ................................................................................................................................... 111
Table 25: Capacitance ................................................................................................................................... 112
Table 26: Test Conditions .............................................................................................................................. 112
Table 27: DC Characteristics and Operating Conditions (3.3V) ....................................................................... 113
Table 28: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 114
Table 29: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 115
Table 30: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 115
Table 31: AC Characteristics: Normal Operation (3.3V) .................................................................................. 116
Table 32: AC Characteristics: Normal Operation (1.8V) .................................................................................. 116
Table 33: Program/Erase Characteristics ....................................................................................................... 118
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List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 48-Pin TSOP – Type 1 (Top View) ........................................................................................................ 9
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP – Type 1, CPL ............................................................................................................... 12
Figure 6: 63-Ball VFBGA (10.5mm x 13mm) .................................................................................................... 13
Figure 7: 63-Ball VFBGA (9mm x 11mm) ......................................................................................................... 14
Figure 8: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 15
Figure 9: Array Organization – MT29F4G08 (x8) .............................................................................................. 16
Figure 10: Array Organization – MT29F4G16 (x16) .......................................................................................... 17
Figure 11: Array Organization – MT29F8G08 and MT29F16G08 (x8) ................................................................. 18
Figure 12: Array Organization – MT29F8G16 (x16) .......................................................................................... 19
Figure 13: Asynchronous Command Latch Cycle ............................................................................................ 21
Figure 14: Asynchronous Address Latch Cycle ................................................................................................ 22
Figure 15: Asynchronous Data Input Cycles .................................................................................................... 23
Figure 16: Asynchronous Data Output Cycles ................................................................................................. 24
Figure 17: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 25
Figure 18: READ/BUSY# Open Drain .............................................................................................................. 26
Figure 19: tFall and tRise (3.3V VCC) ................................................................................................................ 27
Figure 20: tFall and tRise (1.8V VCC) ................................................................................................................ 27
Figure 21: IOL vs. Rp (VCC = 3.3V VCC) .............................................................................................................. 28
Figure 22: IOL vs. Rp (1.8V VCC) ....................................................................................................................... 28
Figure 23: TC vs. Rp ....................................................................................................................................... 29
Figure 24: R/B# Power-On Behavior ............................................................................................................... 30
Figure 25: RESET (FFh) Operation .................................................................................................................. 34
Figure 26: READ ID (90h) with 00h Address Operation .................................................................................... 35
Figure 27: READ ID (90h) with 20h Address Operation .................................................................................... 35
Figure 28: READ PARAMETER (ECh) Operation .............................................................................................. 39
Figure 29: READ UNIQUE ID (EDh) Operation ............................................................................................... 48
Figure 30: SET FEATURES (EFh) Operation .................................................................................................... 50
Figure 31: GET FEATURES (EEh) Operation .................................................................................................... 51
Figure 32: READ STATUS (70h) Operation ...................................................................................................... 55
Figure 33: READ STATUS ENHANCED (78h) Operation ................................................................................... 56
Figure 34: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 57
Figure 35: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 58
Figure 36: RANDOM DATA INPUT (85h) Operation ........................................................................................ 59
Figure 37: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 61
Figure 38: READ PAGE (00h-30h) Operation ................................................................................................... 65
Figure 39: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 65
Figure 40: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 66
Figure 41: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 67
Figure 42: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 68
Figure 43: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 70
Figure 44: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 72
Figure 45: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 74
Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 74
Figure 47: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ....................................................................... 76
Figure 48: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 77
Figure 49: ERASE BLOCK TWO-PLANE (60h–D1h) Operation .......................................................................... 78
Figure 50: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 80
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Figure 51: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 80
Figure 52: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 81
Figure 53: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ............ 81
Figure 54: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ........................................................ 81
Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 82
Figure 56: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation .................................... 82
Figure 57: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 84
Figure 58: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 84
Figure 59: UNLOCK Operation ....................................................................................................................... 85
Figure 60: LOCK Operation ............................................................................................................................ 86
Figure 61: LOCK TIGHT Operation ................................................................................................................. 87
Figure 62: PROGRAM/ERASE Issued to Locked Block ...................................................................................... 88
Figure 63: BLOCK LOCK READ STATUS .......................................................................................................... 88
Figure 64: BLOCK LOCK Flowchart ................................................................................................................ 89
Figure 65: OTP DATA PROGRAM (After Entering OTP Operation Mode) ........................................................... 92
Figure 66: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) ... 93
Figure 67: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................. 94
Figure 68: OTP DATA READ ........................................................................................................................... 95
Figure 69: OTP DATA READ with RANDOM DATA READ Operation ................................................................. 96
Figure 70: TWO-PLANE PAGE READ .............................................................................................................. 98
Figure 71: TWO-PLANE PAGE READ with RANDOM DATA READ .................................................................... 99
Figure 72: TWO-PLANE PROGRAM PAGE ....................................................................................................... 99
Figure 73: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT .......................................................... 100
Figure 74: TWO-PLANE PROGRAM PAGE CACHE MODE ............................................................................... 101
Figure 75: TWO-PLANE INTERNAL DATA MOVE ........................................................................................... 102
Figure 76: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ............................ 103
Figure 77: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT ............................................... 104
Figure 78: TWO-PLANE BLOCK ERASE ......................................................................................................... 105
Figure 79: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ........................................................................ 105
Figure 80: Spare Area Mapping (x8) ............................................................................................................... 109
Figure 81: Spare Area Mapping (x16) ............................................................................................................. 110
Figure 82: RESET Operation .......................................................................................................................... 119
Figure 83: READ STATUS Cycle ..................................................................................................................... 119
Figure 84: READ STATUS ENHANCED Cycle .................................................................................................. 120
Figure 85: READ PARAMETER PAGE ............................................................................................................. 120
Figure 86: READ PAGE .................................................................................................................................. 121
Figure 87: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 122
Figure 88: RANDOM DATA READ .................................................................................................................. 123
Figure 89: READ PAGE CACHE SEQUENTIAL ................................................................................................ 124
Figure 90: READ PAGE CACHE RANDOM ...................................................................................................... 125
Figure 91: READ ID Operation ...................................................................................................................... 126
Figure 92: PROGRAM PAGE Operation .......................................................................................................... 126
Figure 93: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 127
Figure 94: PROGRAM PAGE Operation with RANDOM DATA INPUT .............................................................. 127
Figure 95: PROGRAM PAGE CACHE .............................................................................................................. 128
Figure 96: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 128
Figure 97: INTERNAL DATA MOVE ............................................................................................................... 129
Figure 98: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 129
Figure 99: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled ................. 130
Figure 100: ERASE BLOCK Operation ............................................................................................................ 130
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General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
This device has an internal 4-bit ECC that can be enabled using the GET/SET features.
See Internal ECC and Spare Area Mapping for ECC for more information.
Signal Descriptions
Table 1: Signal Definitions
Signal1Type Description2
ALE Input Address latch enable: Loads an address from I/O[7:0] into the address register.
CE#
CE#2
Input Chip enable: Enables or disables one or more die (LUNs) in a target.
For the 16Gb device, CE# controls the first 8Gb of memory; CE2# controls the second 8Gb
of memory.
CLE Input Command latch enable: Loads a command from I/O[7:0] into the command register.
LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the
BLOCK LOCK, connect LOCK to VSS during power-up, or leave it disconnected (internal
pull-down).
RE# Input Read enable: Transfers serial data from the NAND Flash to the host system.
WE# Input Write enable: Transfers commands, addresses, and serial data from the host system to the
NAND Flash.
WP# Input Write protect: Enables or disables array PROGRAM and ERASE operations.
I/O[7:0] (x8)
I/O[15:0] (x16)
I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and command infor-
mation.
R/B#
R/B#2
Output Ready/busy: An open-drain, active-low output that requires an external pull-up resistor.
This signal indicates target array activity.
For the 16Gb device, R/B# indicates the status of the first 8Gb of memory; R/B# indicates
the status of the second 8Gb of memory.
VCC Supply VCC: Core power supply
VSS Supply VSS: Core ground connection
NC No connect: NCs are not internally connected. They can be driven or left unconnected.
DNU Do not use: DNUs must be left unconnected.
Notes: 1. See Device and Array Organization for detailed signal connections.
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2. See Asynchronous Interface Bus Operation for detailed asynchronous interface signal
descriptions.
Signal Assignments
Figure 2: 48-Pin TSOP – Type 1 (Top View)
x8
NC
NC
NC
NC
NC
R/B2#3
R/B#
RE#
CE#
CE2#3
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
x16
NC
NC
NC
NC
NC
R/B#23
R/B#
RE#
CE#
CE2#3
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
x8
VSS1
DNU
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC1
DNU2
VCC
VSS
NC
VCC1
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
DNU
VSS1
x16
VSS
I/O15
I/O14
I/O13
I/O7
I/O6
I/O5
I/O4
I/O12
VCC
DNU2
VCC
VSS
NC
VCC
I/O11
I/O3
I/O2
I/O1
I/O0
I/O10
I/O9
I/O8
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Notes: 1. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
2. For the 3V device, pin 38 is DNU. For the 1.8V device, pin 38 is LOCK.
3. R/B2# and CE2# are available on 16Gb devices only. They are NC for other configura-
tions.
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Signal Assignments
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Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View)
3
WP#
Vcc2
NC
NC
DNU
NC
NC
Vss
1
NC
NC
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
2
NC
NC
NC
8
R/B#
NC
NC
NC
DNU
Vcc
I/O7
Vss
10
NC
NC
NC
NC
9
NC
NC
NC
NC
5
Vss
CLE
NC
NC
LOCK1
NC
NC
I/O3
7
WE#
NC
NC
Vss2
NC
NC
I/O5
I/O6
6
CE#
NC
NC
NC
NC
NC
Vcc
I/O4
4
ALE
RE#
NC
NC
Vcc2
I/O0
I/O1
I/O2
Notes: 1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V de-
vice.
2. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Signal Assignments
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Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View)
3
WP#
Vcc
NC
NC
DNU
I/O8
I/O9
Vss
4
ALE
RE#
NC
NC
Vcc
I/O0
I/O1
I/O2
8
R/B#
NC
NC
NC
DNU
Vcc
I/O7
Vss
10
NC
NC
NC
NC
9
NC
NC
NC
NC
5
Vss
CLE
NC
NC
LOCK1
I/O10
I/O11
I/O3
7
WE#
NC
NC
Vss
I/O15
I/O14
I/O5
I/O6
6
CE#
NC
NC
NC
I/O13
I/O12
Vcc
I/O4
1
NC
NC
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
2
NC
NC
NC
Note: 1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V de-
vice.
Micron Confidential and Proprietary
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Signal Assignments
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Package Dimensions
Figure 5: 48-Pin TSOP – Type 1, CPL
1.20 MAX
0.15 +0.03
-0.02
0.27 MAX
0.17 MIN
See detail A
18.40 ±0.08
20.00 ±0.25
Detail A
0.50 ±0.1
0.80
0.10 +0.10
-0.05
0.10
0.25
Gage
plane
0.25
for reference only
0.50 TYP
for reference
only
12.00 ±0.08
1
24
48
25
Plated lead finish:
100% Sn
Mold compound:
Epoxy novolac
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
Note: 1. All dimensions are in millimeters.
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Package Dimensions
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Figure 6: 63-Ball VFBGA (10.5mm x 13mm)
Ball A1 ID
1.0 MAX
13 ±0.1
Ball A1 ID
0.8 TYP
10.5 ±0.1
0.65 ±0.05
Seating
plane
A
8.8 CTR
7.2 CTR
0.12 A
63X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-
reflow on Ø0.4 SMD
ball pads.
0.25 MIN
0.8 TYP
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
Bottom side saw fiducials may or
may not be covered with soldermask.
Note: 1. All dimensions are in millimeters.
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Package Dimensions
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Figure 7: 63-Ball VFBGA (9mm x 11mm)
Ball A1 ID
Seating
plane
0.1 A
A
1.0 MAX
0.25 MIN
9 ±0.1
Ball A1 ID
(covered by SR)
8.8 CTR
Dimensions apply
to solder balls post-
reflow on Ø0.4 SMD
ball pads.
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu). A
B
C
D
E
F
G
H
J
K
L
M
10 9 8 7 6 5 4 3 2 1
63X Ø0.45
11 ±0.1
0.8 TYP
0.8 TYP
7.2 CTR
Note: 1. All dimensions are in millimeters.
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Package Dimensions
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Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row de-
coder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word
by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput. The status register reports
the status of die operations.
Figure 8: NAND Flash Die (LUN) Functional Block Diagram
Address register
Data register
Cache register
ECC
Status register
Command register
CE#
VCC VSS
CLE
ALE
WE#
RE#
WP#
LOCK1
I/Ox
Control
logic
I/O
control
R/B#
Row decode
Column decode
NAND Flash
array
(2 planes)
Note: 1. The LOCK pin is used on the 1.8V device.
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4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Architecture
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Device and Array Organization
Figure 9: Array Organization – MT29F4G08 (x8)
Cache Register
Data Register
2048 blocks
per plane
4096 blocks
per device
1 block 1 block
DQ0
DQ7
1 page = (2K + 64 bytes)
1 block = (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
1 plane = (128K + 4K) bytes x 2048 blocks
= 2112Mb
1 device = 2112Mb x 2 planes
= 4224Mb
Plane of
even-numbered blocks
(0, 2, 4, 6, ..., 4092, 4094)
Plane of
odd-numbered blocks
(1, 3, 5, 7, ..., 4093, 4095)
642048 64
2112 bytes2112 bytes
6464
2048
2048
2048
Table 2: Array Addressing – MT29F4G08 (x8)
Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00
First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Fifth LOW LOW LOW LOW LOW LOW BA17 BA16
Notes: 1. Block address concatenated with page address = actual page address. CAx = column ad-
dress; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:6] must be 0.
3. BA6 controls plane selection.
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Device and Array Organization
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Figure 10: Array Organization – MT29F4G16 (x16)
Cache Register
Data Register
2048 blocks
per plane
4096 blocks
per device
1 block 1 block
1 page = (1K + 32 words)
1 block = (1K + 32) words x 64 pages
= (64K + 2K) words
1 plane = (64K + 2K) words x 2048 blocks
= 2112Mb
1 device = 2112Mb x 2 planes
= 4224Mb
Plane of
even-numbered blocks
(0, 2, 4, 6, ..., 4092, 4094)
Plane of
odd-numbered blocks
(1, 3, 5, 7, ..., 4093, 4095)
32
1024 32
1056 words
DQ0
DQ15
1056 words
32
32
1024
1024
1024
Table 3: Array Addressing – MT29F4G16 (x16)
Cycle I/O[15:8] I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00
First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8
Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Fifth LOW LOW LOW LOW LOW LOW LOW BA17 BA16
Notes: 1. Block address concatenated with page address = actual page address. CAx = column ad-
dress; PAx = page address; BAx = block address.
2. If CA10 = 1, then CA[9:5] must be 0.
3. BA6 controls plane selection.
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Device and Array Organization
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Figure 11: Array Organization – MT29F8G08 and MT29F16G08 (x8)
Cache Register
Data Register
2048 blocks
per plane
4096 blocks
per die
1 block 1 block
Plane 0: even-
numbered blocks
(0, 2, 4, 6, ...,
4092, 4094)1
Plane 1: odd-
numbered blocks
(1, 3, 5, 7, ...,
4093, 4095)
Plane 0: even-
numbered blocks
(4096, 4098, ...,
8188, 8190)
Plane 1: odd-
numbered blocks
(4097, 4099, ...,
8189, 8191)
64
2048 64
2112 bytes2112 bytes
64
64
2048
2048
2048
1 block 1 block
64
2048 64
2112 bytes2112 bytes
64
64
2048
2048
2048
1 page = (2K + 64 bytes)
1 block = (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
1 plane = (128K + 4K) bytes x 2048 blocks
= 2112Mb
1 die = 2112Mb x 2 planes
= 4224Mb
1 device = 4224Mb x 2 die
= 8448Mb
I/O0
I/O7
Die 0 Die 1
Note: 1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1.
Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1.
Table 4: Array Addressing – MT29F8G08 and MT29F16G08 (x8)
Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00
First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW CA11 CA10 CA9 CA8
Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Fifth LOW LOW LOW LOW LOW BA183BA17 BA16
Notes: 1. CAx = column address; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:6] must be 0.
3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.
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Device and Array Organization
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Figure 12: Array Organization – MT29F8G16 (x16)
Cache Register
Data Register
2048 blocks
per plane
4096 blocks
per die
1 block 1 block
Plane 0: even-
numbered blocks
(0, 2, 4, 6, ...,
4092, 4094)1
Plane 1: odd-
numbered blocks
(1, 3, 5, 7, ...,
4093, 4095)
Plane 0: even-
numbered blocks
(4096, 4098, ...,
8188, 8190)
Plane 1: odd-
numbered blocks
(4097, 4099, ...,
8189, 8191)
32
1024 32
1056 words1056 words
32
32
1024
1024
1024
1 block 1 block
32
1024 32
1056 words1056 words
32
32
1024
1024
1024
1 page = (1K + 32 words)
1 block = (1K + 32) words x 64 pages
= (64K + 2K) words
1 plane = (128K + 4K) bytes x 2048 blocks
= 2112Mb
1 die = 2112Mb x 2 planes
= 4224Mb
1 device = 4224Mb x 2 die
= 8448Mb
I/O0
I/O7
Die 0 Die 1
Note: 1. Die 0, Plane 0: BA18 = 0; BA6 = 0. Die 0, Plane 1: BA18 = 0; BA6 = 1.
Die 1, Plane 0: BA18 = 1; BA6 = 0. Die 1, Plane 1: BA18 = 1; BA6 = 1.
Table 5: Array Addressing – MT29F8G16 ( x16)
Cycle I/O[15:8] I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/O0
First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8
Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 PA8
Fifth LOW LOW LOW LOW LOW LOW BA183BA17 BA16
Notes: 1. Block address concatenated with page address = actual page address. CAx = column ad-
dress; PAx = page address; BAx = block address.
2. If CA10 = 1, then CA[9:5] must be 0.
3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.
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Device and Array Organization
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Asynchronous Interface Bus Operation
The bus on the device is multiplexed. Data I/O, addresses, and commands all share the
same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and
commands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, address input
cycles, and one or more data cycles, either READ or WRITE.
Table 6: Asynchronous Interface Mode Selection
Mode1CE# CLE ALE WE# RE# I/Ox WP#
Standby2H X X X X X 0V/VCC
Command input L H L H X H
Address input L L H H X H
Data input L L L H X H
Data output L L L H X X
Write protect X X X X X X L
Notes: 1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
2. WP# should be biased to CMOS LOW or HIGH for standby.
Asynchronous Enable/Standby
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-
chronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
Asynchronous Commands
An asynchronous command is written from I/O[7:0] to the command register on the ris-
ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are
accepted by die (LUNs) even when they are busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a command
is issued.
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Asynchronous Interface Bus Operation
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Figure 13: Asynchronous Command Latch Cycle
WE#
CE#
ALE
CLE
I/Ox COMMAND
tWP
tCH
tCS
tALH
tDH
tDS
tALS
tCLH
tCLS
Don’t Care
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Asynchronous Addresses
An asynchronous address is written from I/O[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, like ad-
dress cycles that follow the READ STATUS ENHANCED (78h) command.
Figure 14: Asynchronous Address Latch Cycle
WE#
CE#
ALE
CLE
I/Ox Col
add 1
tWP tWH
tCS
tDH
tDS
tALS
tALH
tCLS
Col
add 2 Row
add 1 Row
add 2 Row
add 3
Don’t Care Undefined
tWC
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