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OVP
TPS92690
RT
SYNC
1
2
3
4
VIN
VCC
IS
GATE
16
15
14
13
SS/SD
COMP
AGND
ILIM
5
6
7
8
PGND
CSP
IADJ
VREF
12
11
10
9
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TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
TPS92690-Q1 N-Channel Controller for Dimmable LED Drives
With Low-Side Current Sense
1 Features 3 Description
The TPS92690-Q1 device is a high-voltage, low-side
1• TPS9260-Q1 is an Automotive Grade Product NFET controller with an adjustable output current
That is AEC-Q100 Grade 1 Qualified sense resistor voltage. Ideal for LED drivers, it
• Input Voltage Range from 4.5 to 75 V contains all of the features needed to implement
• Adjustable Current Sense (50 to 500 mV) current regulators based on boost, SEPIC, flyback,
and Cuk topologies.
• Low-Side Current Sensing
• 2-ΩMOSFET Gate Driver Output current regulation is based on peak current-
mode control supervised by a control loop. This
• Input Undervoltage Protection methodology eases the design of loop compensation
• Output Overvoltage Protection while providing inherent input voltage feed-forward
• Cycle-by-Cycle Current Limit compensation. The TPS92690-Q1 device includes a
high-voltage start-up regulator that operates over a
• PWM Dimming Input wide input range between 4.5 and 75 V. The PWM
• Programmable Oscillator Frequency controller is designed for high-speed capability
• External Synchronization Capability including an oscillator frequency range up to 2 MHz.
The TPS92690-Q1 device includes an error amplifier,
• Slope Compensation precision reference, cycle-by-cycle current limit, and
• Programmable Soft-Start Function thermal shutdown.
• HTSSOP (PWP), 16-Pin, Exposed Pad Package The TPS92690-Q1 device is AEC-Q100 Grade 1
qualified.
2 Applications
• LED Drivers Device Information(1)
• Constant Current Regulator: Boost, Cuk, Flyback, PART NUMBER PACKAGE BODY SIZE (NOM)
and SEPIC TPS92690-Q1 HTSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 17
1 Features.................................................................. 18 Application and Implementation ........................ 18
2 Applications ........................................................... 18.1 Application Information............................................ 18
3 Description............................................................. 18.2 Typical Applications ............................................... 20
4 Revision History..................................................... 29 Power Supply Recommendations...................... 31
5 Pin Configuration and Functions......................... 39.1 Bench Supply Current Limit.................................... 31
6 Specifications......................................................... 410 Layout................................................................... 32
6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 32
6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 33
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 34
6.4 Thermal Information.................................................. 411.1 Community Resources.......................................... 34
6.5 Electrical Characteristics........................................... 511.2 Trademarks........................................................... 34
6.6 Typical Characteristics.............................................. 711.3 Electrostatic Discharge Caution............................ 34
7 Detailed Description.............................................. 911.4 Glossary................................................................ 34
7.1 Overview................................................................... 912 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 9Information........................................................... 34
7.3 Feature Description................................................. 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
Initial release.
November 2015 * Released as a separate data sheet from the
TPS92690 data sheet (SLVSBK3)
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PGND
RT
SYNC
IS
IADJ
VREF
GATE
VCC
VIN
AGND
CSP
COMP
SS/SD
ILIM
OVP
nDIM 116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Thermal Pad
TPS92690-Q1
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SLVSCU0 –NOVEMBER 2015
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With PowerPAD
Top View
Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
AGND 7 GND Connect to PGND through DAP exposed thermal pad for proper ground return path.
COMP 6 I Connect ceramic capacitor to GND to set loop compensation.
CSP 11 I Connect to positive terminal of sense resistor in series with LED stack.
GATE 13 O Connect to main N-channel MOSFET gate of switching converter.
IADJ 10 I Connect resistor divider from VREF to set error amplifier reference voltage.
ILIM 8 I Connect resistor divider from VREF to set current limit threshold voltage at IS pin.
Connect to drain of main N-channel MOSFET or to source of MOSFET if sense resistor is used for
IS 14 I improved accuracy.
Connect resistor divider from VIN to set UVLO threshold and hysteresis. Connect through diode or
nDIM 1 I MOSFET to PWM dim concurrently.
OVP 2 I Connect resistor divider from output voltage to set OVP threshold and hysteresis.
PGND 12 GND Connect to AGND through the exposed thermal pad for proper ground return path.
RT 3 O Connect resistor to AGND to set base switching frequency.
SS/SD 5 I Connect capacitor to AGND to set soft-start delay. Pull pin below 75 mV for low-power shutdown.
Connect external PWM signal to set switching frequency. Must be higher than base frequency set at RT
pin. Can also connect series resistor and capacitor to drain of main MOSFET and capacitor to AGND to
SYNC 4 I implement zero-crossing detection for quasi-resonant topologies. In either case, a falling edge on SYNC
triggers a new on-time at GATE. If tied to ground, internal oscillator is used.
VCC 15 O Bypass with 2.2-µF ceramic capacitor to provide bias supply for controller.
Connect to input supply of converter. Bypass with 100-nF ceramic capacitor to AGND as close to the
VIN 16 I device as possible.
Connect to the IADJ pin directly or through resistor divider. Bypass with 100-nF ceramic capacitor to
VREF 9 O AGND.
Thermal Pad GND
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6 Specifications
6.1 Absolute Maximum Ratings
All voltages are with respect to GND, –40°C < TJ= TA< 125°C, all currents are positive into and negative out of the specified
terminal (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage VIN –0.3 76 V
nDIM, OVP –0.3 76
Input voltage IS(2) –0.3 76 V
CSP, IADJ, SS/SD, ILIM –0.3 6
VCC, GATE(3) –0.3 14
Output voltage V
COMP, RT, VREF –0.3 6
IS –1
Continuous input current GATE –1 1 mA
SYNC 1
Output current VREF –1 mA
Operating junction temperature, TJ(4) 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The IS pin can sustain –2 V for 100 ns without damage.
(3) the GATE pin can sustain –2.5 V for 100 ns. The VCC pin can sustain –2.5 V for 100 ns.
(4) Maximum junction temperature is internally limited.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 ±1250
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIN Input voltage 4.5 12 75 V
TJOperating junction temperature –40 25 125 °C
VIADJ(max) Maximum operating IADJ voltage 0 5 V
6.4 Thermal Information TPS92690-Q1
THERMAL METRIC(1) PWP (TSSOP) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 39.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23.8 °C/W
RθJB Junction-to-board thermal resistance 17.5 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 17.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
–40°C < TJ= TA< 125°C, VIN = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STARTUP REGULATOR (VCC)
VCCREG VCC regulation voltage ICC = 0 mA 6.35 6.9 7.45 V
ICCLIM VCC current limit VVCC = 0 V –20 –30 mA
IQQuiescent current 2 3 mA
ISD Shutdown current VSS/SD = 0 V 45 65 μA
VVCC rising 4.1 4.50
VCCUV VCC UVLO threshold V
VVCC falling 3.61 4.01
VCCHYS VCC UVLO hysteresis 83 mV
REFERENCE VOLTAGE OUTPUT
VREF Reference voltage No load 2.4 2.45 2.5 V
ERROR AMPLIFIER
CSP input bias current –0.6 0 0.6 μA
COMP sink current 17.1 28.5 39.9 μA
COMP source current VIADJ = 5 V –12.6 –16.8 –21 μA
gMTransconductance VIADJ = 1 V, 0 V ≤VCSP ≤0.8 V 33 μA/V
Transconductance bandwidth –6dB 1 MHz
IADJ pin input impedance 1 MΩ
VCSP Error amplifier reference voltage Precise value implied in offset VIADJ/10 V
VVCC = 4.5 V, 1 V ≤VCOMP ≤1.4 V, –1.5 0 1.5
TA= 25°C mV
VVCC > 6 V, 1 V ≤VCOMP ≤3 V, VIADJ
Error amplifier input offset voltage –1.8 0 1.8
≤1.25 V, TA= 25°C
VVCC > 6 V, 1 V ≤VCOMP ≤3 V, VIADJ –1.44 0 1.44 VCSP%
> 1.25 V, TA= 25°C (% of )
PWM COMPARATOR AND SLOPE COMPENSATION
DMAX Maximum duty cycle Internal oscillator only 90% 94.4%
No slope added 950 1100 1250
IS to PWM offset voltage mV
D = DMAX (maximum slope added) 125
IOFF IS source current No slope added –11.9 μA
IOFF + ISL D = DMAX (maximum slope added) –60 μA
CURRENT LIMIT
ILIM delay to output 60 100 ns
tON(min) Leading edge blanking time 200 300 ns
Current limit off-timer 38 μs
ILIM offset voltage D = 50% –19 –5.6 5 mV
LOW POWER SHUTDOWN AND SOFTSTART
VSD Shutdown threshold voltage VSS/SD falling 30 86 mV
VSDH Shutdown hysteresis 24 mV
VSS/SD > (VSD + VSDH) –10.8 μA
ISS SS/SD current source VSS/SD < VSD –1.1 μA
OSCILLATOR AND EXTERNAL SYNCHRONIZATION
RRT = 121 kΩ312 350 389
ƒSW Switching frequency RRT = 100 kΩ372 418 464 kHz
RRT = 84.5 kΩ436 490 544
Rising 2.05 2.36
SYNC threshold voltage (falling edge triggers V
on-time) Falling 0.95 1.31
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Electrical Characteristics (continued)
–40°C < TJ= TA< 125°C, VIN = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Positive 6.2
SYNC Clamp Voltage V
Negative –0.5
OVERVOLTAGE PROTECTION
Rising 1.23 1.282
OVP OVLO threshold V
Falling 1.144 1.19
OVP hysteresis source current OVP active (high) –14 –21.5 –28 μA
PWM DIMMING INPUT AND UVLO
Rising 1.23 1.285
nDIM/UVLO threshold V
Falling 1.14 1.19
nDIM hysteresis current –14 –21.6 –28 μA
GATE DRIVER
GATE sourcing resistance GATE = High 2.4 6 Ω
GATE sinking resistance GATE = Low 1 5 Ω
Source –0.47 A
Peak GATE current Sink 1.1 A
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 175 °C
TSD(hys) Thermal shutdown hysteresis 25 °C
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200
400
600
800
20 40 60 80 100
PWM Duty Cycle (%)
Output Current (mA)
1A Nominal
G000
200
400
600
800
0.0 0.5 1.0 1.5 2.0 2.5
IADJ Voltage (V)
Output Current (mA)
G000
495
497
499
501
503
505
10 15 20 25 30 35
Input Voltage (V)
Output Current (mA)
12 LEDs
G000
300
400
500
600
700
800
900
1000
40 60 80 100 120 140 160
RT Resistance (kΩ)
Switching Frequency (kHz)
G000
85
87
89
91
93
95
8 12 16 20 24 28 32 36
Input Voltage (V)
Efficiency (%)
12 LEDs
500mA
G000
85
87
89
91
93
95
8 10 12 14 16
Input Voltage (V)
Efficiency (%)
6 LEDs
500mA
G000
TPS92690-Q1
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SLVSCU0 –NOVEMBER 2015
6.6 Typical Characteristics
Unless otherwise noted, –40°C ≤TA= TJ≤125°C, VVIN = 14 V, CBYP = 2.2 µF, CCOMP = 0.1 µF
Figure 1. Boost Efficiency vs Input Voltage Figure 2. Boost Efficiency vs Input Voltage
Figure 3. Boost Line Regulation Figure 4. Switching Frequency vs RT Resistance
Figure 5. 160-Hz Boost PWM Dimming Figure 6. IADJ Analog Dimming (RCS = 0.25 Ω)
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330
340
350
360
370
−40 −25 −10 5 20 35 50 65 80 95 110 125
Ambient Temperature (°C)
Output Current (mA)
12V Input
36V Output @ 350mA
G000
2.4
2.42
2.44
2.46
2.48
2.5
0 50 100
Ambient Temperature (°C)
VREF Voltage (V)
G000
405
410
415
420
425
430
435
−40 −25 −10 5 20 35 50 65 80 95 110 125
Ambient Temperature (°C)
Switching Frequency (kHz)
G000
90
91
92
93
94
95
−40 −25 −10 5 20 35 50 65 80 95 110 125
Ambient Temperature (°C)
Efficiency (%)
12V Input
36V Output @ 350mA
G000
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
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Typical Characteristics (continued)
Unless otherwise noted, –40°C ≤TA= TJ≤125°C, VVIN = 14 V, CBYP = 2.2 µF, CCOMP = 0.1 µF
Figure 7. Switching Frequency vs Ambient Temperature Figure 8. Efficiency vs Ambient Temperature
(RT= 100 kΩ)
Figure 9. Output Current vs Ambient Temperature Figure 10. VREF Voltage vs Ambient Temperature
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VCC
VREF
AGND
ILIM
VIN
nDIM
SYNC
RT
SS/SD
CSP
IADJ
IS
COMP
6.9-V LDO
Regulator
Oscillator
nUVLO
Fault
ISS
SS/SD
+
9R
gM Error
Amplifier
S Q
R
Artificial Ramp
nUVLO
DMAX = 0.9
+PWM
IOFF
ROFF
RSL
+ILIM 40-µs
Latch
LEB
Clock
Standby
Fault
1.24 V
+
1.24 V
+OVP
LEB
Reset
Dominant
20 µA
PGND
GATE
VCC
100 NŸ100 NŸ
+
1.24 V
Thermal
Limit
TLIM
+Reference
Standby
UVLO
(4.1 V) 1.24 V
VCC UVLO
SS/SD
75 mV
20 µA
R
TPS92690-Q1
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SLVSCU0 –NOVEMBER 2015
7 Detailed Description
7.1 Overview
The TPS92690-Q1 device is an N-channel MOSFET (NFET) controller for boost, SEPIC, Cuk, and flyback
current regulators which are ideal for driving LED loads. The controller has wide input voltage range allowing for
regulation of a variety of LED loads. The low-side current sense, with low adjustable threshold voltage, provides
an excellent method for regulating output current while maintaining high system efficiency.
The TPS92690-Q1 device uses peak current mode control providing good noise immunity and an inherent cycle-
by-cycle current limit. The adjustable current sense threshold provides a way to analog dim the LED current,
which can also be used to implement thermal foldback. The dual function nDIM pin provides a PWM dimming
input that controls the main GATE output for PWM dimming the LED current also.
When designing, the maximum attainable LED current is not internally limited because the TPS92690-Q1 device
is a controller. Instead it is a function of the system operating point, component choices, and switching frequency
allowing the TPS92690-Q1 device to easily provide constant currents up to 5 A. This simple controller contains
all the features necessary to implement a high efficiency versatile LED driver.
7.2 Functional Block Diagram
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O
V
O IN
nV
D
nV
=
+
O
O IN
V
D
V V
=
+
O IN
O
V V
D
V
-
=
Time
tON = D×tS .IL(min)
0
tOFF = (1±D)×tS
tS .
IL(max)
'iL(P-P)
iL
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
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7.3 Feature Description
7.3.1 Current Regulators
Current regulators can be designed to accomplish different functions: boost, buck-boost, and flyback. The
TPS92690-Q1 device is designed to drive a ground referenced N-channel FET and sense a ground referenced
LED load. This control architecture is perfect for driving boost, SEPIC, flyback, or Cuk topologies. It does not
work with a floating buck or buck-boost topology since the LED current sense amplifier is ground referenced.
Looking at the boost design in the Typical Boost Application, the basic operation of a current regulator can be
analyzed. During the time that the N-channel FET (Q1) is turned on (tON), the input voltage source stores energy
in the inductor (L1) while the output capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF),
the re-circulating diode (D1) becomes forward biased and L1 provides energy to both COand the LED load.
Figure 11 shows the inductor current (iL(t)) waveform for a regulator operating in CCM.
Figure 11. Basic CCM Inductor Current Waveform
The average output LED current (ILED) is proportional to the average inductor current (IL), therefore if ILis tightly
controlled, ILED is well regulated. As the system changes input voltage or output voltage, the ideal duty cycle (D)
is varied to regulate ILand ultimately ILED. For any current regulator, D is a function of the conversion ratio:
Use Equation 1 to calculate the duty cycle for an application using the boost topology.
(1)
Use Equation 2 to calculate the duty cycle for an application using the buck-boost (SEPIC/Cuk) topology.
(2)
Use Equation 3 to calculate the duty cycle for an application using the flyback topology.
where
• n is the primary to secondary turns ratio of the coupled inductor, n:1 (3)
7.3.2 Peak Current Mode Control
Peak current mode control is used by the TPS92690-Q1 device to regulate the average LED current through an
array of HBLEDs. This method of control uses a series resistor in the LED path to sense LED current and can
use either a series resistor in the MOSFET path or the MOSFET RDS(on) for both cycle-by-cycle current limit and
input voltage feed forward. The controller has a fixed switching frequency set by an internal programmable
oscillator therefore slope compensation is added to mitigate current mode instability. A detailed explanation of
this control method is presented in the following sections.
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CSP
IADJ
IS
COMP
+
9R
gM Error
Amplifier
Artificial Ramp
+PWM
IOFF
ROFF
RSL
+ILIM
To GATE
ILIM
CCMP
CF*
RF*
RCS
0 - 5 V
GATE
RLIM*
IT
0 - 400 mV
+
±
VLIM
+
±
ILED
VCS
R
SW 11 9
T
1
2.29 10 R 80 10
- -
¦ =
´ ´ + ´
TPS92690-Q1
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SLVSCU0 –NOVEMBER 2015
Feature Description (continued)
7.3.3 Switching Frequency and Synchronization
The switching frequency of the TPS92690-Q1 device is programmed using an external resistor (RT) connected
from the RT pin to GND. This switching frequency is defined as shown in Equation 4.
(4)
The Typical Characteristics shows a graph of switching frequency versus timing resistance on RT. For maximum
operational range and best efficiency, TI recommends a switching frequency of 1 MHz or lower. It is possible to
reduce the solution size in applications with switching frequencies as high as 2 MHz in some situations. Higher
frequencies require an increased gate-drive current and that can result in higher AC losses, both of which result
in decreased efficiency. It is also possible that the minimum on-time (leading edge blanking time) limits the
minimum operational duty cycle and reduces the input voltage range for a given output voltage.
Alternatively, an external PWM signal can be applied to the SYNC pin to synchronize the device to an external
clock. If the PWM signal frequency applied is higher than the base frequency set by the timing (RT) resistor, the
internal oscillator is bypassed and the switching frequency is equal to the synchronized frequency. The PWM
signal should have an amplitude between 2.5 and 5 V. The device triggers a switch-on time on the falling edge of
the PWM signal and operates correctly regardless of the duty cycle of the applied signal.
Figure 12. Current Sense and Control Circuitry (* optional)
7.3.4 Current Sense and Current Limit
The TPS92690 device implements peak current mode control using the circuit shown in Figure 12. The peak
detection is accomplished with a comparator that monitors the main MOSFET current, comparing it with the
COMP pin. When the IS pin voltage (plus the DC level shift and the ramp discussed later) exceeds the COMP
pin voltage, the MOSFET is turned off. The MOSFET is turned back on when the oscillator starts a new on-time
and the cycle repeats.
The IS pin incorporates a cycle-by-cycle overcurrent protection function. Current limit is accomplished by a
redundant internal current sense comparator. If the voltage at the current sense comparator input (IS) exceeds
the voltage at the ILIM pin, the MOSFET is turned off and the COMP pin is pulled to ground and discharged. The
MOSFET turns back on after either the 43-µs current limit timeout has passed or after the COMP pin is
recharged, whichever is longer. The IS input pin has an internal N-channel MOSFET which pulls it down at the
conclusion of every cycle. The discharge device remains on an additional 216 ns (typical) after the beginning of a
new cycle to blank the leading edge spike on the current sense signal. This blanking time also results in a
minimum switch-on time of 216 ns which determines a minimum duty cycle dependent upon switching frequency.
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ADJ1
IADJ
ADJ1 ADJ2
R
V VREF
R R
= ´
+
LIM1
LIM ILIM
LIM1 LIM2
R
V V VREF
R R
= = ´
+
LIM
CL
LIM
V
I
R
=
IADJ
CS
V
V
10
=
CS
LED
CS
V
I
R
=
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Feature Description (continued)
IS sensing can be done in one of two ways. The most accurate current sensing is accomplished by using a
resistor, RLIM. This adds a component that dissipates additional power but the result is higher accuracy and no
limitation on the maximum MOSFET drain voltage. For applications that have a maximum MOSFET drain voltage
below 75 V MOSFET RDS(on) sensing can be used by connecting the IS pin directly to the drain of the MOSFET
and eliminating RLIM. This results in higher efficiency but the accuracy depends on the accuracy of the MOSFET
RDS(on). Care must be taken to use the maximum expected RDS(on) when setting the current limit threshold at the
ILIM pin.
7.3.5 Average LED Current
The COMP pin voltage is dynamically adjusted, via the internal error amplifier, to maintain the desired regulation.
A sense resistor in series with the LEDs sets the average LED current regulation. The voltage across the sense
resistor (VCS) is regulated to the IADJ voltage divided by 10.
The IADJ pin can be set to any value up to 2.45 V by connecting it to VREF through a resistor divider for static
output current settings. IADJ can also be used to change the regulation point if connected to a controlled voltage
source up to 5 V or potentiometer to provide analog dimming. It is also possible to configure the IADJ pin for
thermal foldback functions.
(5)
(6)
The TPS92690 device maintains high accuracy at any level of VCS. However, the accuracy remains better with
higher levels as offsets and other errors become a smaller percentage of the overall VCS voltage. Power losses
are also higher with higher VCS voltages. A good tradeoff for accuracy and efficiency is to set the maximum VCS
voltage to between 100 and 250 mV.
In some applications, such as standard boost or flyback topologies, the output capacitor can be connected from
the output directly to ground. In these cases the CS pin can be directly connected to RCS. In other applications an
additional filter may be desired on the CS pin (RFand CF). Use these filters with topologies where the current
through RCS is not continuous such as in the Cuk configuration. Another example would be a boost regulator
where PWM dimming is required and the output capacitor is connected directly across the LEDs. In these cases
it is recommended to add a 47-Ωresistor for RFand a 47-nF capacitor for CFto achieve the best accuracy and
line regulation.
7.3.6 Precision Reference (VREF)
The TPS92690 device includes a precision 2.45-V reference. This can be used in conjunction with a resistor
divider to set voltage levels for the ILIM pin and the IADJ pin to set the maximum current limit and LED current. It
can also be used with high impedance external circuitry requiring a reference. To set the current limit (ICL) using
VREF you can use the following equations:
(7)
(8)
When RDS(on) sensing is being used substitute RLIM in the above equation with RDS(on). A small amount of
capacitance (CLIM) can be placed from the ILIM pin to ground for filtering if desired. If so, a value between 47 pF
and 100 nF should be used but this value should not exceed the value of CCMP to avoid false triggering of the
current limit. To set the IADJ voltage level using VREF use the following equation:
(9)
If desired, place a small capacitor (CADJ) from the IADJ pin to ground for additional filtering. A value between 47
pF and 100 nF should be sufficient.
12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
( ) ADJ1
IADJ ADJ
ADJ1 ADJ2
R
V VREF V
R R
= - ´ +
VREF
IADJ
TPS92690
RADJ2
RADJ1
VIADJ
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Feature Description (continued)
7.3.7 Low-Level Analog Dimming
The IADJ pin can be driven as low as 0 V. The device encounters a minimum on-time at some level, depending
on the switching frequency. When the voltage on the IADJ pin falls beyond this point, the device begins to skip
pulses to maintain average output current regulation. Depending on external components and regulator
bandwidth this skipping may or may not result in visible flicker. If flicker is present below this level higher inductor
and/or output capacitor values may help and a lower COMP pin capacitor value may help. In many cases this
level occurs at very low LED current and it is more desirable to simply limit the low level on the IADJ pin as
shown in Figure 13.
Figure 13. Limiting Minimum IADJ Voltage
The resulting IADJ voltage can be found using the following equation:
(10)
7.3.8 Soft-Start and Shutdown
The TPS92690 device can be placed into low power shutdown by grounding the SS/SD pin (any voltage below
86 mV). During low power shutdown, the device limits the quiescent current to approximately 40 µA, typical.
The SS/SD pin also has a 10-µA current source (or 1 µA when below the 86-mV shutdown threshold), which
charges a capacitor from SS/SD to GND to soft-start the converter. The SS/SD pin is attached through a PNP
transistor to COMP therefore it controls the speed at which COMP rises at startup. When VCCUV is below the
falling threshold, SS/SD is pulled down to reset the capacitor voltage to zero. Then when VCCUV rising threshold
is exceeded, the pin is released and charges via the 10-µA current source.
7.3.9 VCC Regulator and Start-Up
The TPS92690 device includes a high voltage, low dropout bias regulator. When power is applied, or SS/SD is
released, the regulator is enabled and sources current into an external capacitor (CBYP) connected to the VCC
pin. The recommended bypass capacitance for the VCC regulator is 2.2 to 3.3 µF. This capacitor should be rated
for 10 V or greater and an X7R dielectric ceramic is recommended. The output of the VCC regulator is monitored
by an internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage
and the supply is also internally current limited. VCC may also be driven externally to increase the GATE voltage
and reduce the RDS(on) of the external switching MOSFET. The maximum voltage on this pin is 14 V and should
not exceed the VIN voltage. The bypass capacitor voltage rating may need to be increased accordingly.
The start-up time of the device to full output current depends on the value of CBYP, CSS (soft-start capacitor),
CCMP, and CO(output capacitor) as shown in Figure 14:
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS92690-Q1
SU VCC CMP CO
t t t t= + +
SS
SS
0.3V C
t
11 A
´
=
m
CMP
CMP SS
CS
0.7V C
t
V 35 S
-
´
=
´ m
O O
CO
LED
C V
t
I
´
=
CMP
CMP
CS
1V C
t
V 35 S
´
=
´ m
BYP
VCC
4.1V C
t
30mA
´
=
TIme
0.7
1.0
1.0
tVCC
tCMP-SS tSS tCO
tCO
tCMP-SS
tVCC
Voltage (V)
0
0
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Feature Description (continued)
Figure 14. Start-up Waveforms
First, CBYP is charged to be above the VCC UVLO threshold of 4.1 V. The CBYP charging time (tVCC) can be
estimated as:
(11)
Assuming there is no CSS (top trace), or if CSS is less than 40% of CCMP, CCMP is then charged to 1V over the
charging time (tCMP) which can be estimated as:
(12)
Once CCMP = 1 V, the device starts switching to charge COuntil the LED current is in regulation. The COcharging
time (tCO) can be roughly estimated as:
(13)
If CSS is greater than 40% of CCMP (bottom trace), the compensation capacitor only charges to 0.7 V over a
smaller CCMP charging time (tCMP-SS) which can be estimated as:
(14)
Then COMP clamps to SS, forcing COMP to rise (the last 300 mV before switching begins) according to the CSS
charging time (tSS) which can be estimated as:
(15)
The system start-up time tSU (for CSS < 0.4 CCMP) or tSU-SS (for CSS > 0.4 CCMP) is defined as:
(16)
14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
nDIM
TPS92690
RUV2
RUV1
+
1.24 V
20 µA
UVLO
VIN
RUVH
(optional)
HYSO OV2
V 20 A R= m ´
OV1 OV2
TURN OFF
OV1
R R
V 1.24V
R
-
´
= ´
OVP
TPS92690
ROV2
ROV1
+
1.24 V
20 µA
OVLO
VO
SU SS VCC CMP SS SS CO
t t t t t
- -
= + + +
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Feature Description (continued)
(17)
As a general rule of thumb, standard smooth startup operation can be achieved with CSS = CCMP. If SD/SS is
being driven by an external source the equations above may need to be modified depending on the current
sourcing capability of the external source.
7.3.10 Overvoltage Protection (OVP)
Figure 15. Overvoltage Protection Circuitry
The TPS92690 device includes a dedicated OVP pin which can be used for either input or output over-voltage
protection. This pin features a precision 1.24-V threshold with 20 µA (typical) of hysteresis current as shown in
Figure 15. When the OVP threshold is exceeded, the GATE pin is immediately pulled low and a 20-µA current
source provides hysteresis to the lower threshold of the OVP hysteretic band.
The over-voltage turn-off threshold (VTURN-OFF) and the hysteresis (VHYSO) are defined by:
(18)
(19)
7.3.11 Input Undervoltage Lockout (UVLO)
The nDIM pin is a dual function input that features an accurate 1.24-V threshold with programmable hysteresis
as shown in Figure 16. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO.
When the pin voltage rises and exceeds the 1.24-V threshold, 20 µA (typical) of current is driven out of the nDIM
pin into the resistor divider providing programmable hysteresis.
Figure 16. UVLO Circuit
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS92690-Q1
nDIM
TPS92690
RUV2
RUV1
VIN
RUVH
Standard PWM
DDIM
Inverted PWM
QDIM
( )
UVH UV1 UV2
HYS UV2
UV1
R R R
V 20 A R
R
æ ö
´ +
= m ´ +
ç ÷
ç ÷
è ø
UV 2
HYS
V 20 A R= m ´
UV1 UV2
TURN ON
UV1
R R
V 1.24V
R
-
´
= ´
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Feature Description (continued)
When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra resistor
to set the hysteresis. This allows the standard resistor divider to have smaller values minimizing PWM delays
due to a pull-down MOSFET at the nDIM pin (see PWM Dimming). In general, at least 3 V of hysteresis is
preferable when PWM dimming if operating near the UVLO threshold. The turn-on threshold (VTURN-ON) is defined
as follows:
(20)
The hysteresis (VHYS) is defined as follows:
UVLO Only
(21)
PWM Dimming and UVLO
(22)
7.3.12 PWM Dimming
The active low nDIM pin can be driven with a PWM signal which controls the main N-channel FET. The
brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness is
approximately proportional to the PWM signal duty cycle (that is, 30% nDIM high duty cycle equals about 30%
LED brightness). This function can be ignored if PWM dimming is not required by using nDIM solely as a VIN
UVLO input as described in the Input Undervoltage Lockout (UVLO) section or by tying it directly to VCC or VIN
when UVLO is not required.
Figure 17. PWM Dimming Circuit
When using a MOSFET (QDIM), connect the drain to the nDIM pin and the source to GND. Apply an external
logic-level PWM signal to the gate of QDIM. Brightness is proportional to the negative duty cycle of the PWM
signal. When using a Schottky diode (DDIM), connect the anode to the nDIM pin. Apply an external logic-level
PWM signal to the cathode of the diode and brightness is proportional to the positive duty cycle of the PWM
signal.
7.3.13 Control Loop Compensation
Compensating the TPS92690 device is relatively simple for most applications. To prevent subharmonic
oscillations due to current mode control, a minimum inductor value should be chosen. This minimum value can
be approximated with the following equation:
16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
2
D
RHPZ
r D '
2 D L1
´
=p ´ ´
¦
m
C
CMP
g
2 Cp ´
¦ =
P1
O CMP
1
2 R C
=p ´ ´
¦
( )
O
min
SW
3
V 425 10
L H
2
´ ´
= m
´ ¦
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Feature Description (continued)
(23)
Compensating the control loop simply requires a capacitor from the COMP pin to ground. Most LED driver
applications do not require high bandwidth response since there are no significant output transients and
generally limited, low bandwidth input transients. The high output impedance (RO) of the error amplifier (typically
200MΩ) enables a low bandwidth system where standard poles and zeros, including the right half plane zero in
many cases, can be neglected. In this case the bandwidth of the system generally becomes the bandwidth of the
error amplifier. TI recommends a CCMP value of 1 to 100 nF, which results in the following dominant pole and
crossover frequency:
(24)
(25)
A 1-nF capacitor results in a bandwidth of approximately 5.2 kHz while a 100-nF capacitor results in a bandwidth
of approximately 52 Hz. Larger values are recommended for most applications unless higher bandwidth is
required. Larger values are also recommended for applications requiring PWM dimming as it allows the COMP
pin to hold its level more accurately during the LED current off time. In applications where the duty cycle (D)
exceeds 0.5 (VIN < VO/ 2 for a boost regulator) the location of the right half plane zero should be calculated to
ensure stability using the following equation:
(26)
Where D and D’ are calculated using the minimum input voltage. The crossover frequency, ƒC, should be a
decade below ƒRHPZ for maximum stability. CCMP should be adjusted accordingly if required.
7.3.14 Thermal Shutdown
The TPS92690 device includes thermal shutdown protection. If the die temperature reaches approximately
175°C the device shuts down (GATE pin low). If the die temperature is allowed to cool until it reaches
approximately 150°C the device resumes normal operation.
7.4 Device Functional Modes
This device has no additional functional modes
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS92690-Q1
IN
L PP
SW
V D
i
L f
-
´
D =
´
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not included in the TI component
specification, and TI does not warrant its accuracy or completeness. TI customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Inductor
The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy
is stored in the inductor and transferred to the load in different ways (as an example, boost operation is detailed
in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the switching
subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP). In the design process, L1 is chosen to
provide a desired ΔiL-PP. For a Cuk regulator the second inductor (L2) has a direct connection to the load, which
is good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to
the LED ripple current ΔiLED-PP since the inductor ripple in L2 is equal to that in L1. However, for boost and other
buck-boost regulators, there is always an output capacitor which reduces ΔiLED-PP, therefore the inductor ripple
can be larger than in the Cuk regulator case where output capacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED).
Therefore, for the Cuk regulator with no output capacitance, ΔiLED-PP should also be less than 40% of ILED unless
a large output capacitor is used. For the boost and other buck-boost topologies, ΔiL-PP can be much higher
depending on the output capacitance value. However, ΔiL-PP is suggested to be less than 100% of the average
inductor current (iL) to limit the RMS inductor current. ΔiL-PP is defined as:
(27)
Be sure to observe the minimum inductor value from the Control Loop Compensation section. L1 is also
suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable RMS
inductor current (IL-RMS).
8.1.2 LED Dynamic Resistance
When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RCS.
LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the
forward voltage of a single LED (VLED) by the forward current (ILED) can lead to an incorrect calculation of the
dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value.
Figure 18. Dynamic Resistance
Obtaining rLED is accomplished by referring to the manufacturer LED I-V characteristic. It can be calculated as the
slope at the nominal operating point as shown in Figure 18. For any application with more than 2 series LEDs,
RCS can be neglected allowing rDto be approximated as the number of LEDs multiplied by rLED.
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Product Folder Links: TPS92690-Q1
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Application Information (continued)
8.1.3 Output Capacitor
For boost, SEPIC, and flyback regulators, the output capacitor (CO) provides energy to the load when the
recirculating diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a Cuk
topology simply reduces the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases,
COis sized to provide a desired ΔiLED-PP. As mentioned in Inductor,ΔiLED-PP is recommended by manufacturers to
be <40% of the average LED current (ILED).
COshould be carefully chosen to account for derating due to temperature and operating voltage. It must also
have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current
rating, long lifetime, and good temperature performance. An X7R dielectric rating is suggested.
8.1.4 Input Capacitor
The input capacitor (CIN) only needs to provide the ripple current due to the direct connection to the inductor. CIN
is selected given the maximum input voltage ripple (ΔVIN-PP) which can be tolerated. ΔVIN-PP is suggested to be
less than 10% of the input voltage (VIN). An input capacitance at least 100% greater than the calculated CIN value
is recommended to account for derating due to temperature and operating voltage. When PWM dimming, even
more capacitance can be helpful to minimize the large current draw from the input voltage source during the
rising transition of the LED current waveform.
The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the
best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R
dielectric rating is suggested.
For most applications, it is recommended to bypass the VIN pin with an 0.1-µF ceramic capacitor placed as close
as possible to the pin. In situations where the bulk input capacitance may be far from the TPS92690 device, a
10-Ωseries resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150-
kHz filter to eliminate undesired high frequency noise.
8.1.5 MOSFET Selection
The TPS92690 device requires an external N-channel FET (Q1) as the main power MOSFET for the switching
regulator. Q1 is recommended to have a voltage rating at least 15% higher than the maximum transistor voltage
to ensure safe operation during the ringing of the switch node. In practice, all switching regulators have some
ringing at the switch node due to the diode parasitic capacitance and the lead inductance. The current rating is
recommended to be at least 10% higher than the average transistor current. The power rating is then verified by
calculating the power loss given the average transistor current and the N-channel FET on-resistance (RDS(on)).
In general, the N-channel FET should be chosen to minimize total gate charge (Qg) when ƒSW is high and
minimize RDS(on) otherwise. This minimizes the dominant power losses in the system. Frequently, higher current
N-channel FETs in larger packages are chosen for better thermal performance.
8.1.6 Recirculating Diode
A recirculating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is
a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is
recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node and a current rating at least 10% higher than the average diode
current. The power rating is verified by calculating the power loss through the diode. This is accomplished by
checking the typical diode forward voltage from the I-V curve on the product datasheet and multiplying by the
average diode current. In general, higher current diodes have a lower forward voltage and come in better
performing packages minimizing both power losses and temperature rise.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS92690-Q1
TPS92690
COMP
IADJ
VREF
DAP
CSP
GATE
VCC
IS
PGND
VIN 16
15
AGND
ILIM
VIN
OVP
RT
nDIM
SYNC
SS/SD
1
2
3
4
5
6
7
8
11
10
9
14
13
12
ILED
VOUT
VOUT
SYNC
PWM
Dim
RUV2
RUV1
RUVH
ROV 2
ROV 1
RT
CSS
CCMP
CLIM
RLIM 2
RLIM1 CREF
CADJ
RADJ 1
RADJ 2
CF
RF
RCS
Q1
CIN
CBYP
D1T1
CO
CSYNC1
CSYNC2
RSYNC
TPS92690
COMP
IADJ
VREF
DAP
CSP
GATE
VCC
IS
PGND
VIN 16
15
ILED
AGND
ILIM
VIN
OVP
RT
nDIM
SYNC
SS/SD
1
2
3
4
5
6
7
8
11
10
9
14
13
12
OVP
OVP
PWM
Dim
RUV2
RUV1
RUVH
RT
CSS
CCMP
CLIM
RLIM1
RLIM 2
L1
D1
Q1
CIN
CBYP
RF
CFRCS
CADJ
RADJ 1
RADJ 2
CREF
ROV 1
ROV 2
CO
L2CCUK
Q2
Q3
ROV 3
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
8.2 Typical Applications
8.2.1 Basic Topology Schematics
Figure 19. CUK Topology (Buck-Boost)
Figure 20. Quasi-Resonant Flyback Topology
20 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
TPS92690
COMP
IADJ
VREF
DAP
CSP
GATE
VCC
IS
PGND
VIN 16
15
ILED
AGND
ILIM
VIN
OVP
RT
nDIM
SYNC
SS/SD
1
2
3
4
5
6
7
8
11
10
9
14
13
12
VOUT
VOUT
CCMP
CSS
CF
RF
RCS
ROV2
ROV1
RT
RUV1
RUV2 RUVH
RADJ 1
RADJ 2
RLIM 1
RLIM 2
CLIM
CADJ
CREF
CBYP
CIN
CO
D1L1
Q1
PWM
Dim
TPS92690
COMP
IADJ
VREF
DAP
CSP
GATE
VCC
IS
PGND
VIN 16
15
ILED
AGND
ILIM
VIN
OVP
RT
nDIM
SYNC
SS/ SD
1
2
3
4
5
6
7
8
11
10
9
14
13
12
VOUT
VOUT
PWM
Dim
RUV2
RUV1
RUVH
ROV 2
ROV 1
RT
CSS
CCMP
CLIM
RLIM2
RLIM 1
RADJ 1
RADJ 2
CREF
CADJ
Q1
RCS
CO
CIN
CBYP
D1L1
L2
CS
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Typical Applications (continued)
Figure 21. SEPIC Topology (Buck-Boost)
Figure 22. Boost Topology With PWM Dimming
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TPS92690-Q1
RT= 1F80×10F9
2.29×10F11 ×420kHz = 103.9k3
DMAX = VOFVIN(min )
VO
=27
35 = 0.771
DMIN = VOFVIN(max )
VO
=16
35 = 0.457
D =
VOFVIN
VO
=
23
35 = 0.657
D LED
r N r 10 0.5 5 u u : :
O LED
V N V 10 3.5V 35V u u
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.1.1 Design Requirements
N = 10
VLED = 3.5 V
rLED = 500 mΩ
VIN = 12 V
VIN-MIN =8V
VIN-MAX = 19 V
fSW = 420 kHz
VCS = 50 mV
ILED = 500 mA
ΔiL-PP < 650 mA
ΔiLED-PP < 50 mA
ΔvIN-PP = 50 mV
VLIM = 100 mV
ILIM =5A
VTURN-ON = 7.8 V
VHYS =2V
VTURN-OFF = 40 V
VHYSO =5V
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Operating Point
Solve for VOand rD:
(28)
(29)
Solve for D, DMAX, and DMIN:
(30)
(31)
(32)
8.2.1.2.2 Switching Frequency
Solve for RT:
(33)
A close standard resistor is 105 kΩresulting in fSW = 402 kHz. Choose RT= 105 kΩ.
22 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
MAX
CO RMS LED MAX
D0.771
I I 500mA 0.92 A
1 D 0.229
u u
CO=
ILED × D
rD׿iLED FPP × fSW
=
500mA × 0.657
w3× 50mA × 420kHz = 3.suJF
22
LED L PP
L RMS LED
I I D'
1 500 mA 1 640 mA 0.343
I 1 1 1.47 A
D' 12 I 0.343 12 500 mA
§ · § ·
' u u
u u
¨ ¸ ¨ ¸
© ¹
© ¹
¿iLFPP =
VIN × D
L × fSW
=
12V × 0.657
uuJH × 420kHz = 640mA
V D 12 V 0.657
IN
L 28.9 H
i f 650mA 420kHz
L PP SW
uu
P
' u u
L1min =
VO× 425 × 103
2 × fSW
=
35V × 425 × 103
2 × 420kHz = 17.yJH
ADj2 IADj
ADj1 REF IADI
R V 100k 0.5 V
R 25k
V V 2.5 V 0.5 V
u: u
:
VIADJ = 10 × VCS = 10 × 50mV = 500mV
CS
CS LED
V50mV
R 0.1
I 500mA
:
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Typical Applications (continued)
8.2.1.2.3 Average LED Current
Solve for RCS using our desired 50-mV sense voltage:
(34)
Solve for VIADJ:
(35)
A resistor divider can be used from the reference pin (VREF) to IADJ, select RIAD2 = 100 kΩand solve for RIAD1:
(36)
The closest standard value is to choose RADJ1 = 25.5 kΩ.
8.2.1.2.4 Inductor Ripple Current
Solve for the minimum value of L1 for stability:
(37)
The inductor value required to meet the ripple current requirements is:
(38)
The closest standard inductor is 33 µH therefore ΔiL-PP is:
(39)
Determine minimum allowable RMS current rating:
(40)
The chosen component is L1 = 33 µH.
8.2.1.2.5 Output Capacitance
Solve for CO:
(41)
Add some capacitance to account for voltage de-rating and temperature and choose CO= 4.7 µF.
Determine minimum allowable RMS current rating:
(42)
Since this is a PWM dimming application the output capacitor should be placed directly across the LED string
and not connected to ground. So the CS pin should have additional filtering in the form of RF= 47 Ωand CF= 47
nF.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TPS92690-Q1
LED
T RMS I500 mA
I D 0.657 1.18 A
D' 1 0.657
u u
ITFMAX =
DMAX
1FDMAX
× ILED =
0.771
1F0.771 × 500mA = 1.68A
T MAX O
V V 35 V
L PP
CIN RMS i640mA
I 185mA
12 12
'
CIN =
¿iLFPP
8 × ¿V
IN FPP × fSW
=
640mA
8 × 50mV × 420kHz = 3.zJF
CCMP (min ) = gm
tN× fC
=
uuJA/V
tN× 164Hz = 32nF
fRHPZ =
rD×:1FDMAX ;2
tN× DMAX × L1 =
w3×:1F0.771;2
tN× 0.771 × uuJH= 1.64kHz
pCo D O
1 1
f 6.77 kHz
2 r C 2 5 4.7 F
S u u S u : u P
LIM2 LIM
LIM1 REF LIM
R V 100 k 0.1V
R 4.17 k
V V 2.5 V 0.1V
u: u
:
RLIM =
VLIM
ILIM
=
100mV
5A = 0.rt3
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.1.2.6 Peak Current Limit
Solve for RLIM:
(43)
The closest standard resistor is 0.02 Ω; therefore, choose RLIM = 0.02 Ω.
Assume RLIM2 = 100 kΩand calculate RLIM1:
(44)
The closest standard value is RLIM1 = 4.22 kΩ
8.2.1.2.7 Loop Compensation
Check the frequency of the output pole:
(45)
Check the frequency of the RHP zero:
(46)
The lower of the two is the RHP zero at 1.64 kHz, so the maximum crossover frequency should be 164 Hz or
less. Calculate the minimum COMP capacitor value:
(47)
To ensure stability over all conditions add some margin and choose CCMP = 47 nF.
8.2.1.2.8 Input Capacitance
Solve for the minimum CIN:
(48)
To minimize power supply interaction a 200% larger capacitance or more should be used particularly with PWM
dimming, therefore the actual ΔvIN-PP is much lower. Choose CIN = 10 µF.
Determine minimum allowable RMS current rating:
(49)
8.2.1.2.9 NFET
Determine minimum Q1 voltage rating and current rating:
(50)
(51)
The RMS current rating used in conjunction with the chosen FET RDS-ON to calculate power dissipation is:
(52)
24 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
90
92
94
96
98
100
10 12 14 16 18
Input Voltage (V)
Efficiency (%)
10 LEDs @ 500mA
G000
ROV1 = 1.24V ×ROV2
VTURN FOFF F1.24V =1.24V ×249k3
40V F1.24V = 8k:
ROV2 =
VHYSO
trJA=
5V
trJA= 250k3
RUVH =
RUV1 ×:VHYS FtrJA × RUV2 ;
trJA × :RUV1 + RUV2 ;=
1.89k3×:2V FtrJA × 10k3;
trJA × :10k3× 1.89k3;= 14.3k3
RUV 1 = 1.24V ×RU V2
VTURN FON F1.24V =1.24V ×10k3
7.8VF1.24V = 1.89k:
IDFMAX = ILED = 500mA
V
RD FMAX = V
O= 35V
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Typical Applications (continued)
8.2.1.2.10 Diode
Determine minimum D1 voltage rating and current rating:
(53)
(54)
8.2.1.2.11 Input UVLO
Since this is a PWM dimming application RUVH will be used. Start by picking RUV2 = 10 kΩand solve for RUV1:
(55)
The closest standard resistor is 1.89 kΩso choose RUV1 = 1.89 kΩ.
Solve for RUVH given the hysteresis requirements:
(56)
The closest standard resistor is 14.3 kΩso choose RUVH = 14.3 kΩ.
8.2.1.2.12 Output OVLO
Solve for ROV2:
(57)
The closest standard resistor is 249 kΩ; therefore, choose RUV2 = 249 kΩ. Solve for ROV1:
(58)
Choose the nearest standard resistor value of ROV1 = 8.06 kΩ.
8.2.1.3 Application Curve
Figure 23. Efficiency vs Input Voltage
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS92690-Q1
nDIM
OVP
TPS92690
RT
SYNC
1
2
3
4
VIN
VCC
IS
GATE
16
15
14
13
SS/SD
COMP
AGND
ILIM
5
6
7
8
PGND
CSP
IADJ
VREF
12
11
10
9
VOUT
VOUT
VIN
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.2 Simplified Application
Figure 24. Simplified Application Schematic
8.2.2.1 Design Requirements
Number of series LEDs: N
Single LED forward voltage: VLED
Single LED dynamic resistance: rLED
Nominal input voltage: VIN
Input voltage range: VIN-MAX, VIN-MIN
Switching frequency: fSW
Current sense voltage: VCS
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Peak current limit: ILIM
Input voltage ripple: ΔvIN-PP
Output OVLO characteristics: VTURN-OFF, VHYSO
Input UVLO characteristics: VTURN-ON, VHYS
Total start-up time: tTSU
26 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
L1min =
VO× 425 × 103
2 × fSW
:JH;
RADJ1 = RADJ2 × VIADJ
VREF FVIADJ
CS
CS LED
V
R I
IADJ
CS V
V 10
9
T11 SW
1 80 10
R 2.29 10 f
u
u u
O
O IN
V
D
V V
=
+
O IN
O
V V
D
V
-
=
D LED
r N r= ´
O LED
V N V= ´
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Typical Applications (continued)
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Operating Point
Given the number of series LEDs (N), the forward voltage (VLED) and dynamic resistance (rLED) for a single LED,
solve for the nominal output voltage (VO) and the nominal LED string dynamic resistance (rD):
(59)
(60)
Solve for the ideal nominal duty cycle (D):
Boost
(61)
Buck-Boost
(62)
Using the same equations, find the minimum duty cycle (DMIN) using maximum input voltage (VIN-MAX) and the
maximum duty cycle (DMAX) using the minimum input voltage (VIN-MIN). Also, remember that D' = 1 - D.
8.2.2.2.2 Switching Frequency
Set the switching frequency (fSW) by solving for RT:
(63)
8.2.2.2.3 Average LED Current
For all topologies, set the average LED current (ILED) knowing the desired current sense voltage (VCS) and
solving for RCS:
(64)
(65)
If the calculated RCS is too far from a desired standard value, then VCS will have to be adjusted to obtain a
standard value.
Setup the IADJ voltage by assuming RADJ2 = 100 kΩand solving for RADJ1:
(66)
If the calculated RADJ1 is too far from a desired standard value, then RADJ2 can be adjusted to obtain a standard
value.
8.2.2.2.4 Inductor Ripple Current
Find the minimum inductor value and calculate the nominal inductor ripple current (ΔiL-PP) by solving for the
appropriate inductor (L1):
8.2.2.2.4.1 Minimum Inductor Value
(67)
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS92690-Q1
m
CMP C
g
C 2 f
S u
RLIM =
V
LIM
ILIM
LIM1
LIM REF LIM1 LIM2
R
V V R R
u
1-DMAX
DMAX
ICO-RMS = ILED x
O
C = SWPP-LEDD füir xx LED DI x
IL-RMS = 1 + 1
12 xILED
'IL-PP x D' ¸
¹
·
¨
©
§2
D'
ILED x
IN
L PP
SW
V D
i
L f
-
´
D =
´
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.2.2.4.2 Inductor Ripple Current
(68)
If the inductor ripple current is too high given the chosen value increase L1 to get the required inductor current
ripple. For buck-boost applications replace VOwith VIN + VOwhen solving for L1.
The minimum allowable inductor RMS current rating (IL-RMS) can be calculated as:
8.2.2.2.4.3 RMS Inductor Current
(69)
8.2.2.2.5 LED Ripple Current
Set the nominal LED ripple current (ΔiLED-PP), by solving for the output capacitance (CO):
8.2.2.2.5.1 Output Capacitor
(70)
To set the worst case LED ripple current, use DMAX when solving for CO.
The minimum allowable RMS output capacitor current rating (ICO-RMS) can be approximated:
8.2.2.2.5.2 Output Capacitor RMS Current
(71)
8.2.2.2.6 Peak Current Limit
Set the peak current limit (ILIM) by setting the ILIM pin voltage and solving for the transistor path sense resistor
(RLIM):
(72)
(73)
8.2.2.2.7 Loop Compensation
Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the
necessary loop compensation can be determined.
A maximum bandwidth (fC) of 10 kHz is recommended and the COMP pin capacitor can be calculated using:
8.2.2.2.7.1 Compensation Capacitor
(74)
Check the location of the right-half plane zero and the output pole and make sure the crossover frequency is at
least a decade below the lowest of the two using the following equations:
28 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
IT-MAX = x ILED
1 - DMAX
DMAX
OMAXINMAXT VVV +
=--
O
V
=
MAXT
V-
1-DMAX
DMAX
ICIN-RMS = ILED x
12
ICIN-RMS = 'iL-PP
CIN = 'VIN-PP x fSW
ILED x D
CIN = 8 x 'VIN-PP x fSW
'iL-PP
fpCo = 1
2è× rD× CO
2
D
RHPZ
r D '
2 D L1
´
=p ´ ´
¦
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Typical Applications (continued)
8.2.2.2.7.2 RHP Zero
(75)
8.2.2.2.7.3 Output Capacitor Pole
(76)
If the input voltage range is wide use the maximum duty cycle (DMAX) corresponding to the minimum input
voltage to calculate the RHP zero. In general smaller CCMP values will provide greater bandwidth but the
bandwidth may be limited by the location of the RHP zero or output pole. For PWM dimming applications the
largest capacitor value that will fit the applications requirements is suggested.
8.2.2.2.8 Input Capacitance
Set the nominal input voltage ripple (ΔvIN-PP) by solving for the required capacitance (CIN):
Boost
(77)
Buck-Boost
(78)
Use DMAX to set the worst case input voltage ripple.
The minimum allowable RMS input current rating (ICIN-RMS) can be approximated:
Boost
(79)
Buck-Boost
(80)
8.2.2.2.9 NFET
The NFET voltage rating should be at least 15% higher than the maximum NFET drain-to-source voltage (VT-
MAX):
Boost
(81)
Buck-Bosst
(82)
The current rating should be at least 10% higher than the maximum average NFET current (IT-MAX):
8.2.2.2.9.1 Maximum Average NFET Current
(83)
Approximate the nominal RMS transistor current (IT-RMS) :
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS92690-Q1
( )
RR +x 2UV1UV
A20P
( )
xHYS A20V xP- R 2UV
R1UV
UVH
R =
RUV1 =1.24VV ONTURN -
-
R1.24V UV2
x
RUV2 =A20P
VHYS
ROV1 =1.24VV OFFTURN -
-
R1.24V OV2
x
ROV2 =VHYSO
A20P
FDDD VIP x=
ID-MAX = ILED
VRD-MAX = VIN-MAX + VO
VRD-MAX = VO
DSON
2
RMSTT RIP x= -
IRMST =
-D
x
ILED
Dc
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.2.2.9.2 RMS Transistor Current
(84)
Given an NFET with on-resistance (RDS-ON), solve for the nominal power dissipation (PT):
(85)
8.2.2.2.10 Diode
The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (VRD-MAX):
Boost
(86)
Buck-Boost
(87)
The current rating should be at least 10% higher than the maximum average diode current (ID-MAX):
8.2.2.2.10.1 Maximum Average Diode Current
(88)
Replace DMAX with D in the ID-MAX equation to solve for the average diode current (ID). Given a diode with forward
voltage (VFD), solve for the nominal power dissipation (PD): (89)
8.2.2.2.11 Output OVLO
The output OVLO is programmed with the turn-off threshold voltage (VTURN-OFF) and the desired hysteresis
(VHYSO). To set VHYSO, solve for ROV2:
(90)
To set VTURN-OFF, solve for ROV1:
(91)
8.2.2.2.12 Input UVLO
For all topologies, input UVLO is programmed with the turn-on threshold voltage (VTURN-ON) and the desired
hysteresis (VHYS).
Method 1: If no PWM dimming is required, a two resistor network can be used. To set VHYS, solve for RUV2:
(92)
To set VTURN-ON, solve for RUV1:
(93)
Method 2: If PWM dimming is required, a three resistor network is suggested. To set VTURN-ON, assume RUV2 =
10 kΩand solve for RUV1 as in Method 1. To set VHYS, solve for RUVH:
(94)
30 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
( )
BASESSSUTSUSS ttC --
-x
=V2.0 A10P
OCMPBYPBASESSSU CCk28C168t x
+
x:
+
x:
=
-- O
V
LED
I
COCMPVCCSU tttt ++=
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
Typical Applications (continued)
8.2.2.2.13 Soft-Start
For all topologies, if soft-start is desired, find the start-up time without CSS (tSU):
(95)
Then, if the desired total start-up time (tTSU) is larger than tSU, solve for the base start-up time (tSU-SS-BASE),
assuming that a CSS greater than 40% of CCMP will be used:
(96)
Then solve for CSS:
(97)
8.2.2.2.14 PWM Dimming Method
PWM dimming can be performed several ways:
Method 1: Connect the dimming MosFET (Q3) with the drain to the nDIM pin and the source to GND. Apply an
external PWM signal to the gate of QDIM. A pull down resistor may be necessary to properly turn off Q3.
Method 2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to the
cathode of the same diode.
8.2.2.2.15 Analog Dimming Method
Analog dimming can be performed several ways:
Method 1: Place a potentiometer in place of RIADJ1.
Method 2: Connect a controlled voltage source to the IADJ pin to control the current sense voltage (VCS).
9 Power Supply Recommendations
9.1 Bench Supply Current Limit
It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your
converter analysis and optimization. If not set high enough, current limit can be tripped during start up or when
your converter output power is increased, causing a foldback or shut-down condition. It is a common oversight
when powering up a converter for the first time.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TPS92690-Q1
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
The performance of any switching regulator depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines maximizes noise rejection and minimizes the generation of EMI
within the circuit.
Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing these
paths. In the boost regulator, the discontinuous current flows through the output capacitor (CO), D1, Q1, and RLIM
(if used). These loops should be kept as small as possible and the connections between all the components
should be short and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1
connect) should be just large enough to connect the components. To minimize excessive heating, large copper
pours can be placed adjacent to the short current path of the switch node.
The RT, COMP, CSP, IS, IADJ, ILIM, and SYNC pins are all high-impedance inputs which couple external noise
easily. Therefore, the loops containing these nodes should be minimized whenever possible.
In some applications the LED or LED array can be far away (several inches or more) from the TPS92690, or on
a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or
separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the
effects of parasitic inductance on the AC impedance of the capacitor.
32 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
Note critical paths and component placement:
Minimize power loop containing discontinuous currents
x Ground plane under IC for signal routing helps minimize noise coupling
SS/SD
COMP
IADJ
TPS92690
SYNC
PGND
AGND
ILIM
CSP
VREF
DAP
GATE
nDIM
VIN
OVP
RT
VCC
VOUT VIN
IS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ILED
GND
Input
Power
Minimize signal current loops (components close to IC)
STAR GROUND
Power Ground
discontinuous switching frequency currents
VOUT
TPS92690-Q1
www.ti.com
SLVSCU0 –NOVEMBER 2015
10.2 Layout Example
Figure 25. Layout Recommendation
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Links: TPS92690-Q1
TPS92690-Q1
SLVSCU0 –NOVEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TPS92690-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 12-Nov-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS92690Q1PWP/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92690
Q1PWP
TPS92690Q1PWPR/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92690
Q1PWP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Nov-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS92690-Q1 :
•Catalog: TPS92690
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS92690Q1PWPR/NOP
BHTSSOP PWP 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS92690Q1PWPR/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
14X 0.65
16X 0.30
0.19
2X
4.55
(0.15) TYP
0 - 8 0.15
0.05
3.3
2.7
3.3
2.7
2X 1.34 MAX
NOTE 5
1.2 MAX
(1)
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
5.1
4.9
B4.5
4.3
4X 0.166 MAX
NOTE 5
4214868/A 02/2017
PowerPAD HTSSOP - 1.2 mm max heightPWP0016A
PLASTIC SMALL OUTLINE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
PowerPAD is a trademark of Texas Instruments.
TM
116
0.1 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.400
THERMAL
PAD
17
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(3.4)
NOTE 9
(5)
NOTE 9
(3.3)
(3.3)
( 0.2) TYP
VIA (1.1) TYP
(1.1)
TYP
4214868/A 02/2017
PowerPAD HTSSOP - 1.2 mm max heightPWP0016A
PLASTIC SMALL OUTLINE
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
1
89
16
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
17
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
EXPOSED
METAL
SOLDER MASK
DEFINED
SOLDER MASK
METAL UNDER SOLDER MASK
OPENING
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
(3.3)
(3.3)
BASED ON
0.125 THICK
STENCIL
14X (0.65)
(R0.05) TYP
(5.8)
4214868/A 02/2017
PowerPAD HTSSOP - 1.2 mm max heightPWP0016A
PLASTIC SMALL OUTLINE
2.79 X 2.790.175 3.01 X 3.010.15 3.3 X 3.3 (SHOWN)0.125 3.69 X 3.690.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SYMM
SYMM
1
89
16
BASED ON
0.125 THICK
STENCIL
BY SOLDER MASK
METAL COVERED SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
17
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