74HC/HCT4543 MS! BCD TO 7-SEGMENT LATCH/DECODER/DRIVER FOR LCDs FEATURES | TYPICAL | * Latch storage of BCD inputs | SYMBOL | PARAMETER CONDITIONS NIT @ Blanking inputs | HC | HCT @ Output capability: non-standard propagation delay Icc category: MSI D. to 0 29 33 ns tPHL/ nen Cl = 15 pF PHL LD to O, Van = SV 32 | 31 ns GENERAL DESCRIPTION 'PLH BI to O, cc * 20 28 ns The 74HC/HCT4543 are high-speed . 5 Si-gate CMOS devices and are pin C input capacitance 36 | 35 | pF compatible with 4543" of the dissioation | 4000B series. They are specified in Cap power dissipatio k notes 1 and 2 42 42 pF | compliance with JEDEC standard no, 7A. Capacitance per package | The 74HC/HCT4543 are 8CD to 7-segment latch/decoder/drivers for liquid crystal displays. They have four address inputs (Og to 03), an active HIGH latch disable input (LD), an active HIGH blanking input (BI), an active HIGH phase input (PH) and seven buffered segment outputs (Qg to Og). The 4543 provides the function of a 4-bit storage latch and an 8-4-2-1 BCD to 7-segment decoder driver. The 4543 can invert the logic !evels of the output combination. The phase (PH}, blanking (BI) and latch disable (LD) inputs are used to reverse the function table phase, blank the display and store a BCD code, respectively. For liquid crystal displays a square-wave is applied to PH and the electrical common back-plane of the display. The outputs of the 4543 are directly connected to the segments of the liquid crystal. GND = OV; Tamp = 25 C; ty = tp = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (Pp in pW}: Pp =Cpp x Vcc x fit (CL x Vcc? x fg) where: fj = input frequency in MHz CL output load capacitance in pF fo = output frequency in MHz Vcc = supply voltage in V Z (Cy. x Vcc? x fg) = sum of outputs 2. For HC the condition is Vj = GND to Vcc For HCT the condition is Vj = GND to Vcc 1.5 V PACKAGE OUTLINES SEE PACKAGE INFORMATION SECTION PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 LD latch disable input {active HIGH) 5,3,2,4 Og to D3 address (data) inputs 6 PH phase input (active HIGH} 7 BI blanking input (active HIGH) 8 GNO ground (0 V} 9, 10, 11, 12 13, 15, 14 Q, to Qg segment Outputs 16 Voc positive supply voltage vo [| U [16] Yoc or (a [is] % 2 fas 95 (4] 13] 4 oo] 4543 E ou ( 6 | 1] Se ano [a | BE 7293282 Fig. 1 Pin configuration. s109 a,b. 9 , BCO/7SEG > 3 fee [T} atop 3 I5-10 6 . 10 2-0, 290.1 blo aren Loo.2 croft IP 3 2 12 Qg he 12 90.4 1D 4 13 1.0 a, ena 8 sore per a *4n10 110 bh 1 TC $ oss en gio +8 6 PR a, 4 72932641 3293263 Fig. 2 Logic symbol, Fig. 3 IEC lagic symbol. December 1990 1091c ta hs tha hy [io es 7293285 Fig. 4 Functional diagram. 7293208 Fig. 5 Segment designation. FUNCTION TABLE APPLICATIONS Driving LCD displays Driving fluorescent displays Driving incandescent displays Driving gas discharge displays INPUTS OUTPUTS DISPLAY LO | BI | PH* | D3/ Dz] Dy] Do} Ga} Oy | Qe] Ay] Gg} Ay | Ay x PHIL x |x) xX] xX foye fuyuye ye |e | blank H Lee c}/e}]ufe}yH tH |HIT HH] HY]L fo H bie LJ}oe}elH |e tH | Hype] eyey|ye } 4 H Lic je ]e |] Hf o|H TH} LY aH] HY] oe] Hf 2 H Lic ob | t |] H | H |H | H PH] aA] ob} by aR 3 H}eEin ce fH| ule letH fa} e lela] uy HJLIL L|H]|LJAH JH] L FH] HY} LTH YH YS HJbeit LiH{|H{L TH) L THI] H | HR] H YH | 6 HLL LiH | HI HI|HIT AH FAY e |e | ek Ge |? HJeLIL H{L]tL tL |H |] H |H|H)]H:H]H |] 8 H JL] L H|]L]t TH |H I] HyYH] HJ] ut] HTH | 9 HJ} LIL H/LC}]JH]LEJEFE|JeLIL] ue] L |] L | blank H Liye H|L]JH]H JE ]JeL}|eL|YL]L]L |] EL | blank H RU k H/}/H] eye Je|LJe|L]_e]L | L | blank H Lik H/}H]LJH Poe} e Jefeye]e fb } blank H Lie H{/H{JHIL Fe L TL | ue] ue] L | L fT blank H Lie H|H/}|H/HILEFEYL | LI] Lit |e ft blank L bie x |x |x | x * * as . as above H as above inverse of above above For liquid crystal displays, apply a square-wave to PH. ** Depends upon the BCD-code previously applied when LO = HIGH. H =HIGH voltage levei L = LOW voltage level X =dont care 1082 January 1986BCD to 7-segment latch/decoder/driver for LCDs 74HC/HCT4543 MSI 7293975 Fig. 6 Logic diagram. Ll} _! 4293267 Pit Le i ~ | i ee! Fig. 7 Display. RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134), For RATINGS see chapter HCMOS family characteristics, section Family specifications, standard outputs. January 1986 109374HC/HCT4543 MSI DC CHARACTERISTICS FOR 74HC Output capability: non-standard tee category: MSI Voltages are referenced to GND (ground = 0 V) Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER 1 UNIT | Vec| Vi OTHER +25 -40 to +851 40 to +125 v min, | typ. | max. } min. | max. | min. | max. 1.5 11.2 1.5 1.5 2.0 VIH HIGH level input voitage 3.15} 2.4 3.15 3.15 Vv 45 42,31 4.2 4.2 6.0 | 0.7 | 0.5 0.5 0.5 2.0 VIL LOW level input voltage 1.8 | 1.35 1,35 1.35 Vv 4.5 2.8 | 1.8 18 1.8 6.0 19 | 2.0 19 1.9 2.0 VIH -19=20uA VOH HIGH tevel output voltage | 4.4 | 4.5 44 4.4 v 45 or -lo=20uA 5.9 | 6.0 5.9 5.9 6.0 VIL ~IQ= 20 uA . v HIGH tevel volt 3.98 10.15 3.84 37 V 45 vin -Ig = 1.0 mA OH evel output voltage | 5 48] 0.16 5.34 5.2 6.0 YIL -Io =1.3mA 0 | 01 0.1 0.1 20 | Vin | to=20uA VOL LOW level output voltage 0 0.1 0.1 0.1 v 45 or lo=20uA 0 0.1 0.1 0.1 6.0 VIL lO = 20 pA Vv LOW level output voltage 0.15] 0.26 0.33 0.4 Vv 45 on lo = 1.0maA OL Dut voitag 0.16} 0.26 0.33 0.4 60 | yy | lo=13ma vec +fy input leakage current 0.1 1.0 1.0 uA 6.0 or GND Vcc {coc | quiescent supply current 8.0 80.0 160.0 | uA 6.0 or Ig =0 | GND 1094 January 1986BCD to 7-segment latch/decoder/driver for LCDs 74HC/HCT4543 MSI AC CHARACTERISTICS FOR 74HC GND = OV; t, = t = 6 ns; Cy = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40 to +85 | -40 to +125 Vv min.| typ. | max. | min.| max. | min. | max. . 91 340 425 510 2.0 teHL/ | Propagation delay 33 | 68 85 102 | ns | 45 | Fig. 12 'PLH Dn to Qn 26 | 58 72 87 6.0 . 102 | 370 465 555 2.0 *PHL/ | Propagation delay 37 | 74 93 tins | 45 | Fig 13 'PLH LD to Q, 30 163 73 94 6.0 . 66 | 265 330 400 2.0 tPHL/ | Propagation delay 24 | 53 86 80 |ns | 45 | Fig. 14 'PLH BI to Qn 19 | 45 56 68 6.0 . 5 | 200 250 300 2.0 teyt/ propagation delay 20 | 40 50 60 ns 45 'PLH PH to Qn 16 | 34 43 51 6.0 63 | 250 315 375 2.0 THU output transition time 23 =| 50 63 75 ns 4.5 Figs 12, 13 and 14 TLH 18 | 43 54 64 6.0 . 35 11 45 55 2.0 LD pulse width : t 7 4 9 1 ns 4.5 Fig. 13 Ww HIGH or LOW 6 13 8 9 60 set-up time 60 | 8 % 2.0 Fig. 15 t . 12 13 15 1 ns 4.5 ig. 1 Su Dp, to LD 10 12 13 15 6.0 . 30 =| 3 40 45 2.0 th hold time 6 1 8 9 ns 4.5 Fig. 15 Dp ta LD 5 4 7 8 6.0 March 1988 109574HC/HCT4543 MSI DC CHARACTERISTICS FOR 74HCT Output capability: non-standard lec category: MSI Voltages are referenced to GND (ground = 0 V) Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | Vcc | VI OTHER +25 40 to +85 | ~40 to +125 Vv min. | typ. | max. | min. | max. | min. | max. } 45 Vil HIGH level input voltage 2.0 | 1.6 2.0 2.0 v to 5.5 45 VaL LOW level input voltage 1.2 | 0.8 0.8 0.8 v to 5.5 VIH VOH HIGH level output voltage | 4.4 | 4.5 4.4 44 v 45 or -IQ=20KA } VIL VIH VOH HIGH level output voltage | 3.98 [4.32 3.84 3.7 v 4.5 or lo =1.0 mA VIL ViH VOL LOW level output voltage 0 0.1 0.1 0.1 v 45 | or lo = 20uA VIL VIH VOL LOW level output voltage 0.15} 0.26 0.33 0.4 v 4.5 or Io =1.0mA VIL Vec ti input leakage current 0.1 1.0 1.0 uA 5.5 or GNO Vcc lec Quiescent supply current 8.0 80.0 160.0 | uA 5.5 or i9o=0 GND sina air: 3 5 | gg | over nou Alec unit load coefficient is 1 100 | 360 450 490 | HA ef 72tV vec . GND; (note 1) . Note to HCT types The value of additional quiescent supply current (AIcc) for a unit load of 1 is given here. To determine Oicc per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT Og, 01, D2| 1.00 D3 0.50 Bi 0.50 LD 1.50 PH 1.25 1096 January 1986BCD to 7-segment latch/decoder/driver for LCDs 74HC/HCT4543 MSI AC CHARACTERISTICS FOR 74HCT GND = OV; t, = te = 6 ns; Cy = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | Voc | WAVEFORMS +25 | 4010 +85 | 4010 +125 Vv min.| typ.| max. | min.| max. | min. | max. tpyi/ propagation delay | : tPLH Dp t0 On 38 | 80 100 120 | ns 4.5 Fig. 12 tpHt/ propagation delay . ten LD two, 36 | 68 85 102 | ns 4.5 | Fig. 13 teHe/ propagation delay 01 tPLH BI to On 32 | 66 83 | 99 as 4.5 Fig. 14 ft L tPHL/ propagation delay } | tPLH PH to Q, 24 | 66 83 99 ns 45 rH! output transition time 23 | 50 63 | 75 (| ns 4.5 | Figs 12, 13 and 14 LD pulse width 15 45 Fig. 13 w HIGH or LOW 10 |4 8 "s ey ne set-up time . tu D, MOLD 12 | 4 15 18 as 45 | Fig. 18 hald time 1 45 Fig. 15 th Dp to LD 8 2 10 2 ns ig March 1988 109774HC/HCT4543 MSt APPLICATION DIAGRAMS common =2F backplane square wave, 7293281 GND W Veg Fig. 8 Connection to liquid crystai (LCD} display readout. appropriate voltage aga output 1293262 Fig. 9 Connection to incandescent display readout. aopropriata voltage 4543 output y GND 7293283 Fig. 10 Connection to gas discharge display readout. asa outaut QO pe to filament GNO Lo, seoply whe, GNO oF aopropriate 7299284 voltage Dalow GND Fig. 11 Connection to fluorescent display readout. 1098 January 1986BCD to 7-segment latch/decoder/driver for LCDs 74HC/HCT4543 MSI AC WAVEFORMS D, INPUT va LO INPUT Yn 2 ! | tw el PHL lo FPL Hm lee toe er Me Cee I Q, OUTPUT Q, OUTPUT Vig 1 7267877 tH = le ~~ ven tha 7293268 cel te OTHE ce! be trun Fig. 12 Waveforms showing the address input (Dy) to output (Q,_} propagation delays and the output transition times. Fig. 13 Waveforms showing the latch disable input (LD) to output (Q,) propagation delays and the output transition times. B) INPUT Q, OUTPUT 7293269 Fig. 14 Waveforms showing the blanking (BI) to output (Q,) propagation delays and the output transition times. 0D, INPUT LO INPUT Ms f \ 1299270 Fig. 15 Waveforms showing the address (Dy) to latch disable (LD) input set-up and hold times. Note to Fig. 15 The shaded areas indicate when the input is permitted to change for predictable output performance. Note to AC waveforms (1) HC : Vy = 50%: Vj = GND to Vcc. HCT: Vy = 1.3V; Vy = GND to 3V. January 1986 1099