TC74HCT574AFWG-ELP - TOSHIBA

September, 2014 − Rev. 11 1Publication Order Number:

MC74HCT574A/D

MC74HCT574A

Octal 3-State Noninverting

D Flip-Flop with

LSTTL-Compatible Inputs

High−Performance Silicon−Gate CMOS

The MC74HCT574A is identical in pinout to the LS574. This

device may be used as a level converter for interfacing TTL or NMOS

outputs to High Speed CMOS inputs.

Data meeting the setup time is clocked to the outputs with the rising

edge of the Clock. The Output Enable input does not affect the states

of the flip−flops, but when Output Enable is high, all device outputs

are forced to the high−impedance state. Thus, data may be stored even

when the outputs are not enabled.

The HCT574A is identical in function to the HCT374A but has the

flip−flop inputs on the opposite side of the package from the outputs to

facilitate PC board layout.

Features

•Output Drive Capability: 15 LSTTL Loads

•TTL NMOS Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 mA

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

•Chip Complexity: 286 FETs or 71.5 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

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MARKING DIAGRAMS

SOIC−20

HCT574A

AWLYYWWG

20

1

See detailed ordering and shipping information on page 5 o

f

this data sheet.

ORDERING INFORMATION

1

20

HCT

574A

ALYWG

G

TSSOP−20

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

SOIC−20

DW SUFFIX

CASE 751D

TSSOP−20

DT SUFFIX

CASE 948E

FUNCTION TABLE

Inputs Output

OE Clock D Q

LHH

LLL

L L,H, X No Change

HXXZ

X = don’t care

Z = high impedance

PIN ASSIGNMENT

D4

D2

D1

D0

OUTPUT

ENABLE

GND

D7

D6

D5

D3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q3

Q2

Q1

Q0

VCC

CLOCK

Q7

Q6

Q5

Q4

DATA

INPUTS

D0 219

Q0

D1

D2

D3

D4

D5

D6

D7

CLOCK

OUTPUT ENABLE

3

4

5

6

7

8

9

11

1

18

17

16

15

14

13

12

Q1

Q2

Q3

Q4

Q5

Q6

Q7

NON-

INVERTING

OUTPUTS

PIN 20 = VCC

PIN 10 = GND

Figure 1. Logic Diagram

MC74HCT574A

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2

ÎÎÎÎÎÎÎÎÎÎÎ

Design Criteria

ÎÎÎ

Value

ÎÎÎ

Units

ÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Count*

ÎÎÎ

71.5

ÎÎÎ

ea

ÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Propagation Delay

ÎÎÎ

1.5

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power Dissipation

ÎÎÎ

5.0

ÎÎÎ

mW

ÎÎÎÎÎÎÎÎÎÎÎ

Speed Power Product

ÎÎÎ

0.0075

ÎÎÎ

pJ

*Equivalent to a two−input NAND gate.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V

Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V

Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V

Iin DC Input Current, per Pin ±20 mA

Iout DC Output Current, per Pin ±35 mA

ICC DC Supply Current, VCC and GND Pins ±75 mA

PDPower Dissipation in Still Air, SOIC Package† 500 mW

Tstg Storage Temperature –65 to +150 _C

TLLead Temperature, 1 mm from Case for 10 secs

(SOIC Package) 260

_C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of

these limits are exceeded, device functionality should not be assumed, damage may occur and

reliability may be affected.

†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

Vin, Vout DC Input Voltage, Output V oltage

(Referenced to GND) 0 VCC V

TAOperating Temperature, All Package Types –55 +125 _C

tr, tfInput Rise and Fall Time (Figure 2) 0 500 ns

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HCT574A

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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbo

l

Parameter Test Conditions VCC

V

Guaranteed Limit

Unit

–55 to

25_C≤ 85_C≤ 125_C

VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V

|Iout| ≤ 20 mA4.5

5.5 2.0

2.0 2.0

2.0 V

VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V

|Iout| ≤ 20 mA4.5

5.5 0.8

0.8 0.8

0.8 V

VOH Minimum High−Level Output Voltage Vin = VIH or VIL

|Iout| ≤ 20 mA4.5

5.5 4.4

5.4 4.4

5.4

Vin = VIH or VIL

|Iout| ≤ 6.0 mA 4.5 3.98 3.84 3.7 V

VOL Maximum Low−Level Output Voltage Vin = VIH or VIL

|Iout| ≤ 20 mA4.5

5.5 0.1

0.1 0.1

0.1

Vin = VIH or VIL

|Iout| ≤ 6.0 mA 4.5 0.26 0.33 0.4

Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 mA

ICC Maximum Quiescent Supply Current

(per Package) Vin = VCC or GND

Iout = 0 mA5.5 4.0 40 160 mA

IOZ Maximum Three−State Leakage

Current Vin = VIL or VIH (Note 1)

Vout = VCC or GND 5.5 −0.5 –5.0 –10 mA

DICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input

Vin = VCC or GND, Other Inputs

lout = 0 mA5.5

≥ –55_C 25_C to 125_C

mA

2.9 2.4

1. Output in high−impedance state.

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbo

l

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

– 55 to

25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

fMAX

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 5)

ÎÎÎÎ

30

ÎÎÎÎ

24

ÎÎÎÎÎ

20

ÎÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q

(Figures 2 and 5)

ÎÎÎÎ

30

ÎÎÎÎ

38

ÎÎÎÎÎ

45

ÎÎÎ

ns

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎÎÎ

28

ÎÎÎÎ

35

ÎÎÎÎÎ

42

ÎÎÎ

ns

ÎÎÎÎ

tPZH,

tPZL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay Time, Output Enable to Q

(Figures 3 and 6)

ÎÎÎÎ

28

ÎÎÎÎ

35

ÎÎÎÎÎ

42

ÎÎÎ

ns

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 2, 3 and 5)

ÎÎÎÎ

12

ÎÎÎÎ

15

ÎÎÎÎÎ

18

ÎÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎÎ

10

ÎÎÎ

pF

CPD Power Dissipation Capacitance (Per Flip−Flop)*

Typical @ 25°C, VCC = 5.0 V

pF

58

*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TIMING REQUIREMENTS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbo

l

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Figure

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock

ÎÎÎÎ

4

ÎÎÎÎ

10

ÎÎÎ

13

ÎÎÎÎ

ÎÎÎ

15

ÎÎÎ

ns

ÎÎÎÎ

th

ÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data

ÎÎÎÎ

4

ÎÎÎÎ

5.0

ÎÎÎ

5.0

ÎÎÎÎ

ÎÎÎ

5.0

ÎÎÎ

ns

ÎÎÎÎ

tw

ÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock

ÎÎÎÎ

2

ÎÎÎÎ

15

ÎÎÎ

19

ÎÎÎÎ

ÎÎÎ

22

ÎÎÎ

ns

ÎÎÎÎ

tr, If

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

ÎÎÎÎ

2

ÎÎÎÎ

ÎÎÎ

500

ÎÎÎ

ÎÎÎÎ

500

ÎÎÎ

500

ÎÎÎ

ns

MC74HCT574A

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4

EXPANDED LOGIC DIAGRAM

CLOCK

ENABLE

OUTPUT

11

1

D0

2

C

19

D

Q

Q0

D1

3

C

18

D

Q

Q1

D2

4

C

17

D

Q

Q2

D3

5

C

16

D

Q

Q3

D4

6

C

15

D

Q

Q4

D5

7

C

14

D

Q

Q5

D6

8

C

13

D

Q

Q6

D7

9

C

12

D

Q

Q7

SWITCHING WAVEFORMS

CLOCK

Q

trtf

3.0 V

GND

2.7 V

1.3 V

0.3 V

90%

1.3 V

10%

tPLH tPHL

tTLH tTHL

tw

1/fmax

Q

1.3 V

90%

10%

tPZL tPLZ

tPZH tPHZ

3.0 V

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

OUTPUT

ENABLE

1.3 V

Figure 2.

1.3 V

CLOCK

3.0 V

VALID

GND

3.0 V

GND

tsu th

1.3 V

DATA

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

Figure 3.

Figure 4. Figure 5. Test Circuit

Figure 6. Test Circuit

MC74HCT574A

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ORDERING INFORMATION

Device Package Shipping†

MC74HCT574ADWG SOIC−20 WIDE

(Pb−Free) 38 Units / Rail

MC74HCT574ADWR2G SOIC−20 WIDE

(Pb−Free) 1000 Tape & Reel

MC74HCT574ADTR2G TSSOP−20

(Pb−Free) 2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC74HCT574A

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6

PACKAGE DIMENSIONS

TSSOP−20

DT SUFFIX

CASE 948E−02

ISSUE C

DIM

A

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

A

B

−T−

0.100 (0.004)

C

DGH

SECTION N−N

K

K1

JJ1

N

M

F

−W−

SEATING

PLANE

−V−

−U−

S

U

M

0.10 (0.004) V S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E 6.40 0.252

--- ---

S

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HCT574A

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7

PACKAGE DIMENSIONS

SOIC−20

DW SUFFIX

CASE 751D−05

ISSUE G

20

1

11

10

B20X

H10X

C

L

18X A1

A

SEATING

PLANE

q

hX 45_

E

D

M

0.25 M

B

M

0.25 S

AS

B

T

e

T

B

A

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

__

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Phone: 421 33 790 2910

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Phone: 81−3−5817−1050

MC74HCT574A/D

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