NLHV18T3244MNTWG - ON SEMICONDUCTOR

May, 2013 − Rev. 0

1Publication Order Number:

NLHV18T3244/D

NLHV18T3244

18-Channel Level Shifter

The NLHV18T3244 is an 18−channel level translator designed for

high voltage level shifting applications such as displays. The 18

channels are divided into twelve and two three channel groups, with

each group controlled by the inverting inputs SEL1, SEL2 and, SEL3;

respectively. The EN input is used to select the ‘ON’ or power saving

shutdown modes.

Each channel consists of a high voltage output buffer. The output

buffers use N−channel low side and P−channel high side transistors.

The output signal on pins OUT1 to OUT18 is pulled by the transistors

to the positive high or negative low voltage on the VHx and VLx power

supply pins, respectively, depending on the voltage of the inverting

pins.

Features

•18 Non−Inverting / Inverting Channels

•VH1, VH2 Supply Range: 5 V to 25 V

•VL1, VL2 Supply Range: −13 V to 0 V

•VHx – VLx Difference Range: 5 V to 25 V

•VL1 and VL2 can be tied together or connected to independent supply

voltages as long as VL1 ≤ VL2

•VD Supply Range: 2 V to 5.5 V

•Outputs Specified with 1000 pF Capacitive Loads

•Disable Function

•Low Standby Current

•No Glitch on Power−Up

•Available in: 5 mm x 10 mm, 0.5 mm pitch, QFN50 Package

Typical Applications

•OLED Drivers

•High Voltage Level Shifters

•Piezoelectric Motor Drivers

MARKING

DIAGRAM

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QFN50

CASE 485BW

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

NLHV

18T3244

AWLYYWWG

NLHV18T3244

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Figure 1. Simplified Schematic − Option I (VL1 3 VL2)

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FUNCTION TABLE (X Input = ‘Don’t Care, Hi−Z = High Impedance Tri−State Output)

Input Output

EN SEL1 SEL2 SEL3 Block 1 (OUT1−OUT12) Block 2 (OUT13 − OUT15) Block 3 (OUT16 − OUT18)

GND X X X Hi−Z Hi−Z Hi−Z

VDGND GND GND Normal Normal Normal

VDGND GND VDNormal Normal Inverted

VDGND VDGND Normal Inverted Normal

VDGND VDVDNormal Inverted Inverted

VDVDGND GND Inverted Normal Normal

VDVDGND VDInverted Normal Inverted

VDVDVDGND Inverted Inverted Normal

VDVDVDVDInverted Inverted Inverted

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Figure 2. Pin Assignments

(Top View)

PIN ASSIGNMENTS

Pin Name Pin Number Pin Name Pin Number Pin Name Pin Number

OUT1 1 OUT18 18 IN8 35

OUT2 2 GND 19 IN7 36

OUT3 3 VH2 20 IN6 37

OUT4 4 VL2 21 IN5 38

OUT5 5 VH1 22 IN4 39

OUT6 6 VL1 23 IN3 40

OUT7 7 VD 24 IN2 41

OUT8 8 IN18 25 IN1 42

OUT9 9 IN17 26 GND 43

OUT10 10 IN16 27 SEL3 44

OUT11 11 IN15 28 SEL2 45

OUT12 12 IN14 29 SEL1 46

OUT13 13 IN13 30 EN 47

OUT14 14 IN12 31 VD 48

OUT15 15 IN11 32 VL1 49

OUT16 16 IN10 33 VH1 50

OUT17 17 IN9 34 No Connect Center Tap

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ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Condition Value Unit

VHx High−side DC Supply Voltage −0.5 to +30 V

VLx Low−side DC Supply Voltage −15 to +0.5 V

VHx −

VLx

Differential VH – VL Voltage 0 to +30 V

VDLogic Supply Voltage −0.5 to +5.5 V

VIInput (IN1 – IN18), Invert (SEL1 – SEL3)

and Enable (EN) Control Pins

−0.5 to VD + 0.5 V

VOUT Output Voltage Pins (OUT1 – OUT18) VLx – 0.5 to VHx + 0.5 V

IOUT Continuous Output Current (OUT1 –

OUT18)

One channel is sinking or

sourcing current while the

remaining seventeen channels

are disconnected (IOUT = 0 A)

100 mA

IHX DC Supply Current Through VHX 100 mA

ILX DC Supply Current Through VLX 100 mA

IDDC Supply Current Through VD50 mA

RqJA Junction to Ambient Resistance (Note 1) 68 °C/W

TJJunction Temperature +115 °C

TSTG Storage Temperature −65 to +150 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. 4 layer PCB with 100 sq. mm, 1 oz. heat spreading including traces, JEDEC 51.7 equivalent.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VH1 High−side DC Supply Voltage 5 25 V

VH2 High−side DC Supply Voltage (Note 2) 5 25 V

VL1 Low−side Negative DC Supply Voltage (Note 3)

(VL1 ≤ VL2)

−13 0 V

VL2 Low−side Negative DC Supply Voltage (Note 4) VL1 0 V

VHx − VLx Differential VH – VL Voltage 5 25 V

VDLogic Supply Voltage 2 5.5 V

VIInput (IN1 – IN18), Invert (SEL1 – SEL3) and Enable (EN) GND VDV

VOUT Output Voltage (OUT1 – OUT18) VLx VHx V

TAOperating Temperature Range −40 +85 °C

nt/nVInput Transition Rise or Rate

VI, VIO from 30% to 70% of VD; VD =3.3 ± 0.3 V 0 10

2. VH1 and VH2 can be connected together.

3. VL1 must be at the lowest DC supply voltage.

4. VL1 and VL2 can be connected together.

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ELECTRICAL CHARACTERISTICS (VHx =15 V, VLx = −5 V, VD = 2 to 5.5 V and EN = VD; unless otherwise specified)

Symbol Parameter Parameter Test Conditions

−405C to +855C

Unit

Min Typ Max

POWER SUPPLY

IDDigital Supply Static

Current

Enabled (EN = VD)IN1 to IN18 = 0 V or

IN1 to IN18 = VD

2 mA

Disabled (EN = 0 V),

(Power Down)

5 10 mA

IH1 Block 1 and 2 High

Voltage Supply Static

Current

Enabled (EN = VD)IN1 to IN18 = 0 V or

IN1 to IN18 = VD

2 mA

Disabled (EN = 0 V),

(Power Down)

5mA

IH2 Block 3 High Voltage

Supply Static Current

Enabled (EN = VD)IN1 to IN18 = 0 V or

IN1 to IN18 = VD

2 mA

Disabled (EN = 0 V),

(Power Down)

5mA

IL1 Block 1 and 2 Low

Voltage Supply Static

Current

Enabled (EN = VD)IN1 to IN18 = 0 V or

IN1 to IN18 = VD

2 mA

Disabled (EN = 0 V),

(Power Down)

5mA

IL2 Block 3 Low Voltage

Supply Static Current

Enabled (EN = VD)IN1 to IN18 = 0 V or

IN1 to IN18 = VD

2 mA

Disabled (EN = 0 V),

(Power Down)

5mA

VH1 High−Side DC Supply 1 5 15 25 V

VH2 High−Side DC Supply 2 5 17 25 V

VL1 Low−Side DC Supply 1 VL1 ≤ VL2

VL1 must be the lowest voltage in all

conditions

−13 −5 0 V

VL2 Low−Side DC Supply 2 VL1 −5 0 V

VHx − VLDifferential VHx – VL Voltage 5 25 V

INPUT (IN1 – IN18, EN, SEL1 – SEL3)

VIH Logic ‘1’ Input Voltage 0.7 x VDV

VIL Logic ‘0’ Input Voltage 0.3 x VDV

IIH Logic ‘1’ Input Current VI = VIH 0.1 10 mA

IIL Logic ‘0’ Input Current VI = VIL 0.1 10 mA

CIN Input Capacitance TA = 25_C3.5 pF

RIN Input Resistance TA = 25_C50 MW

OUTPUT (OUT1 – OUT18)

VOH VOUT High Voltage INx = 3.3 V, IL = 20 mA VHX−0.2 V

VOL VOUT Low Voltage INx = 0 V, IL = 20 mA VLX +

0.12 V

ROH ON Resistance, VH to OUTx IL = 20 mA 5 8.5 W

ROL ON Resistance, VL to OUTx IL = 20 mA 5 7.5 W

IPEAK Peak Output Current CL = 1000 pF 1100 mA

IOZ Output Tri−state Mode Leakage Current INx = 3.3 V, VD = 3.3 V, EN = GND 5mA

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SWITCHING CHARACTERISTICS (CL = 1000 pF, VHx = 15 V, VLx = −5 V, VD = 3.3 V and EN = 3.3 V; unless otherwise specified)

Symbol Parameter Test Conditions

−405C to +855C

Unit

Min Typ Max

tROutput Rise Time Measured from 10% to 90% 20 35 ns

tFOutput Fall Time Measured from 90% to 10% 20 35 ns

tRFD Output Rise and Fall Time Mismatch (per

channel)

5 ns

tSK Output Skew Matching (channel−to−channel) Measured from 50% to 50% 5 ns

tD+ Turn−On Propagation Delay Measured from 50% to 50% 55 ns

tD−Turn−Off Propagation Delay Measured from 50% to 50% 55 ns

tDD High−to−Low/Low−to−High Propagation

Delay Mismatch (per channel)

Measured from 50% to 50% 5 ns

SC#MAX Maximum channels switched in 100 ns se-

quence

Delta between inputs of channels

must be 100 ns if channels are

switched in sequence

Con_OUT Outputs connected together to increase drive

capability

fMAX Maximum switching Frequency For all VHx and VLx voltages 100 kHz

tEN Enable Time Measured from 50% EN to 50%

OUT_xx

9.8 15 ms

tDIS Disable Time Measured from 50% EN to 50%

OUT_xx_Hi−Z

2.2 ms

DATA RATES (CL = 1000 pF, VHx = 15 V, VLx = −5 V, VD = 3.3 V and EN = 3.3 V; unless otherwise specified)

Channel Conditions Data Rate Unit

IN1 − IN6 (Note 5) Simultaneous Switching (Turn ON and OFF in sequence, 100 ns

between channels)

120 Hz

Per Channel 56 kHz

IN7− IN12 (Note 5) Per Channel 120 Hz

IN13 – IN 15 (Note 5) Per Channel 120 Hz

IN16 – IN18 (Note 5) Simultaneous Switching

(Turn ON and OFF sequence, 100 ns between channels)

120 Hz

5. While IN1 − IN6 are switching, IN1 − IN18 are not switching.

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APPLICATIONS INFORMATION

Power−Up Sequence

The recommended power−up sequence of the power

supplies is provided in Figure 3.

Figure 3. Power−Up Sequence

VH2 = 17 V

VH1 = 15 V

VL2 = 0 V

VL1 = -5 V

200 ms 20 ms 20 ms

Power Supply Guidelines

Supply voltage VL1 must be less than or equal to voltage

VL2. The substrate is connected to VL1; thus, VL1 must be

the at lowest voltage potential to ensure proper biasing of the

internal level shifting circuits. In addition, setting VL1 to the

lowest voltage ensures proper operation of the overvoltage

and ESD protection circuits connected on the supply voltage

and input/output lines, respectively.

For optimal performance, 0.1 and 1 mF decoupling

capacitors are recommended for the VD, VL1, VL2, VH1, and

VH2 power supply pins. High frequency ceramic or tantalum

capacitors are good design choices to filter and bypass any

noise signals on the supply voltage lines to the ground plane

of the PCB. The noise immunity will be maximized by

placing the capacitors as close as possible to the supply and

ground pins, along with minimizing the PCB connection

traces. In addition, a ferrite bead can be placed between the

two decoupling capacitors to form a bi-directional LC Tee

filter if additional noise immunity is required.

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Recommended PCB Options

2 Layer PCB

•Traces = 1.4 mm width, tin plating, copper 2 oz

•Routing of power lines will be in top layer

•In order to minimize inductance, returning current will

be routed as close as possible to the power lines

4 Layer PCB

•Traces = 1.4 mm width, tin plating, copper 2 oz

•In order to reduce inductance, construction of layers

will be as drawing below

•Power lines will be routed in top and returning current

will be routed in inner1 right below the power lines

Figure 4. Recommended 4Layer PCB Options

PCB Layout Instructions

•The power devices should be placed as close as

possible to each other in order to reduce inductance

•Decoupling filter capacitors should be placed as close

as possible to the device in order to reduce ripple on

supply.

•The VH, VL and VD decoupling filter capacitors

connected between the power supply and GND should

be constructed from scaled capacitors. A small value

capacitor of 0.1 mF, which filters high frequency, should

be placed as close as possible to the device. A larger

value capacitor of 1 mF, which filters low frequency

should be placed adjacent to the small capacitor, but

farther away from the device.

•All output line should be far from each other to prevent

cross talk

•All input lines should be matched in length to meet

skew timing

ORDERING INFORMATION

Device Package Shipping†

NLHV18T3244MNTWG QFN−50

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

QFN50, 5x10, 0.5P

CASE 485BW

ISSUE O

SEATING

NOTE 4

0.15 C

(A3) A

50X

BOTTOM VIEW

DETAIL A

TOP VIEW

SIDE VIEW

DA B

0.15 C

ÉÉÉ

PIN ONE

LOCATION

0.10 C

0.08 C

A0.10 B

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.25mm FROM TERMINAL TIP

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.18 0.30

D5.00 BSC

D2 3.20 3.45

E10.00 BSC

8.45E2 8.20

e0.50 BSC

L0.30 0.50

L1 0.00 0.15

NOTE 3

PLANE

DIMENSIONS: MILLIMETERS

0.32

8.51

0.50

3.51

50X

0.63

50X

5.30

10.30

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DETAIL B

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTION K0.20 MIN

PITCH

50X

PKG

OUTLINE

RECOMMENDED

0.10 BC

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

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