ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL GENERAL DESCRIPTION FEATURES The ICS813321-04 is a two stage device - a VCXO ICS followed by a FemtoClockTM PLL. The FemtoClock HiPerClockSTM PLL can multiply the crystal frequency of the VCXO up to a range of 122MHz to 160MHz, with a random rms phase jitter of less than 1ps (1.875MHz - 20MHz). This phase jitter performance meets the requirements of 1Gb/10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to OC48. * One 3.3V or 2.5V LVPECL output pair * Crystal operating frequency range: 14MHz - 20MHz * VCO range: 490MHz - 640MHz * Output frequency range: 122MHz - 160MHz * VCXO pull range: 50ppm (typical APR) @ 3.3V * Supports the following applications (among others): SONET, Ethernet, Fibre Channel * RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.53ps (typical) @ 3.3V * Supply voltage modes: VCC/VCCO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages PIN ASSIGNMENT BLOCK DIAGRAM VCO_SEL Pullup XTAL_IN 0 19.44MHz XTAL_OUT VCXO Phase Detector VCO N = /4 490MHz - 640MHz 1 VC M = /25 (default), /32 Pullup 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCO_SEL nc OE SEL VC nc XTAL_IN XTAL_OUT ICS813321-04 OE Pullup 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View SEL IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL Q nQ nc VCCO Q nQ VEE nc VCCA VCC 1 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TABLE 1. PIN DESCRIPTIONS 1, 6, 11, 15 nc Unused 2 VCCO Power Output supply pin. 3, 4 Q, nQ Output Differential clock outputs. LVPECL interface levels. No connect. 5 VEE Power Negative supply pin. 7 VCCA Power Analog supply pin. 8 VCC Power 9, 10 XTAL_OUT, XTAL_IN Input 12 VC Input Core supply pin. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. VCXO control voltage input. 13 SEL Input 14 OE Input 16 VCO_SEL Input Pulldown Select pin. LVCMOS/LVTTL interface levels. See Table 3. Output enable pin. When HIGH, the output is active. Pullup When LOW, the output is in a high impedance state. LVCMOS/LVTTL interface. Pullup VCO select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics Table, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k TABLE 3. SEL FUNCTION TABLE Control Input SEL M 0 /25 (defalut) 1 /32 IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 2 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 92.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VCC - 0.10 3.3 VCC V 3.135 3.3 VCC Core Supply Voltage VCCA Test Conditions VCCO Output Supply Voltage 3.465 V ICCA Analog Supply Current 10 mA IEE Power Supply Current 130 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, VCCO = 2.5V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC - 0.10 3.3 VCC V VCCO Output Supply Voltage 2.375 2.5 2.625 V ICCA Analog Supply Current 10 mA IEE Power Supply Current 130 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.5V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter Minimum Typical Maximum Units 2.375 2.5 2.625 V Analog Supply Voltage VCC - 0.10 2.5 VCC V 2.375 2.5 VCC Core Supply Voltage VCCA Test Conditions VCCO Output Supply Voltage 2.625 V ICCA Analog Supply Current 10 mA IEE Power Supply Current 125 mA IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 3 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions OE, VCO_SEL SEL OE, VCO_SEL SEL Minimum Typical Maximum Units VCC = 3.3V 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V VCC = VIN = 3.465V or 2.625V 5 A VCC = VIN = 3.465V or 2.625V 150 A VCC = 3.465V or 2.625V, VIN = 0V -150 A VCC = 3.465V or 2.625V, VIN = 0V -5 A TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1. 0 V NOTE 1: Outputs terminated with 50 to VCCO - 2V. TABLE 4F. LVPECL DC CHARACTERISTICS, VCC = 3.3V5% OR 2.5V5%, VCCO = 2.5V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.5 V 0.4 1.0 V NOTE 1: Outputs terminated with 50 to VCCO - 2V. IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 4 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter fOUT fVCO Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range t R / tF Output Rise/Fall Time t jit(O) Test Conditions Minimum VCO_SEL = 1 122 Typical 155.52MHz (1.875MHz - 20MHz) Maximum Units 160 MHz 0.53 20% to 80% odc Output Duty Cycle NOTE 1: Phase jitter using a cr ystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. ps 490 640 MHz 250 600 ps 48 52 % Maximum Units 160 MHz TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V5%, VCCO = 2.5V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter fOUT fVCO Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range t R / tF Output Rise/Fall Time t jit(O) Test Conditions Minimum VCO_SEL = 1 122 155.52MHz (1.875MHz - 20MHz) Typical 0.64 20% to 80% odc Output Duty Cycle NOTE 1: Phase jitter using a cr ystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. ps 490 640 MHz 250 600 ps 48 52 % Maximum Units 160 MHz TABLE 5C. AC CHARACTERISTICS, VCC = VCCO = 2.5V5%, VEE = 0V, TA = 0C TO 70C Symbol Parameter fOUT fVCO Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range t R / tF Output Rise/Fall Time t jit(O) Test Conditions Minimum VCO_SEL = 1 122 155.52MHz (1.875MHz - 20MHz) 20% to 80% odc Output Duty Cycle NOTE 1: Phase jitter using a cr ystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 5 Typical 0.53 ps 490 640 MHz 250 60 0 ps 48 52 % ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TYPICAL PHASE NOISE AT 155.52MHZ 0 -10 -20 155.52MHz -30 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical) -40 dBc Hz -60 NOISE POWER -50 -80 OC-12 Filter -70 Raw Phase Noise Data -90 -100 -110 -120 -130 -140 -150 -160 -170 Phase Noise Result by adding Sonet OC-12 Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 6 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL PARAMETER MEASUREMENT INFORMATION 2.8V0.04V 2V 2V 2.8V0.04V 2V VCC, VCCO Qx VCC SCOPE VCCO Qx SCOPE VCCA VCCA LVPECL LVPECL nQx nQx VEE VEE -1.3V0.165V -0.5V 0.125V 3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT 2V 2V Qx Noise Power VCC, VCCO Phase Noise Plot SCOPE VCCA Phase Noise Mask LVPECL nQx VEE f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -0.5V 0.125V RMS PHASE JITTER 2.5V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT Q 80% 80% nQ VSW I N G Clock Outputs t PW 20% 20% tR t PERIOD tF odc = t PW x 100% t PERIOD OUTPUT RISE/FALL TIME IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 7 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813321-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. 3.3V or 2.5V VCC .01F 10 .01F 10F VCCA FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 8 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50 125 FOUT 125 FIN Zo = 50 Zo = 50 FOUT 50 RTT = 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o FIN 50 VCC - 2V Zo = 50 RTT 84 FIGURE 2A. LVPECL OUTPUT TERMINATION IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 84 FIGURE 2B. LVPECL OUTPUT TERMINATION 9 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 10 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL VCXO CRYSTAL SELECTION Choosing a crystal with the correct characteristics is one of the most critical steps in using a Voltage Controlled Crystal Oscillator (VCXO). The crystal parameters affect the tuning range and VC accuracy of a VCXO. Below are the key variables and an example of using the crystal parameters to calculate the tuning range of the VCXO. Oscillator Control Voltage CV C VCXO (Internal) XTAL CL1 - Control voltage used to tune frequency - Varactor capacitance, varies due to the change in control voltage CL1, CL2 - Load tuning capacitance used for fine tuning or centering nominal frequency CS1, CS2 - Stray Capacitance caused by pads, vias, and other board parasitics V CS1 VC CV CS2 CL2 Optional FIGURE 4. VCXO OSCILLATOR CIRCUIT TABLE 6. EXAMPLE CRYSTAL PARAMETERS Symbol Parameter fN Nominal Frequency fT Frequency Tolerance fS Frequency Stability Test Conditions Minimum Typical Maximum Units 20 MHz 20 ppm 20 ppm 70 C 14 Operating Temperature Range 0 CL Load Capacitance 12 pF CO Shunt Capacitance 4 pF C1, C2 Pullability Ratio ESR Equivalent Series Resistance 220 20 Drive Level 1 Aging @ 25C 3 per year mW ppm Fundamental Mode of Operation IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 240 11 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TABLE 7. VARACTOR PARAMETERS Symbol Parameter CV_LOW Low Varactor Capacitance Test Conditions VC = 0V Minimum 6 pF CV_HIGH High Varactor Capacitance VC = 3.3V 11 pF FORMULAS C Low = (C (C L1 L1 + C S 1 + CV _ Low ) (C L 2 + C S 2 + CV _ Low ) C High = + C S 1 + CV _ Low ) + (C L 2 + C S 2 + CV _ Low ) (C (C L1 Typical Maximum Units + C S1 + CV _ High ) (C L 2 + C S 2 + CV _ High ) L1 + C S 1 + CV _ High ) + (C L 2 + C S 2 + CV _ High ) * CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. CLow determines the high frequency component on the TPR. * CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. CHigh determines the low frequency component on the TPR. 1 1 10 6 - Total Pull Range (TPR ) = C Low C C 0 High 2 C 0 C 1 1 + 2 C 1 1 + C 0 0 C Absolute Pull Range (APR) = Total Pull Range - (Frequency Tolerance + Frequency Stability + Aging) EXAMPLE CALCULATIONS aging is 15ppm. Third, though many boards will not require load tuning capacitors (CL1, CL2), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. Typical values for the load tuning capacitors will range from 0 to 4pF. Using the tables and figures above, we can now calculate the TPR and APR of the VCXO using the example crystal parameters. For the numerical example below there were some assumptions made. First, the stray capacitance (CS1, CS2), which is all the excess capacitance due to board parasitic, is 4pF. Second, the expected lifetime of the project is 5 years; hence the inaccuracy due to (0 + 4p + 15p ) * (0 + 4p + 15p ) CLow = (0 + 4p + 27.4p ) * (0 + 4p + 27.4p ) = 9.5p CHigh = (0 + 4p + 15p ) * (0 + 4p + 15p ) 1 TPR = 2* 220 * (1 + 9.5p 4p ) - (0 + 4p + 27.4p ) * (0 + 4p + 27.4p ) = 15.7p 6 *110 = 212ppm 15.7p 2* 220 * 1 + 4p 1 ( ) TPR = 106ppm APR = 106ppm - (20ppm + 20ppm + 15ppm) = 51ppm (C0/C1 ratio) can be used. Also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability. The example above will ensure a total pull range of 106 ppm with an APR of 51ppm. Many times, board designers may select their own crystal based on their application. If the application requires a tighter APR, a crystal with better pullability IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 12 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS813321-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS813321-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450mW Total Power_MAX (3.465V, with output switching) = 450mW + 30mW = 480mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.480W * 92.4C/W = 114.4C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE JA FOR 16-PIN TSSOP, FORCED CONVECTION JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 0 1 2.5 92.4C/W 88.0C/W 75.91C/W 13 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CCO * For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (V L CCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) = L [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (V _MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) = L CCO L [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 14 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL RELIABILITY INFORMATION TABLE 9. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4C/W 88.0C/W 75.91C/W TRANSISTOR COUNT The transistor count for ICS813321-04 is: 3948 IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 15 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 10. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 16 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS813321AG-04 13321A04 16 lead TSSOP tube 0C to 70C ICS813321AG-04T 13321A04 16 lead TSSOP 2500 tape & reel 0C to 70C ICS813321AG-04LF 3321A04L 16 lead "Lead-Free" TSSOP tube 0C to 70C ICS813321AG-04LFT 3321A04L 16 lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM VCXO LVPECL FEMTOCLOCKTM PLL 17 ICS813321AG-04 REV. A NOVEMBER 28, 2007 ICS813321-04 VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCKTM PLL Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA