VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
ICS813321-04
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 1 ICS813321AG-04 REV. A NOVEMBER 28, 2007
GENERAL DESCRIPTION
The ICS813321-04 is a two stage device – a VCXO
followed by a FemtoClock™ PLL. The FemtoClock
PLL can multiply the crystal frequency of the VCXO
up to a range of 122MHz to 160MHz, with a random
rms phase jitter of less than 1ps (1.875MHz –
20MHz). This phase jitter performance meets the requirements
of 1Gb/10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Chan-
nel, and SONET up to OC48.
FEATURES
• One 3.3V or 2.5V LVPECL output pair
• Crystal operating frequency range: 14MHz - 20MHz
• VCO range: 490MHz - 640MHz
• Output frequency range: 122MHz - 160MHz
• VCXO pull range: ±50ppm (typical APR) @ 3.3V
• Supports the following applications (among others):
SONET, Ethernet, Fibre Channel
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.53ps (typical) @ 3.3V
• Supply voltage modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
BLOCK DIAGRAM
VCXO Phase
Detector
VCO
490MHz - 640MHz
M = ÷25 (default),
÷32
N = ÷4
0
1
Q
nQ
VC
OE
XTAL_IN
XTAL_OUT
19.44MHz
Pullup
SEL
Pullup
VCO_SEL Pullup
PIN ASSIGNMENT
nc
VCCO
Q
nQ
VEE
nc
VCCA
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCO_SEL
nc
OE
SEL
VC
nc
XTAL_IN
XTAL_OUT
ICS813321-04
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 2 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
ρεβμυΝεμαΝεπψΤνοιτπιρχσεΔ
51,11,6,1cndesunU.tcennocoN
2V
OCC
rewoP.nipylppustuptuO
4,3Qn,QtuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD
5V
EE
rewoP.nipylppusevitageN
7V
ACC
rewoP.nipylppusgolanA
8V
CC
rewoP.nipylppuseroC
01,9NI_LATX,TUO_LATXtupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC
.tuptuoehtsiTUO
_LATX
21V
C
tupnI.tupniegatlovlortnocOXCV
31LEStupnInwodlluP.3elbaTeeS.slevelecafretniLTTVL/SOMCVL.niptceleS
41EOtupnIpullu
P
.evitcasituptuoeht,HGIHnehW.nipelbanetuptuO
.etatsecnadepmihgihanisituptuoeht,WOLnehW
.ecafretniLTTVL/
SOMCVL
61LES_OCVtupnIpulluP.slevelecafretniLTTVL/SOMCVL.niptcelesOCV
:ETON nwodlluPdnapulluP .seulavlacipytro
f,elbaTscitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
TABLE 3. SEL FUNCTION TABLE
tupnIlortnoC M
LES
0)tulafed(52÷
123÷
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 3 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA 92.4°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 573.25.2526.2V
V
ACC
egatloVylppuSgolanAV
CC
01.0–5.2V
CC
V
V
OCC
egatloVylppuStuptuO 573.25.2526.2V
I
ACC
tnerruCylppuSgolanA 01Am
I
EE
tnerruCylppuSrewoP 521Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanAV
CC
01.0–3.3V
CC
V
V
OCC
egatloVylppuStuptuO 531.33.3564.3V
I
ACC
tnerruCylppuSgolanA 01Am
I
EE
tnerruCylppuSrewoP 031Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanAV
CC
01.0–3.3V
CC
V
V
OCC
egatloVylppuStuptuO 573.25.2526.2V
I
ACC
tnerruCylppuSgolanA 01Am
I
EE
tnerruCylppuSrewoP 031Am
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 4 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
OCC
4.1-V
OCC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
OCC
0.2-V
OCC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI V
CC
V3.3=2V
CC
3.0+V
V
CC
V5.2=7.1V
CC
3.0+V
V
LI
egatloVwoLtupnI V
CC
V3.3=3.0-8.0V
V
CC
V5.2=3.0-7.0V
I
HI
tnerruChgiHtupnI
,EO
LES_OCV V
CC
V=
NI
V526.2roV564.3=5Aµ
LESV
CC
V=
NI
V526.2roV564.3=051Aµ
I
LI
tnerruCwoLtupnI
,EO
LES_OCV V
CC
V,V526.2roV564.3=
NI
V0=051-Aµ
LESV
CC
V,V526.2roV564.3=
NI
V0=5-Aµ
TABLE 4F. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
OCC
4.1-V
OCC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
OCC
0.2-V
OCC
5.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 4.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 5 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
TABLE 5C. AC CHARACTERISTICS, VCC = VCCO = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO1=LES_OCV221061zHM
t)Ø(tij ;)modnaR(,rettiJesahPSMR
2,1ETON )zHM02-zHM578.1(zHM25.55135.0sp
f
OCV
egnaRkcoLOCVLLP 094046zHM
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02052006sp
cdoelcyCytuDtuptuO 8425%
.ecafretnilatsyrcagnisurettijesahP:1ETON
.56dradnat
SCEDEJhtiwecnadroccanidenifedsiretemarapsihT:2ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO1=LES_OCV221061zHM
t)Ø(tij ;)modnaR(,rettiJesahPSMR
2,1ETON )zHM02-zHM578.1(zHM25.55146.0sp
f
OCV
egnaRkcoLOCVLLP 094046zHM
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02052006sp
cdoelcyCytuDtuptuO 8425%
.ecafretnilatsyrcagnisurettijesahP:1ETON
.56dradnat
SCEDEJhtiwecnadroccanidenifedsiretemarapsihT:2ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO1=LES_OCV221061zHM
t)Ø(tij ;)modnaR(,rettiJesahPSMR
2,1ETON )zHM02-zHM578.1(zHM25.55135.0sp
f
OCV
egnaRkcoLOCVLLP 094046zHM
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02052006sp
cdoelcyCytuDtuptuO 8425%
.ecafretnilatsyrcagnisurettijesahP:1ETON
.56dradnat
SCEDEJhtiwecnadroccanidenifedsiretemarapsihT:2ETON
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 6 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TYPICAL PHASE NOISE AT 155.52MHZ
155.52MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.53ps (typical)
OFFSET FREQUENCY (HZ)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M
➤
➤
➤
dBc
Hz
NOISE POWER
OC-12 Filter
Raw Phase Noise Data
Phase Noise Result by adding
Sonet OC-12 Filter to raw data
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 7 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
VEE
2V
-1.3V±0.165V
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
OUTPUT RISE/FALL TIME
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
RMS PHASE JITTER
-0.5V ± 0.125V
2.5V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
VCC,
VCCO
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Q
nQ
SCOPE
Qx
nQx
LVPECL
V
EE
2.8V±0.04V
-0.5V ± 0.125V
VCCA
VCCO
2.8V±0.04V
2V
VCCA
SCOPE
Qx
nQx
LVPECL
VEE
2V
VCC,
VCCO
2V
VCCA
2V
VCC
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 8 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
APPLICATION INFORMATION
FIGURE 1. POWER SUPPLY FILTERING
V
CC
V
CCA
3.3V or 2.5V
10Ω
10µF.01µF
.01µF
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT PINS
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS813321-04
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VCC pin and
also shows that VCCA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 9 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TERMINATION FOR 3.3V LVPECL OUTPUT
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating fre-
quency and minimize signal distortion. Figures 2A and 2B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 10 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground
level. The R3 in Figure 3B can be eliminated and the termination
is shown in Figure 3C.
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driver
Zo = 50 Ohm
+
-
2.5V
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 11 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of the
most critical steps in using a Voltage Controlled Crystal Oscillator
(VCXO). The crystal parameters affect the tuning range and
FIGURE 4. VCXO OSCILLATOR CIRCUIT
VC- Control voltage used to tune frequency
CV- Varactor capacitance, varies due to the
change in control voltage
CL1, CL2 - Load tuning capacitance used for fine
tuning or centering nominal frequency
CS1, CS2 - Stray Capacitance caused by pads,
vias, and other board parasitics
accuracy of a VCXO. Below are the key variables and an example
of using the crystal parameters to calculate the tuning range of
the VCXO.
Oscillator
VC
CV
CS1
CL1
CS2
CL2
CV
XTAL
VCXO (Internal)
Optional
➤
➤
➤
➤
➤
Control Voltage
TABLE 6. EXAMPLE CRYSTAL PARAMETERS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
N
ycneuqerFlanimoN 4102zHM
f
T
ecnareloTycneuqerF 02±mpp
f
S
ytilibatSycneuqerF 02±mpp
egnaRerutarepmeTgnitarepO 007C°
C
L
ecnaticapaCdaoL 21Fp
C
O
ecnaticapaCtnuhS 4Fp
C
,1
C
2
oitaRytiliballuP 022042
RSEecnatsiseRseireStnelaviuqE 02
leveLevirD 1Wm
C°52@gnigA raeyrep3±mpp
noitarepOfoedoM la
tnemadnuF
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 12 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
WOL_V
ecnaticapaCrotcaraVwoLV
C
V0=6Fp
C
HGIH_V
ecnaticapaCrotcaraVhgiHV
C
V3.3=11Fp
TABLE 7. VARACTOR PARAMETERS
FORMULAS
(
)
(
)
()( )
LowVSLLowVSL
LowVSLLowVSL
Low CCCCCC
CCCCCC
C
_22_11
_22_11
+++++
++⋅++
=
(
)
(
)
()( )
HighVSLHighVSL
HighVSLHighVSL
High CCCCCC
CCCCCC
C
_22_11
_22_11
+++++
++⋅++
=
6
01
0
01
0
10
12
1
12
1
)( ⋅
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
⎟
⎠
⎞
⎜
⎝
⎛+⋅⋅
−
⎟
⎠
⎞
⎜
⎝
⎛+⋅⋅
=
C
C
C
C
C
C
C
C
TPRRangePull
T
otal
HighLow
•C
Low is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the TPR.
•C
High is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the TPR.
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal parameters.
For the numerical example below there were some assumptions
made. First, the stray capacitance (CS1, CS2), which is all the excess
capacitance due to board parasitic, is 4pF. Second, the expected
lifetime of the project is 5 years; hence the inaccuracy due to
aging is ±15ppm. Third, though many boards will not require load
tuning capacitors (CL1, CL2), it is recommended for long-term
consistent performance of the system that two tuning capacitor
pads be placed into every design. Typical values for the load tuning
capacitors will range from 0 to 4pF.
TPR = ±106ppm
APR = 106ppm – (20ppm + 20ppm + 15ppm) = ±51ppm
The example above will ensure a total pull range of
±106 ppm with an APR of ±51ppm. Many times, board designers
may select their own crystal based on their application. If the
application requires a tighter APR, a crystal with better pullability
(C0/C1 ratio) can be used. Also, with the equations above, one
can vary the frequency tolerance, temperature stability, and aging
or shunt capacitance to achieve the required pullability.
1
⋅
⎟
⎟
⎟
⎟
⎠
⎞
⎟
⎠
⎞
1
2· 220 · (1 + 9.5pƒ 4pƒ ) 2· 220 · (1 +15.7pƒ 4pƒ )
1
–
TPR = · 106 = 212ppm
CLow =(0 + 4pƒ + 15pƒ ) · (0 + 4 pƒ + 15pƒ )
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ ) = 9.5pƒCHigh =(0 + 4pƒ + 27.4 pƒ ) · (0 + 4 pƒ + 27.4pƒ )
(0 + 4pƒ + 27.4pƒ ) · (0 + 4 pƒ + 27.4 pƒ ) = 15.7pƒ
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 13 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813321-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813321-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450mW
Total Power_MAX (3.465V, with output switching) = 450mW + 30mW = 480mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 92.4°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.480W * 92.4°C/W = 114.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θθ
θθ
θJA FOR 16-PIN TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.4°C/W 88.0°C/W 75.91°C/W
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 14 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
– 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCCO_MAX
– 1.7V
(VCCO_MAX – VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCCO_MAX
– 2V))/R
L
] * (VCCO_MAX
– VOH_MAX) = [(2V – (V
CCO_MAX – VOH_MAX
))/R
L
] * (VCCO_MAX
– VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCCO_MAX
– 2V))/R
L
] * (VCCO_MAX
– VOL_MAX) = [(2V – (V
CCO_MAX – VOL_MAX
))/R
L
] * (VCCO_MAX
– VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
VOUT
VCCO
VCCO - 2V
Q1
RL
50Ω
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 15 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS813321-04 is: 3948
TABLE 9. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.4°C/W 88.0°C/W 75.91°C/W
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 16 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N61
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.401.5
ECISAB04.6
1E03.405.4
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
IDT™ / ICS™ VCXO LVPECL FEMTOCLOCK™ PLL 17 ICS813321AG-04 REV. A NOVEMBER 28, 2007
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
TABLE 11. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
40-GA123318SCI40A12331POSSTdael61ebutC°07otC°0
T40-G
A123318SCI40A12331POSSTdael61leer&epat0052C°07otC°0
FL40-GA123318SCIL40A1233POSST"eerF-daeL"dael61ebutC°07otC°
0
TFL40-GA123318SCIL40A1233POSST"eerF-daeL"dael61leer&epat0052C°07otC°0
.tnailpmocSHoReradnanoitarugifnocee
rF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
ICS813321-04
VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
