W83194BR-39B STEP-LESS 3-DIMM CLOCK W83194BR-39B Step-less Frequency VIA PC/PM 133 Clock Gen. with S.S.T. Date: May 24, 2005 -I- Revision: A1 Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B Table of Contents1. 2. 3. 4. 5. 6. 7. 8. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 Crystal I/O.................................................................................................................................3 5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs............................................................................3 5.3 I2C Control Interface ................................................................................................................4 5.4 Fixed Frequency Outputs.........................................................................................................4 5.5 Power Pins................................................................................................................................4 MODE PIN -POWER MANAGEMENT INPUT CONTROL ......................................................... 5 FREQUENCY BY HARDWARE.................................................................................................. 5 FUNCTION DESCRIPTION ........................................................................................................ 5 8.1 2-WIRE I2C CONTROL INTERFACE.....................................................................................5 8.2 SERIAL CONTROL REGISTERS...........................................................................................6 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 9. SPECIFICATIONS .................................................................................................................... 13 9.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................13 9.2 AC CHARACTERISTICS.......................................................................................................13 9.3 DC CHARACTERISTICS ......................................................................................................14 9.4 BUFFER CHARACTERISTICS.............................................................................................14 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 10. 11. 12. 13. 14. Register 0: CPU Frequency Select Register (default = 0)..............................................8 Register 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped) ........................9 Register 2: PCI Clock Register (1 = enable, 0 = Stopped) .............................................9 Register 3: SDRAM Clock Register (1 = enable, 0 = Stopped) ......................................9 Register 4: Reserved Register (1 = enable, 0 = Stopped) ...........................................10 Register 5: Reserved Register .....................................................................................10 Register 6: Watchdog Timer Register ..........................................................................10 Register 7: M/N Program Register ...............................................................................11 Register 8: M/N Program Register ...............................................................................11 Register 9: Spread Spectrum Programming Register ..................................................11 Register 10: Divisor and Step-less Enable Register ....................................................12 Register 11: Winbond Chip ID Register (Read Only) ................................................12 Register 12: Winbond Chip ID Register (Read Only) ................................................12 TYPE 1 BUFFER FOR CPU CLOCK...........................................................................14 TYPE 2 BUFFER FOR IOAPIC....................................................................................15 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ ...........................................................15 TYPE 4 BUFFER FOR SDRAM (0:12) ........................................................................15 TYPE 5 BUFFER FOR PCICLK (0:4,F) .......................................................................16 OPERATION OF DUAL FUNCTION PINS ............................................................................... 16 ORDERING INFORMATION..................................................................................................... 18 HOW TO READ THE TOP MARKING...................................................................................... 18 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 18 REVISION HISTORY ................................................................................................................ 19 - II - W83194BR-39B 1. GENERAL DESCRIPTION The W83194BR-39B is a Clock Synthesizer, which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-39B provides 64 CPU/PCI frequencies, which are selectable with smooth transitions by hardware or software. W83194BR-39B also provides 13 SDRAM clocks controlled by the none-delay buffer in pin. The W83194BR-39B provides step-less frequency programming by controlling the VCO freq. and the programmable PCI clock output divisor ratio. A watchdog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots (ISA, PCI, CPU, DIMM) is not recommend. 2. PRODUCT FEATURES * * * * * * * * * * * * * * * * * * * * Supports Pentium II and III CPU with I2C. 2 CPU clocks (one free-running CPU clock) 13 SDRAM clocks for 3 DIMMs 6 PCI synchronous clocks One IOAPIC clock for multiprocessor support Optional single or mixed supply: (Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 = 3.3V, VddL1 = VddL2 = 2.5V) < 250ps skew among CPU and SDRAM clocks < 250ps skew among PCI clocks < 5ns propagation delay SDRAM from buffer input Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns. Smooth frequency switch with selections from 66 MHz to 200 MHz CPU Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio I2C 2-Wire serial interface and I2C read back 0.25% or 0.5% spread spectrum function to reduce EMI in freq. table mode Programmable spread spectrum in the M/N step-less mode Programmable registers to enable/stop each output and select modes MODE pin for power Management RESET# out when watch dog timer time out One 48 MHz for USB & one 24 MHz for super I/O 48-pin SSOP package -1- Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B 3. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Vddq1 * PD#/REF0^ Vss Xin Xout Vddq2 PCICLK_F/MODE0* PCICLK0^/FS3& Vss PCICLK1^ PCICLK2^ PCICLK3^ PCICLK4 Vddq2 BUFFER IN Vss SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 Vss SDATA* SDCLK* 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VddL1 IOAPIC REF1/FS2* Vss CPUCLK_F CPUCLK1 VddL2 RESET$ SDRAM12 Vss SDRAM 0 SDRAM 1 Vddq3 SDRAM 2 SDRAM 3 Vss SDRAM 4 SDRAM 5 Vddq3 SDRAM 6 SDRAM 7 Vddq4 48MHz/FS0* 24MHz/FS1* * :internal 120K pull-high &:Internal 120K pull-down ^ :1.5X strength #: active low $ :open drain 4. BLOCK DIAGRAM 48MHz PLL2 Xin STOP XTAL OSC Xout 24MHz 1/2 a BUFFER IN IOAPIC 2 CPUCLK_F PLL1 STOP Spread Spectrum FS(0:3)* MODE* STOP LATCH a CPUCLK1 SDRAM12 4 POR 4 PCI Clock Divider CPU_STOP# STOP 12 5 SDRAM(0:11) PCICLK(0:4) PCICLK_F PCI_STOP# Control Logic SDATA* Config. Reg. SDCLK* REF(0:1) -2- W83194BR-39B 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN DESCRIPTION Input OUT Output I/O Bi-directional Pin # Active Low & Internal 120K pull-down * Internal 120k pull-up 5.1 Crystal I/O PIN PIN NAME TYPE 4 Xin IN 5 Xout OUT DESCRIPTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs PIN PIN NAME TYPE DESCRIPTION 44 CPUCLK_F OUT 43 CPUCLK1 OUT 41 RESET# OD 47 IOAPIC OUT Free running CPU clock. Not affected by PD# Low skew (< 250ps) clock outputs for host frequencies such as CPU, Chipset and Cache. Powered by VddL2. Low if PD# is low. RESET# (open drain, 4ms low active pulse when Watch Dog time out) High drive buffered output of the crystal, and is powered by VddL1. 17,18,20,21,2 8,29,31,32,34 , 35,37,38,40 SDRAM [0:12] OUT PCICLK_F OUT *MODE0 IN PCICLK0^ OUT FS3& IN 10,11,12,13 PCICLK [1:3]^ PCICLK 4 OUT 15 BUFFER IN IN 7 8 SDRAM clock outputs. Fan out buffer outputs from BUFFER IN pin. (Controlled by chipset) Free running PCI clock during normal operation. Latched Input. *Mode0=1, Pin 2 is REF0; *Mode0=0, Pin2 is PD# Low skew (< 250ps) PCI clock outputs. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU and PCI clocks. Low skew (< 250ps) PCI clock outputs. PCICLK 0:3 are double strength pins PCICLK 4 is not. Inputs to fan out for SDRAM outputs. -3- Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B 5.3 I2C Control Interface PIN PIN NAME TYPE DESCRIPTION 2 23 SDATA* I/O Serial data of I C 2-wire control interface 24 SDCLK* IN Serial clock of I2C 2-wire control interface 5.4 Fixed Frequency Outputs PIN PIN NAME TYPE REF0^ OUT 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads.(pin7 *Mode0=1) PD# IN Halt all clocks at logic 0 level, when input low (pin7 *Mode0=0) REF1 OUT FS2* IN 24MHz OUT FS1* I/O 48MHz OUT FS0* IN 2 46 25 26 DESCRIPTION 14.318MHz reference clock. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 24MHz output clock. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz output for USB during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 5.5 Power Pins PIN PIN NAME DESCRIPTION 1 Vddq1 Power supply for Ref [0:1] crystal and core logic. 48 VddL1 Power supply for IOAPIC output, either 2.5V or 3.3V. 42 VddL2 Power supply for CPUCLK [0:3], either 2.5V or 3.3V. 6, 14 Vddq2 Power supply for PCICLK_F, PCICLK [0:4], 3.3V. 19, 30, 36 Vddq3 Power supply for SDRAM [0:12], and CPU PLL core, nominal 3.3V. 27 Vddq4 Power for 24 & 48MHz output buffers and fixed PLL core. 3,9,16,22,33, 39,45 Vss Circuit Ground. -4- W83194BR-39B 6. MODE PIN -POWER MANAGEMENT INPUT CONTROL MODE0, PIN7 (LATCHED INPUT) PIN 2 0 PD# (Input) 1 REF0 (Output) 7. FREQUENCY BY HARDWARE FS3 FS2 FS1 FS0 CPU (MHZ) PCI (MHZ) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 80.00 75.00 83.30 66.82 103.00 112.00 68.01 100.23 120.00 115.00 120.00 105.00 140.00 155.00 124.00 133.30 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 30.00 38.33 40.00 35.00 35.00 38.75 31.00 33.30 8. FUNCTION DESCRIPTION 8.1 2-WIRE I2C CONTROL INTERFACE The clock generator is a slave I2C component, which can be read back the data, stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83194BR-39Binitializes with default register settings. Use of the 2-wire control interface is then optional. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. -5- Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B Byte writing starts with a "start" condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an "acknowledge" (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller: Clock Address A(6:0) & R/W Ack 8 bits dummy Command code 8 bits dummy Byte count Ack Ack Byte0,1,2... until Stop Ack Byte2, 3, 4... until Stop Set R/W to 1 when read back", the data sequence is as follows: Clock Address A(6:0) & R/W Ack Byte 0 Byte 1 Ack 8.2 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the default state at true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the sequence described below (Register 0, Register 1, Register 2...) will be valid and acknowledged. FREQUENCY BY SOFTWARE SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU (MHZ) PCI (MHZ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 80.00 75.00 83.30 66.82 103.00 112.00 68.01 100.23 120.00 115.00 120.00 105.00 140.00 155.00 124.00 133.30 160.00 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 30.00 38.33 40.00 35.00 35.00 38.75 31.00 33.30 40.00 127.00 31.75 -6- W83194BR-39B FREQUENCY BY SOFTWARE, continued. SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU (MHZ) PCI (MHZ) 0 0 1 1 0 0 0 0 1 1 0 1 130.00 135.00 32.50 33.75 0 1 0 1 0 0 136.00 34.00 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 137.00 139.00 140.00 141.00 142.00 143.00 144.00 145.00 146.00 148.00 149.00 34.25 34.75 35.00 35.25 35.50 35.75 36.00 36.25 36.50 37.00 37.25 1 0 0 0 0 0 151.00 37.75 1 0 0 0 0 1 152.00 38.00 1 0 0 0 1 0 153.00 38.25 1 0 0 0 1 1 154.00 38.50 1 0 0 1 0 0 155.00 38.75 1 0 0 1 0 1 156.00 39.00 1 0 0 1 1 0 157.00 39.25 1 0 0 1 1 1 158.00 39.50 1 0 1 0 0 0 159.00 39.75 1 0 1 0 0 1 162.00 40.50 1 0 1 0 1 0 163.00 32.60 1 0 1 0 1 1 164.00 32.80 1 0 1 1 0 0 165.00 33.00 1 0 1 1 0 1 167.00 33.40 1 0 1 1 1 0 168.00 33.60 1 0 1 1 1 1 169.00 33.80 1 1 0 0 0 0 170.00 34.00 1 1 0 0 0 1 172.00 34.40 1 1 0 0 1 0 174.00 34.80 1 1 0 0 1 1 176.00 35.20 -7- Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B FREQUENCY BY SOFTWARE, continued. SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU (MHZ) PCI (MHZ) 1 1 0 1 0 0 178.00 35.60 1 1 0 1 0 1 180.00 36.00 1 1 0 1 1 0 182.00 36.40 1 1 0 1 1 1 184.00 36.80 1 1 1 0 0 0 186.00 37.20 1 1 1 0 0 1 188.00 37.60 1 1 1 0 1 0 190.00 38.00 1 1 1 0 1 1 192.00 38.40 1 1 1 1 0 0 194.00 38.80 1 1 1 1 0 1 196.00 39.20 1 1 1 1 1 0 198.00 39.60 1 1 1 1 1 1 200.00 40.00 8.2.1 Register 0: CPU Frequency Select Register (default = 0) BIT @POWERUP PIN DESCRIPTION 7 0 - SSEL5 (for frequency table selection by software via I2C) 6 0 - SSEL4 (for frequency table selection by software via I2C) 5 0 - SSEL3 (for frequency table selection by software via I2C) 4 0 - SSEL2 (for frequency table selection by software via I2C) 3 0 - SSEL1 (for frequency table selection by software via I2C) 2 0 - SSEL0 (for frequency table selection by software via I2C) 1 0 - 0 = Selection by hardware 1 = Selection by software I2C - Bit 7:2 0 0 - 0 = Running 1 = Tristate all outputs -8- W83194BR-39B 8.2.2 Register 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped) BIT @POWERUP PIN DESCRIPTION 7 1 - Reserved 6 1 - Reserved 5 0 - 0 = Normal 1 = Spread Spectrum enabled 4 0 - 0 = 0.25% Spread Spectrum Modulation 1 = 0.5% Spread Spectrum Modulation 3 1 40 2 1 - 1 1 43 CPUCLK1 (Active / Inactive) 0 1 44 CPUCLK_F (Active / Inactive) 8.2.3 SDRAM12 (Active / Inactive) Reserved Register 2: PCI Clock Register (1 = enable, 0 = Stopped) BIT @POWERUP PIN 7 1 - Reserved 6 1 7 PCICLK_F (Active / Inactive) 5 1 - Reserved 4 1 14 PCICLK4 (Active / Inactive) 3 1 12 PCICLK3 (Active / Inactive) 2 1 11 PCICLK2 (Active / Inactive) 1 1 10 PCICLk1 (Active / Inactive) 0 1 8 PCICLK0 (Active / Inactive) 8.2.4 DESCRIPTION Register 3: SDRAM Clock Register (1 = enable, 0 = Stopped) BIT @POWERUP PIN DESCRIPTION 7 1 46 REF1 (Active / Inactive) 6 1 2 REF0 (Active / Inactive) 5 1 26 48MHz (Active / Inactive) 4 1 25 24MHz (Active / Inactive) 3 1 47 IOAPIC (Active / Inactive) 2 1 21,20,18,17 SDRAM (8:11) (Active / Inactive) 1 1 32,31,29,28 SDRAM (4:7) (Active / Inactive) 0 1 38,37,35,34 SDRAM (0:3) (Active / Inactive) -9- Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B 8.2.5 Register 4: Reserved Register (1 = enable, 0 = Stopped) BIT @POWERUP PIN 7 1 - Reserved 6 X - Latched FS3# 5 X - Latched FS2# 4 X - Latched FS1# 3 X - Latched FS0# 2 1 - Reserved 1 1 - Reserved 0 1 - Reserved 8.2.6 DESCRIPTION Register 5: Reserved Register BIT @POWERUP PIN 7 1 - Reserved 6 0 - Reserved 5 0 - Reserved 4 1 - Reserved 3 0 - Reserved 2 0 - Reserved 1 1 - Reserved 0 1 - Reserved 8.2.7 DESCRIPTION Register 6: Watchdog Timer Register BIT @POWERUP PIN DESCRIPTION 7 0 - 6 0 - Second timeout status (READ ONLY) 5 0 - Second count 5 4 0 - Second count 4 3 0 - Second count 3 2 0 - Second count 2 1 0 - Second count 1 0 0 - Second count 0 Enable Count 1 = start timer 0 = stop timer - 10 - W83194BR-39B 8.2.8 Register 7: M/N Program Register BIT @POWERUP PIN 7 0 - N value bit 8 6 0 - Test 1(Please do not modify) 5 1 - Test 0 (Please do not modify) 4 0 - M value bit 4 3 0 - M value bit 3 2 0 - M value bit 2 1 0 - M value bit 1 0 0 - M value bit 0 8.2.9 DESCRIPTION Register 8: M/N Program Register BIT @POWERUP PIN DESCRIPTION 7 0 - N value bit 7 6 0 - N value bit 6 5 0 - N value bit 5 4 0 - N value bit 4 3 0 - N value bit 3 2 0 - N value bit 2 1 0 - N value bit 1 0 0 - N value bit 0 8.2.10 Register 9: Spread Spectrum Programming Register BIT @POWERUP PIN DESCRIPTION 7 0 - Spread spectrum up count 3 6 0 - Spread spectrum up count 2 5 0 - Spread spectrum up count 1 4 0 - Spread spectrum up count 0 3 0 - Spread spectrum down count 3 2 0 - Spread spectrum down count 2 1 0 - Spread spectrum down count 1 0 0 - Spread spectrum down count 0 - 11 - Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B 8.2.11 Register 10: Divisor and Step-less Enable Register BIT @POWERUP PIN 7 0 - 6 0 - 5 X - 4 X - 3 X - 2 1 0 0 0 0 - DESCRIPTION 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/2M Reserved PCI Ratio SEL2 0,0,0 = 2 0,0,1 = 3 PCI Ratio SEL1 0,1,0 = 4 0,1,1 = 5 PCI Ratio SEL0 1,0,0 = 6 1,0,1...= X Reserved Reserved Reserved 8.2.12 Register 11: Winbond Chip ID Register BIT @POWERUP PIN 7 6 5 4 3 2 1 0 0 1 1 0 0 0 1 0 - (Read Only) DESCRIPTION Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID 8.2.13 Register 12: Winbond Chip ID Register (Read Only) BIT @POWERUP PIN DESCRIPTION 7 0 - Winbond Chip ID 6 1 - Winbond Chip ID 5 0 - Winbond Chip ID 4 1 - Winbond Chip ID 3 0 - Winbond Version ID 2 0 - Winbond Version ID 1 0 - Winbond Version ID 0 1 - Winbond Version ID - 12 - W83194BR-39B 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). SYMBOL PARAMETER RATING Vdd VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V TSTG Storage Temperature - 65C to + 150C TB Ambient Temperature - 55C to + 125C TA Operating Temperature 0C to + 70C 9.2 AC CHARACTERISTICS Vdd = Vddq3 = 3.3V 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V, TA = 0C to +70C PARAMETER SYMBOL Output Duty Cycle MIN TYP MAX UNITS TEST CONDITIONS 45 50 55 % Measured at 1.5V 1 2.6 4 ns 15 pF Load Measured at 1.5V 15 pF Load Measured at 1.5V CPU/SDRAM to PCI Offset tOFF Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) tSKEW 250 ps tCCJ 250 ps tJA 500 ps BWJ 500 KHz 0.4 1.6 ns 15 pF Load on CPU and PCI outputs Vover 0.7 1.5 V 22 at source of 8 inch PCB run to 15 pF load VRBE 0.7 2.1 V Ring Back must not enter this range. CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V ~ 2.0V) tTLH & Fall (2.0V ~0.4V) Time tTHL Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion - 13 - Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B 9.3 DC CHARACTERISTICS Vdd = Vddq3 = 3.3V 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V, TA = 0C to +70C PARAMETER SYMBOL MIN TYP MAX UNITS 0.8 Vdc TEST CONDITIONS Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL -66 A Input High Current IIH 5 A VOL 0.4 Vdc All outputs Vdc All outputs using 3.3V power Output Low Voltage IOL = 4 mA Output High Voltage IOH = 4mA VOH 2.0 Vdc 2.4 Ioz Dynamic Supply Current for Vdd + Vddq3 Idd3 mA Idd2 mA ICPUS3 mA ICPUS2 mA IPD3 mA Dynamic Supply Current for Vddq2 + Vddq2b CPU Stop Current for Vdd + Vddq3 CPU Stop Current for Vddq2 + Vddq2b PCI Stop Current for Vdd + Vddq3 10 A Tri-State leakage Current CPU = 66.6 MHz PCI = 33.3 Mhz with load Same as above Same as above Same as above 9.4 BUFFER CHARACTERISTICS 9.4.1 TYPE 1 BUFFER FOR CPU CLOCK PARAMETER SYMBOL MIN Pull-Up Current Min IOH (min) -27 Pull-Up Current Max IOH (max) Pull-Down Current Min IOL (min) Pull-Down Current Max Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V IOL (max) TRF (min) TYP MAX -27 27 0.4 1.6 TRF (max) - 14 - UNITS TEST CONDITIONS mA Vout = 1.0 V mA Vout = 2.0V mA Vout = 1.2 V mA Vout = 0.3 V ns 10pF Load ns 20pF Load W83194BR-39B 9.4.2 TYPE 2 BUFFER FOR IOAPIC PARAMETER SYMBOL Pull-Up Current Min IOH (min) Pull-Up Current Max IOH (max) Pull-Down Current Min IOL (min) Pull-Down Current Max IOL (max) Rise/Fall Time Min Between 0.7 V and 1.7 V TRF (min) Rise/Fall Time Max Between 0.7 V and 1.7 V TRF (max) 9.4.3 MIN MAX -29 28 0.4 1.8 UNITS TEST CONDITIONS mA Vout = 1.4 V mA Vout = 2.7 V mA Vout = 1.0 V mA Vout = 0.2 V ns 10pF Load ns 20pF Load TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ PARAMETER SYMBOL MIN Pull-Up Current Min IOH (min) -29 Pull-Up Current Max IOH (max) Pull-Down Current Min IOL (min) Pull-Down Current Max IOL (max) Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V 9.4.4 TYP TRF (min) TYP MAX TEST CONDITIONS mA Vout = 1.0 V mA Vout = 3.135V mA Vout = 1.95 V mA Vout = 0.4 V ns 10pF Load 4.0 ns 20pF Load MAX UNITS -23 29 1.0 TRF (max) UNITS TYPE 4 BUFFER FOR SDRAM (0:12) PARAMETER SYMBOL Pull-Up Current Min IOH (min) Pull-Up Current Max IOH (max) Pull-Down Current Min IOL (min) Pull-Down Current Max IOL (max) Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V TRF (min) MIN TYP -46 53 0.5 1.3 TRF (max) - 15 - TEST CONDITIONS mA Vout = 1.65 V mA Vout = 3.135 V mA Vout = 1.65 V mA Vout = 0.4 V ns 20pF Load ns 30pF Load Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B 9.4.5 TYPE 5 BUFFER FOR PCICLK (0:4,F) PARAMETER SYMBOL MIN Pull-Up Current Min IOH(min) -33 Pull-Up Current Max IOH(max) Pull-Down Current Min IOL(min) Pull-Down Current Max IOL(max) Rise/Fall Time Min Between 0.8 V and 2.0 V Rise/Fall Time Max Between 0.8 V and 2.0 V TYP MAX -33 30 38 TRF(min) 0.5 2.0 TRF(max) UNITS TEST CONDITIONS mA Vout = 1.0 V mA Vout = 3.135 V mA Vout = 1.95 V mA Vout = 0.4 V ns 15pF Load ns 30pF Load 10. OPERATION OF DUAL FUNCTION PINS Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins is latched into their appropriate internal registers. Once the correct information is properly latched, these pins will change into output pins and will be pulled low by default. At the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency. 2.5V #7 PCICLK_F/MODE #46 REF1/FS2 #25 24/FS1 #26 48/FS0 Output tri-state Vdd Output pull-low Within 3ms Input All other clocks Output tri-state Output Output pull-low Each of these pins has a large pull-up resistor (250 k @3.3V) inside. The default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 k resistor is recommended to be connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if a logic 0 is desired. The 10 k resistor should be placed before the serious terminating resistor. Note that this logic will only be latched at initial power on. If optional EMI reducing capacitors are needed, they should be placed as close to the series terminating resistor as possible and after the series-terminating resistor. These capacitors have typical values ranging from 4.7pF to 22pF. - 16 - W83194BR-39B OPERATION of dual function pins, continued. Vdd 10k Series Terminating Resistor Device Pin Clock Trace EMI Reducing Cap 10k Optional Ground Ground Programming Header Vdd Pad Ground Pad 10k Series Terminating Resistor Device Pin Clock Trace EMI Reducing Cap Optional Ground - 17 - Publication Release Date: May 24, 2005 Revision A1 W83194BR-39B 11. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83194BR-39B 48 PIN SSOP Commercial, 0C to +70C 12. HOW TO READ THE TOP MARKING W83194BR-39B 28051234 814GBA 1st line: Winbond logo and the type number: W83194BR-39B 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR B: Winbond internal use code A: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. 13. PACKAGE DRAWING AND DIMENSIONS - 18 - W83194BR-39B 14. REVISION HISTORY VERSION DATE PAGE DESCRIPTION n.a. All of the versions before 0.50 are for internal use. 1.0 02/Apr n.a. Change version and version on web site to 1.0 2.0 2/18/03 All Update new form A1 May 24, 2005 19 ADD Important Notice Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 19 - Publication Release Date: May 24, 2005 Revision A1