November 2006 Cover Page HYS72T64400HFN-[3S/3.7]-B HYS72T128420HFN-[3S/3.7]-B HYS72T256420HFN-[3S/3.7]-B 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.1 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Revision History Revision History: 2006-11-14, Rev. 1.1 All Adapted internet edition Page 25 Updated "SPD Codes" on Page 25 Previous Revision: 2006-11-14, Rev. 1.0 All Conversion to QAG template We Listen to Your Comments We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 09142006-87TL-4SLW 2 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 1 Overview This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family. 1.1 Features * 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications. * Module organisation one rank 64M x 72, one rank 128M x 72, two ranks 128M x 72, two ranks 256M x 72 * JEDEC Standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V ( 0.1 V) power supply. * Built with 512Mb DDR2 SDRAMs in 60-ball FBGA Chipsize Packages. * Re-drive and re-sync of all address, command, clock and data signals using AMB (Advanced Memory Buffer). * High-Speed Differential Point-to-Point Link Interface at 1.5 V (Jedec standard pending). * Host Interface and AMB component industry standard compliant. * Supports SMBus protocol interface for access to the AMB configuration registers. * Detects errors on the channel and reports them to the host memory controller. * Automatic DDR2 DRAM Bus Calibration. * Automatic Channel Calibration. * Full Host Control of the DDR2 DRAMs. * Over-Temperature Detection and Alert. * Hot Add-on and Hot Remove Capability. * MBIST and IBIST Test Functions. * Transparent Mode for DRAM Test Support. * Low profile: 133.35mm x 30.35 mm * 240 Pin gold plated card connector with 1.00mm contact centers (JEDEC standard pending). * Based on JEDEC standard reference card designs (Jedec standard pending). * SPD (Serial Presence Detect) with 256 Byte serial E2PROM.Performance: * RoHS Compliant Products1) TABLE 1 Performance for DDR2-667 and DDR2-533 Product Type Speed Code -3S -3.7 Unit Speed Grade PC2-5300 5-5-5 PC2-4200 4-4-4 -- 333 266 MHz 266 266 MHz max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 200 200 MHz 15 15 ns 15 15 ns 45 45 ns 60 60 ns 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.1, 2006-11 09142006-87TL-4SLW 3 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 1.2 Description This document describes the electrical and mechanical features of Qimonda's 240-pin, PC2-4200F, PC2-5300F ECC type, Fully Buffered Double-Data-Rate Two Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FBDIMMs). Fully Buffered DIMMs use commodity DRAMs isolated from the memory channel behind a buffer on the DIMM. They are intended for use as main memory when installed in systems such as servers and workstations. PC24200, PC2-5300 refers to the DIMM naming convention indicating the DDR2 SDRAMs running at 266, 333 MHz clock speed and offering 4200, 5300 MB/s peak bandwidth. FBDIMM features a novel architecture including the Advanced Memory Buffer. This single chip component, located in the center of each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SDRAMs including data in- and output. The AMB communicates with the host controller and / or the adjacent DIMMs on a system board using an Industry Standard High-Speed Differential Point-to-Point Link Interface at 1.5 V. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The Advanced Memory Buffer interface is responsible for handling channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the memory channel. Fully Buffered DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. The maximum memory capacity is 288 DDR2 SDRAM devices per channel or 8 DIMMs. TABLE 2 Ordering Information (Pb-free components and assembly) Product Type1) Compliance Code2) Description SDRAM Technology 512MB 1Rx8 PC2-4200F-444-11-A 1 Rank, FB-DIMM 512 Mbit (x8) PC2-4200F (DDR2-533): HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B 1GB 2Rx8 PC2-4200F-444-11-B 2 Ranks, FB-DIMM 512 Mbit (x8) HYS72T256420HFN-3.7-B 2GB 2Rx4 PC2-4200F-444-11-H 2 Ranks, FB-DIMM 512 Mbit (x4) HYS72T64400HFN-3S-B 512MB 1Rx8 PC2-4200F-444-11-A 1 Rank, FB-DIMM 512 Mbit (x8) HYS72T128420HFN-3S-B 1GB 2Rx8 PC2-4200F-444-11-B 2 Ranks, FB-DIMM 512 Mbit (x8) HYS72T256420HFN-3S-B 2GB 2Rx4 PC2-4200F-444-11-H 2 Ranks, FB-DIMM 512 Mbit (x4) PC2-5300F (DDR2-667): 1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating Rev. A dice are used for DDR2 SDRAM components. To learn more on Qimonda DDR2 module and component nomenclature see section 8 of this datasheet. 2) The Compliance Code is printed on the module label and describes the speed grade, e.g. "PC2-4200F-444-11-A", where 4200F means Fully Buffered DIMM with 4.26 GB/sec. Module Bandwidth and "444-11" means CAS latency = 4, trcd latency = 4 and trp latency = 4 using JEDEC SPD Revision 1.1 and assembled on Raw Card "A". Rev. 1.1, 2006-11 09142006-87TL-4SLW 4 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B TABLE 3 Address Format DIMM Density Module Organization Memory Ranks ECC/ Non-ECC # of SDRAMs # of row/bank/columns bits 512 MB 64M x72 1 1 GB 128M x72 2 2 GB 256M x72 2 ECC Raw Card ECC 9 13/2/10 A ECC 18 13/2/10 B 36 13/2/11 H TABLE 4 Components on Modules Product Type DRAM components1) DRAM Density DRAM Organisation HYS72T64000HF HYB18T512800BF 512 Mbit 64M x8 HYS72T128020HF HYB18T512800BF 512 Mbit 64M x8 HYS72T256020HF HYB18T512400BF 512 Mbit 128M x4 1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component datasheet. Rev. 1.1, 2006-11 09142006-87TL-4SLW 5 Note2) Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 2 Pin Configuration The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1. TABLE 5 Pin Configuration of FB-DIMM Pin# Name Pin Type Buffer Type Function 228 SCK I HSDL_15 System Clock Input, positive line 229 SCK I HSDL_15 System Clock Input, negative line RESET I LV-CMOS AMB reset signal 22 PN0 O HSDL_15 Primary Northbound Data, positive lines 25 PN1 O HSDL_15 28 PN2 O HSDL_15 31 PN3 O HSDL_15 34 PN4 O HSDL_15 37 PN5 O HSDL_15 51 PN6 O HSDL_15 54 PN7 O HSDL_15 57 PN8 O HSDL_15 60 PN9 O HSDL_15 63 PN10 O HSDL_15 66 PN11 O HSDL_15 48 PN12 O HSDL_15 40 PN13 O HSDL_15 23 PN0 O HSDL_15 26 PN1 O HSDL_15 29 PN2 O HSDL_15 32 PN3 O HSDL_15 35 PN4 O HSDL_15 38 PN5 O HSDL_15 52 PN6 O HSDL_15 55 PN7 O HSDL_15 58 PN8 O HSDL_15 61 PN9 O HSDL_15 64 PN10 O HSDL_15 Clock Signals Control Signals 17 Northbound Rev. 1.1, 2006-11 09142006-87TL-4SLW 6 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Pin# Name Pin Type Buffer Type 67 PN11 O HSDL_15 49 PN12 O HSDL_15 41 PN13 O HSDL_15 142 SN0 I HSDL_15 145 SN1 I HSDL_15 148 SN2 I HSDL_15 151 SN3 I HSDL_15 154 SN4 I HSDL_15 157 SN5 I HSDL_15 171 SN6 I HSDL_15 174 SN7 I HSDL_15 177 SN8 I HSDL_15 180 SN9 I HSDL_15 183 SN10 I HSDL_15 186 SN11 I HSDL_15 168 SN12 I HSDL_15 160 SN13 I HSDL_15 143 SN0 I HSDL_15 146 SN1 I HSDL_15 149 SN2 I HSDL_15 152 SN3 I HSDL_15 155 SN4 I HSDL_15 158 SN5 I HSDL_15 172 SN6 I HSDL_15 175 SN7 I HSDL_15 178 SN8 I HSDL_15 181 SN9 I HSDL_15 184 SN10 I HSDL_15 187 SN11 I HSDL_15 169 SN12 I HSDL_15 161 SN13 I HSDL_15 70 PS0 I HSDL_15 73 PS1 I HSDL_15 76 PS2 I HSDL_15 79 PS3 I HSDL_15 82 PS4 I HSDL_15 93 PS5 I HSDL_15 96 PS6 I HSDL_15 99 PS7 I HSDL_15 Function Secondary Northbound Data, positive lines Southbound Rev. 1.1, 2006-11 09142006-87TL-4SLW 7 Primary Southbound Data, positive lines Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Pin# Name Pin Type Buffer Type 102 PS8 I HSDL_15 90 PS9 I HSDL_15 71 PS0 I HSDL_15 74 PS1 I HSDL_15 77 PS2 I HSDL_15 80 PS3 I HSDL_15 83 PS4 I HSDL_15 94 PS5 I HSDL_15 97 PS6 I HSDL_15 100 PS7 I HSDL_15 103 PS8 I HSDL_15 91 PS9 I HSDL_15 190 SS0 O HSDL_15 193 SS1 O HSDL_15 196 SS2 O HSDL_15 199 SS3 O HSDL_15 202 SS4 O HSDL_15 213 SS5 O HSDL_15 216 SS6 O HSDL_15 219 SS7 O HSDL_15 222 SS8 O HSDL_15 210 SS9 O HSDL_15 191 SS0 O HSDL_15 194 SS1 O HSDL_15 197 SS2 O HSDL_15 200 SS3 O HSDL_15 203 SS4 O HSDL_15 214 SS5 O HSDL_15 217 SS6 O HSDL_15 220 SS7 O HSDL_15 223 SS8 O HSDL_15 211 SS9 O HSDL_15 Function Primary Southbound Data, negative lines Secondary Southbound data, positive lines Secondary Southbound data, negative lines EEPROM 120 SCL I CMOS Serial Bus Clock 119 SDA I/O OD Serial Bus Data 239 SA0 I CMOS Serial Address Select Bus 2:0 240 SA1 I CMOS 118 SA2 I CMOS Rev. 1.1, 2006-11 09142006-87TL-4SLW 8 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Pin# Name Pin Type Buffer Type Function 238 VDDSPD PWR - EEPROM Power Supply 9,10,12,13,129,130,132,133 VCC PWR - AMB Core Power / Channel Interface Power 15,117,135,237 VTT PWR - Address/Command/Clock Termination Power 1,2,3,5,6,7,108,109,111,112,113,115 VDD ,116,121,122,123,125,126, 127,231,232,233,235,236 PWR - Power Supply 4,8,11,14,18,21,24,27,30,33,36, 39,42,43,46,47,50,53,56,59,62, 65,68,69,72,75,78,81,84,85,88, 89,92,95,98,101,104,107,110, 114,124,128,131,134,138,141, 144,147,150,153,156,159,162, 163,166,167,170,173,176,179, 182,185,188,189,192,195,198, 201,204,205,208,209,212,215, 218,221,224,227,230,234 VSS GND - Ground Plane RFU NC - Not connected Voltage ID Power Supplies Other Pins 19,20,44,45,86,87,105,106,139, 140,164,165,206,207,225,226 136 VID0 - - 16 VID1 - - 137 Test AI - Rev. 1.1, 2006-11 09142006-87TL-4SLW 9 VREF Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B TABLE 6 Abbreviations for Buffer Type Abbreviation Description HSDL_15 High-Speed Differential Point-to-Point Link Interface at 1.5 V LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. TABLE 7 Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NU Not Usable NC Not Connected Rev. 1.1, 2006-11 09142006-87TL-4SLW 10 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B FIGURE 1 Pin Configuration for FB-DIMM (240 pin) 9'' 9'' 9'' 9'' 9&& 966 9&& 977 5(6(7 1& 966 31 31 966 31 31 966 31 31 966 31 966 1& 966 31 31 966 31 31 966 31 31 966 31 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 966 36 36 966 36 36 966 36 966 1& 966 36 36 966 36 36 966 36 1& 966 9'' 9'' 9'' 9'' 977 6'$ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ Rev. 1.1, 2006-11 09142006-87TL-4SLW 9'' 966 9'' 966 9&& 9&& 966 9,' 966 1& 31 966 31 31 966 31 31 966 31 31 966 1& 966 31 966 31 31 966 31 31 966 31 31 966 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 36 966 36 36 966 36 36 966 1& 966 36 966 36 36 966 36 36 966 1& 9'' 966 9'' 966 9'' 6$ 6&/ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 0337 11 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 9'' 966 9'' 966 9&& 9&& 966 9,' 966 1& 61 966 61 61 966 61 61 966 61 61 966 1& 966 61 966 61 61 966 61 61 966 61 61 966 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 9'' 9'' 9'' 9'' 9&& 966 9&& 977 7(67 1& 966 61 61 966 61 61 966 61 61 966 61 966 1& 966 61 61 966 61 61 966 61 61 966 61 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 3LQ 66 3LQ 966 3LQ 66 3LQ 66 3LQ 966 3LQ 66 3LQ 66 3LQ 966 3LQ 1& 3LQ 966 3LQ 66 3LQ 966 3LQ 66 3LQ 66 3LQ 966 3LQ 66 3LQ 66 3LQ 966 3LQ 1& 3LQ 6&. 3LQ 966 3LQ 9'' 3LQ 966 3LQ 9'' 3LQ 9''63' 3LQ 6$ 966 66 66 966 66 66 966 66 966 1& 966 66 66 966 66 66 966 66 1& 966 6&. 9'' 9'' 9'' 977 6$ Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 3 Basic Functionality The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification. 3.1 Advanced Memory Buffer Functionality The Advanced Memory Buffer will perform the following FBDIMM channel functions: * Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB DIMM position. * Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. * If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames. * Detects errors on the channel and reports them to the host memory controller. * Support the FB-DIMM configuration register set as defined in the register chapters. * Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM. * Provides a read buffer FIFO and a write buffer FIFO. * Supports an SMBus protocol interface for access to the AMB configuration registers. * Provides logic to support MEMBIST and IBIST Design for Test functions. * Provides a register interface for the thermal sensor and status indicator. * Functions as a repeater to extend the maximum length of FB-DIMM Links. Transparent Mode for DRAM Test Support In this mode, the Advanced Memory Buffer will provide lower speed tester access to DRAM pins through the FB-DIMM I/O pins. This allows the tester to send an arbitrary test pattern to the DRAMs. Transparent mode only supports a maximum DRAM frequency equivalent to DDR2 400. Transparent mode functionality: * Reconfigures FB-DIMM inputs from differential high speed link receivers to two single ended lower speed receivers (~200 MHz) * These inputs directly control DDR2 Command/Address and input data that is replicated to all DRAMs * Uses low speed direct drive FB-DIMM outputs to bypass high speed Parallel/Serial circuitry and provide test results back to tester DDR2 SDRAM Interface * 72-bit DDR2 SDRAM memory array * Supports DDR2 at speeds of 533, 667MT/s * Supports 256Mb, 512Mb and 1Gb devices in x4 and x8 configurations 3.2 Interfaces Figure 2 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FB-DIMM links, one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the Advanced Memory Buffer to a host memory Rev. 1.1, 2006-11 09142006-87TL-4SLW controller or an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM. 12 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B FIGURE 2 Block Diagram Advanced Memory Buffer Interface -EMO RY)NTERFACE ."&"$ IN,IN K ."&" $ OUT,IN K 0RIM AR YOR(O ST $IR ECTION 3"&" $ IN,IN K 3"&" $ OUT,IN K !-" 3ECONDA RYO RTO OPTIO NALNEXT&" $ 3-" -0"4 Interface Topology The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives the data to the next DIMM until the host is reached. FIGURE 3 Block Diagram of Channel Southbound and Northbound Paths (OST 3OU THB OUND .OURTHBO UND !-" !-" !-" !-" NC Rev. 1.1, 2006-11 09142006-87TL-4SLW -0"4 13 NC Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 3.3 High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces The Advanced Memory Buffer supports one FB-DIMM Channel consisting of two bidirectional link interfaces using highspeed differential point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards this information back towards the host and multiplexes in any 3.3.1 read return data or status information that is generated internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs. Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound on 14 secondary differential pairs. DDR2 Channel The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data, and eight check-bit signals. There are two copies of address and command signals to support DIMM routing and electrical requirements. Four transfer bursts are driven on the data and check-bit lines at 800 MHz. 3.3.2 Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The Advanced Memory Buffer provides four copies of the command clock phase references (CLK[3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble. SMBus Slave Interface The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration registers independent of the FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100 kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot and 3.3.3 to set link strength, frequency and other parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the unique ID. Channel Latency FB-DIMM channel latency is measured from the time a read request is driven on the FB-DIMM channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory controller. When not using the Variable Read Latency capability, the latency for a specific DIMM on a channel is always equal to the latency for any other DIMM on that channel. However, the latency for each DIMM in a specific configuration with some number of DIMMs installed may not be equal to the latency for each FB-DIMM in a configuration with some different number of DIMMs installed. As more DIMMs are added to the channel, additional latency is required to read from each DIMM on the Rev. 1.1, 2006-11 09142006-87TL-4SLW channel. Because the channel is based on the point-to-point interconnection of buffer components between DIMMs, memory requests are required to travel through N-1 buffers before reaching the Nth buffer. The result is that a 4 DIMM channel configuration will have greater idle read latency compared to a 1 DIMM channel configuration. The Variable Read Latency capability can be used to reduce latency for DIMMs closer to the host. The idle latencies listed in this section are representative of what might be achieved in typical AMB designs. Actual implementations with latencies less than the values listed will have higher application performance and vice versa. 14 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 3.3.4 Peak Theoretical Channel Throughput An FB-DIMM channel transfers read completion data on the Northbound data connection. 144 bits of data are transferred for every Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 from a single channel or a DRAM burst of four from two lock stepped channels provides a total of 72 bytes of data (64 bytes plus 8 bytes ECC). The FB-DIMM frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FB-DIMM channel clock to the DRAM command clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput as a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data connection is 4.267 GB/sec. Write data is transferred on the Southbound command and data connection, via Command+Wdata frames. 72 bits of data are transferred for every Command+Wdata frame. Two Command+Wdata frames match the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 transfers 3.4 from a single channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data (64 bytes plus 8 bytes ECC). When the frame rate matches the DRAM command clock, the Southbound command and data connection will exhibit one half the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Southbound command and data connection is 2.133 GB/sec. The total peak theoretical throughput for a single FBDIMM channel is defined as the sum of the peak theoretical throughput of the Northbound data connection and the Southbound command and data connection. When the frame rate matches the DRAM command clock, this is equal to 1.5 times the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput of a single DDR2-533 channel would be 4.267 GB/sec., while the peak theoretical throughput of the entire FB-DIMM PC4200F channel would be 6.4GB/sec. Hot-add The FB-DIMM channel does not provide a mechanism to automatically detect and report the addition of a new DIMM south of the currently active last DIMM. It is assumed the system will be notified through some means of the addition of one or more new DIMMs so that specific commands can be sent to the host controller to initialize the newly added 3.5 DIMM(s) and perform a Hot-Add Reset to bring them into the channel timing domain. It should be noted that the power to the DIMM socket must be removed before a "hot-add" DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform function. Hot-remove In order to accomplish removal of DIMMs the host must perform a Fast Reset sequence targeted at the last DIMM that will be retained on the channel. The Fast Reset re-establish the appropriate last DIMM so that the Southbound Tx outputs of the last active DIMM and the Southbound and Northbound outputs of the DIMMs beyond the last active DIMM are disabled. Once the appropriate outputs are disabled the 3.6 system can coordinate the procedure to remove power in preparation for physical removal of the DIMM if needed. It should be noted that the power to the DIMM socket must be removed before a "hot-add" DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform function. Hot-replace Hot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process. Rev. 1.1, 2006-11 09142006-87TL-4SLW 15 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 4 Electrical Characteristics 4.1 Operating Conditions TABLE 8 Absolute Maximum Ratings Symbol VDD VCC VDDQ VDDL VIN, VOUT TSTG VTT Parameter Rating Unit Note 1) Min. Max. Voltage on VDD pin relative to VSS -0.5 +2.3 V Voltage on VCC pin relative to VSS -0,3 1.75 V Voltage on VDDQ pin relative to VSS -0.5 +2.3 V 1)2) Voltage on VDDL pin relative to VSS -0.5 +2.3 V 1)2) Voltage on any pin relative to VSS -0.3 +1.75 V 1) Storage Temperature -55 +100 C 1)2) Voltage on VTT pin relative to VSS -0.5 2.3 V 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TABLE 9 Operating Temperature Range Symbol Parameter Values Min. Max. Unit Note TCASE DRAM Component Case Temperature Range 0 +95 C 1)2)3) TCASE AMB Component Case Temperature Range 0 +110 C 1) 1) Within the DRAM Component Case Temperature range all DRAM specification will be supported. 2) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self-refresh operation. 3) Above 85 C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. Rev. 1.1, 2006-11 09142006-87TL-4SLW 16 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B TABLE 10 Supply Voltage Levels and DC Operating Conditions Parameter Symbol Limit Values Unit Min. Nom. Max. Note AMB Supply Voltage VCC 1.455 1.5 1.575 V DRAM Supply Voltage VDD 1.7 1.8 1.9 V Termination Voltage VTT 0.48 xVDD 0.50 xVDD 0.52 xVDD V EEPROM Supply Voltage VDDSPD 3.0 3.3 3.6 V DC Input Logic High(SPD) VIH(DC) 2.1 -- VDDSPD V 1) DC Input Logic Low(SPD) VIL(DC) -- -- 0.8 V 1) DC Input Logic High(RESET) VIH(DC) 1.0 -- -- V 2) DC Input Logic Low(RESET) VIL(DC) -- -- +0.5 V 1) Leakage Current (RESET) IL -90 -- +90 2) Leakage Current (Link) IL -5 -- +5 3) 1) applies for SMB and SPD Bus Signals 2) applies for AMB CMOS Signal RESET 3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications TABLE 11 Timing Parameters Parameter Symbol Min. Typ. Max. Units Notes EI Assertion Pass-Thru Timing tEI Propagatet -- -- 4 clks EI Deassertion Pass-Thru Timing tEID -- -- Bitlock clks 2) EI Assertion Duration tEI 100 -- -- clks 1)2) FBD Cmd to DDR Clk out that latches Cmd -- -- 8.1 -- ns 3) FBD Cmd to DDR Write -- -- TBD -- ns DDR Read to FBD (last DIMM) -- -- 5.0 -- ns Resample Pass-Thru time -- -- 1.075 -- ns ResynchPass-Thru time -- -- 2.075 -- ns Bit Lock Interval tBitLock -- -- 119 frames 1) Frame Lock Interval tFrameLock -- -- 154 frames 1) 4) 1) Defined in FB-DIMM Architecture and Protocol Spec 2) Clocks defined as core clocks = 2x SCK input 3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to the DRAMs 4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs Rev. 1.1, 2006-11 09142006-87TL-4SLW 17 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B TABLE 12 Environmental Parameters Parameter Symbol Rating Units Note Operating Temperature TOPR See Note Operating Humidity (relative) HOPR 10 to 90 % 2) Storage Temperature TSTG -50 to +100 C 2) Storage Humidity (without condensation) HSTG 5 to 95 % 2) Barometric pressure (operating) PBAR 3050 m 2) Barometric pressure (storage) PBAR 14240 m 2) 1) 1) The designer must meet the case temperature specifications for individual module components. 2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device funcional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Rev. 1.1, 2006-11 09142006-87TL-4SLW 18 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 5 Current Spec. and Conditions The following table provides an overview of the measurement conditions. TABLE 13 IDD Measurement Conditions Parameter Symbol Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary channel disabled CKE high. Command and address lines stable. DRAM clock active ICC_Idle_0 IDD_Idle_0 Idle Current, first DIMM L0 state, idle (0 BW) Primary and Secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active ICC_Idle_1 IDD_Idle_1 Active Power L0 state 50% DRAM BW, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. ICC_Active_1 IDD_Active_1 Active Power, data pass through L0 state 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active. ICC_Active_2 IDD_Active_2 Training Primary and Secondary channels enabled. 100% toggle on all channels lanes. DRAMs idle (0 BW). CKE high. Command and address lines stable. DRAM clock active. ICC_Training IDD_Training IBIST Over all IBIST modes DRAM Idle (0 BW) Primary channel Enabled Secondary channel Enabled CKE high. Command and Address lines stable DRAM clock active ICC_IBIST IDD_IBIST Rev. 1.1, 2006-11 09142006-87TL-4SLW 19 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Parameter Symbol MemBIST Over all MemBIST modes >50% DRAM BW (as dictated by the AMB) Primary channel Enabled Secondary channel Enabled CKE high. Command and Address lines stable DRAM clock active ICC_MEMBIST IDD_MEMBIST Electrical Idle DRAM Idle (0 BW) Primary channel Disabled Secondary channel Disabled CKE low. Command and Address lines Floated DRAM clock active, ODT and CKE driven low ICC_EI IDD_EI Notes 1. 2. 3. 4. 5. 6. 7. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes. Burst Length = 4. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM). Modeled with 27 termination for command, address, and clocks, and 47 termination for control. Termination is referenced to VTT = VDD / 2. Rev. 1.1, 2006-11 09142006-87TL-4SLW 20 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B TABLE 14 Product Type HYS72T64400HFN-3S-B HYS72T128420HFN-3S-B HYS72T256420HFN-3S-B ICC/IDD Specification for PC2-5300F Speed Grade PC2-5300F PC2-5300F PC2-5300F Symbol Max. Max. Max. ICC_Idle_0 2.02 2.08 2.04 A PCC_Idle_0 3.07 3.16 3.09 W IDD_Idle_0 0.76 1.1 2.07 A PDD_Idle_0 1.34 1.94 3.65 W ITOT_Idle_0 2.85 3.2 4.13 A PTOT_Idle_0 4.47 5.12 6.76 W ICC_Idle_1 2.61 2.7 2.64 A PCC_Idle_1 3.92 4.05 3.96 W IDD_Idle_1 0.76 1.09 1.96 A PDD_Idle_1 1.34 1.93 3.45 W ITOT_Idle_1 3.44 3.83 4.62 A PTOT_Idle_1 5.32 6.01 7.42 W ICC_Active_1 2.78 2.86 2.82 A PCC_Active_1 4.16 4.28 4.22 W IDD_Active_1 1.8 2.19 3.84 A PDD_Active_1 3.17 3.85 6.71 W ITOT_Active_1 4.63 5.05 6.69 A PTOT_Active_1 7.37 8.13 10.96 W ICC_Active_2 2.67 2.66 2.77 A PCC_Active_2 4 3.98 4.16 W IDD_Active_2 0.64 0.64 1.8 A PDD_Active_2 1.13 1.13 3.17 W ITOT_Active_2 3.41 3.37 4.65 A PTOT_Active_2 5.22 5.17 7.39 W ICC_IBIST 3.61 3.74 3.65 A PCC_IBIST 5.37 5.55 5.43 W IDD_IBIST 0.62 0.93 1.78 A PDD_IBIST 1.09 1.65 3.15 W ITOT_IBIST 4.3 4.72 5.45 A Rev. 1.1, 2006-11 09142006-87TL-4SLW 21 Unit Note Internet Data Sheet Product Type HYS72T64400HFN-3S-B HYS72T128420HFN-3S-B HYS72T256420HFN-3S-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Speed Grade PC2-5300F PC2-5300F PC2-5300F Symbol Max. Max. Max. PTOT_IBIST 6.53 7.24 8.58 W ICC_Training 3.28 3.39 3.33 A PCC_Training 4.9 5.06 4.96 W IDD_Trainig 0.62 0.93 1.78 A PDD_Training 1.09 1.65 3.15 W ITOT_Trainig 3.98 4.38 5.13 A PTOT_Training 6.07 6.75 8.12 W ICC_EI 1.46 1.52 1.48 A PCC_EI 2.22 2.3 2.25 W IDD_EI 0.12 0.14 0.22 A PDD_EI 0.21 0.25 0.39 W ITOT_EI 1.62 1.72 1.83 A PTOT_EI 2.47 2.61 2.75 W ICC_MEMBIST 2.84 2.92 2.91 A PCC_MEMBIST 4.25 4.37 4.35 W IDD_MEMBIST 2.26 2.58 4.23 A PDD_MEMBIST 3.99 4.54 7.4 W ITOT_MEMBIST 5.18 5.51 7.17 A PTOT_MEMBIST 8.31 8.92 11.77 W Rev. 1.1, 2006-11 09142006-87TL-4SLW 22 Unit Note Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B TABLE 15 Product Type HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B HYS72T256420HFN-3.7-B ICC/IDD Specification for PC2-4200F Speed Grade PC2-4200F PC2-4200F PC2-4200F Symbol Max. Max. Max. ICC_Idle_0 1.72 1.77 1.74 A PCC_Idle_0 2.61 2.69 2.65 W IDD_Idle_0 0.72 1.02 1.93 A PDD_Idle_0 1.27 1.81 3.4 W ITOT_Idle_0 2.48 2.81 3.69 A PTOT_Idle_0 3.92 4.51 6.06 W ICC_Idle_1 2.24 2.3 2.27 A PCC_Idle_1 3.37 3.47 3.42 W IDD_Idle_1 0.72 1.01 1.9 A PDD_Idle_1 1.27 1.79 3.35 W ITOT_Idle_1 3.03 3.33 4.21 A PTOT_Idle_1 4.71 5.27 6.8 W ICC_Active_1 2.4 2.47 2.45 A PCC_Active_1 3.6 3.71 3.68 W IDD_Active_1 1.83 2.19 3.96 A PDD_Active_1 3.23 3.86 6.92 W ITOT_Active_1 4.27 4.67 6.41 A PTOT_Active_1 6.88 7.57 10.6 W ICC_Active_2 2.28 2.28 2.39 A PCC_Active_2 3.44 3.44 3.59 W IDD_Active_2 0.6 0.6 1.84 A PDD_Active_2 1.05 1.05 3.24 W ITOT_Active_2 2.94 2.96 4.26 A PTOT_Active_2 4.55 4.57 6.86 W ICC_IBIST 3.07 3.17 3.12 A PCC_IBIST 4.6 4.74 4.67 W IDD_IBIST 0.57 0.85 1.64 A PDD_IBIST 1.02 1.51 2.89 W ITOT_IBIST 3.72 4.04 4.78 A Rev. 1.1, 2006-11 09142006-87TL-4SLW 23 Unit Note Internet Data Sheet Product Type HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B HYS72T256420HFN-3.7-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Speed Grade PC2-4200F PC2-4200F PC2-4200F Symbol Max. Max. Max. PTOT_IBIST 5.68 6.26 7.58 W ICC_Training 2.81 2.89 2.85 A PCC_Training 4.21 4.34 4.28 W IDD_Trainig 0.57 0.85 1.64 A PDD_Training 1.02 1.51 2.89 W ITOT_Trainig 3.46 3.76 4.52 A PTOT_Training 5.3 5.86 7.19 W ICC_EI 1.21 1.25 1.23 A PCC_EI 1.85 1.91 1.87 W IDD_EI 0.11 0.14 0.23 A PDD_EI 0.19 0.24 0.41 W ITOT_EI 1.37 1.45 1.59 A PTOT_EI 2.08 2.21 2.39 W ICC_MEMBIST 2.43 2.5 2.5 A PCC_MEMBIST 3.65 3.76 3.76 W IDD_MEMBIST 2.19 2.54 4.03 A PDD_MEMBIST 3.87 4.47 7.05 W ITOT_MEMBIST 4.7 5.05 6.54 A PTOT_MEMBIST 7.59 8.24 10.82 W Rev. 1.1, 2006-11 09142006-87TL-4SLW 24 Unit Note Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 6 SPD Codes This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 16 "PC2-5300F-555" on Page 25 * Table 17 "PC2-4200F-444" on Page 30 TABLE 16 Product Type HYS72T64400HFN-3S-B HYS72T128420HFN-3S-B HYS72T256420HFN-3S-B PC2-5300F-555 Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-5300F-555 PC2-5300F-555 PC2-5300F-555 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 0 SPD Size CRC / Total / Used 92 92 92 1 SPD Revision 11 11 11 2 Key Byte / DRAM Device Type 09 09 09 3 Voltage Level of this Assembly 12 12 12 4 SDRAM Addressing 44 44 48 5 Module Physical Attributes 23 23 23 6 Module Type 07 07 07 7 Module Organization 09 11 10 8 Fine Timebase (FTB) Dividend and Divisor 00 00 00 9 Medium Timebase (MTB) Dividend 01 01 01 10 Medium Timebase (MTB) Divisor 04 04 04 11 0C 0C 0C 12 tCK.MIN (min. SDRAM Cycle Time) tCK.MAX (max. SDRAM Cycle Time) 20 20 20 13 CAS Latencies Supported 33 33 33 Rev. 1.1, 2006-11 09142006-87TL-4SLW 25 Internet Data Sheet Product Type HYS72T64400HFN-3S-B HYS72T128420HFN-3S-B HYS72T256420HFN-3S-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-5300F-555 PC2-5300F-555 PC2-5300F-555 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 14 tCAS.MIN (min. CAS Latency Time) 3C 3C 3C 15 Write Recovery Values Supported (WR) 42 42 42 16 tWR.MIN (Write Recovery Time) 3C 3C 3C 17 Write Latency Times Supported 72 72 72 18 Additive Latency Times Supported 50 50 50 19 3C 3C 3C 1E 1E 1E 3C 3C 3C 00 00 00 B4 B4 B4 F0 F0 F0 28 tRCD.MIN (min. RAS# to CAS# Delay) tRRD.MIN (min. Row Active to Row Active Delay) tRP.MIN (min. Row Precharge Time) tRAS and tRC Extension tRAS.MIN (min. Active to Precharge Time) tRC.MIN (min. Active to Active / Refresh Time) tRFC.MIN LSB (min. Refresh Recovery Time Delay) tRFC.MIN MSB (min. Refresh Recovery Time Delay) tWTR.MIN (min. Internal Write to Read Cmd Delay) tRTP.MIN (min. Internal Read to Precharge Cmd Delay) 29 Burst Lengths Supported 30 Terminations Supported 07 07 07 31 Drive Strength Supported 01 01 01 32 C2 C2 C2 33 tREFI (avg. SDRAM Refresh Period) TCASE.MAX Delta / T4R4W Delta 50 50 50 34 Psi(T-A) DRAM 7A 7A 7A 20 21 22 23 24 25 26 27 A4 A4 A4 01 01 01 1E 1E 1E 1E 1E 1E 03 03 03 35 T0 (DT0) DRAM 48 48 48 36 T2Q (DT2Q) DRAM 2E 2E 2E 37 T2P (DT2P) DRAM 36 36 36 38 T3N (DT3N) DRAM 27 27 27 39 T4R (DT4R) / T4R4W Sign (DT4R4W) DRAM 4C 4C 4C Rev. 1.1, 2006-11 09142006-87TL-4SLW 26 Internet Data Sheet Product Type HYS72T64400HFN-3S-B HYS72T128420HFN-3S-B HYS72T256420HFN-3S-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-5300F-555 PC2-5300F-555 PC2-5300F-555 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 40 T5B (DT5B) DRAM 20 20 20 41 T7 (DT7) DRAM 23 23 23 42 - 78 Not used 00 00 00 79 FBDIMM ODT Values 01 22 22 80 Not used 00 00 00 81 Channel Protocols Supported LSB 02 02 02 82 Channel Protocols Supported MSB 00 00 00 83 Back-to-Back Access Turnaround Time 10 10 10 84 AMB Read Access Delay for DDR2-800 56 56 58 85 AMB Read Access Delay for DDR2-667 40 40 42 86 AMB Read Access Delay for DDR2-533 36 36 38 87 Psi(T-A) AMB 30 30 30 88 TIdle_0 (DT Idle_0) AMB 60 60 6A 89 TIdle_1 (DT Idle_1) AMB 7A 7A 84 90 TIdle_2 (DT Idle_2) AMB 6E 6E 6E 91 TActive_1 (DT Active_1) AMB A1 A1 AF 92 TActive_2 (DT Active_2) AMB 7F 7F 8B 93 TL0s (DT L0s) AMB 00 00 00 94 - 97 Not used 00 00 00 98 AMB Junction Temperature Maximum (Tjmax) 00 00 00 99 Category Byte 0A 0A 0A 100 Not used 00 00 00 101 AMB Personality Bytes: Pre-initialization (1) 80 80 80 102 AMB Personality Bytes: Pre-initialization (2) 20 20 20 103 AMB Personality Bytes: Pre-initialization (3) 00 00 00 104 AMB Personality Bytes: Pre-initialization (4) 44 44 44 Rev. 1.1, 2006-11 09142006-87TL-4SLW 27 Internet Data Sheet Product Type HYS72T64400HFN-3S-B HYS72T128420HFN-3S-B HYS72T256420HFN-3S-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-5300F-555 PC2-5300F-555 PC2-5300F-555 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 105 AMB Personality Bytes: Pre-initialization (5) 04 04 04 106 AMB Personality Bytes: Pre-initialization (6) 80 80 80 107 AMB Personality Bytes: Post-initialization (1) 48 48 48 108 AMB Personality Bytes: Post-initialization (2) 53 53 53 109 AMB Personality Bytes: Post-initialization (3) B3 B3 B1 110 AMB Personality Bytes: Post-initialization (4) 43 43 43 111 AMB Personality Bytes: Post-initialization (5) 65 65 65 112 AMB Personality Bytes: Post-initialization (6) 4C 4C 4C 113 AMB Personality Bytes: Post-initialization (7) 00 00 00 114 AMB Personality Bytes: Post-initialization (8) 10 10 10 115 AMB Manufacturers JEDEC ID Code LSB 80 80 80 116 AMB Manufacturers JEDEC ID Code MSB 89 89 89 117 DIMM Manufacturers JEDEC ID Code LSB 85 85 85 118 DIMM Manufacturers JEDEC ID Code MSB 51 51 51 119 Module Manufacturing Location xx xx xx 120 Module Manufacturing Date Year xx xx xx 121 Module Manufacturing Date Week xx xx xx 122 125 Module Serial Number xx xx xx 126 Cyclical Redundancy Code LSB 20 1C EA 127 Cyclical Redundancy Code MSB 42 4A CB 128 Module Product Type, Char #1 37 37 37 129 Module Product Type, Char #2 32 32 32 130 Module Product Type, Char #3 54 54 54 131 Module Product Type, Char #4 36 31 32 132 Module Product Type, Char #5 34 32 35 Rev. 1.1, 2006-11 09142006-87TL-4SLW 28 Internet Data Sheet Product Type HYS72T64400HFN-3S-B HYS72T128420HFN-3S-B HYS72T256420HFN-3S-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-5300F-555 PC2-5300F-555 PC2-5300F-555 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 133 Module Product Type, Char #6 34 38 36 134 Module Product Type, Char #7 30 34 34 135 Module Product Type, Char #8 30 32 32 136 Module Product Type, Char #9 48 30 30 137 Module Product Type, Char #10 46 48 48 138 Module Product Type, Char #11 4E 46 46 139 Module Product Type, Char #12 33 4E 4E 140 Module Product Type, Char #13 53 33 33 141 Module Product Type, Char #14 42 53 53 142 Module Product Type, Char #15 20 42 42 143 Module Product Type, Char #16 20 20 20 144 Module Product Type, Char #17 20 20 20 145 Module Product Type, Char #18 20 20 20 146 Module Revision Code 9x 9x 9x 147 Test Program Revision Code xx xx xx 148 DRAM Manufacturers JEDEC ID Code LSB 85 85 85 149 DRAM Manufacturers JEDEC ID Code MSB 51 51 51 150 informal AMB content revision tag (MSB) 01 01 01 151 informal AMB content revision tag (LSB) 09 09 09 152 175 Not used 00 00 00 176 255 Blank for customer use FF FF FF Rev. 1.1, 2006-11 09142006-87TL-4SLW 29 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B TABLE 17 Product Type HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B HYS72T256420HFN-3.7-B PC2-4200F-444 Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-4200F-444 PC2-4200F-444 PC2-4200F-444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 0 SPD Size CRC / Total / Used 92 92 92 1 SPD Revision 11 11 11 2 Key Byte / DRAM Device Type 09 09 09 3 Voltage Level of this Assembly 12 12 12 4 SDRAM Addressing 44 44 48 5 Module Physical Attributes 23 23 23 6 Module Type 07 07 07 7 Module Organization 09 11 10 8 Fine Timebase (FTB) Dividend and Divisor 00 00 00 9 Medium Timebase (MTB) Dividend 01 01 01 10 Medium Timebase (MTB) Divisor 04 04 04 11 tCK.MIN (min. SDRAM Cycle Time) tCK.MAX (max. SDRAM Cycle Time) 0F 0F 0F 20 20 20 13 CAS Latencies Supported 33 33 33 14 tCAS.MIN (min. CAS Latency Time) 3C 3C 3C 15 Write Recovery Values Supported (WR) 32 32 32 16 tWR.MIN (Write Recovery Time) 3C 3C 3C 17 Write Latency Times Supported 72 72 72 12 18 Additive Latency Times Supported 50 50 50 19 tRCD.MIN (min. RAS# to CAS# Delay) tRRD.MIN (min. Row Active to Row Active Delay) tRP.MIN (min. Row Precharge Time) tRAS and tRC Extension 3C 3C 3C 1E 1E 1E 3C 3C 3C 00 00 00 20 21 22 Rev. 1.1, 2006-11 09142006-87TL-4SLW 30 Internet Data Sheet Product Type HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B HYS72T256420HFN-3.7-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-4200F-444 PC2-4200F-444 PC2-4200F-444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 23 B4 B4 B4 28 tRAS.MIN (min. Active to Precharge Time) tRC.MIN (min. Active to Active / Refresh Time) tRFC.MIN LSB (min. Refresh Recovery Time Delay) tRFC.MIN MSB (min. Refresh Recovery Time Delay) tWTR.MIN (min. Internal Write to Read Cmd Delay) tRTP.MIN (min. Internal Read to Precharge Cmd Delay) 29 Burst Lengths Supported 30 Terminations Supported 07 07 07 31 Drive Strength Supported 01 01 01 32 tREFI (avg. SDRAM Refresh Period) TCASE.MAX Delta / T4R4W Delta C2 C2 C2 33 50 50 50 34 Psi(T-A) DRAM 7A 7A 7A 24 25 26 27 F0 F0 F0 A4 A4 A4 01 01 01 1E 1E 1E 1E 1E 1E 03 03 03 35 T0 (DT0) DRAM 40 40 40 36 T2Q (DT2Q) DRAM 29 29 29 37 T2P (DT2P) DRAM 36 36 36 38 T3N (DT3N) DRAM 21 21 21 39 T4R (DT4R) / T4R4W Sign (DT4R4W) DRAM 40 40 40 40 T5B (DT5B) DRAM 1E 1E 1E 41 T7 (DT7) DRAM 22 22 22 42 - 78 Not used 00 00 00 79 FBDIMM ODT Values 01 22 22 80 Not used 00 00 00 81 Channel Protocols Supported LSB 02 02 02 82 Channel Protocols Supported MSB 00 00 00 83 Back-to-Back Access Turnaround Time 10 10 10 84 AMB Read Access Delay for DDR2-800 56 56 58 Rev. 1.1, 2006-11 09142006-87TL-4SLW 31 Internet Data Sheet Product Type HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B HYS72T256420HFN-3.7-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-4200F-444 PC2-4200F-444 PC2-4200F-444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 85 AMB Read Access Delay for DDR2-667 40 40 42 86 AMB Read Access Delay for DDR2-533 36 36 38 87 Psi(T-A) AMB 30 30 30 88 TIdle_0 (DT Idle_0) AMB 52 52 5B 89 TIdle_1 (DT Idle_1) AMB 66 66 71 90 TIdle_2 (DT Idle_2) AMB 60 60 60 91 TActive_1 (DT Active_1) AMB 84 84 92 92 TActive_2 (DT Active_2) AMB 6A 6A 71 93 TL0s (DT L0s) AMB 00 00 00 94 - 97 Not used 00 00 00 98 AMB Junction Temperature Maximum (Tjmax) 00 00 00 99 Category Byte 0A 0A 0A 100 Not used 00 00 00 101 AMB Personality Bytes: Pre-initialization (1) 80 80 80 102 AMB Personality Bytes: Pre-initialization (2) 20 20 20 103 AMB Personality Bytes: Pre-initialization (3) 00 00 00 104 AMB Personality Bytes: Pre-initialization (4) 44 44 44 105 AMB Personality Bytes: Pre-initialization (5) 04 04 04 106 AMB Personality Bytes: Pre-initialization (6) 80 80 80 107 AMB Personality Bytes: Post-initialization (1) 48 48 48 108 AMB Personality Bytes: Post-initialization (2) 53 53 53 109 AMB Personality Bytes: Post-initialization (3) B3 B3 B1 110 AMB Personality Bytes: Post-initialization (4) 43 43 43 111 AMB Personality Bytes: Post-initialization (5) 65 65 65 112 AMB Personality Bytes: Post-initialization (6) 4C 4C 4C 113 AMB Personality Bytes: Post-initialization (7) 00 00 00 Rev. 1.1, 2006-11 09142006-87TL-4SLW 32 Internet Data Sheet Product Type HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B HYS72T256420HFN-3.7-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-4200F-444 PC2-4200F-444 PC2-4200F-444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 114 AMB Personality Bytes: Post-initialization (8) 10 10 10 115 AMB Manufacturers JEDEC ID Code LSB 80 80 80 116 AMB Manufacturers JEDEC ID Code MSB 89 89 89 117 DIMM Manufacturers JEDEC ID Code LSB 85 85 85 118 DIMM Manufacturers JEDEC ID Code MSB 51 51 51 119 Module Manufacturing Location xx xx xx 120 Module Manufacturing Date Year xx xx xx 121 Module Manufacturing Date Week xx xx xx 122 125 Module Serial Number xx xx xx 126 Cyclical Redundancy Code LSB FC C0 F6 127 Cyclical Redundancy Code MSB 7C 74 ED 128 Module Product Type, Char #1 37 37 37 129 Module Product Type, Char #2 32 32 32 130 Module Product Type, Char #3 54 54 54 131 Module Product Type, Char #4 36 31 32 132 Module Product Type, Char #5 34 32 35 133 Module Product Type, Char #6 34 38 36 134 Module Product Type, Char #7 30 34 34 135 Module Product Type, Char #8 30 32 32 136 Module Product Type, Char #9 48 30 30 137 Module Product Type, Char #10 46 48 48 138 Module Product Type, Char #11 4E 46 46 139 Module Product Type, Char #12 33 4E 4E 140 Module Product Type, Char #13 2E 33 33 141 Module Product Type, Char #14 37 2E 2E Rev. 1.1, 2006-11 09142006-87TL-4SLW 33 Internet Data Sheet Product Type HYS72T64400HFN-3.7-B HYS72T128420HFN-3.7-B HYS72T256420HFN-3.7-B HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Organization 512MB 1 GByte 2 GByte x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 2 Ranks (x4) Label Code PC2-4200F-444 PC2-4200F-444 PC2-4200F-444 JEDEC SPD Revision Rev. 1.1 Rev. 1.1 Rev. 1.1 Byte# Description HEX HEX HEX 142 Module Product Type, Char #15 42 37 37 143 Module Product Type, Char #16 20 42 42 144 Module Product Type, Char #17 20 20 20 145 Module Product Type, Char #18 20 20 20 146 Module Revision Code 7x 7x 7x 147 Test Program Revision Code xx xx xx 148 DRAM Manufacturers JEDEC ID Code LSB 85 85 85 149 DRAM Manufacturers JEDEC ID Code MSB 51 51 51 150 informal AMB content revision tag (MSB) 01 01 01 151 informal AMB content revision tag (LSB) 09 09 09 152 175 Not used 00 00 00 176 255 Blank for customer use FF FF FF Rev. 1.1, 2006-11 09142006-87TL-4SLW 34 Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-A 7 Package Outline near the device power pins. The AMB device in the center of the DIMM has a metal Heat Sink. The FB-DIMM mechanical outlines are consistent with JEDEC MO-256. All Components are surface mounted on one or both sides of the PCB and positioned on the PCB to meet the minimum and maximum trace lengths required for DDR2 SDRAM signals. Bypass capacitors for DDR2 SDRAM devices are located TABLE 18 Raw Card Reference JEDEC Raw Card Infineon PCB Dimensions Width [mm] R/C A L-DIM-240-21 Figure 4 133.35 Height [mm] 30.35 Thickness [mm] 8.2 Notes 1) R/C B L-DIM-240-22 Figure 5 133.35 30.35 8.2 1) R/C H L-DIM-240-25 Figure 6 133.35 30.35 8.2 1) 1) Thickness includes Infineon Heat Sink. Some early production modules with Jedec Heatspreader may be thicker up to 8.2mm. Attention: Heat Sink heat up during operation. When unplugging a DIMM from a system direct skin contact should be avoided until the Heat Sink has reached room temperature. Attention: The Heat Sink is mechanically loaded. Do not remove. Removal of the clip may cause injuries. Attention: Any mechanical stress on the Heat Sink should be avoided. Touching the Heat Sink while plugging or unplugging the module may permanently damage the DIMM. Rev. 1.10, 2006-11 11182005-JVRU-2GJ1 35 Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-A FIGURE 4 Package Outline L-DIM-240-21 with Full Heat Sink ! " # !8 X # ! " ). $ETAILO FC ONTA CTS ! " # "URRMA XALLOWE D ',$ 2. General tolerances +/- 0.15 3. Drawing according to ISO 8015 Notes 1. Please contact your sales or marketing representative for more details on package dimensions. Rev. 1.10, 2006-11 11182005-JVRU-2GJ1 36 Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-A FIGURE 5 Package Outline L-DIM-240-22 with Full Heat Sink ! " # !8 X # ! " -). $ETAILO FC ONTACTS ! " # 2. General tolerances +/- 0.15 3. Drawing according to ISO 8015 Notes 1. Please contact your sales or marketing representative for more details on package dimensions. Rev. 1.10, 2006-11 11182005-JVRU-2GJ1 37 Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-A FIGURE 6 Package Outline L-DIM-240-25 with Full Heat Sink ! " # -! 8 X # ! " ). $ETA ILOFC ONTA CTS ! " # "URRMA XALLOW E D ',$ 2. General tolerances +/- 0.15 3. Drawing according to ISO 8015 Notes 1. Please contact your sales or marketing representative for more details on package dimensions. Rev. 1.10, 2006-11 11182005-JVRU-2GJ1 38 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B 8 DDR2 Nomenclature TABLE 19 Nomenclature Fields and Examples Example for Field Number 1 2 3 4 5 6 7 8 9 10 11 Micro-DIMM HYS 64 T 64128 0 2 0 K M -5 -A DDR2 DRAM HYB 18 T 5121G 16 0 A C -5 TABLE 20 DDR2 DIMM Nomenclature Field Description Values Coding 1 Qimonda Module Prefix HYS Constant 2 Module Data Width [bit] 64 Non-ECC 72 ECC 3 DRAM Technology T DDR2 4 Memory Density per I/O [Mbit]; Module Density1) 32 256 MByte 64 512 MByte 128 1 GByte 256 2 GByte 512 4 GByte 0 .. 9 Look up table 5 Raw Card Generation 6 Number of Module Ranks 0, 2, 4 1, 2, 4 7 Product Variations 0 .. 9 Look up table 8 Package, Lead-Free Status A .. Z Look up table 9 Module Type D SO-DIMM M Micro-DIMM R Registered U Unbuffered F Fully Buffered -2.5 PC2-6400 6-6-6 -3 PC2-5300 4-4-4 -3S PC2-5300 5-5-5 10 Speed Grade Rev. 1.1, 2006-11 09142006-87TL-4SLW -3.7 PC2-4200 4-4-4 -5 PC2-3200 3-3-3 39 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Field Description Values Coding 11 Die Revision -A First -B Second 1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding". TABLE 21 DDR2 DRAM Nomenclature Field Description Values Coding 1 Qimonda Component Prefix HYB Constant 2 Interface Voltage [V] 18 SSTL_18 3 DRAM Technology T DDR2 4 Component Density [Mbit] 256 256 Mbit 512 512 Mbit 1G 1 Gbit 2G 2 Gbit 40 x4 80 x8 5+6 Number of I/Os 16 x16 7 Product Variations 0 .. 9 Look up table 8 Die Revision A First B Second C FBGA, lead-containing F FBGA, lead-free -2.5 DDR2-800 6-6-6 9 Package, Lead-Free Status 10 Speed Grade Rev. 1.1, 2006-11 09142006-87TL-4SLW -3 DDR2-667 4-4-4 -3S DDR2-667 5-5-5 -3.7 DDR2-533 4-4-4 -5 DDR2-400 3-3-3 40 Internet Data Sheet HYS72T[64/128/256]4[00/20]HFN-[3S/3.7]-B Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.5 3.6 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Current Spec. and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 12 12 12 14 14 14 14 15 15 15 15 6 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 DDR2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Rev. 1.1, 2006-11 09142006-87TL-4SLW 41 Internet Data Sheet Edition 2006-11 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com