Advanced Power Electronics Corp. AP1280 2A SINK/SOURCE BUS TERMINATION REGULATOR DESCRIPTIOON FEATURES Ideal for DDR-I, DDR-II and DDR-III V TT Applications The AP1280 is a simple, cost-effective and highspeed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2V DDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The AP1280 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AP1280 are available in the ESOP-8 (Exposed Pad) & SO-8 surface mount packages. Sink and Source 2A Continuous Current Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL_18, HSTL, SCSI-2 and SCSI-3 Interfaces. High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in ESOP-8 (Exposed Pad) & SO-8 Packages VIN and VCNTL No Power Sequence Issue RoHS Compliant and 100% Lead (Pb)-Free APPLICATION Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems TYPICAL APPLICATION VCNTL=3.3V VIN=2.5V/1.8V/1.5V CIN VIN R1 RTT AP1280 REFEN VOUT 2N7002 EN CCNTL VCNTL CSS R2 GND COUT RDUMMY R1 = R2 = 100K, RTT = 50 / 33 / 25 COUT,min = 10uF (Ceramic) + 100uF under the worst case testing condition CSS = 1F, CIN = 470F(Low ESR), CCNTL = 47F Data and specifications subject to change without notice 1 201003052 Advanced Power Electronics Corp. AP1280 ABSOLUTE MAXIMUM RATINGS(Note1) Input Voltage (VIN) ------------------------------------------- 6V CNTL Pin Voltage (VCNTL) --------------------------------- 6V Power Dissipation (PD) ------------------------------------- Internally Limited Storage Temperature Range (TST) ---------------------- -65 to +150C Lead Temperature (Soldering, 10sec.) ---------------- 260C Thermal Resistance from Junction to Case (R thjc) ESOP-8 28C/W SO-8 40C/W Note1 : Exceeding the absolute maximum rating may damage the device. OPERATING RATING(Note2) Input Voltage (VIN) ------------------------------------------- 2.5V to 1.5V +3% CNTL Pin Voltage (VCNTL) --------------------------------- 5.5V or 3.3V +5% Junction Temperature Range (TJ) ----------------------- -40 to +125C Ambient Temperature Range (T A) ---------------------- -40 to +85C Note2 : The device is not guaranteed to function outside its operating conditions. ORDERING / PACKAGE INFORMATION ( Top View ) AP1280X-HF ( Top View ) VIN 1 8 NC VIN 1 8 VCNTL GND 2 7 NC GND 2 7 VCNTL REFEN 3 REFEN 3 6 VCNTL VOUT 4 VOUT 4 5 VCNTL Halogen-Free MP : ESOP-8 M : SO-8 GND 6 VCNTL 5 NC ESOP-8 SO-8 o Rthja = 120oC/W Rthja = 75 C/W ELECTRICAL SPECIFICATIONS (VIN=1.8V, VCNTL=3.3V, VREFEN=0.9V, COUT=10uF(Ceramic), TA =25oC, unless otherwise specified) Parameter SYM TEST CONDITION MIN TYP MAX UNITS Input VCNTL Operation Current ICNTL IOUT = 0A - 1 2.5 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown), RLOAD = 180 - 50 90 uA VOS IOUT = 0A -20 - 20 IOUT = 2A -20 - 20 IOUT = -2A -20 - 20 2.2 - - Output (DDR / DDRII / DDRIII) Output Offset Voltage (Note3) (Note4) Load Regulation VLoad mV Protection Current Limit Thermal Shutdown Temperature Thermal Shutdown Hysteresis ILIM TSD 3.3V < VCNTL < 5V 130 160 - TSD 3.3V < VCNTL < 5V - 30 - 0.65 - - - - 2 A o C REFEN Shutdown Shutdown Threshold VIH Enable VIL Shutdown V Note3. VOS offset is the voltage measurement defined as V OUT subtracted from VREFEN. Note4. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. 2 Advanced Power Electronics Corp. AP1280 PIN DESCRIPTIONS PIN SYMBOL VIN PIN DESCRIPTION Power Input Voltage. GND VOUT Ground Pin VCNTL Gate Drive Voltage Output Voltage REFEN Reference Voltage Input and Chip Enable BLOCK DIAGRAM VCNTL VIN Current Limit Thermal Protection REFEN + EA - VOUT APPLICATION INFORMATION Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the AP1280. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AP1280 and the preceding powe converter. 3 Advanced Power Electronics Corp. AP1280 Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. Thermal Consideration AP1280MP regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125 oC. The power dissipation definition in device is: P D = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( TJ(MAX) -TA ) / Rthja Where T J(MAX) is the maximum operation junction temperature 125 oC, TA is the ambient temperature and the R thja is the junction to ambient thermal resistance. The junction to ambient o thermal resistance (Rthja is layout dependent) for ESOP-8 package (Exposed Pad) is 75 C/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at T A = o 25 C can be calculated by following formula: P D(MAX) = (125oC - 25oC) / 75oC/W = 1.33W The thermal resistance R thja of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. 4 Advanced Power Electronics Corp. AP1280 TYPICAL PERFORMANCE CHARACTERISTICS Output Voltage vs. Temperature 0.92 Shutdown Threshold vs. Temperature 0.55 Shutdown Threshold (V) Output Voltage (V) Turn On 0.5 0.915 0.91 0.905 0.9 0.895 0.89 0.45 Turn Off 0.4 0.35 0.3 0.25 -50 -25 0 25 50 75 100 125 -50 -25 0 o 50 75 100 125 o Temperature ( C) VCNTL = 3.3V VIN = 1.8V, Temperature ( C) VIN = 1.8V, VCNTL = 3.3V VIN = 1.8V, VCNTL = 3.3V VIN Current vs. Temperature 16 25 VCNTL Current vs. Temperature 2 15 VCNTL Current (mA) VIN Current (uA) 1.8 14 13 12 11 10 1.6 1.4 1.2 1 9 0.8 8 0.6 7 0.4 6 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature ( C) VIN = 1.8V, VCNTL = 3.3V 75 100 125 Sink Current Limit vs. Temperature 4 Sink Current Limit (A) Source Current Limit (A) 50 VIN = 1.8V, VCNTL = 3.3V Source Current Limit vs. Temperature 4 25 Temperature (oC) o 3.5 3 2.5 2 3.5 3 2.5 2 1.5 1.5 -50 -25 0 25 50 Temperature (oC) VIN = 1.8V, VCNTL = 3.3V 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (oC) VIN = 1.8V, VCNTL = 3.3V 5 Advanced Power Electronics Corp. AP1280 TYPICAL PERFORMANCE CHARACTERISTICS Load Transient (Source test) Load Transient (Sink test) VOUT VOUT IOUT IOUT VIN=1.8V, VCNTL=3.3V VIN=1.8V, VCNTL=5V VIN = 1.8V, VCNTL = 3.3V VIN = 1.8V, VCNTL = 3.3V VREF = 0.9V Supplied by a regulator VREF = 0.9V Supplied by a regulator Output Short-Circuit Protection (Source) Output Short Circuit(A) Output Short Circuit(A) Output Short-Circuit Protection (Sink) Time (1ms/div) VIN = 1.8V, VCNTL = 3.3V Time (1ms/div) VIN = 1.8V, VCNTL = 3.3V 6 ADVANCED POWER ELECTRONICS CORP. Package Outline : ESOP-8 P Millimeters Q SYMBOLS MIN A2 MAX A 5.80 6.00 6.20 B 4.80 4.90 5.00 C 3.80 3.90 4.00 D 0 4 8 E 0.40 0.65 0.90 F 0.19 0.22 0.25 M 0.00 0.08 0.15 H 0.35 0.42 0.49 L 1.35 1.55 1.75 0.375 REF. J B NOM K 45 G 1.27 TYP. P 2.15 2.25 2.35 Q 2.15 2.25 2.35 L I J 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. Part Marking Information & Packing : ESOP-8 Part Number 1280MP YWWSSS Package Code Date Code (YWWSSS) YLast Digit Of The Year WWWeek SSSSequence Draw No. M1-MP-8-G-v01 ADVANCED POWER ELECTRONICS CORP. Package Outline : SO-8 D SYMBOLS 8 7 6 5 E1 1 2 3 E 4 e B Millimeters MIN NOM MAX A 1.35 1.55 1.75 A1 0.10 0.18 0.25 B 0.33 0.41 0.51 c 0.19 0.22 0.25 D 4.80 4.90 5.00 E 5.80 6.15 6.50 E1 3.80 3.90 4.00 e 1.27 TYP G 0.254 TYP L 0.38 0.90 0.00 4.00 8.00 A 1.All Dimension Are In Millimeters. A1 2.Dimension Does Not Include Mold Protrusions. G Part Marking Information & Packing : SO-8 Laser Marking Part Number Package Code 1280M YWWSSS Date Code (YWWSSS) YLast Digit Of The Year WWWeek SSSSequence Draw No. M1-M-8-G-v01