AP1280M-HF - Advanced Power Electronics Corp. USA

Advanced Power

Electronics Corp.

2A SINK/SOURCE BUS TERMINATION REGULATOR

FEATURE

DESCRIPTIOON

Ideal for DDR-I, DDR-II and DDR-III VTT Applications

Sink and Source 2A Continuous Current

Integrated Power MOSFETs

Generates Termination Voltage for SSTL_2, SSTL_18,

HSTL, SCSI-2 and SCSI-3 Interfaces.

High Accuracy Output Voltage at Full-Load

Output Adjustment by Two External Resistors

Low External Component Count

Shutdown for Suspend to RAM (STR) Functionality

with High-Impedance Output

Current Limiting Protection

On-Chip Thermal Protection

Available in ESOP-8 (Exposed Pad) & SO-8 Packages

VIN and VCNTL No Power Sequence Issue

RoHS Compliant and 100% Lead (Pb)-Free

APPLICATIO

Desktop PCs, Notebooks, and Workstations

Graphics Card Memory Termination

Set Top Boxes, Digital TVs, Printers

Embedded Systems

Active Termination Buses

DDR-I, DDR-II and DDR-III Memory Systems

Data and specifications subject to change without notice

201003052

AP1280

TYPICAL APPLICATION

The AP1280 is a simple, cost-effective and high-

speed linear regulator designed to generate termination

voltage in double data rate (DDR) memory system to

comply with the JEDEC SSTL_2 and SSTL_18 or other

specific interfaces such as HSTL, SCSI-2 and SCSI-3

etc. devices requirements. The regulator is capable of

actively sinking or sourcing up to 2A while regulating an

output voltage to within 40mV. The output termination

voltage cab be tightly regulated to track 1/2VDDQ by two

external voltage divider resistors or the desired output

voltage can be pro-grammed by externally forcing the

REFEN pin voltage.

The AP1280 also incorporates a high-speed

differential amplifier to provide ultra-fast response in

line/load transient. Other features include extremely low

initial offset voltage, excellent load regulation, current

limiting in bi-directions and on-chip thermal shut-down

protection.

The AP1280 are available in the ESOP-8

(Exposed Pad) & SO-8 surface mount packages.

VIN VCNTL

REFEN VOUT

GND

RTT

VIN=2.5V/1.8V/1.5V

VCNTL=3.3V

R2CSS

CIN

COUT

CCNTL

2N7002 AP1280

RDUMMY

R1 = R2 = 100KΩ, RTT = 50Ω / 33Ω / 25Ω

COUT,min = 10uF (Ceramic) + 100uF under the worst case testing condition

CSS = 1µF, CIN = 470µF(Low ESR), CCNTL = 47µF

Advanced Power

Electronics Corp. AP1280

ABSOLUTE MAXIMUM RATINGS(Note1)

Input Voltage (VIN) ------------------------------------------

CNTL Pin Voltage (VCNTL) --------------------------------

Power Dissipation (PD) ------------------------------------

Internally Limited

Storage Temperature Range (TST) ---------------------

-65 to +150°C

Lead Temperature (Soldering, 10sec.) ---------------- 260°C

ESOP-8 28°C/W

SO-8 40°C/W

Note1 : Exceeding the absolute maximum rating may damage the device.

OPERATING RATING(Note2)

Input Voltage (VIN) ------------------------------------------

2.5V to 1.5V +3%

CNTL Pin Voltage (VCNTL) --------------------------------

5.5V or 3.3V +5%

Junction Temperature Range (TJ) ----------------------

-40 to +125°C

Ambient Temperature Range (TA) ---------------------- -40 to +85°C

Note2 : The device is not guaranteed to function outside its operating conditions.

ORDERING / PACKAGE INFORMATION

(VIN=1.8V, VCNTL=3.3V, VREFEN=0.9V, COUT=10uF(Ceramic), TA =25oC, unless otherwise specified)

Parameter SYM TEST CONDITION MIN TYP MAX UNITS

VCNTL Operation Current ICNTL IOUT = 0A - 1 2.5 mA

Standby Current ISTBY VREFEN < 0.2V (Shutdown), RLOAD = 180Ω-50 90 uA

Output Offset Voltage(Note3) VOS IOUT = 0A -20 - 20

IOUT = 2A -20 - 20

IOUT = -2A -20 - 20

Current Limit ILIM 2.2 - - A

Thermal Shutdown Temperature TSD 3.3V < VCNTL < 5V 130 160 -

Thermal Shutdown Hysteresis ΔTSD 3.3V < VCNTL < 5V - 30 -

VIH Enable 0.65 - -

VIL Shutdown - - 2

Note3. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.

Note4. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation

in the load range from 0A to 2A.

Thermal Resistance from Junction to Case (Rthjc)

ELECTRICAL SPECIFICATIONS

Input

Output (DDR / DDRII / DDRIII)

Load Regulation(Note4) ΔVLoad mV

Protection

REFEN Shutdown

Shutdown Threshold V

AP1280X-HF

MP : ESOP-8

M : SO-8

Halogen-Free

(Top View )

REFEN

ESOP-8

NCGND

VIN

VCNTL

VOUT

GND

(Top View)

REFEN

SO-8

GND

VIN

VCNTL

VOUT

VCNTL

Rth

a = 75oC/W Rth

a = 120oC/W

Advanced Power

Electronics Corp. AP1280

PIN DESCRIPTIONS

PIN SYMBOL PIN DESCRIPTION

VIN Power Input Voltage.

GND Ground Pin

VOUT Output Voltage

VCNTL Gate Drive Voltage

REFEN Reference Voltage Input and Chip Enable

BLOCK DIAGRA

APPLICATION INFORMATION

Input Capacitor and Layout Consideration

-EA

Current Limit

Thermal Protection

REFEN

VOUT

VIN

VCNTL

Place the input bypass capacitor as close as possible to the AP1280. A low ESR capacitor

larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize

parasitic resistance and inductance.

Inappropriate layout may result in large parasitic inductance and cause undesired oscillation

between AP1280 and the preceding powe converter.

Advanced Power

Electronics Corp. AP1280

Consideration while designs the resistance of voltage divider

Thermal Consideration

Make sure the sinking current capability of pull-down NMOS if the lower resistance was

chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider

form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start

while another is for noise immunity.

AP1280MP regulators have internal thermal limiting circuitry designed to protect the device

during overload conditions.For continued operation, do not exceed maximum operation junction

temperature 125oC. The power dissipation definition in device is:

PD = (VIN - VOUT) x IOUT + VIN x IQ

The maximum power dissipation depends on the thermal resistance of IC package, PCB

layout, the rate of surroundings airflow and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by following formula:

PD(MAX) = ( TJ(MAX) -TA ) / Rthja

Where TJ(MAX) is the maximum operation junction temperature 125oC, TA is the ambient

temperature and the Rthja is the junction to ambient thermal resistance. The junction to ambient

thermal resistance (Rthja is layout dependent) for ESOP-8 package (Exposed Pad) is 75oC/W on

standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA =

25oC can be calculated by following formula:

PD(MAX) = (125oC - 25oC) / 75oC/W = 1.33W

The thermal resistance Rthja of ESOP-8 (Exposed Pad) is determined by the package design

and the PCB design. However, the package design has been decided. If possible, it's useful to

increase thermal performance by the PCB design. The thermal resistance can be decreased by

adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't

stretch infinitely and avoid the tin overflow.

Advanced Power

Electronics Corp. AP1280

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 1.8V, VCNTL = 3.3V

VIN = 1.8V, VCNTL = 3.3V VIN = 1.8V, VCNTL = 3.3VVIN = 1.8V, VCNTL = 3.3V

VIN = 1.8V, VCNTL = 3.3V VIN = 1.8V, VCNTL = 3.3V

VIN = 1.8V, VCNTL = 3.3V

Output Voltage vs. Temperature

0.89

0.895

0.9

0.905

0.91

0.915

0.92

-50 -25 0 25 50 75 100 125

Temperature (oC)

Output Voltage (V)

Shutdown Threshold vs. Temperature

0.25

0.3

0.35

0.4

0.45

0.5

0.55

-50 -25 0 25 50 75 100 125

Temperature (oC)

Shutdown Threshold (V)

Turn On

Turn Off

VIN Current vs. Temperature

-50 -25 0 25 50 75 100 125

Temperature (oC)

VIN Current (uA)

VCNTL Current vs. Temperature

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

Temperature (oC)

VCNTL Current (mA)

Source Current Limit vs. Temperature

1.5

2.5

3.5

-50 -25 0 25 50 75 100 125

Temperature (oC)

Source Current Limit (A)

Sink Current Limit vs. Temperature

1.5

2.5

3.5

-50 -25 0 25 50 75 100 125

Temperature (oC)

Sink Current Limit (A)

Advanced Power

Electronics Corp. AP1280

TYPICAL PERFORMANCE CHARACTERISTICS

Load Transient (Source test) Load Transient (Sink test)

VIN = 1.8V, VCNTL = 3.3V VIN = 1.8V, VCNTL = 3.3V

VREF = 0.9V Supplied by a regulatorVREF = 0.9V Supplied by a regulator

Output Short-Circuit Protection (Sink) Output Short-Circuit Protection (Source)

VIN = 1.8V, VCNTL = 3.3V VIN = 1.8V, VCNTL = 3.3V

VIN=1.8V, VCNTL=3.3V

VIN=1.8V, VCNTL=5V

OUT

IOUT I

Output Short Circuit(A)

Time (1ms/div) Time (1ms/div)

Package Outline : ESOP-8

Millimeters

SYMBOLS MIN NOM MAX

A 5.80 6.00 6.20

B 4.80 4.90 5.00

C 3.80 3.90 4.00

D 0°4°8°

E 0.40 0.65 0.90

F 0.19 0.22 0.25

M 0.00 0.08 0.15

0.35 0.42 0.49

L 1.35 1.55 1.75

P 2.15 2.25 2.35

Q 2.15 2.25 2.35

1.All Dimension Are In Millimeters.

2.Dimension Does Not Include Mold Protrusions.

Part Marking Information & Packing : ESOP-8

Draw No. M1-MP-8-G-v01

0.375 REF.

45°

1.27 TYP.

ADVANCED POWER ELECTRONICS CORP.

1280MP

YWWSSS

Package Code

Part Number

Date Code (YWWSSS)

Y：Last Digit Of The Year

WW：Week

SSS：Sequence

Package Outline : SO-8

MIN NOM MAX

1.35 1.55 1.75

0.10 0.18 0.25

0.33 0.41 0.51

0.19 0.22 0.25

4.80 4.90 5.00

5.80 6.15 6.50

3.80 3.90 4.00

0.38 －0.90

0.00 4.00 8.00

1.All Dimension Are In Millimeters.

2.Dimension Does Not Include Mold Protrusions.

Part Marking Information & Packing : SO-8

Laser Marking

Draw No. M1-M-8-G-v01

1.27 TYP

0.254 TYP

ADVANCED POWER ELECTRONICS CORP.

SYMBOLS Millimeters

134

5678

Part Number

1280M

YWWSSS

Package Code

Date Code (YWWSSS)

Y：Last Digit Of The Year

WW：Week

SSS：Sequence