SGS-THOMSON VE MICROELECTRONICS STLC7545 ENHANCED V.34 BIS ANALOG FRONT-END BFULL ECHO CANCELLING CAPABILITY B FULLY COMPATIBLE WITH THE ST7544 #16-BIT OVERSAMPLING A/D AND D/ACONVERTERS - Programmable down-sampling frequency from 7200 to 22kHz. - Sampling frequency can be 3, 4,6, 8, 12, 16 x symbol rate. - Programmable Over sampling frequency (128, 160 or 192 x sampling frequency). - The STLC7545 can work with external oversampling clocks. - Programmable symbol rate (600, 1200, 1600, 2400, 2560, 2743, 2800, 2954, 3000, 3200, 3429 and 3491). - Bit rates of 300bps, 600bps, 1200 and all multiples of 2400bps up to 38400bps can be generated. - Dynamic range : 92dB with a sampling frequency 9600Hz, oversampling ratio 160. - Total harmonic distortion :-89dB. BON CHIP REFERENCE VOLTAGE BTHREE PROGRAMMABLE DIGITAL FILTERS SEC- TIONS (up to 14th order each, coefficients loaded into RAM): - Tx interpolation filter - Rx decimation filter - Rx reconstruction filter BANCILLARY CONVERTERS FOR EYE-DIAGRAM MONITORING BCLOCK SYSTEM BASED ON DIGITAL PHASE LOCKED LOOPS - Separate Tx DPLLand Rx DPLL - Terminal clock input for Tx synchronization on all multi- ples of 2400Hz (VFast synchronization mode) or on sub-multiple of baud rate (7544 synchronization mode) - Bit, Baud, sampling and highest synchronous clock outputs - Maximum master clock frequency is 38MHz BESINGLE OR DUAL SYNCHRONOUS SERIAL INTER- FACE TO DSP BANALOG POWER SUPPLY VOLTAGE : +5V DIGITAL POWER SUPPLY FROM 3.3V TO 5V BLOW POWER CONSUMPTION : - 100mW operating power at the nominal crystal fre- quency of 36.864MHz (digital supply at 3.3) - Less than 5mW in the Low-Power Reset Mode #0.7um CMOS PROCESS BPLOC44 OR TQFP44 (1.4mm body thickness) April 1996 PRELIMINARY DATA DESCRIPTION The STLC7545 is a single chip Analog Front-End (AFE) designed to implement high speed voice-grade Modems up to 38400 bps with echo cancelling capability. Associated with one or several Digital Signal Processors (DSP), it provides a powertul solution for the implementa- tion of multi-mode Modems meeting CCITT (V.17, V.21, V.22, V.22 bis, V.23, V.26, V.27, V.29, V.32,V.32 bis, V.33, V.34 and V.34 bis} and BELL (103, 202, 212A...) recom- mendations. It is fully compatible with the $T7544 and is also well suited emerging applications involving bit rates up to 38400 bps (inthe VFast synchronization mode). The transmit section includes a 16-bit over-sampling D/A converter with a programmable interpolating filter. The receive section includes a 16-bit oversampling A/D con- verter with two programmable filters (one for decimation and the other for reconstruction). Oversampling ratio is selectable to either 128, 160 or 192. Two additional 8-bit D/A converters allow eyediagram monitoring on a scope for modem performance adjustment. Two independant clock generator systems are provided, one synchronized on the Tx rate and the other on the Rx rate. In External Clock Mode, external oversampling clocks can be provided to the chip. Two independant synchronous serial interfaces (SS1) allow several versatile ways of communicating with standard DSPs. To save power, e.g. in lap-top modem applications, the lowpower reset mode can be used to reduce the power consumption to less than 5mW. PLCC44 (Plastic Chip Carrier) ORDER CODE : STLC7545CFN TQFP44 (10 x 10 x 1.4mm) (Plastic Quad Flat Pack) ORDER CODE : STLC7545TQFP4Y 1/53 This is advance information on anew product now in development or undergoing evaluation. Details are subject io Change without notice.STLC7545 TABLE OF CONTENTS | PIN DESCRIPTION ....................000.0..0 000002000 ccc eee 1.1 PIN CONNECTIONS (Top View)... 0.000000. 0000 000 cee cee eee 1.2 PIN LIST... 0.000.000.0000 000000 ccc eee eee eee 1.3 PIN FUNCTION . 0.000000... 0000000000000 02 ce ee Il BLOCK DIAGRAM. .............. 0.000000. 0000002 ce eee III FUNCTIONAL DESCRIPTION.................0.2.0.20....0...02.....020-. Ul. SIGNAL TRANSFER BLOCK DIAGRAM. ........................220....... l.2 TRANSMIT D/ASECTION. .....0.0000.000.0 0000000000000 000 cece eee 2.1 Interpolation Filters. ........0..0.0.02 020.000.002.050 00 2c ce ee 2.1.1 Programmable Interpolation Filter (IIR1) 2.2... ....2.2.222.2.2002.....-.-----. 2.1.2 FIR Filter (FIR1) . 2... ce ee eee 2.2 D/A Converter... 2.00 ee eee IIL. Receive A/D Section.......0.000000000 000000000 ce ee 3.1 A/D Gonverter... 2.000.000.0000 000002 eee 3.2 Decimation Filters. ....000000000 0000000000002 ce ee 3.2.1 FIR Filter (FIR2) 2.0... ce ee eee ee 3.2.2 Programmable Decimation Filter (IIR@) 22.2.2... eee 3.3 Eye-diagram Display ... 2.0.20... 02 ce tt eee ee l.4 RECEIVE RECONSTRUCTION SECTION ........020020.200...2.0........... 1.4.1 Programmable Interpolation Filter (IIR3) . 2.0... .00.00 0000.0... 0.0.2.0. Il.4.2 FIR Filter (FIRS). 20. eee eee HLS CLOCK GENERATION. ..........0.0200.. 000.000.000.000 ce ee eee ee 1.5.14 TransmitDPLL. ww. Il.5.2 TransmitGlocks . 2.0.02. eee 5.2.1 InternalMode.... 2... 0.000 eee 5.2.2 External Mode. 20... eee ee ee eens 5.3 Receive DPLL...... 0.0 0000000 000000 0c ee I.5.4 Receive Clocks. 0.0.0. eee I.5.4.1 InternalMode.... 2... 0.0 eee Il.5.4.2 External Mode. .......0.0.0.0 000.0 ce ce eee I.6 SERIAL INPUT/OUTPUT SYNCHRONOUS INTERFACES ...............22... 1.6.1 Tx Glock Related Registers .... 2.0.0.0... ee eee 6.2 Rx Clock Related Registers..................... 0020000202022 e eee eee IV SERIAL INTERFACE OPERATION...............................0....... IV.4 DUAL SERIAL INTERFACE MODE (S8SIA, SSIB).... 2... ..020200000....0....... IVv.2 SINGLE SERIAL INTERFAGE MODE............0..020...02.2..0.00....000.... IV.3 COEFFICIENT LOADING MODE..................2...0.0.0..0.2.020000.. IV.4 COEFFICIENT READING ............0.000..0. 0000000000 0c ee eee IV.5 GRYSTAL SELECTION (XTAL10, XTAL11}) . 20.2000 0... ee eee IV.6 FRAME FREQUENCY PROGRAMMING. ..............0...0.2...2......0... IV.7 INITIALIZATION and LOW-POWER RESET MODE.......................... 2/53 E G5-THOMSON TH MierosLecrronesSTLC7545 TABLE OF CONTENTS (continued) Page Vv CIRCUIT PROGRAMMING .................... 0.2 ...202220 2000020222 e ee eee 23 V4 MODE FIELD..............0.00.0.00 00000000 cee 23 V2 ADDRESS FIELD.............0002000000 02 ee 23 V2.1 RAM Address Field. ..........0..0.000 0000.02 eee 23 V2.2 Transmit Gontrol Register Address Field. .........02.. 0020.00... 0. 0020.0005- 23 V.2.3 Receive Control Register Address Field........... 2... ...002. 000002 e eee eee 24 V3 CONTROL REGISTER DATA FIELD....................0.0.2..002-.020-0--- 24 V3.1 Transmit Gontrol Register Programming ...............0.. 0.0020 ee eee eee ee 24 V3.2 Receive Control Register Programming. .......... 02.0.2... 000. eee eee eee 24 V.3.3 Control Bit Function Summary. ... 2... 2.2 eee 25 V.3.3.1 TXCTRL Word... 2.2.22 0 ee ee eee 25 V.3.3.2 RxCTRL Word ..... 0.222 eee eee 25 VI PROGRAMMABLE FUNCTIONS .......................2.20200-02 00000005: 26 Vid TRANSMIT SECTION 2... ....200000 0.00.00 200.0 022 cee eee 26 VIL Transmit Bit Rate Clock Frequency Programming with FQ=36.864MHz........... 27 VI1.2 Transmit Bit Rate Clock Frequency Programming with FQ=25.8048MHz.......... 27 VL1.3 Transmit Bit Rate Clock Frequency Programming with FQ=18.432MHz........... 28 Vi.1.4 Transmit Bit Clock Frequency Programming. Divisor Rank..................... 29 VL1.5 Transmit Sampling Clock Frequency Programming with FQ=36.864MHz.......... 30 VL1.6 Transmit Sampling Clock Frequency Programming with FQ=25.8048MHz......... 30 VL1.7 Transmit Sampling Clock Frequency Programming with FQ=18.432MHz. ......... 30 V1.1.8 Transmit Sampling Glock Frequency Programming. Divisor Rank................ 31 VIL1.9 Transmit Baud Rate Frequency Programming. Divisor Rank. . Lecce eee ee 31 Vi1.10 Highest Synchronous Transmit Frequency Programming. Divisor Rank Lecce ee eee 31 Vi1.11 Band SplitMode... 0... een eee 31 Vi.1.12 = Transmit Synchronization Signal Programming..................... 0020020505 32 V1I.1.13 Clock Mode Programming & R2 Divisor. ..........000.0 002000 2 eee 32 Vi1.14 Transmit Attenuator Programming....................-.-..-.-.00000200220-- 32 Vi1.15 | Phase Comparator Frequency and Decimation or InterpolationRatio. ............ 32 VI1.16 Phase Shift Frequency.......... 00.000... ce tees 33 Vi.1.17 = Transmit Test Programming. ... 0.20... 0.0.00. 00 ccc eee 33 Vi2 RECEIVE SECTION. .........0.0.0.0.00.0.00.00000000 cece eee 34 VI21 Receive Bit Rate Glock Frequency Programming with FQ=36.864MHz............ 35 ViL2.2 Receive Bit Rate Clock Frequency Programming with FQ=25.8048MHz........... 35 ViL2.3 Receive Bit Rate Clock Frequency Programming with FQ=18.432MHz............ 36 Vi.2.4 Receive Bit Rate Clock Frequency Programming. Divisor Rank ................. 37 ViL2.5 Receive Sampling Clock Frequency Programming with FQ=36.864MHz .......... 38 VI2.6 Receive Sampling Clock Frequency Programming with FQ=25.8048MHz ......... 38 VI2.7 Receive Sampling Clock Frequency Programming with FQ=18.432MHz.......... 38 V12.8 Receive Sampling Clock Frequency Programming. Divisor Rank ................ 39 V1.2.9 Receive Baud Rate Frequency Programming. Divisor Rank .................-.. 39 V1.2.10 Highest Synchronous Transmit Bit Frequency Programming. Divisor Rank. ........ 39 Vi2.11 Receive Fine Phase Shift Programming. ................... 00200000 eee eee 40 VI2.12 Receive Coarse Phase ShiftProgramming ......................-0 00000020 0e 40 VI2.13 InterpolationRatio . 22.2... eee 41 VI.2.14 Receive Test Programming & R2 Divisor....... 0.00.0... 0.002 ee 41 3/53 & GS-THOMSON TH WickozLecrROMIGSSTLC7545 TABLE OF CONTENTS (continued) Page Vil ELECTRICAL SPECIFICATIONS ......................22-.02002000 0002005: 42 VIL ABSOLUTE MAXIMUM RATINGS (referenced ito GND) .....................-. 42 VIL2 DCG CHARACTERISTICS .. 00.2... ee 42 VIL2.1 Power Supply And Common Mode Voltage.............0....0.........0.0005. 42 VIL2.2 Digital Interface... ee eee 42 VIL2.3 Crystal Oscillator Interface (XTAL10,XTALI1})......... 0.2.02... 0200200202 eee 42 VIL2.4 Analog Interface... 2. eee teens 43 VIL3 AC ELECTRICAL SPECIFICATIONS. ..................2220-020002 002020055 44 VIL3.4 Serial Channel Timing ..... 2.20.0... 0000. eee ee 44 Vill TRANSMIT CHARACTERISTICS ................0..2..2 00000 ee ee 45 VII TEST GONDITIONS. .......0..000.000.0.000 0000 02 e eee 45 VIIL2 PERFORMANGE OF THE TX CHAIN. .................2220000 002 eee eee 45 VIIL3 SMOOTHING FILTER TRANSFER CHARACTERISTICS. ...................-. 45 IX RECEIVE CHARACTERISTICS. .......................220 0020002022 e eee eee 46 IX.1 TEST GONDITIONS. ...........00.00.0.00000 0 0c eee eee 46 IX.2 PERFORMANCE OF THE RX CHAIN. ..................0.-.020020002000205- 46 X TYPICAL APPLICATIONS. ....................0.0022 00202 eee 47 X.1 MULTI-STANDARD MODEM WITH ECHO GANCELLING ..................... 47 X.2 LINE INTERFACE ...............0.0. 020.0050 0 cece ee eee 47 X.3 COMMON MODE VOLTAGE GENERATION AND DECOUPLING. .............. 48 X.4 CRYSTALOSCILLATOR..............0.. 20000000000 e cece eee 48 Xl ANNEXE A. ... 2.2222 eee 49 XL IIR FILTEROPERATION...........0...0.0.0.0.00 200000202 e ee eee 49 XI.1.1 COEFFIGIENT ROUNDING. .............0.0.00.0.0.2 0002020202 e eee eee 49 X1L.1.2 DETAILED OPERATION .................000020 00022 eee eee 49 Xll PACKAGE MECHANICAL DATA .................. 2.200200 cee ee eee 52 4/53 E G5-THOMSON TH MierosLecrronesSTLC7545 | - PIN DESCRIPTION 1.1 - PIN CONNECTIONS (Top View) PLOG44 & a Lu i c = a =~ 5 o ake 5S BZZRE BRE Sees AR HGH EX ee o - oe ms $29 3 4 TxD [7 oO 39 [|] AGNDT Txpo []8 381] Vou Fsx [| 9 37 [| AVo5 BCLKx [|] 10 36 [] Raz EYEY [ ] 11 35 [] Rxat DGNDe2 [| 12 34 [7] AGNDR Dpm L] 13 33 [] Voge EveXx [] 14 32 1] Voem AxGLK [|] 15 31 [| RxOCLK (TEST3}) AxHSCLK [] 16 30 [7] EOCMODE (TEST?) RxSYNG [| 17 28 [| NLPR (NRESET) oO n or N oo st w oo he x re - NN iat NN an) Lay Ny N LITJLIWILICICLILCI LIU ew OY ~ yp AY NN oe aa23 69 832455 & emf GA GE EE e = FR 5 = x x e TQFP44 a) a Lu Me Qo & a a s w 3 Ba@a@aeriiezezrage PEP SASSER RE CI if e y +9939 838858 8 & mot]! OQ 33 [] AGNDT TxDO ia 2 32 | Vom Fsx [] 3 at [] Avg5 BCLKX [_] 4 30 [] Rxa2 EvEY []5 297] RxAl DGNDz2 [| 6 28 |] AGNDR DYoy L f 2? | Vacep EYEX U 8 26 | VaeEN RxcLK [] 9 25 |] RxOCLK (TEST3} RxHSCLK [_] 10 24 |] EOCMODE (TESTI) Pxsyne [| 11 23 [] NLPR (NRESET} NX mo + DOD hy Oo HF O Tr WN \ Fr Fr Fr YF YF Fr Fr FN NON / LILILILILILILILILILILI iar] Mw oM < @ Gwy er sagg9283223 cemn kX Oa g & =< Ee eR oO RXR Note : The pin names in the parenthesis are the corresponding for the ST/7544. 5/53 Gi -THOMSGN TH WickozLecrROMIGS 7545-01.EPS 7545-01.EPSSTLC7545 | - PIN DESCRIPTION (continued) 1.2 - PIN LIST PQFP | PLCC NAME DESCRIPTION 39 1 DGND1 Digital Ground (OV) 40 2 DVpp1 Positive Digital Power Supply (3.15V to 5.25V) 41 3 BCLKR Receive bit Clock Output 42 4 FSR Receive Frame Synchronization Output 43 5 RxDO Receive Serial Data Output 44 6 RxDI Receive Serial Data Input 1 7 TxD] Transmit Serial Data Input 2 8 TxDO Transmit Serial Data Output 3 9 FSX Transmit Frame Synchronization Output 4 10 BCLKX Transmit Bit Clock Output 5 11 EYEY 8 bit Y D/AC Output for Eye Pattern display 6 12 DGND2 Digital Ground (OV) 7 13 DVpp2 Positive Digital Power Supply (3.15V to 5.25V) 8 14 EYEX 8bit X D/AC Output for Eye Pattern display 9 15 RxGLk Receive Bit Rate Clock Cutput 10 16 RxHSCLK | Receive Highest Clock Output 11 17 RxSYNC | Receive Synchronization Pulse Output le 18 RxRCGLK Receive Baud Rate Clock Output 13 19 TxXRCLK | Transmit Baud Rate Clock Output 14 20 TxSYNC | Transmit Synchronous Pulse Output 15 21 TxHSCLK | Transmit Highest Clock Cutput 16 22 TxGLK Transmit Bit Rate Clock Output 17 23 DGND3 Digital Ground (OV) 18 24 DVpp3 Positive Digital Power Supply (3.15V to 5.25V) 19 25 TxSCLK | Transmit Synchronization Clock Input 20 26 XTAL2 Crystal Output 21 27 XTAL10 External Clock/Crystal Input 1 22 28 XTAL11 External Clock/Crystal Input 2 23 29 NLPR Low Power Reset Input 24 30 EOCMODE | External Oversampling Clock Mode Input. Must be tied to DGND in either the (TEST1) STLG7545 normal mode or the 7544 mode. 25 31 RxOCLK | Receive Oversampling Clock Input. Qutput high-impedance in normal mode. (TEST3) 26 32 VREFN 16 bit D/AC and A/DC Negative Reference Voltage 27 33 VREFP 16 bit D/AC and A/DC Positive Reference Voltage 28 34 AGNDR Analog Ground (OV) 29 35 RxA1 Receive Positive Analog Input 30 36 RxA2 Receive Negative Analog Input 31 37 AVop Positive Analog Power Supply (+5V1+5%) 32 38 Vom Common Mode Voltage Output (2.5V +10%) 33 39 AGNDT Analog ground (OV) 34 40 TxA1 Smeoothing filter positive Output 35 41 TxA2 Smeoothing filter negative Output 36 42 TxOCLK | Transmit Oversampling Clock Inout. Output high-impedance in normal mode. (TEST2) 37 43 BFRS Bit Frame Rate Select Input 38 44 SSIM Serial Synchronous Interface Mode Input Note : The pin names in brackets are the corresponding names for the ST/544. 6/53 E G5-THOMSON TH MierosLecrronesSTLC7545 | - PIN DESCRIPTION (continued) 1.3 - PIN FUNCTION 1.3.1 - Power Supply (9 Pins) Analog Vpp Supply (AVpp) This pin is the positive analog power supply (+5V+5%) for the Transmit and the Receive sec- tions. It is net internally connected to digital Vop supply (BDVpp1-3). Digital Vpp Supply (DVb01,DVop2,D Vpps) These pins are the positive digital power supply (3.5V to 5.25V) for Transmit and Receive digital internal circuitry. Analog Ground (AGNDT,AGNDR) These pins are the analog ground return of the analog Transmit (Receive) section. Digital Ground (DGND1,DGNDB2,DGND3) These pins are the ground connections for Trans- mit and Receive internal digital circuitry. Note 1: To obtain published performance, the analog Vop and Digital Voo should be decoupled with respect to AGND and DGND, respectively. The decoupling is intended to isolate digital noise from the analog section; decoupling capacitors should be asclose as possible totherespective analog and digital supply pins. Note 2: All the ground pins must be tied together. In the following section, the ground and supply pins are refered to as GND and Vop, respectively. 1.3.2 - Clock and Control Signals (16 Pins) External Clock/Crystal Inputs (XTAL10, XTAL1 1) XTAL10 and XTAL11 inputs must be tied to exter- nal crystal(s) or external clock(s). These inputs are selected from the TxCtrl register. The maximum clock rate is 38MHz. XTAL1Ois the default External Clock/Crystal input. It is mandatory to shortcircuit XTAL10 and XTAL11 when asingle external crystal or clock generator is used. The nominal master clock frequency is 36.864MHz (this frequency and the frequency 25.8048MHz are well suited for the V.34 application) but the onchip amplifier is de- signed for a parrallel crystal oscillator with a fre- quency equal to 18.432MHz. The other master clocks frequencies (18.432MHz, 25.8048MHzand 29.4912MHz) are well suited for the well Known CCITT recommendations (V.21 through V.32bis). Crystal Outputs (XTAL2) This output is to be tied to one or two external crystals (see Figure 1). If an external clock is used, XTAL2 should be left open circuit. Low power and Reset Input (NLPR) This pin , when low, synchronizes the STLC7545 clock system and puts it in low power mode. NLPR pin must be tied to Vop during normal operation. GS-THOMSON TH WickozLecrROMIGS Access to the chip is disabled during power-on reset until the clock oscillator starts. The reset time duration can be increased by connecting the NLPR input to an external RC network (see Figure 9). The Low-Power Reset Mode is activated when this pin is tied to GND (Operation of all clocks and the analog section is stopped). Transmit Synchronization Clock Input (TxSCLK) This pin can be connected to an external terminal clock to phase-lock the internal transmit clocks. It can be disabled under software control to allow the Tx DPLL to free run or phase lock on the Rx clock system. To phase lock the TxDPLL there must be transition on TxSGLK input within FCOMP period when programming TxGR2 register. Transmit Bit Rate Clock Output (TxCLk) This pin outputs the synchronous transmit bit clock selected for the MODEM. Transmit Baud Rate Clock Output (TxRCLK) This pin, when the bit D4 within receive register RxGR3 is set to 0, outputs the synchronaus trans- mit baud rate clock (initial state). When bit D4 is set to 1 this pin outputs the frequency comparison signal FCOMP (used by the TxDPLL in both 7544 mode and V.Fast synchronization) when bit 0 of RxCR1 is set to 0 this output is disabled. Transmit Synchronization Pulse Output (TxSYNC) This pin outputs the synchronization transmit reset pulse when a softresetis applied to the STLG7545. Combined with TXHSCLK clock it can be used to externally provide any synchronous transmit clock. Transmit Highest Clock Output (TxHSCLK) This pin outputs the highest synchronous transmit clock to provide any external or multiplexing clock when bit 0 of RxGR1 is set to 0 this output is disabled. Transmit Oversampling Clock input (TxOCLK) This input can be connected to an external clock to provide the chip with the aver-sampling clock, de- pending on the External Gver sampling Mode input (EQCMODE). In nermal mode this pin should be static (tied to GND or Vpp). Receive Bit Rate Clock Output (RxCLK) This pin outputs the synchronous receive bit clock selected for the MODEM. Receive Baud Rate Clock Output (RxRCLK) This pin outputs the synchronous Receive baud rate clock when bit Oof RxCR1 is set to 0 this output is disabled. 7/53STLC7545 | - PIN DESCRIPTION (continued) Receive Synchronization Pulse Output (RxSYNC) This pin outputs the synchronization receive reset pulse when a softresetis applied tothe STLC7545. Combined with RxHSCLK clock it can be used to externally provide any synchronous receive clock. Receive Highest Clock Output (RxHSCLK) This pin outputs the highest synchronous receive clock to give any external or multiplexing clock when bit 0 of RxCR1 is set to O this output is disabled. Receive Oversampling Clock input (RxOCLK) This input can be connected to an external clock to provide the chip with the oversampling clock, de- pending on the External Qver sampling Made input Pin (EQGMODE). In normal mode this pin should be static (tied to GND or Vpp). External Oversampling Clock Mode (EQCMODE) This pinis used for selecting one ofthe two possible oversampling modes. When EOQCMODE is tied to GND, all the clock are provided internally (mode compatible with the 817544). When EOQCMOLDE is tied to Vpp, the eversampling clocks must be input on TxOCLK and RxOCLK pins. The TxHSCLK (RxHSCLK) and TxSync (RxSync) signals along with external fractional divider can be used to pro- vide the oversampling clocks to the STLG7545. 1.3.3 - Synchronous Serial Interfaces (SSIA,SSIB) (10 pins} Serial Synchronous Interface Mode input (SSIM) This input activates one or both serial interfaces. When SSIM is tied to Vpp, both A and B ports are functional : port A (SSIA) is dedicated to the Trans- mit channel and port B (SSIB) is dedicated to the Receive channel. When SSIM Is tied to GND only port A (SSIA) is selected. In this case SSIA carries both Tx and Rx Signals and EYE pattern. Bit Frame Rate Select input (BFRS) This input selects one of the twe possible bit tre- quencies for the BCLKX and BCLKR clocks. When BFRS is tied to Vpp the BCLKX (BGLKR) frequen- cies are equals to the oversampling ratio (divider V Table 40) times the FSX (FSR) frequencies. When BFRS is tied to GND, BCLKX (BCLKR} frequencies are equal to V/2 times the FSX (FSR) frequencies. Frame Synchronization Transmit output (FSX) This output clock is the Transmit Frame synchreni- zation pulse signal of the SSIA port which has 8/53 Kr SSS:THOMson MICROELECTRONICS nominal frequency equal to the transmit sampling frequency. This pulse indicates the beginning of the 16-bit serial words on the serial data input/output port A. Bit Clock Transmit output (BCLKX) This output pin provides the serial bit clock for the SSI port A. The BCLKX frequency equals V or V/2 times the Transmit sampling frequency, depending on the Bit Frame Select Input (BFRS). Serial Data Transmit input (TxD) This input receives word-oriented serial data. Data is loaded fram TxDI into the Transmit Shift Register (TSRIN) on the falling edge of BCLKX and trans- fered tothe Transmit Butfer Register (TBRIN} when a complete 16 bit word has been received. Data is assumed to be received MSB Tirst. Serial Data Transmit output (TxDO) This output sends word-oriented serial data. The 16 bit Data Word loaded in the Transmit Buffer Register (TBROUT) is transtered to the Transmit shift Register (TSROUT) and clocked out of TSROUT on the rising edge of BCLKX. Serial words are transmitted MSB first. Receive Frame Synchronization output (FSR) This output clock is the Receive Frame synchroni- zation pulse signal of SSI port B which has tre- quency equal to the receive sampling frequency. This pulse is used to indicate the beginning of serial words on the serial data input/output port B. Receive Bit Clock output (BCLKR) This output pin provides the serial bit clock for the SSI port B. The BCLKR frequency is V times or (V/2) times, selected by BFRS ) the receive sam- pling frequency. Receive Serial Data input (RxDI) This input receives word-oriented serial data. Data is clocked from RxDlinto the Receive Shift Register (RSRIN) on the falling edge of BCLKR and trans- fered to the Receive Butter Register (RBRIN} when a complete 16-bit word has been received. Data is assumed to be received MSB Tirst. Receive Serial Data output (RxDO} This output sends word-oriented serial data. The 16-bit Data Word loaded in the Receive Buffer Register (RBROUT) is transtered to the Receive Shift Register (RSROUT) and clocked out of RSROUT on the rising edge of BCLKR. Serial words are transmitted MSB first.STLC7545 | - PIN DESCRIPTION (continued) 1.3.4 - Analog Interface (9 pins} D/AC and A/DC Positive Reference Voltage out- put (VreFP) This pin provides the Positive Reference Voltage used by the 16-bit converters. The reference volt- age, Vrer, is the voltage difference between the Vrerp and VReEFN outputs, and its nominal value is 2.5V. Vrerp should be externally decoupled with respect to Vcm (see Figure 17). D/AC and A/DC Negative Reference Voltage (VREFN) This pin provides the Negative Reference Voltage used by the 16 bit converters, and should be exter- nally decoupled with respect to Vom. Common Mode Voltage Output (Vcm) This output pin is the common mode Voltage (AVpp-AGND)2 internally generated. This output must be decoupled with respect to AGND. This output pin could be forced externally (compatible with 817544 application). Smoothing filter positive Output (TxA1} This pin is the positive output ofthe fully ditferential analog smoothing filter. Smoothing filter negative Output (TxA2) This pinis the negative output ofthe fullyditferential analog smoothing single pole switch capacitor fil- ter. Outputs TxA1 and TxA2 provide analog signals GS-THOMSON TH WickozLecrROMIGS with maximum peak to peak amplitude 2 x VReF, and must be followed by an external continuous time two pole smoothing filter (see Figure 16). The smoothing filter order depends of the acceptable transmit signal spectrum on the line. The cut-oft frequency of the external filter must be greater than two times the transmit sampling frequency (Fsx}, so that the combined frequency response of both the internal and external filters is flat in the pass band. Receive Positive Analog Input (RxA1) This pin is the differential positive A/DC Input. Receive Negative Analog Input (RxA2} This pin is the differential negative A/DC Input. These analog inputs (RxA1,RxA2) are presented to the SigmaDelta modulator, the analog input peak to peak signal range must be less than 2 x VREF, and must be preceeded by an external continucus- time single pole anti-aliasing filter (see Figure 16). The cut-off frequency of the filter must be lower than one haltthe transmit over-sampling frequency (TxOSCK). These filters should be set as close as possible to the RxA1 (RxA2} pins. D/AC output for Eye Pattern (EYEX,EYEY) These pins are the outputs of two 8-bit digital to analog converters used to monitor, on a CRT, the X and Y quadrature signals of the eye pattern of the demodulated signal. 9/53STLC7545 ll - BLOCK DIAGRAM Figure 1 : General Block Diagram B Synchronous Serial Port A (SSIA) Port B (SSIB) Synchronous Senal Dpn1 DYppa DYpp3 FSX CLEX TxDI TxDO SSIM BFRS (FSR) BCLER) (RxDD) (RxDO) DGND1 DGND2 DGND3 Vy ft + CONTROL REGISTERS w Mw [] a bal ie) pea] - wo owol 2 5 O M4 + 4 g 2 35/8 n$42g6 Ss 2 @ 8 o 26 S4HHs8 2 EES zZ 6 & & & Bw x om mw em ew Tx & Rx DPLLCLOCK GENERATORS [| -_ S WITCH - Tx FILTER CAPACITOR LU 16 bits & LPF & DIAC p| ATTENUATOR 1 aA (12+1) bits | coefficients REFERENCE T VOLTAGE | i > DIGITAL INTER FACE Rx FILTER - + 16 bits & A/DC _ wy D7:D0 [isis > DIGITAL B DIAC | RECONSTRUCTION 16 bits FILTER 16 bits 8 DAC | D15:D8 J App AGNDT TxAl TxA2 Ve EFP Ve EEN RxAlL RxA2 EYEX EYEY AGNDR 10/53 ST GS-THOMSON MICROELECTRONICS 7545-03.EPSlll - FUNCTIONAL DESCRIPTION Ill.1 - SIGNAL TRANSFER BLOCK DIAGRAM The STLC7545 Block Diagram illustrates three paths as follows : The Transmit D/A Section, the Receive A/D section and the Receive Reconstruction section. Figure 2 : Signal Transter Block Diagram STLC7545 TxDO ~ BCLEKX @ j SSIA Secial/Pavallel < 16-bit data bus synchronized to the Tx clock system Fsx sg ] Conversion TxDI om Jb V7 A A ResSig | RxTx | TaSig Fsx Txoclk | Fsx Fsx Fsx ] _rH] taPexy | Ee es Le ee ee Status | RxS1 | | RxS2 | or 5 x Fsx or 5 x Fsx or 5 x Fsx i fl or 6 x Fsx or 6 x Fsx Selector Txoclk PIR3 Txoclk Txoclk FIRI FT 4 Txoclk I Txoclk = 128 Fsx 81 Control or 160 x Fsx Txoclk WH] Logic or 192 x Fsx Fsr Fscs yne - amiss Input am Output FerSyne (Rx Signal + Echo) (Tx Signal) SSIM RxDO v BCLKR q 4 SSIB Fer <f 4 Gai data bus synchronized to the Rx clock system 2 RxDI = Cr] Note : Register 16-bit data bus Tx} 3 4 A ped vith Tristate Output 11/53 & GS-THOMSON TH WickozLecrROMIGS 7645-04.EPSSTLC7545 lll - FUNCTIONAL DESCRIPTION (continued) Ill.2 - TRANSMIT D/A SECTION The functions included in the Tx D/A section are detailed hereafter. IIl.2.1 - Interpolation Filters The oversampling is performed by two cascaded digital interpolating filters : IIR1 and FIR1. The IIR1 and FIR1 filters are sampled at 4 x Fsx and 128 x Fsx (5 x Fsx and 160 x Fsx} (6 Fsx and 192 x Fsx), respectively. 111.2.1.1- Programmable Interpolation Filter (1IR1) IIR1 is an infinite impulse response interpolating filter. The purpose of this digital filter is to interpolate 4-times (5 times, 6 times) the digital signal coming fram the DSP. This filter is sampled at the basic sampling frequency, (e.g. 9600 x 4 Hz), and must exhibit, asa minimum, a low-pass section which is mandatory to remove replicas above half the sam- pling frequency (e.g. 4800Hz) (see Figure 13). The digital samples are encoded in 16-bit twos complement format. The IIRi1 filter is a cascade of seven biquads (see Figure Ai}. The filter coefficients are loaded into the associated RAM (38 x 13). Each coetticientis coded into 12bits and can be doubled by virtue of an extra bit. All 38 coefficients have to be loaded to implement an IIR transfer function (see An- nexe A). This filter has been made programmable to offer each user the possibility to add filtering charac- teristics, e.g. high-pass section or equalization, matched to a particular application. I.2.1.2 - FIR Filter (FIR1) FIR1 is a finite impulse response interpolating filter. lis input sampling frequency is 4 x Fsx (or 5 x Fsx) (or 6 x Fsx) and its interpolation ratio is 32. The 2 transfer function of this FIR is : 3 ~32 H(z) = 1-Z 32(1-z ) with Z = exp 2xF/Txoclk) and Txoclk = 128 (160, 192) x Fsx 12/53 E G5-THOMSON TH MierosLecrrones Ill.2.2 - D/A Converter The 128-times (160 times, 192 times) oversampled D/A converter includes asecond order digital noise shaper, a one bit D/A converter and a single pole analog low-pass filter. The gain of the last output silage can be pregrammed to OdB,-6dB or infinite attenuation. The cut-off frequency of the single pole switch-capacitor low-pass filter is : fe-3dB=Txoclk /(2 x 7 x 10) where Txoclk = 128 (160, 192} x Fsx Continuous-time filtering of the analog differential output is necessary using an off-chip amplifier and a few external passive components (see Fig- ure 16). At least 86dB signal to noise plus distortion ratio can be obtained in the frequency band 300- 3400Hz, with a -6dBr output signal. lll.3 - RECEIVE A/D SECTION The different functions included in the Rx A/D section are detailed hereafter. The format used at the digital interfaces of the Rx channel is two's complement encoded 16-bit. 11.3.1 - A/D Converter The 128 (160, 192) oversampled A/D converter is based on a second order sigma-delta modulator. The signal to noise plus distortion ratio obtained for a signal spectrum limited to the 300-3400Hz tele- phone band, is typically 86dB with a -6dBr input signal. IlI.3.2 - Decimation Filters The 128 (160, 192) decimation is performed by two interpolatingdigital filters : FIR2 and IIR2, which are sampled at 128 x Fsx and 4 x Fsx (160 x Fsx and 5 x Fsx) (192x Fsx and 6 x Fsx), respectively. 1.3.2.1 - FIR Filter (FIR2) FIR2 is a finite impulse response decimating filter. lis sampling frequency is 128 x Fsx (or 160 x Fsx or 192 x Fsx) and itsdecimation ratio is 32. The Z transter function of this FIR is : 3 -32 He-| Stan 32(1-z ) with Z = exp (j2nF/Txoclk) and Txoclk= 128 (160, 192) x FsxSTLC7545 lll - FUNCTIONAL DESCRIPTION (continued) I1.3.2.2- Programmable Decimation Filter (IIR2) IIR2is an intinite impulse response filter. It provides the low-pass filtering needed to remove the noise remaining above half the sampling trequency (e.g. 4800Hz) (see Figure 14). The output of the IIR2, RxTx, will be processed by the DSP. In "band split? mode (see Table 21), RxTx becomes the input signal to IIR3. The RxTx will always be avail- able on serial interface (SSIA in Figure 2). The IIR@ filter is a cascade of seven biquads. The fitter coefficients are loaded into the associated RAM (38 x 13). The filter transter function has been made pro- grammable in order to meet specific requirements. The sampling frequency is 4-times (5-times, 6- times) the down-sampling frequency selected for the Tx section (e.g. 9600 x 4Hz). To support echo cancelling applications the clocks used for the A/D converter and the decimation fitters are synchronized on the Tx system clock, i.e. on the Tx rate. It must be pointed out that using a single clock system in A/D and D/A conversions is important for reducing induced noise. The 12+1 bit filter coefficients are loaded into the internal RAM2 and must be loaded from the serial bus. All 38 coefficients have to be loaded to imple- ment an IIR transfer function. IlI.3.3 - Eye-diagram Display Two 8-bit digital to analog converters are provided to monitor, on a CRT, the X and Y quadrature signals of the eye pattern related to the demodu- lated signal. The format of the data input is MSB first, 8-bit twos complement, and most significant byte for EYEY sample and least significant byte tor the EYEX sample. The reference voltage of these two converters is the power supply voliage Vop. The EYE pattern can be monitored on one or two Synchronous Serial Interface mode. Ill.4- RECEIVE RECONSTRUCTION SECTION As the Rx channel sampling is synchronized to the Tx system clock, it is necessary to reconstruct the Rx signal in order to get samples synchronized to the Rx symbol rate recovered in the demodulator. The function of the reconstruction filter (IIR3 and FIR3) is to oversample by 128 x Fsx (160 x Fsx, GS-THOMSON TH WickozLecrROMIGS 192 x Fsx) the receive signal (ResSig) comming from the DSP after echo cancellation. The over- sampled signal is then down-sampled at Fsr rate to make it available to the DSP as RxSig at SSIB or Rx$1/RxS2 at SSIA (see section IV.1 and IV.2). The down sampling precess does not introduce significant error. The transfer function of the first section of the reconstruction filter is programmable in the same way as the Tx and Rx IIR filters previously de- scribed. Ill.4.1 - Programmable Interpolation Filter (IIR3) IIR3 is an infinite impulse response interpolating filter. The purpose of this digital filter is to interpolate 4-times (5-times, 6-times) the digital signal fram the DSP. This filter is sampled at 4-times (5-times, 6-times) the basic sampling frequency, (e.g. 9600 x 4Hz). The digital samples are encoded in 16-bit two's complement format. The IIR3 filter is a cascade of seven biquads. The filter coetficients are loaded into the associated RAM (38 x 13). Each coefficient is coded into 12 bits and can be doubled by virtue of an extra bit. All 38 coefficients have to be loaded to implement an IIR transfer function. This filter has been made programmable to offer each user the possibility to add filtering charac- teristics, e.g. highpass section or equalization, matched to a particular application. For example, in a band-split MODEM application, the first section can be a wide channel band-pass filter (allowing the DSP to supervise boundary audio tones) and the second section can be dedi- cated to high band and low band splitting. 11.4.2 - FIR Filter (FIRS) FIR3 is a finite impulse response interpolating filter. lis input sampling frequency is 4 x Fsx (5 x Fsx), (6x Fsx) and the interpolation ratio is 32. The Z transfer function of this FIR is : 3 {7% H(z) =| > 8) sen | with Z = exp (2aF/Txoclk) and Txoclk = 128 (160, 192) x Fsx 13/53STLC7545 lll - FUNCTIONAL DESCRIPTION (continued) IlI.5 - CLOCK GENERATION Master clock is obtained from either a crystal tied between pins XTAL10 (or XTAL11) and XTAL2 or from an external signal connected to the XTAL10 (or XTAL11) pin, in the latter case, the XTAL2 pin should be lett open circuit. Two external crystals (or two external master clack signals), software selectable one at a time, can be used to cope with complex applications. It is man- datory to shortcircuit XTAL10 and XTAL11 whena single external crystal or clock generator is used. The crystal selection is done by bit D13 (QS) in TxCTRL word of the serial interface A. Setting QS to O select the XTAL11 input and TxGLK =FQ/(NxRx Sx Tx CS) with CS = 8. Setting QS to 1 select the XTAL10 Input and TxGLK = FQ/ (Nx Rx& x T x C8) with CS = 16. To insure the start-up of the STLC7545, the XTAL10 input must always be tied to a crystal or an external clock signal, as that pin is automatically selected when powering-on the device. The ditferent transmit (Tx} and Receive (Rx) clocks are obtained by master clock frequency division in several programmable counters. The Tx and Rx clocks can be synchronized on external signals by performing phase shifts in the frequency division process (equivalent to adding or suppressing mas- ter clock transitions at the counter inputs). Two independantdigital phase locked loops (DPLL) are Table 1 : Listof usual frequency available implemented using this principle , one for Tx and one for Rx. Two clock modes are available, selected by the External Qversampling Clock Mode input pin (EQCMODE). When the EQCMODE pin is tied to the GND the internal clock mode is selected. In this mode all the clock are generated internally. When the EOQCMODE pin is tied to Vpp, the External Oversampling Clock Made is selected. In external oversampling clock mode, the user must provide the chip with the oversampling fre- quency Knowing the interpolation and the decima- tion ratios selected in the TxCR3 and RxCR3 register. It can be provided from the highest syn- chronous clock (TXHSCLK and RxHSCLK) using an external divider. In any case, the user will have to comply with the relation : Crystal frequency FQ must be greater than 470 x 4 x Fsx with an over- sampling ratio of 128 or than 470 x 5 x Fsx with an oversampling ratio of 160 or than470x 6 x Fsx with an oversampling ratio of 192. Several values can be chosen for the master clack frequency. The four frequencies given in table 1 are of particular interest, as they are compatible with standard Modem frequencies. Note : In the remainder of the datasheet, unless otherwise indicated, 36.864MHz will be considered as the nominal master clock frequency. Tha maximum master clock fraquency is 38MHz. Frecuency Symbol Rate Frequency Bit Rate (bps) Sampling (bps) FQ (MHz) Fbaud (baud) Fsx, Fsr (Hz) (1) 18.432 (2) 600, 1200, 1600, 2400 All up to 19200 3,4,5,6,8,12 or 16 times Fbaud 25.8048 600, 1200, 1600, 2400, 2800 All up to 28800 3,4,5,6,8,12 or 16 times Fbaud 29.4912 (2) 600, 1200, 1600, 2400 Allup to 19200 | 3,4,5,6,8,12 or 16 times Foaud 36.864 (3) 600, 1200, 1600, 2400, 2560, 2743, 2954, All up to 38400 3,4,5,6,8,12 or 16 times Foaud 3000, 3200, 3429, 3491 Notes: 1. Depending on the symbol rate frequency 2. 7544 like 3. This crystal frequency provides all the symbol rates satisfying the relation : Symbol rate = (2400 x 16VK with K = (16, 15, 14, 13, 12, 11) Symbol rate = (2400 x 8K with K = (8, 7,6) Symbol rate = (2400 x 10K with K = (8, 7) 14/53 E G5-THOMSON TH MierosLecrronesSTLC7545 lll - FUNCTIONAL DESCRIPTION (continued) 11.5.1 - Transmit DPLL Frequency control of the Tx cleck system (Fig- ure 10) is obtained by performing additional up or down counting steps in the three input dividers M, N and P. These elementary phase shifts of one master clock period are repeated at either the rate of the Fsx clock, or half that rate, depending on the required capture and tracking ranges (see Table 15 and 26). The average updated frequency then varies be- tween the following limits : FQ - FSHIFT < Faverage < FQ + FSHIFT Where FQ is the master clock frequency and FSHIFT equals Fsx or Fsx/2 (see table 26). The TxDPLL phase comparison which determines lead or lag decisions, is simply obtained by sam- pling the synchronization clock, TxSGLK or RxCLK, on the falling edges of an internal clock taken from the division chain, FCOMP (see table 25). FCOMP frequency must be an integer submultiple of the synchronization clock. This frequency determines the Tx jitter magnitude. In V.34 synchronization mode FCOMP is equal to 2400Hz, and in 7544 mode the synchronization clock FGOMP can be chosen tebe equal to the baud rate frequency. Only phase shifts of the same sense (lead or lag) are performed during each FCOMP period. The actual phase shifts during FCOMP period are given by the ratio FSHIFT/FCOMP These phase shifts are performed at the inputs of the M,N, and P dividers to lock the DPLL to the synchronisation signal (see Table 22). If there is no transition on TxSCLK Pin, the Tx DPLL is free running. To phase lock the TxDPLL there must be transis- tion on TxSCLK input within FCOMP peried when programming TxCR2 register. The Tx clock system may also run treely without any phase shift. In this case, the TxSCLK input is no longer active. The DPLL capture and tracking range equals +FSHIFT/FQ. They have to be greater than + 200ppm to comply with GCITT recommenda- tions. FSHIFT = Fsx/2 minimizes the jitter. Because of this, there is a trade-off between higher capture and tracking ranges and lower jitter. Ex : FQ = 36.864MHz and FSHIFT = 9600Hz. Capture and tracking range =+ FSHIFT/FQ = + 9600Hz/36.864MHz= + 260ppm GS-THOMSON TH WickozLecrROMIGS 11.5.2. Transmit Clocks 1.5.2.1 - Internal Mode The internal clock mode is selected when the pin EQCMODE is tied to GND. In this mode the STLG7545 provides three Tx programmable syn- chronous modem clocks : - a transmit bit rate clock TxCLK - a transmit baud rate clock TxRCLK - a transmit highest synchronous clock TxHSCLK, associated with the TxSYNC synchronization pulse, useful te generate additional clocks (e.g. extra divisors) if needed. The outputs of the TxRGLK and TxHSGLK clocks, can be disabled when not used, but in 7544 syn- chronisation mode a correct baud rate frequency must be programmed as the FCOMP clock tre- quency depends on it. The Tx clock system provides the sampling and oversampling clocks as well as the bit and synchro clocks (BGLKX and FSX) used by the serial inter- face A (SSI-A} described in section IV. The counters of the Tx clock system (Figure 10) are automatically reset when powering-on the STLG7545 and when the NLPR input level is low. They can also be reset, under software control, during the following conditions : (1) on the next falling edge of the TXSCLK terminal clock or of the RxCLK receive bit rate clock (SST bit Table 22). (2) on the next falling edge of the TxRCLK transmit baud rate clock (baud chain clock reset) and in the next falling edge of FCOMP (bit chain clocks) when TxCRO, TxCR2 or TxCR3 register is accessed. The case (1) gives the capability to speed-up the Tx DPLL synchronization; the case (2) is useful to tix the phase of the bit rate clock with respect to the baud rate clock, in particular after each modification of the bit or baud rate value. The internally generated pulse resetting the Tx counters is output at the TxSYNG pin in order to synchronize external functions using the TXHSCLK clock. Ill.5.2.2 - External Mode The external clock mode is selected when the pin EQCGMODE is tied tothe Vpp. Inthis mode the user must provide the STLG7545 with the transmit over- sampling clock. The internal DPLL can be used if the external transmit oversampling clock is gener- ated by a divider synchronized by both the TxHSCLK and TxSync signals. 15/53STLC7545 lll - FUNCTIONAL DESCRIPTION (continued) I11.5.3- Receive DPLL The synchronization of the Rx counters delivering the Rx clocks (Figure 11) is performed by addition or suppression of master clock periods under DSP control. Inthis case, the phase comparison function of the RxDPLL is implemented in the associated DSP recovering the received symbols. Two types of phase shift control are provided inthe STLO7545 : - a coarse phase lag of programmable magnitude, obtained from the suppression of 64 to 4096 successive master clock transitions. This control is to be used to reduce the RxDPLL locking time. a fine phase lead or lag of programmable magni- tude (i.e. 8 to 32 master clock periods or one Tx oversampling clock period) continuouslyused to implement the phase controlloop. (see Table 38). Each elementary phase shitt, correspondingto an addition or a subtraction of one master clock transition, is synchronized on an internal clock with frequency equal to the Rxoclk (128, 160 or 192 times the Rx sampling frequency Fsr}. A phase shift is therefore, always completed in less than one Fsr period. IlI.5.4- Receive Clocks II1.5.4,1- Internal Mode The internal clock mode is selected when the pin EQCMODE is tied to GND. In this mode the STLG7545 provides three Rx synchronous pro- grammable modem clocks : - receive bit rate clock RxCLK - receive baud-rate clock RXRGLK - receive highest synchronous clock, RxHSCLK associated with the RxSYNC synchronization pulse useful te generate additional clocks The RxRGLK and RxHSCLK outputs can be dis- abled when not usec. The bit rate clock frequency of the Rx modem can be chosen to be cifferent from its Tx counterpart, provided Rx to Tx loopback is not required. The Rx clock system also provides the Rx sampling clock as well as the bitand synchro clocks (BCLKR and FSR) used by the serial inter- tace B (SSI-B) described in section IV. The digital reconstruction filter implemented in the STLG7545 makes possible the choice of a receive nominal sampling frequency citferent from the transmit nominal sampling frequency. The counters of the Rx clock system (Figure 11) are reset when pow- ering on the STLG7545 and when the NLPR input level is low. They can also be reset, under sottware control, on the next falling edge of the RxRCLK receive baud rate clock when the RxCRO, RxCR1 or RxCR3 register are accessed : this feature is used to fix the phase of the bit rate clock with respect to the baud rate clock, e.g. after each modification of the bit or baud rate value. The 16/53 E G5-THOMSON TH MierosLecrrones internally generated pulse resetting the Rx count- ers is outputat the RxSYNC pin in order to be used with the RxHSCLK clock. 111.5.4.2 - External Mode The external clock mode is selected when the pin EQCGMODE is tied the Vpp. In this mode the user must provide the STLG7545 with the receive over- sampling clock. The internal DPLL can be used if the external receive oversampling clock is gener- ated by a divider synchronized by both the RxHSCLK and RxSync signals. 1.6 - SERIAL INPUT/OUTPUT SYNCHRONOUS INTERFACES The STLG7545 has two Synchronous Serial Inter- faces ports, SSIA and SSIB. They allow inde- pendent transmit and receive paths. Through the two serial ports, the STLC7545 can talk to various digital signal processors. The various serial inter- face signals and internal registers are given below : SSIPORT A (SSIA) - Transmit Frame Synchronization output (FSX) - Transmit Bit clock output (BCLKX) - Transmit Serial Data input (TxD) - Transmitinput Shift Register (TSRIN) - Transmitinput Buffer Register (TBRIN) - Transmit output Shift Register (TSROUT) - Transmit Serial Data output (TxDO) SSI PORT B (SSIB) - Receive Frame Synchronization output (FSR) - Receive Bit clock output (BCLKR) - Receive Serial Data input (RxDI) - Receive input Shitt Register (RSRIN) - Receive input Butter Register (RBRIN) - Receive output Shift Register (RSROUT) - Receive Serial Data output (RxDBO) INPUT MODES - Synchronous Serial Interface Mode (SSIM} - Bit Frame Rate Select (BFRS) With SSIM input, the user can choose either single interface mode or dual interface mode. In single interface mode (section IV.2), only port SSIA is operational. Where as in dual interface mode (sec- tion IV.1), both SSIA and SSIB ports are opera- tional. These two ports carry data inside a synchronous frame consisting of four/five or eight/ten sixteen bit time slots (only the four first time slots are used for transporting information. SSIA port is synchronous to the Tx system clock and SSIB port is synchronous to Rx system clock. The format of the signal samples carried on these portis two's complementwith MSB sentor received tirst. As explained hereafter itis also possible to use the port A only to transfer the data between the STLC7545 and the associated DSP.STLC7545 Ill - FUNCTIONAL DESCRIPTION (continued) IlI.6.1 - Tx Clock Related Registers Figure 3 : Tx Clocks Related Registers TxOCLK _ 7 16 bits TSROUT }aa 7 $SIM = Clock 7 (1241) bit Coett BFRS Generator 7 RAM es yyy s 16 bits f. in TxDI rsx BCLKX WClkx 7 TxCtl == Et TxG Ro 16 bits 18bits | 16 bits TSRIN =|} [4 ss TBRIN 7 we 7 ad TxSig a F F jp 8 bbls Ressig BCLKX WCIkx Fe o [ = 16 bits AxCrl f > f Eye Pattern a FxRCO S 5 __ fF = SsIM BCLKX WCIkx S = wo @ 16 bit Y y 3 [=< ZA "s FRixTx x oO CG 3 wo (124143) bit |] Coeff RAM 7 + Status TxDO <! 16 bits gl st 16 bit i FxS2 IlI.6.2 - Rx Clock Related Registers Figure 4 : Rx Clocks Related Registers RxOCLK _ SSIM | Glock BFRS gs Generator RxDI ist BCLKR WClkr 716 bits | _f1ehis RxCirl = |} Rx RCO som __t = s w a a oO 3 oO = 16 bits r RSRIN 7 | RBRIN [4 2 8 bit 2 fa | | EVEX A 4 8 , 7 16 bits BCLKR WOlkr 5 8 bits 4A} EVEY Cc BCLKR WClkr & ty z a 2 5 16 bit 16 bit RSROUT [ae 7 = SL A oresssig 2 xo 1 17/53 GS-THOMSON TH WickozLecrROMIGS 7545-05.EPS 7B45-06.EPSSTLC7545 IV - SERIAL INTERFACE OPERATION Serial data transmission (reception) is initiated by a frame synchro signal FSX (FSR). The Data is clocked from TxDI (RxDI} into TSRIN (RSRIN) on the falling edge of BCLKX (BCLKR)} and transfered to the TBRIN (RBRIN) register when a complete 16 bit word has been received. Data is assumed to be received MSB Tirst. Serial data transmission (reception) output is initi- ated by a frame synchro signal FSX (FSR). The 16-bit Data word is loaded into TSROUT (RSROUT) and serially clocked out of TSROUT (RSROUT) to TxDO (RxDO) on the rising edge of BCLKX (BCLKR). BGLKX (BCLKR} frequency can be programmed to be either 64 or 128 (80 or 160) (90 or 192) times Fsx (Fsr) using the Bit Frame Select (BFRS} input pin. This mean that the frame contains four, five, Figure 5 : Serial Channel Timing six, eight, ten or twelve time slots of 16 bits. The time slots used tor circuit operation are indicated in the next paragraph. IV.1-DUAL SERIAL INTERFACE MODE (SSIA, SSIB) When SSIM Is tied to Vpp, both Aand B ports are functional : port A (SSIA) is dedicated to the Tx channel and port B (SSIB) to the Rx channel. The timing diagram showing the data format is given in Figures 5 and 6. The time-slot TXO1 is dedicated to RAM coefficient reading. The RAM coefticient is selected by the address bits RAO to RA1 in the TxCtrl word (see Table 4). Reading is initiated by the rising edge ot Start bit Stb (bit D14 in Table 3) inthe TxCtrl word. Note : RxSig is also available in two time slot RxS1 and RxS2 on the time slot TxO2 and TxO3 on SSIA {see section IV.2) Fsx } (Fsr) BCLKX (BCLKR) ey 0 -QBQQOBOGOGOOOOHOS E G5-THOMSON TH MierosLecrrones 7E45-07.EPSSTLC7545 IV - SERIAL INTERFACE OPERATION (continued) Figure 6 : Serial Channel Timing. Dual Port Mode SSIA BCLKX Fsx Sh TxCtrl Mode | Add | Data TRS TxDI 4 3 5 8 | TxSig | ResSig Unused ' : (TxI0) (Txl1) (Txl2) (TxI3) (Txl4) RxTx RAM FT Hz CE TxBO 4 TR? | 13 Unused Unused Unused : (Tx00) (Tx01) (Tx02) (Tx03) (Tx04) SSIB BCLKR Fsr JI RxCtrl Add Daa YO pO TRE os TRH AxDI 4 8 8 | EYEY-EYEX Reserved Reserved : ; (TRIO) (TRI) (TRI2) (TRI3) (TRI4) po mit CS TRE Hz (TROO) (TRO1) (TRO?) (TRO3} (TR0O4} IV.2 - SINGLE SERIAL INTERFACE MODE When SSIM is tied to GND, only port A (SSIA) is selected. In this case, port A carries both Tx and Rx signal samples and control words at Tx sam- pling rate (Fsx). The RxDI input should be tied to Vop. Since port B is not functional in this mode, the RxSig (synchro- nized to Fsr) will be available in the two time slots, Rx$1 and RxS2, synchronizedto Fsx. The reason for the two time slots is that the Fsr could be different in magnitude and phase from the Fsx. The status bit StO and Sti are used to indicate which of the RxS1 and RxS2 are valid. Please see the table following. For example, it Fsx = 9600Hz and Fsr = 14400Hz both Rx81 and RxS2 could carry validdata. Figure 7 shows the timingdiagram. GS-THOMSON TH WickozLecrROMIGS The time-slot TXO1 is dedicated to RAM coefficient reading. The RAM coefficient is selected by ad- dress bits (RAO to RA1) in the TxCirl word (see Table 4). Reading is initiated by the rising edge of a Start bit Stb (bit D14 in Table 3} in the TxCtrl word. The time-slot TxI3 is dedicated to the RxCtrl word or the EYE-PATTERN, selected in the TxCtrl (see Table 5). Table 2 STATUS WORD IN Tx01 TIME SLOT D1 DO Valid Data Sti Sto 0 0 None 0 1 None 1 0 RxS2 1 1 RxS1 and RxS2 (1) Note 1: The RxS1 sampleprecedes the RxS2 sample. 19/53 7545-08.EPSSTLC7545 IV - SERIAL INTERFACE OPERATION (continued) Figure 7 : Serial Channel Timing. Single Port Mode SSIA BCLKX Fsx J] RxCtrl or TxCtrl Eye-pattern Moda] Add | Data Adds ] Daas fo | TxD 4 4 5 8 TxSig ResSig | EVEY | EVER } (Txl0) (Txl1) (Txl2) (Tx3) (Txl4) TxDO 4 RxTx RAM si RxS1 | RxS2 | __S__ 13 1] 2 ; (Tx00) (Tx01) (Tx02) (Tx03) (Tx04) IV.3 - COEFFICIENT LOADING MODE The Coefficient Loading Mode is selected by the Mode Select bit (MS) in the TxCtrl Word (Table 3). When the MS bit is a lagic1 the loading mode is selected. The IIR RAMS (RAM1 to RAM3) are selected in the TxCtrl word by two address bits (RAO to RA1). Each coefficient RAM stores 38 coetticients of 13 bits. Therefore the size of the coefficient RAM is 38 x 16 bits. The first frame transfers 2 coefficients and the 12 following frames Figure 8 : Coefficient Loading Mode each transfer 3 coefficients into the selected RAM, as shown in Figure 8. The transter is initiated by the rising edge ofthe Start bit coefficient Stb which is loaded into the TxCtrl word. When the coefficient loading mode is selected all data path are fixed to zero. Notes : 1. Coefficient loading is the same tor both dual and single interface modes. 2. In coetficient loading mede , the EYE-PATTERN (time slot TxI3) (and the RxCtr in a single serial interface) cannot be accessed SSIA BCLKX Fsx Ti 1st Frame TxCtrl TxDI 4 Mods | Add | Data | Unused | Cost 1 | Cost 2 3 5 8 (TxlO) (Txl1} (Txl2) (Tx13) (Txl4) (a). 1st Frame BCLKX Fsx 13th Frame TxCtrl TxDI Move Ace Pata | Coot 36 | Cost 37 | Coett 38 (TxlO) (Txl1} (Txl2) (Tx3} (Txl4) (b). 13th Frame 20/53 GS-THOMSON Lf, MICROELECTRONICS 7545-09.EPS 7545-10.EPSSTLC7545 IV - SERIAL INTERFACE OPERATION (continued) IV.4 - COEFFICIENT READING Coefficient reading is selected in DATA mocecnly, i.e. when the Mode Select bit (MS) in the TxCtrl werd is tied to logical 0. The IIR RAMS (RAM1 to RAMS) are selected in the TxCtrl word by two address bits (RAO to RA1). The 38 coefticients of 13 bits are available, one per frame, inthe timeslot TxO1 on the output Tx port A (see Figures 6, 7). The reading is available on the rising edge of the Start bit Stb loaded into the TxCtrl word. The first coefficient is output with one frame of delay on TxO1. IV.5 - CRYSTAL SELECTION (XTAL10, XTAL11) For application needing different or higher symbol rates, the user can software select different master clock frequencies for the STLC7545. Two XTAL inputs are provided for this purpose. The active XTAL input is selected in the time slot Txl1 with the Quartz Select bit (QS). It is mandatory to shoricir- cuit the XTAL10 and XTAL11 inputs when a single external crystal or clock generator is used. IV.6 - FRAME FREQUENCY PROGRAMMING When using the nominal master clock frequency, the frame frequency can be from 7200Hz to 16000Hz (see Tables 15 and 32}. Whenever the frame trequency Fsx (Fsr) is modified, the data to the STLG7545 during that frame should be high in the time slots Txl1 (Rxl1}, Txl2 (Rxl2) and TxI3 GS-THOMSON TH WickozLecrROMIGS (RxI3). This is because the BGLKX (BCLKR) during that frame may not be correct. Therefore, when- ever the Fsx (Fsr) is changed the user has to send information tothe STLC7545 after one frame delay. IV.7 - INITIALIZATION AND LOW-POWER RESET MODE Internal power-on circuitry automatically resets the DPLL, the clock generator counters, and initializes the internal control registers. The clocks affected are the symbol clock, the bit clock and the sampling clock. The initial status of these registers is given in the PROGRAMMABLE FUNCTIONS section. The transmit attenuator is initialized to an infinite attenuationmode (see Table 24) to avoid the trans- mission of undesirable signals on the phone line. During hardware low power reset (NLPR pin is tied to GND), the input of the inverter (across the crys- tal) will be high (DVpo), the DPLLs and the clock generator counters are initialized, all the analog circuitry is placed in low-power mode and the XTAL oscillator is stopped. Access to the circuit is disabled during reset until the clock oscillator starts. The duration of the reset time can be increased by connecting the NLPR input to an external RC timeconstant as indicated in Figure 9. In normal operation the NLPR input is used to control the LowPower mode. When NLPR is not used, it must be tied to Vpp. 21/53STLC7545 IV - SERIAL INTERFACE OPERATION (continued) Figure 9 : Power-on Initialization Circuitry ATALIO- XTAL11 (*) The software controlled reset is synchronized on the next falling edge of the baud rate clocks. : Tx and Rx DPLL [|g 8 CLOCK GENERATORS fag General Reset SOFTWARE CONTROLLED | ' RESET (*) q : CLK Low-Power : oIpD Q ANALOG FUNCTIONS : ; to ' CONTROL | rewier-on 8 REGISTERS Internal Reset Pulse ' Generator 7545-11.EPS 22/53 G7 SGS-THOMSON TH MierosLecrronesSTLC7545 V - CIRCUIT PROGRAMMING This section defines the contral and status words required to program the STLG7545. The circuit contiguration is managed by the control words TxCtrl and RxCtrland the SSIM, BFRS inputs. The control words contain three fields : - Mode Field 3 bits (D15-D13) - Address Field 5 bits (D12-D8) - Data Field 8 bits (D7-D0) V.1- MODE FIELD Table 3 : Mode Field mode control bit 2 bits for Coeff Ram address 3 bits for Control Registers address Control Registers content TxCtrl Word Di5 Di4 D13 Select mode MS Sib Qs 0 Data Mode and Control Register access mode Fi Coefficient Loading Mode and Filter Data Memory Reset (INI) T . Start bit for Coefficient Loading or Reading. The loading is initiated by a rising edge, i.e. a logical one programmed aftera logical zero. - 1 XTAL10 Selected (INI) (CS equals 16 in bit chain clock) - 0 XTAL11 Selected (CS equals 8 in bit chain clock) INI: initial value V.2- ADDRESS FIELD V.2.1- RAM Address Field Table 4 : RAM Adcress Field TxCtrl Word D1i5 D1i4 D1i3 Di2 D114 Did DS D8 RAM Address MS Stb Qs RAO RAI AD2 AD1 ADO - t - 0 0 - - - RAM 1 (INI) - t - 0 1 - - - RAM 2 - t - 1 0 - - - RAM 3 - - - 1 1 - - - Not RAM access INI: initial value V.2.2 - Transmit Control Register Address Field Table 5 : TransmitControl Register Address Field Register Name TxCtrl Word (2) Dis D14 D13 D12 B11 Dio Dg D8 MS Stb Qs RAO RAI AD2 AD1 ADO TxCRO (1) - - - - - 0 0 0 TxCRi1 (1) - - - - - 0 0 1 TxCR2 - - - - - 0 1 0 TxCR3 (1) - - - - - 0 1 1 None - 1 1 1 EYE Pattern on Txl3 1 1 0 (3) Notes : 1. A reset is generated when programming these registers (see II1.5.2.1). 2. No registeraccess for ihe non-specitied code 3. In singla interfaca made only 23/53 GS-THOMSON TH WickozLecrROMIGSSTLC7545 V - CIRCUIT PROGRAMMING (continued) V.2.3 - Receive Control Register Address Field Table 6 : Receive Control Register Address Field Register Name RxcCtrl Word (2, 3) D15 D14 D13 Di2 D11 D1i0 Dg D8 - - - AD2 AD1 ADO RxCR0 (Note 1) RxCR1 (Note 1) RxCR2 RxCR3 (Note 1) None +/oa/o/a/a -=/Aa/iAtola -=/Aa/ol-lo Notes : 1. A resat is generated when programming the RxGRO, RxCR1 and RxCR3 registers, this resetis synchronous with the falling edge of the Rx symbol clock. . In single interface mode, the RxCtrl registers cannot be programmed during the coefficient loading mode (see Figures 7 and 8}. . No registeraccess for the non-specified code V.3 - CONTROL REGISTER DATA FIELD V.3.1 - Transmit Control Register Programming Table 7 : TransmitControl Register Programming Register Data Programmed Function D7 | D | DS | D4 | DS | De | D1 Do TxCRO | No Ri RO $1 So T2 T1 TO | Tx Bit rate clock generator TxCR1 MO | Qi Qo U2 U4 Uo PO BS | Tx Sampling, Baud and HS clock generators; Band Split configuration. TxCR2 | AT1 | ATO |] LTX | LO | SST] RB VF R2 | Tx Attenuator, TxClock Synchronization, V.Fast Synchronization mode, Divider by 12/11 Bit clock TxCR3 | V2 V1 Vo W | HQ1 | HOO] TsO | DL | Tx Sampling (used with TxCR1}, FCOMP and FSHIFT frequency programming HALF-INTEGER Q DIVIDER (used with TxCR1}, Test configuration V.3.2 - Receive Control Register Programming Table 8 : Receive Control Register Programming Register Data Programmed Function D7 | D | DS | D4 | DS | De | Di DO RxCRO | NO Ri RO $1 So T2 T1 TO | Rx Bit rate clock generator RxCR1 Mo} Qi Qo U2 ui Uo PO | ECK | Rx Sampling, Baud and HS clock generators, Baud and HS clock Enable RxCR2 LL | PS3 | PS2 | PS1 | PSO | AP2 | AP1 | APO | Rx Fine and Coarse Phase, Shift Contrel RxGR3 | V2 V1 VO | EMX | R2 R3 | HQ1 | HGO | Rx Sampling (used with RxGri), FCOMP or TxRCLK output enable HALF-INTEGER @ DIVIDER (used with RxCR1), Divider by 12/11 and 15/13 Bit clock, Test configuration 248s G7 SGS-THOMSON JZ wicnosecrrancsSTLC7545 V - CIRCUIT PROGRAMMING (continued) V.3.3 - Control Bit Function Summary V.3.3.1 - TxCTRL WORD Table 9 : TxGTRL Word, Programmed Function Table Bit Programmed Function 11,12,13,14 No N Divisor rank : 3, 4 " R3,R2,R1,R0 | R Divisor rank: 15/13, 12/11, 10/9, 8/7, 6/5, 4/3, 1 (1) * $1,S0 $ Divisor rank : 1, 3, 5, 7 * T2,T1,T0 T Divisor rank : 4, 8, 16, 32, 64, 128, 256, 512 14,15,16,17,18 Mo M Divisor rank : 3, 4 * Q1,Q0 Q Divisor rank : 5, 6, 7, 8 19 U2,U1,U0 U Divisor rank : 3, 4,5, 6,7, 8, 12, 16 20 PO P Divisor rank : 3, 4 el BS Band Splitor Echo cancelling mode. (In band split mode the IIR2 Filter outputis internally tied to IIR3 Filter Input) 22 LTX Synchronization signal : TxSCLK or RxCLK 22 LC Synchronization enabling : Lock or Free DPLL. 22 SST TxDPLL reset on the next falling edge of the synchronization signal. SST is automatically reset after its action is completed. 23 VF 7544 and V.34 synchronization mode 23 R2, R38 R Divisor rank 24 AT1,ATO Tx Attenuation : OdB, 6dcB or infinite 25 V2,V1,VO V Divisor rank : 128 , 160, 192 25 F F Divisor rank 24 Ww FSHIFT frequency : Fsx or Fsx / 2 (Related to frequency capture range of the TxDPLL as FQ-FSHIFT < FAVERAGE < FQ + FSHIFT) 27 Ts0,HQ1, HQ0 | HALF-INTEGER @ DIVIDER (used with TxCR1 Q bit). Test Functions. Must be set to logical 0 for normal operation 27 DBL Test Loop Note 1 : The R2 and R3 bits are foundin the TxCR2 register Table 23 V.3.3.2 - RxCTRL WORD Table 10 : RxCTRL Word, Programmed Function Table Bit Programmed Function 28,29 30,31 No N Divisor rank : 3, 4 . R3,R2, R Divisor rank: 15/13, 12/11, 10/9, 8/7, 6/5, 4/3, 1 (1) Ri ,RO " $1,530 S Divisorrank : 1, 3, 5, 7 * T2,T1,TO | T Divisor rank : 4, 8, 16, 32, 64, 128, 256, 512 32,33,34,35 Mo M Divisor rank : 3, 4 * Q1,Q06 Q Divisor rank : 5, 6, 7, 8 36 U2,U1,U0 | U Divisor rank: 3, 4,5, 6,7, 8,12, 16 37 PO P Divisor rank : 3, 4 37 ECK Tx/RxRGLK and Tx/RxHSCLK output enabling 38 LL Rx DPLL Lead/Lag control 38 P$1,PS0 | Rx DPLL Phase Shift magnitude : 0, 8, 12, 16, 20, 24, 28, PS2 38 PS3 Rx DPLL Phase Shift magnitude : One 128*Fsx period. This bitis reset after phase shift completion. 39 AP2,AP1 Rx DPLL Coarse Phase Lag : 0, 64, 128, 256512, 1024, APO 40 V2,V1,V0 | V Divisor rank 41 EMX FCOMP or TxRCLK output enable (used in V.Fast synchronization mede to multiplex the transmit bit Frame) 41 H@0,HQ1 | Half-integer Q divider (used with RxCR1 Q bit) 41 R3, Re R Divisor rank Note 1 : The R2 and R3 bits are foundin the RxCR3 register Table 41 25/53 GS-THOMSON TH WickozLecrROMIGSSTLC7545 VI - PROGRAMMABLE FUNCTIONS V1.1 - TRANSMIT SECTION The different transmit (Tx) clocks are obtained by frequency division in several counters (see Fig- ure 10). Note 1: TxPCLK is an internal Processing Clock used by the three IIR filters Note 2: The phase of internal clock FCOMP will be compared to the synchronization signal (Ta- ble 22) in order te control TxDPLL (see Tables 22, 25 and 26). In V.34 synchronization mode FCOMP is automatically set to 2400/F Hz if the crystal frequency is equal to 36.864MHz (with QS = 1) or 25.8048MHz (with QS = 0) and if the bit rate clock is multiple of 2400Hz chosen from the Table. In 7544 mode V divisor must be chosen such that the Figure 10 : Transmit Clock Generator FCOMP trequency is an integral sub-multiple of the synchronization frequency. In the 7544 mode the most typical frequency for FCOMP is the baud rate frequency. During each period of FCOMP the average input frequency of the transmit clock generatorcan be : FQ , FQ+ FSHIFT or FQ - FSHIFT with FSHIFT = Fsx or Fsx/2 Note 3 : In 7544 mode the bit rate frequency must always be an integer multiple of the baud rate frequency for the transmit DPLL to lock onto the synchronization signal. Note 4 : The X divisor is programed automatically with respect to QS bit. % Y DVpp TxHS ctx | xOCLK TxS YNC TxRCLK | eecmove 1 Ly y Phase Shift ' OS mode P-1 w} @P P+1 MSCLK Txsyne EMX | MUX 2 TO 1 % . Terminal Clock Phase Shift | > FCOMP a R R ye Txrclk = Fsx/U M-1 fv el SM tm OQ LO (128 or 160) %U M+ 1 or 192 FQ | Up to 38MHz L OSmode mW TxPCLK a (internal) Txoclk Fsx Y V.FAST FS HIFT (internal) Ph Shift Be OMe ase Shi Txsyne Txsync _ (inte rna 1) o hi be 2) 4 Nel 2400Hz | & py} aN Mm SRxSxTxCs % X x | iF N+1 = Txchk = FQOAN xR x5xTxCS) LJ 26/53 E G5-THOMSON TH MierosLecrrones 7E45-12. EPSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) V11.1- Transmit Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=36.864MHz Table 11 : Transmit Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=36.864MHz TxCRO Register Frecuen ovttt) TxcR2 |TxcR2| D7 | De | D5 | D4 | DS | De | Dt Do Divisor (FQ = 36.864MHz) D2 Do rank Txelk = FO/(N*R*S*T*CS) R3 R2 No | Ri Ro | S31 so | T2 | Ti To (1) 0 0 0 1 1 1 0 0 0 0 960 38400 Q Q 1 { 1 0 Q Q 1 0 1024 36000 O 0 0 0 0 1 O 0 0 0 960x8/7 33600 0 0 0 1 1 0 1 0 0 1 1152 32000 1 1 1 0 0 0 Q Q 1 oO | 1024x1513 31200 Q Q 1 { 1 1 Q QO 0 Oo 1280 28800 0 1 1 0 0 1 0 0 0 o | 1280x12/11 26400 QO 0 1 { 1 0 1 Q 0 1 1536 24000 0 0 1 1 0 1 0 0 0 0 1280x4/3 21600 0 0 0 { 1 1 0 0 0 1 1920 19200 (INI) 0 0 0 0 0 1 0 0 0 1 1920x8/7 16800 0 0 0 1 1 0 1 0 1 0 2304 16000 0 0 1 1 1 1 0 0 0 1 2560 14400 0 0 1 1 1 0 1 0 1 0 3072 12000 0 0 0 1 1 1 0 0 1 0 3840 9600 Q Q Oo { 1 0 1 QO 1 1 4608 8000 Q Q 1 { 1 1 Q Q 1 0 5120 7200 0 0 0 1 1 1 0 0 1 1 7680 4800 0 0 0 { 1 1 0 1 0 0 15360 2400 OQ O 0 { 1 1 OQ 1 0 1 30720 1200 Q Q 0 { 1 1 Q 1 1 0 61440 600 0 0 0 1 1 1 0 1 1 1 122880 300 Note: 1. The QSbitin TxCTRL word (bit D3) must be set to1 tohave CS = 16. V11.2- Transmit Bit Rate Clock Frequency Programming with Master clock Frequency FQ=25.8048MHz Table 12: Transmit Bit Rate Clock Frequency Programmingwith Master Clock Frequency FQ=25.8048MHz TxCRO Register Bit Rate Clock Frequency (Hz) TxCR2 DO} D7 D6 D5 D4 D3 De D1 DO Divisor (FQ = 25.8048MHz) R2 No | Ri | Ro | si | So | T2 | T1 | To rank Txclk = FQ/(N*R*S*T*CS) (2) 0 1 1 1 1 1 0 0 0 896 28800 1 1 0 0 1 1 0 0 0 896x12/11 26400 0 1 0 1 1 1 0 0 0 896x6/5 24000 0 1 1 0 1 1 0 0 0 896x4/3 21600 0 0 1 1 1 1 0 0 1 1344 19200 0 0 0 0 1 1 0 0 1 1344x8/7 16800 0 0 0 1 1 1 0 0 1 1344x6/5 16000 0 1 1 1 1 1 0 0 1 1792 14400 0 1 0 1 1 1 0 0 1 1792x6/5 12000 0 0 1 1 1 1 0 1 0 2688 9600 0 0 0 1 1 1 0 1 0 2688x6/5 8000 0 1 1 1 1 1 0 1 0 3584 7200 0 0 1 1 1 1 0 1 1 5376 4800 0 0 1 1 1 1 1 0 0 10752 2400 0 0 1 1 1 1 1 0 1 21504 1200 0 0 1 1 1 1 1 1 0 43008 600 0 0 1 1 1 1 1 1 1 86016 300 Note: 2. The QS bitin TxCTRL word (bit D3) must ba set to 0 tohave CS = 8. 27/53 GS-THOMSON TH WickozLecrROMIGSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VL1.3- Transmit Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=18.432MHz Table 13 : Transmit Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=18.432MHz TxCRO Register Bit Rate Clock Frequency (Hz) D7 D D5 D4 D3 De D1 Do Divisor Txclk= No | Rt | Ro | si | so | t2 | Tt | To rank FOMNTRES*T"CS) (1) 0 1 1 0 1 0 0 0 576 32000 1 1 1 0 1 0 0 0 768 24000 0 1 1 1 0 0 0 0 960 19200 0 0 0 1 0 0 0 0 960x8/7 16800 0 1 1 0 1 0 0 1 1152 16000 1 1 1 1 0 0 0 0 1280 14400 1 1 1 0 1 0 0 1 1536 12000 0 1 1 1 0 0 0 1 1920 9600 (INI) 0 1 1 0 1 0 1 0 2304 8oco 1 1 1 1 0 0 0 1 2560 7200 0 1 1 1 0 0 1 0 3840 4800 0 1 1 1 0 0 1 1 7680 2400 0 1 1 1 0 1 0 0 15360 1200 0 1 1 1 0 1 0 1 30720 600 0 1 1 1 0 1 1 0 61440 300 INI : initial value Notes: 1. The bit R2 and R3in the TxCR2 register (bit DO and D2} mustbe set to 0. The QS bitin TxCTRL word must be set to 1 to have CS =16. 28/53 G7 SGS-THOMSON TH MierosLecrronesSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VI.1.4- Transmit Bit Clock Frequency Programming. Divisor Rank Table 14 : Transmit Bit Clock Frequency Programming. Divisor Rank Bit Rate Clock Frequency(Hz) Txelk = FQ/(N*R*S*T*CS) (1) TxCR2 | TxCR2 | D7 D6 D5 D4 D3 D2 D1 Divisor rank D2 DO R3 R2 No Ri Ro $1 SO T2 T1 - - 0 - - - - - - TxCRO Register oO ;o; o;o;oa;o;oa!1a =/-=/=-|;|-= Jol/alala =!|=Jo/l/al/-/-|ala +7/7/o);+;o;/7+y;o;-+|;a =/-=-/|;Aa | -Jalolala =/-loljo/j/-|-| ala -~/7/O/;/2+/0/;/+7/oa/;-/;o =/-=J;/A/Aaloalalalal. -=l-/;olo/-/|-|/o]o|: =loj-/oj/-;al-|o]. ofa da ofa da ofa da INI : initial value Note 1: The CS divisor is sat by QS bit in TXCTRL word (OS =1 G CS = 16,Q5 =0 4 C5 =8) 29/53 GS-THOMSON TH WickozLecrROMIGSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VL1.5- Transmit Sampling Clock Frequency Programming with Master Clock Frequency FQ=36.864MHz Table 15: Transmit Sampling Clock Frequency Programming with Master Clock Frequency FQ=36.864MHz Mibaud) | UY Mx(YorQ)ratio | prequencyttiz) | ratio | | ange, 600 12 4x8 7200 160 1 1.95E-4 600 16 4x6 9600 160 1 2.60E-4 1200 6 4x8 7200 160 1 1.95E-4 1200 8 4x6 9600 160 1 2.60E-4 1600 5 4x6 8000 192 1 2.17E-4 1600 6 4x6 9600 160 1 2.60E-4 2400 3 4x8 7200 160 1 1.95E-4 2400 4 4x6 9600 160 1 2.60E-4 2400 6 4x5 14400 (INI) 128 2 1.95E-4 2560 3 4x 7.5 7680 160 1 2.08E-4 2560 4 3x 7.5 10240.00 160 1 2.77E-4 2560 6 3x5 15360.00 160 2 2.98E-4 2742.86 3 4x7 8228.57 160 1 2.40E-4 2742.86 4 3x7 10971.43 160 1 2.98E-4 2953.85 3 4x65 8861.54 160 1 2.40E-4 2953.85 4 3x65 11815.38 160 1 3.21E-4 3000 3 4x8 9000 128 1 2.44E-4 3000 4 3x8 12000 128 1 3.26E-4 3200 3 4x6 9600 160 1 2.60E-4 3200 4 3x6 12800 160 1 3.48E-4 3200 5 3x6 16000 128 1 4.34E-4 3428.57 3 4x7 10285.71 128 1 2.79E-4 3428.57 4 3x7 13714.28 128 2 1.86E-4 3490.91 3 4x55 10472.73 160 1 2.84E-4 3490.91 4 3x55 13963.64 160 1 3.79E-4 INI : initial value VI.1.6 - Transmit Sampling Clock Frequency Programming with Master Clock Frequency FQ=25.8048MHz Table 16 : Transmit Sampling Clock Frequency Programming with Master Clock Frequency FQ=25.8048MHz Symbol rate . Samplin V Over-sampling Capture (baud) U M x Qratio Frequency(Hz) ratio w range 2800 3 4x6 8400 128 1 3.26E-4 2800 4 3x6 11200 128 2 2.17E-4 2400 3 4x7 7200 128 1 2.79E-4 2400 4 3x7 9600 128 2 1.86E-4 V1L1.7- Transmit Sampling Clock Frequency Programming with Master Clock Frequency FQ@=18.432MHz Table 17 : Transmit Sampling Glock Frequency Programming with Master Clock Frequency FQ=18.432MHz Symbol Rate : Sampling V Over-sampling Capture (baud) U M x@Q ratio Frequency (H2) ratio w range 1600 5 3x6 8000 128 2 2.17E-4 1600 6 3x5 9600 128 2 2.60E-4 2400 (INI) 3 4x5 7200 128 2 1.95E-4 2400 4 3x5 9600 128 2 2.60E-4 INI : initial value S0/s3 Gar SGS-THOMSON JZ MicrosecrrasiesSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VI.1.8. Transmit Sampling Clock Frequency Programming. Divisor Rank Table 18 : Transmit Sampling Clock Frequency Programming. Divisor Rank Sampling cock Nr ned TxCR1 Register Fsx = FQ/(MxQxV) (1 D7 D6 DS D4 D3 D2 D1 Do Divisor rank Mo Qi Qo U2 Ut Uo PO BS M Q (2) 0 - - - - - - - 3 1 - - - - - - - 4 (INI) - 0 0 - - - - - 5 (INI) (4.5) - 0 1 - - - - - 6 (5.5) - 1 0 - - - - - 7 (6.5) - 1 1 - - - - - 8 (7.5) INI : initial value Notes : 1 . The V divider is programmed in the TxCR3 ragister. 2. To use the fractional Q divider bits HQ1 and HQ0 in Table 27 mustbe setto "1" (otherwise they are set to "0"). VI.1.9. Transmit Baud Rate Frequency Programming. Divisor Rank Table 19 : Transmit Baud Rate Frequency Programming. Divisor Rank TxCR1 Register Balid rate Frequency D7 D6 D5 D4 D3 D2 D1 Do Divisor Rank Mo Qi Qo U2 U1 Uo PO BS U - - - 0 0 0 - - 3 (INI) - - - 0 0 1 - 4 - - - 0 1 0 - - 5 - - - 0 1 1 - - 6 - - - 1 0 0 - - 8 - - - 1 0 1 - - 12 - - - 1 1 0 - - 16 - - - 1 1 1 - - 16 INI : initial value VI.1.10. Highest Synchronous Transmit Frequency Programming. Divisor Rank Table 20 : Highest Synchronous Transmit Frequency Programming. Divisor Rank TxCR1 Register Highest Synchronous Transmit Frequency Txhsclk=FQ/P D7 D D5 D4 D3 D2 D1 Do Divisor Rank Mo Qi Qo U2 U1 Uo PO BS P - - - - - - 0 - 3 (IN| - - - - - - 1 4 INI : initial value VI.1.11. Band Split Mode Table 21 : Band Split Mode TxCR1 Register Band Split Mode D7 D D5 D4 D3 D2 D1 DO MO Q1 Qo Ue U1 UO PO BS - - - - - - - 0 Inactive (INI) Active : Rx Filter Qutput connected to reconstruction filter input (see Figure 1). INI : initial value & GS-THOMSON TH WickozLecrROMIGS 31/53STLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VI.1.12 - Transmit Synchronization Signal Programming Table 22 : Transmit Synchronization Signal Programming TxCR2 Register Tx DPLL Clock D7 DE D5 D4 D3 D2 D1 DO Synchronization AT1 ATO LTX LC SST R83 VF Re - - fe) 1 - - - - TxSCLK (1) - - 1 1 - - - - RxCLK (1) - - - 1 1 - - - Reset on the Next falling edge of the Synchronization Signal (1) (2) - - - 0 - - - - No Synchronization (INI) INI : initial value Notes: 1. lfD4 =1, the TxDPLL will be locked to the synchronization signal ifpresent when programming is done. Otherwise, the Tx DPLL will be free-running. 2. The SST bitis automatically reset after its action is completed. VI.1.13 - Clock Mode Programming & R2& R3 Divisor Table 23 : Glock Mode Programming & R2 & R3 Divisor TxCR2 Register Mode Programming & R2 & R3 Divisor D7 D6 D5 D4 D3 D2 D1 Do AT1 ATO LTX LG SST R3 VF R2 - - - - - - 0 - 7544 synchronization Mode (INI) - - - - - - 1 - V.34 synchronization Mode - - - - - - - Re see Table 14 - R2 = 0 (INI) - - - - - R3 - - see Table 14 - R3 = 0 (INI) INI : initial value VI.1.14- Transmit Attenuator Programming Table 24 : Transmit Attenuator Programming TxCR2 Register Transmit Attenuator D7 D6 D5 D4 D3 D2 D1 DO Attenuation (dB) AT1 | ATO | LTX LG SST R3 VF R2 0 0 - - - - - - Infinite (INI} 1 0 - - - - - - -6 1 1 - - - - - - 0 INI : initial value VI.1.15 - Phase Comparator Frequency and Decimation & Interpolation Ratio Table 25 : Phase Comparator Frequency And Decimation & Interpolation Ratio Tx Phase Comparator Frequency TxCR3 Register FCOMP = Txrclk / F or 2400 / F (2) and V Divisor rank D7 D D5 D4 D3 D2 D1 DO FCOMP Oversampling ratio V2 Vi Vo Ww HQ1 | HQ@o | Tso DL F Vv 0 0 0 - - - - - 1 128 0 0 1 - - - - - 2 128 0 1 0 - - - - - 1 160 0 1 1 - - - - - 2 160 1 0 0 - - - - - 4 128 (INI 1 0 1 - - - - - 1 192 1 1 0 - - - - - 4 160 1 1 1 - - - - - 1 256 (1) INI : initial value Notes : 1. The performance is not guaranteed with this oversampling ratio. 2. FCOMP is depanding of the synchronization mode (normal or V.34)}. 32/53 G7 SGS-THOMSON TH MierosLecrronesVI - PROGRAMMABLE FUNCTIONS (continued) VI.1.16 - Phase Shift Frequency Table 26 : Phase Shift Frequency STLC7545 TxCR3 Register Phase Shift Frequency (1) FSHIFT = Fsx /W D7 D6 D5 D4 D3 D2 D1 Do (Average updated master clock frequency) V2 Vi vo Ww HQ1 | HGo TsO DL W - - - 0 - - Fsx/2 (INI) (FQ + Fsx/2 ) - - - 1 - - Fsx (FQ + Fsx) INI : initial value Note 1: The W bit selects the phase shift frequency of the TxDPLL, and hence the capture range VI.1.17 - Transmit Test Programming Table 27 : Transmit Test Programming TxCR3 Register Test Modes D7 Ds D5 D4 D3 D2 D1 Do Ve V1 Vo Ww HQ1 | HQo | Tso DL 0 0 0 0 Normal Made (INI) - - - - - - - 1 Digital Loop Test (1) - - - - - - 1 - Test 0 (Internal use only) - - - - 0 1 - - Test 1 (Internal use only) - - - - 1 0 - - Test 2 (Internal use only) - - - - 1 1 - - HALF-INTEGER @ DIVIDER (see Table 18) (2) INI : initial value Notes : 1. To parform the digital loop test, the single serial interface and band split modes should be selected, the signal at TxDO pin should be connected to the RxDI pin, and the Fsx should be equal tothe Fsr. Under these conditions, the A/DC input will appear at the output on the D/AC. This testis useful to verify the performance of the ADC, DAC and IIR filters. 2. Test pin EOCMODE must be set to 0 in this configuration. GS-THOMSON TH WickozLecrROMIGS 33/53STLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VL2 - RECEIVE SECTION The different Receive (Rx) clocks are derived from the master clock (FQ) using the dividers shown in Figure 11. The counters of the Rx clock system (without the RxHSGLK) are reset when powering on the STLG7545 and when the NLPR input level is low. Figure 11 : Receive Clock Generator They can also be reset, under software control, on the next falling edge of the RxRCLK receive baud rate clock when the RxCRO, RxCR1 or RxCR3 register are accessed: this feature is used to fix the phase of the bit rate clock with respect to the baud rate clock, e.g. after each modification of the bit or baud rate value. %Y RxHSCLK RxOCLK RxS NC RxRCLK 1 Ly Phase Shift P-1 } % P P41 Rxsyne Phase Shift | y R R FR FQ M-1 % V Up to 38MHz me! > M Let ea bo (128 of 160) Ls % U M+ 1 oc 192 OS mode Coarse arn Rxoclk Fsec Rxrelk= FscfU Phase Shit Rxsyne Y he N-1 ei SN Fae @RxSKXTXKCS WN+1 Raclk=FQANx RxS xTxCS) LJ 34/53 E G5-THOMSON TH MierosLecrrones 7545-13.EPSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) V12.1- Receive Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=36.864MHz Table 28 : Receive Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=36.864MHz RxCRO Register Frequon cyiriz) RxCR3]RxcR3s] D7 | D |] DS | D4 | DS | D2 | Dt Do Divisor (FQ = 36.864MHz) D2 D3 rank Rxelk = FQ/{(N*R*S*T*CS) R83 R2 No | Ri Ro | S1 so | T2 | T1 TO (1) 0 0 0 1 1 1 0 0 0 0 960 38400 0 0 1 1 1 0 0 0 1 0 1024 3600 0 0 0 0 0 1 0 0 0 0 960x8/7 33600 O 0 0 { 1 0 1 0 0 1 1152 32000 1 1 1 0 0 Oo Q Q 1 0 | 1024x1513 31200 0 0 1 1 1 1 0 0 0 0 1280 28800 Q 1 1 0 0 1 Q Q 0 0 | 1280x12/11 26400 0 0 1 1 1 0 1 0 0 1 1536 24000 Q Q 1 { 0 1 Q QO 0 0 1280x4/3 21600 0 0 0 { 1 1 0 0 0 1 1920 19200 (INI) 0 0 0 0 0 1 0 0 0 1 1920x8/7 16800 0 0 0 { 1 0 1 0 1 0 2304 16000 0 0 1 1 1 1 0 0 0 1 2560 14400 0 0 1 1 1 0 1 0 1 0 3072 12000 0 0 0 1 1 1 0 0 1 0 3840 9600 Q Q 0 { 1 0 1 Q 1 1 4608 8000 0 0 1 1 1 1 0 0 1 0 5120 7200 Q Q oO { 1 1 Q QO 1 1 7680 4800 0 0 0 1 1 1 0 1 0 0 15360 2400 Q Q 0 { 1 1 Q 1 0 1 30720 1200 0 0 0 1 1 1 0 1 1 0 61440 600 QO Q 0 { 1 1 QO 1 1 1 122880 300 INI: initial value Note 1 : The OS bit (D13) in TxCTRL word must be set 1 to hava CS = 16. VIL.2.2- Receive Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=25.8048MHz Table 29 : ReceiveBit Rate Clock Frequency Programmingwith Master Clock Frequency FQ=25.8048MHz RxCRO Register Bit Rate Clock Frequency (Hz) RxCR3 D3} D7 D6 D5 D4 D3 D2 D1 DO Divisor (FQ = 25.8048MHz) Re No | Ri | Ro | si | So | T2 | Ti | To rank Rxclk = FQ/(N*R*S*T*CS) (1) 0 1 1 1 1 1 0 0 0 896 28800 1 1 0 0 1 1 0) 0 0 896x12/11 26400 0 1 0 1 1 1 0 0 0 896x6/5 24000 0 1 1 0 1 1 0 0 0 896x4/3 21600 0 a) 1 1 1 1 0 0 1 1344 19200 0 0 0 0 1 1 0 0 1 1344x8/7 16800 0 0 0 1 1 1 0 0 1 1344x6/5 16000 0 1 1 1 1 1 0 0 1 1792 14400 0 1 0 1 1 1 0 0 1 1792x6/5 12000 0 0 1 1 1 1 0 1 0 2688 9600 0 a) 0 1 1 1 0) 1 0 2688x6/5 8000 0 1 1 1 1 1 0 1 0 3584 7200 0 0 1 1 1 1 0 1 1 5376 4800 0 a) 1 1 1 1 1 0 0 10752 2400 0 0 1 1 1 1 1 0 1 21504 1200 0 0 1 1 1 1 1 1 0 43008 600 0 0 1 1 1 1 1 1 1 86016 300 Note: 1. The QSbit (D13) in TxCTRL word must be set 0 tohave CS = 8. 35/53 GS-THOMSON TH WickozLecrROMIGSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) V12.3- Receive Bit Rate Clock Frequency Programming with Master Clock Frequency FQ=18.432MHz Table 30 : Receive Bit Rate Clock Frequency Programming With Master Clock Frequency FQ=18.432MHz RxCRO Register Bit Rate Clock Frequency (Hz) D7 D D5 D4 D3 D2 D1 DO Divisor rank (FQ = 18.482MHz) No | Ri | RO | st | so | t2 | 1 | To Fixelk = FOY(N'R*S*T'CS) (1) 0 1 1 0 1 0 0 0 576 32000 1 1 1 0 1 0 0 0 768 24000 0 1 1 1 0 0 0 0 960 19200 0 0 0 1 0 0 0 0 960*8/7 16800 0 1 1 0 1 0 0 1 1152 16000 1 1 1 1 0 0 0 0 1280 14400 1 1 1 0 1 0 0 1 1536 12000 0 1 1 1 Q oO 9) 1 1920 9600 (INI) 0 1 1 0 1 Q 1 0 2304 8000 1 1 1 1 0 0 0 1 2560 7200 0 1 1 1 0 0 1 0 3840 4800 0 1 1 1 0 0 1 1 7680 2400 0 1 1 1 0 1 0 0 15360 1200 0 1 1 1 0 1 0 1 30720 600 0 1 1 1 0 1 1 0 61440 300 INI: initial value Notes: 1. Thea QSbit (D13) in TxCTRL word must be sat 1 tohave CS = 8. The bitR2 inthe TxCR2 register (bit DO) must be set to 0. 36/53 G7 SGS-THOMSON TH MierosLecrronesSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VI1.2.4 - Receive Bit Rate Clock Frequency Programming. Divisor Rank Table 31 : Receive Bit Rate Clock Frequency Programming. Divisor Rank : Bit Rate Clock Frequency(Hz) RxCRO Register Rxclk = FQ/(N*R*S'T*CS) (1) RxCR3 | RxCR3] D7 D6 D5 D4 D3 D2 D1 Do Divisor rank D2 DO R3 R2 NO Ri Ro 31 So T2 T1 R s - - Oo - - - - - - oO;o;o;oa;a;ay;a;oa =/-=/4= [= |; olalala =!|/=|olo/l/--l|-+ | ala +/o);7+;o;-+s;oay;-+|;oa =/-=-/|}= | = |alalala =a/-|o/oa/-=/|-=|a la ]+-/7/0;7+7)/o;+;oa;-+|ca =/-=-;|;=- ja /a/alala =/|/-=-|To/j/a/=|-/[oa/a -+/7/0o0;-+);/o;-+;o;-+|]oa INI: initial value Note 1 : The CS divisor is setby QSbit (D13) in TxCTRL word(QS = 1 > CS =16, QS =0 > CS = 8} 37/53 GS-THOMSON TH WickozLecrROMIGSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VL2.5- Receive Sampling Clock Frequency Programming with Master Clock Frequency FQ=36.864MHz Table 32 : Receive Sampling Clock Frequency Programming with Master Glock Frequency FQ=36.864MHz Symbol Rate (baud) U MxY orM x Q ratio Sampling Frequency (Hz) V OverSampling ratio 600 12 4x8 7200 160 600 16 4x6 9600 160 1200 6 4x8 7200 160 1200 8 4x6 9600 160 1600 5 4x6 8000 160 1600 6 4x6 9600 192 2400 3 4x8 7200 160 2400 4 4x6 9600 160 2400 6 4x5 14400 (INI) 128 2560 3 4x75 7680 160 2560 4 3x75 10240.00 160 2560 6 3x5 15360.00 160 2742.86 3 4x7 8228.57 160 2742.86 4 3x7 10971.43 160 2953.85 3 4x65 8861.54 160 2953.85 4 3x6.5 11815.38 160 3000 3 4x8 9000 128 3000 4 3x8 12000 128 3200 3 4x6 9600 160 3200 4 3x6 12800 160 3200 5 3x6 16000 128 3428.57 3 4x7 10285.71 128 3428.57 4 3x7 13714.28 128 3490.91 3 4x55 10472.73 160 3490.91 4 3x55 13963.64 160 INI: initial value VL2.6- Receive Sampling Clock Frequency Programming with Master Clock Frequency FQ=25.8048MHz Table33 : Receive Sampling Clock Frequency Programming with Master Clock Frequency FQ=25.8048MHz Symbol Rate (baud) U Mx( or Q) Sampling ratio V OverSampling Frequency (Hz) 2800 3 4x6 8400 128 2800 4 3x6 11200 128 2400 3 4x7 7200 128 2400 4 3x7 9600 128 VI.2.7- Receive Sampling Clock Frequency Programming with Master Clock Frequency FQ=18.432MHz Table 34 : Receive Sampling Clock Frequency Programming with Master Glock Frequency FQ=18.432MHz Symbol Rate (baud) U Mx@Q Sampling ratio V OverSampling Frequency (Hz) 1600 5 3x6 8000 128 1600 6 3x5 9600 128 2400 (INI) 3 4x5 7200 128 2400 4 3x5 9600 128 INI: initial value 38/53 G7 SGS-THOMSON TH MierosLecrronesSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) VL2.8 - Receive Sampling Clock Frequency Programming. Divisor Rank Table 35 : Receive Sampling Glock Frequency Programming. Divisor Rank RxCR1 Register SPAM eax yy D7 D D5 D4 D3 D2 D1 DO Divisor rank MO Qi Qo U2 U1 Uo PO ECK M Q (2) a) - - - - - - - 3 - - - - - - - 4 (INI) - 0 0 - - - - - 5 (INI) (4.5) - 0 1 - - - - - 6 (5.5) - 1 0 - - - - - 7 (6.5) - 1 1 - - - - - 8 (7.5) INI: initial value Notes: 1. The V divider is programmed in the RxCR3 Register 2. To use the fractional divider bits HQ1 and HQ0 in Table 41 mustbe setto 1 (othenvise they are set to "0). VI.2.9 - Receive Baud Rate Frequency Programming. Divisor Rank Table 36 : Receive Baud Rate Frequency Programming. Divisor Rank RxCR1 Register Band rate frequency D7 D6 D5 D4 D3 D2 D1 DO Divisor Rank Mo Qi Qo U2 Ut Uo PO | ECK (1) U - - - 0 0 0 - - 3 (INI) - - - 0 0 1 - - 4 - - - 0 1 0 - - 5 - - - 0 1 1 - - 6 - - - 1 0 0 - - 8 - - - 1 0 1 - - 12 - - - 1 1 0 - - 16 - - - 1 1 1 - - 16 INI: initial value Note: 1. ECKbitis used to enable the RXRCLK and RxHSCLKoutputs (as well as TxROLK and TxHSCLK clock outputs) when sat atlogical 1. The baud rate clock must be programmed toits correct value even though the corresponding output pin is disabled (ECK = 0). VI.2.10 - Highest Synchronous Transmit Bit Frequency Programming. Divisor Rank Table 37 : Highest Synchronous Transmit Bit Frequency Programming. Divisor Rank RxCR1 Register Highest Sy hea Raea. frequency D7 | DB |} DS | D4 | DB | De | D1 DO Divisor Rank Mo | Qi | qo | u2 | ut | Uo | Po | Eck P - - - - - - 0 - 3 (INI) - - - - - - 1 - 4 - - - - - - - 0 Disable RxRCLK, RxHSCLK, TxRCLK and TxHSCLK Output - - - - - - - 1 Enable RxRCLK, RxHSCLK, TxRCLK and TxHSCLK Output (INI) INI: initial value 39/53 & GS-THOMSON TH WickozLecrROMIGSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) V1.2.11- Receive Fine Phase Shift Programming Table 38 : Receive Fine Phase Shift Programming RxCR2 Register Receive Fine Phase Shift Programming D7 D D5 D4 D3 D2 D1 Do Action on RxDPLL LL PS3 Psp PSi Pso | AP2 | API APO Number of Master Clock Pulses Suppressed 0 0 0 0 0 0 0 0 No phase shift (INI) 0 0 0 0 1 0 0 0 8 0 0 0 1 0 0 0 0 12 0 0 0 1 1 0 0 0 16 0 0 1 0 0 0 0 0 20 0 0 1 0 1 0 0 0 24 0 0 1 1 0 0 0 0 28 0 0 1 1 1 0 0 0 32 0 1 0 0 0 0 0 0 One Txoclk oversampling period (1) 1 - - - - - - - As above but lead instead of lag (i.e. addition of Master-Clock pulses) INI: initial value Note 1 : Available only with an internal Q divider. To shift one oversampling period, the chip must know the @ divider value currently used. VI.2.12 - Receive Coarse Phase Shift Programming Table 39 : Receive Coarse Phase Shift Programming RxCR2 Register Receive Coarse Phase Shift Amplitude Programming D7 D6 D5 D4 D3 De D1 DO Number of Master Clock LL | pss | ps2 | pst | Pso | AP2 | AP1 | APO Pulses Suppressed 0 0 0 0 0 0 0 0 Neo Phase Shift (INI) 0 0 0 Q 0 0 0 1 64 0 0 0 0 0 0 1 0 128 0 0 0 0 0 0 1 1 256 0 0 0 0 0 1 0 0 512 0 0 0 Q 0 1 0 1 1024 0 0 0 0 0 1 1 0 2048 0 0 0 Q 0 1 1 1 4096 INI: initial value 40/53 Lf, MICROELECTRONICSSTLC7545 VI - PROGRAMMABLE FUNCTIONS (continued) V1.2.13 - Interpolation Ratio Table 40 : Interpolation Ratio RxCR3 Register INTERF OL ATION RATIO D7 | De | D5 | D4 | Ds | pe | bit | Do V ve | v1 vo | EMx | Re | RS | Hat | Hao 0 0 0 - - - - - 128 0 0 { - - - - - 128 0 1 0 - - - - - 160 0 1 1 - - - - - 160 1 0 0 - - - - - 128 (INI) 1 0 1 - - - - - 192 1 1 0 - - - - - 160 1 1 1 - - - - - 256 (1) INI: initial value Note 1 : The performances are not garanted with this oversampling ratio. VI.2.14 - Receive Test Programming & R2 & R3 Divisor Table 41 : Receive Test Programming and R2 and R3 Divisor RxCR3 Register Test Mode & R2 & R3 Divisor D7 D D5 D4 D3 D2 D1 Do V2 V1 Vo EMX R2 R3 HQ1 | HQo - - - - - 0 0 0 Normal Mode (INI) - - - - R2 - - - see Table 31 (RxCRO) R2 =0 (INI) - - - - - R3 - - see Table 31 (RxCRO) R3 =0 (INI) - - - 0 - - - - Tx RCLK output on TxRCLK pin (INI) - - - 1 - - - - FCOMP output on TxRCLK pin (see Figure 10) - - - - - - 1 1 HALF-INTEGER DIVIDER (see Table 35) INI: initial value GS-THOMSON TH WickozLecrROMIGS 41/53STLC7545 Vil - ELECTRICAL SPECIFICATIONS Unless otherwise noted, electrical characteristics are specified over the operating range. Typical values are given for Vpp =+5V , Tamb = 25C and for nominal crystal frequency FQ = 36.864MHz. VIl.1 - ABSOLUTE MAXIMUM RATINGS (referenced to GND) Table 42 : Absolute Maximum Ratings Symbol Parameter Value Unit Vbp DC Supply Voltage -0.3 to 7.0 Vv V,Vin Digital or Analog Input Voltage - 0.3, Vpp +0.3 Vv latin Digital or Analog Input Current +1 mA lo Digital Output Current +20 mA lout Analog Output Current +10 mA Toper Operating Temperature 0, +70 C Tsig Storage Temperature (plastic) - 40,4 125 C Ppmax | Maximum Power Dissipation 500 mw ESD Electrostatic Discharge Pins RxA1, RxAz2, TxA1, TxA2, AVpp, Vcm 1500 V All other Pins 2000 Vv VIl.2 - DC CHARACTERISTICS (Vpp =5.0V 45%, GND = OV, Ta =0 to +70C, unless otherwise specified) VII.2.1 - Power Supply and Common Mode Voltage Table 43 : Power Supply And Common Mode Voltage Symbol | Parameter | Min. | Typ. | Max. | Unit SINGLE POWER SUPPLY (DVpp = AVpbp) Vpp Supply Voltage 4.75 5 5.25 Vv lppa Analog Supply Current 8 mA Ippp Digital Supply Current 32 mA Ipp-LP_ | Supply Current in Low Power Mode 6500 LA Vom Output Common Mode Voltage Vpp/2-5% | Von/2 | Vop/2+5% V Vcm Output Voltage Load Current (see Note 1) DOUBLE POWER SUPPLY (DVpp # AVpp) DVpp Digital Supply Voltage 3.15 3.3 3.45 Vv AVpp | Analog Supply Voltage 4.75 5 5,25 V lppa Analog Supply Current 8 mA Ippb Digital Supply Current 20 mA Vcm Output Common Mode Voltage (see Note 1) Vpp/2-5% | Vppfe | Vpp/2+5% Vv Note 1: Device is very sensitive to noise on Vcm Pin. Vcm output voltage load current must be DC {<10uA). in order to drive dynamic load, Vcm must be butfered. AC variation in Vom current magnitude decrease A/D and D/A performance. VII.2.2 - Digital Interface (All digital pins except XTAL pins) Table 44 : Digital Interface Symbol | Parameter Min. | Typ. | Max. | Unit (Ta = 25C, DVpp = +8.3V) Vit Low Level Input Voltage 0.8 V Vin High Level Input Voltage DVpp-0.5 Vv li Input Current V; = Vop or Vi = GND -10 +1 10 pA Vou High Level Gutput Voltage (ILoap = -1 mA) DVpp-0.5 V VoL Low Level Output Voltage (ILoap = 1mA) 0.4 Vv Cin Input Capacitance 5 pF (Ta = 25C, DVpp = +3.3V) ViL Low Level Input Voltage -0.3 0.5 Vv Vin High Level Input Voltage DVpp-0.5 Vv lI Input Current Vi= Vpp or Vi = GND -10 +1 10 pA Vou High Level Cutput Voltage (ILoap = -600pA) DVpp-0.5 Vv VoL Low Level Output Voltage (ILoap = 800,1A) 0.3 Vv 42/53 GS-THOMSON MICROELECTRONICS iL,STLC7545 Vil - ELECTRICAL SPECIFICATIONS (continued) VII.2.3 - Crystal Oscillator Interface (XTAL10,XTAL11} Crystal mode only available at DVpp = 5V otherwise external clock oscillator mandatory. Table 45 : Crystal Oscillator Interface Symbol Parameter Min. Typ. Max. Unit VIL Low Level Input Voltage 1.5 V Vin High Level Input Voltage 3.5 Vv I Low Level Input Current (GND < Vi < Vi_max) -15 LA IH High Level Input Current (Vinmin < Vi< Vpp) 15 LA VII.2.4 - Analog Interface Table 46 : Analog Interface Symbol Parameter Min Typ Max Unit VREF Differential Reference Voltage Output = VRerP-VREFN = VREF 2.40 | 2.50 | 2.60 V (with AVpp = 5V) Tempco (VrReF) | VRer Temperature Coefficient 200 ppm/?C Vocwo IN Input Common Mode Ctfset Voltage = FA Pee Vem -300 300 mV VDIF IN Differential Input Voltage : RxA1-RxA2 <= 2*VRer 2* VReF Vpp VorF IN Differential Input DC Offset Voltage : RxA1 = RxA2 = Vom (1) -100 100 mV Vomo our Output common mode voltage offset = DANSE Vom 200 200 mv VbIF our Differential Output Voltage : TxA1-TxA2 <= 2*VRer 2* Vrer Vpp VoFF OUT Differential Output DC Offset Voltage : (TxA1 - TxA2) -100 100 mv Vout Output Voltage EYEX,EYEY GND VDD Vv Rin Input Resistance RxA1, RxA2 100 kQ Rour Output Resistance TxAl ,TxA2 20 Q EYEX, EYEY 50 Q Re Load Resistance TxA1 ,TxA2 16 kQ EYEX, EYEY 1 MQ CL Load Capacitance TxA1 ,TxA2 20 pF EYEX, EYEY 30 pF Note 1 : Input DC offset can be cancelled by high-pass filtering in IIR2 filter 43/53 GS-THOMSON TH WickozLecrROMIGSSTLC7545 Vil - ELECTRICAL SPECIFICATIONS (continued) VII.3 - AG ELECTRICAL SPEGIFICATIONS (Vpp = 5.0 V +5%, Ta = 0 to +70 C) Output Load = 50 pF, Reference levels : Vi_ =0.8 V, VIH =2.2 V, VoL =0.4 V, VoH =2.4V VII.3.1 - Serial Channel Timing Table 47 : Serial Channel Timing Number Parameter Min. Typ. Max. Unit 1 BCLKX, BCLKR Period 300 ns 2 BCLKX, BCLKR Width Low 135 ns 3 BCLKX, BCLKR Width High 135 ns 4 BCLKX, BCLKR Rise Time 30 ns 5 BCLKX, BCLKR Fall Time 30 ns 6 FSX, FSR to BCLKX, BCLKR Setup 100 ns 7 FSX, FSR to BCLKX, BCLKR Hald 100 ns 8 TxDI, RxD! to BCLKX, BCLKR Setup 20 ns ) TxDI, RxDI to BCOLKX, BCLKR Hold 0 ns 10 BCLKX, BCLKR High to TxDO, RxDO Valid 50 50 ns 11 BCLKX, BCLKR To TxDO, RxDO Hiz 50 50 ns Figure 12 : Serial Channel Timming BCLKX {BCLKR) Fsx (Fsr) TxDl (RxD) 7545-14.EPS 44/53 E G5-THOMSON TH MierosLecrronesSTLC7545 Vill - TRANSMIT CHARACTERISTICS VIll.1 - TEST CONDITIONS The Tx characteristics depend on the transfer function of the transmitfilter. The indicated performance is measured when IIR1 filterimplements the 8th order low-pass transfer function (including sinx/x correction) shown in Figure 13. This is achieved by loading the coefticients given in table 48. The frequency response in Figure 13 includes the gain of 72.25cB in front of the biquad 1 (see Figure A1) Figure 13 : Filter Transfer Function (Sampling frequency = 48000Hz, Fsx = 9600Hz, Sample of group delay = 1/5 x Fsx) Frequancy rasanase & He Eo 10009 Hz Cosfficients: li bite plus sion t T t F T T i 5 t } 1 ng 2 " 5 oe bone & me Be Seae Fes? | e : ; Porm : Seale Interval 5 Ez i I 1 i ' t t 4 ~2H ee ee ye ee ae ee me 7 + z } i boy q Tt i 1 i Bo-p- ol a dh LL Le 4 | ' poof aah i i t \ ft iL L 1 t q a Pay { f f l i 68 meme pe mame ay a er TP ai SS ee a K ; t 1 1 on t i 1 i Me i. LLL OLE Tag mie att ee wen he mee teow q P i et t eo 1 i A ' ! i F 4 t { t a ' 1 sr ST arm id TT OT T i ' ' ws ey t # 1 roy i Ho bP wt et a tet 1 t OF ' i p poser ee ' 1 i mah t i Spgs ie Pee % | 5 t t t ac I B -iee | | ; ; | | 1 a I 2 Z 7 3 b 7 FREEZURRE eb daaalisg ireguency H0RRr Table 48 : Interpolator Filter Coefficients WORD | 7200,9600 | WORD | 7200,9600 | WORD | 7200,9600 | WORD | 7200,9600 | WORD | 7200,9600 1 0000,0000 g 0000,ca08 17 4c98,5070 25 a000,a000 33 0750,0858 2 0000,0000 10 0000,a000 18 2438 3508 26 adb8,ac18 34 6aa8 4098 3 a000,a000 11 6368 ,b570 19 d7a8,cfaO ef 5e70,6118 35 a000,a000 4 0000,0000 12 4400 ,48a0 20 a000,a000 28 0748,07a0 36 0000 0000 5 0000,0000 13 0200 2838 al af18,aed8 29 a280 3368 37 0000 0000 6 0000,b7d8 14 d330,cb68 22 5690,59d0 30 a000 a000 38 0008 0008 7 0000,42b0 15 a000,a000 23 2118,2898 31 a910,adfo - - 8 a000,0118 16 b118,b268 24 4f80,dds0 32 5120,5338 - - Filter coefficients (HEX FORMAT) tor Fsx equal to 7200 and S600Hz respectively VIII.2 - PERFORMANCE OF THE Tx CHAIN (from IIR1 filter input to (TxA1-TxA2) output) Typical values are given for Vpp =+5V, Tamb = 25C and for nominal crystal frequency FQ = 36.864MHz. Measurementband = 300Hz to 3.4KHz- Tx DPLL free running. Table 49 : Performance of the Tx chain Symbol Parameter Min | Typ | Max | Unit Gabs Absolute gain at 1kKHz -0.5 0 0.5 dB THD Total harmonic distortion (differential Tx signal : Vout = 1.6Vpp, f= 1kKHz, OverSampling ratio 160) Fsx = 7200Hz -89 dB Fsx = 9600Hz -89 dB DBR Dynamic range (1) (f = 1KHz, OverSampling ratio 160) Fsx =7200Hz 91 dB Fsx = 9600Hz 92 dB PSRR_ | Power supply rejection ratio (f = 1kKHz, Vac = 200mVpp) 50 dB CTxRx | Crosstalk (transmit channel to receive channel) 95 dB Note 1 : Measured over the full 0 to Fsx/2 with a -10dBrinput and extrapolated to fullscale VIIL3 - SMOOTHING FILTER TRANSFER CHARACTERISTICS The cut-off frequency of the single pole switch-capacitor low-pass filter following the DAG (Figure 1) is te-3dB= 128*F sx/(2*n"10) or fc-3dB= 160*Fsx/(2*1*10) 45/53 & GS-THOMSON TH WickozLecrROMIGS 7545-15.7 IFSTLC7545 IX - RECEIVE CHARACTERISTICS IX.1 - TEST CONDITIONS The Rx characteristics depend on the transter function of the receive filter. The indicated performance is measured when IIR2 filter implements the 6th order band-pass transfer function shown in Figure 14. This is achieved by loading the coefficients given in Table 50. Figure 14: Filter Transfer Function (Sampling frequency = 48000Hz, Fsx = 9600Hz, Sample of group delay = 1/5x Fsx) Fraguency respunse et Hz te Mage Ha Coefficients: ib hits plus sian i = t ce ag, (Sauptes) neevval LH? "y i il ! it Sle we dowd oS oo Ce a eras ne bee ae ac De) TRIE femefe mn one BE 3 a FREREER EH iat aampling Tragusncy 4ROO0HE Table 50 : Decimator Filter Coefficients WORD | 7200,9600 | WORD | 7200,9600 | WORD | 7200,9600 | WORD | 7200,9600 | WORD | 7200,9600 { 0000,c000 g 0000,e000 17 4d90,4250 25 a000,a000 33 0d38,0618 2 o000,c000 10 e000,0000 18 25b8,2890 26 ab60,b5b0 34 0000, 1a38 3 ad00,a000 11 b2c0,bf38 19 d1b0,ca18 27 5a40,4e88 35 a000,a000 4 0000,0000 12 59984188 20 a000,a000 28 09b8,238 36 0000, C000 5 0000,0000 13 128,0188 21 b1f8,b748 29 230,d620 37 0000, 0000 8 0000,0000 14 4c80,e000 22 4668 4748 30 a000,a000 38 0008, 0008 7 0000,0000 15 a000,0000 23 1408,1b98 31 a088,b470 - 8 2018 3208 16 a5e0,b8e0 24 de78,cc80 32 6a30,5468 - Filter coefficients (HEX FORMAT} tor Fsx equal to 7200 AND S600Hz respectively IX.2 - PERFORMANCE OF THE Rx CHAIN (from (RxA1-RxA2) input to IIR2 filter output) Typical values are given for Vop =+5V , Tamb =25C and for nominal crystal frequency FQ=36.864MHz. Measurementband = 300Hz to 3.4KHz- Tx DPLL free running. Table 51: Performance of the Rx chain Symbol Parameter Min | Typ | Max | Unit Gabs Absolute gain at 1 KHz -0.5 0 0.5 dB THD Total harmonic distortion (differential Rx signal: Viy = 1.6 Vpp, f = 1kKHz, OverSampling ratio 160) Fsx = 7200 Hz -89 dB Fsx = 9600 Hz -89 dB DR Dynamic range (1) f = 1KHz, OverSampling ratio 160 Fsx = 7200 Hz 91 dB Fsx = 9600 Hz 92 dB PSRR_| Power supply rejection ratio (f = 1KHz, Vac = 200mVpp) 50 dB CTxRx | Crosstalk (receive channel to transmit channel) 95 dB Note 1 : Measured over the full 0 to Fsx/2 with a -10dBrinput and extrapolated to fullscale 46/53 E G5-THOMSON TH MierosLecrrones 7545-18.TIFSTLC7545 X - TYPICAL APPLICATIONS X.1 - MULTI-STANDARD MODEM WITH ECHO CANCELLING Figure 15 : Multistandard Modem with Echo Cancelling Capability To Terminal V.24 Interface CO 7 System ; Bus I fo l ~ [ Mcu [\~ [ [ [ [ [ [ | DSP [ Tx }$ te TxA i [ Modem Data, Serial STLC7545 | Analog Interfaces AFE Signals Rx jij RxA at__ I [ [ [ Modem Clocks t [ t X.2 - LINE INTERFACE Figure 16 : Ditferential Duplexer TxAl TxA? RaAl RxA2 13. 2k LH hb C : Improve the low frequency response. Its value depends on the transformer inductance. C: Reduces the DC offset gain. ZO : Nominal line impedance. 13. 2g [HH 100pF ZO? a | ae Cc Phone aR Line ZO/2 TT _ GS-THOMSON TH WickozLecrROMIGS 47/53 7545-17.EPS 7B45-18.EPSSTLC7545 X - TYPICAL APPLICATIONS (continued) X.3 - COMMON MODE VOLTAGE GENERATION AND DECOUPLING Figure 17 : Voltage Decoupling 5.0V AVoo [|_| VRerp Fe 10uF " 4 2.5V ' 47 Fi) 1 00nF OuF 47nF + 1OULF 47nF VaceN T AGNDT * | AGNDR A + Vom au 7545-19.EPS X.4 - CRYSTAL OSCILLATOR Figure 18 : External Components for Crystal Oscillator CRYSTAL ----. |-----[ --------- _ C ( XTALIL XTALIO XTAL2 t t t C STLC7545 c c t 7545-20.EPS 48/53 E G5-THOMSON TH MierosLecrronesSTLC7545 XI - ANNEXE A XI.1 - IIR FILTER OPERATION Each IIR filtering section included in the ST7544 can perform up to seven biquadratic transfer func- tions in cascade, operating at four times the sam- pling frequency (see Figure A1). Each biquad is defined by tive coefficients, A, B, C, D and E {see Figure A2). An additional coefticient ,F, scales the IIR filter output. Unused biquads are mace transparent by pro- gramming A to one and the four remaining coeffi- cients to zero. Such biquads should preferably be located in the first sections of the IIR filter in order to reduce the calculation noise. XI.1.1 - Coefficient Rounding Initially, coefficients of the Tilter to be implemented must be exclusively between +2 and -2. To derive the actual usable 12+1 bit coefficients, the rounding process described in Figure A3 must be performed. Each 13 bit coetticient K is split into its doubling factor K2, and its 12 bit basic value K1, as the IIR architecture works with 12 bit coefficients and uses an extra accumulation when coefficient doubling is needed. K2 [0,1] and-2"? <K1 <+2" The coefficients are loaded into the different IIR filters through 16 bit wide time slots. The format to be used is as follows : MSB K1 LSB K2 (12-bit) ooo (1 bit) (3-bit) ionen anne 16 bit word -------- > To programme one IIR filter it is necessary to send Figure A1 : IIR Filter Diagram five words per biquad followed by two additional words set to zero and the F coefficient word : B1), (1}, AC), DO), EC}, B2),..., E(7), O000n, 0000, F The total number of words sent is therefore 38. X1.1.2 - Detailed Operation The architecture of the device supporting the IIR filter is based on 28 bitdata path. The basicfunction is as follows: one coefficient K(N) is multipled by one sample X(N) followed by one accumulation with value clampling. It can be precisely described as follows : FUNCTION PAC K(N), X(N), S LOCAL P P = TRUNG (K1(N) x X(N)/2'%) S=S+P IF ABS(S) > 27 THEN IF SIGN(S) >O THEN CLAMP STO 2-1 ELSE CLAMP S$ TO 2 IF K2(N) =1 THENS =S+P IF ABS(S) > 227 THEN IF SIGN(S) >0 THENCLAMP STO 2-1 ELSE CLAMP S TO 2 END OF FUNCTION The TRUNC function is a two's complement trun- cature. As previously mentionned, the second accumula- tion is controlled by the doubling facter K2(N). The complete process of computing 16 bit output samples (Vout) from 16 bit input samples (Vin) appears in Figure A4. BIQUAD#1 BIQUAD#2 BIQUAD#?7 Vin | Vin (1) Your (1) AP Vin | Vour 2) Por Rin 9) Your pl Vour Coefficients: AC), B(1),..., E(1) A(2), B(2),..., E(2) A(7), B(7),..., E(7) GS-THOMSON TH WickozLecrROMIGS 49/53 7546-21.EPSSTLC7545 XI - ANNEXE A (continued) Figure A2 : BIQUAD Structure Vg (N) Vin (N} a> 7 + 1 2 Delay Hn(Z) <A 1+ De Ee 1-BZ -GZ Vv, (N) + BIN) DIN} + Delay Vz (N) CIN) E(N} Vour(N) = Vo(N) + D(N) x Vi(N) + E(N) x Va(N) Next Step with : Vo(N) = Vi(N)} Vi(N) = Vo(N) Equation Set: Vo(N) = B(IN) x V1 (N) + G(N) x Vo(N) + ACN) x Vin(N) Vout () N =BIQUAD NUMBER (1:7) Figure A3 : IIR Coefficients Rounding STARTING COEFFICIENT K(N) (-2 < k(N) < +2) <> K=A,B,C,D, EorF Yes K2(N) = 0 K2(N) = 1 K1(N) = ROUND (2048*k(N)) K1(N) = ROUND (1024*k(N)) K2=Oor1 K1 = 12-Bit Word 50/53 G7 SGS-THOMSON TH MierosLecrrones 7645-22 EPS 7B45-23.EPSSTLC7545 XI - ANNEXE A (continued) Figure A4: IIR Operating Sequence NEW INPUT SAMPLE ACCUMULATOR RESET | Vig (16-bit) Vy STORAGEIN 28-BIT FORMAT T = 800,, x Vy FIRST BIQUAD N=1 $-0 RECURSIVE COEFFICIENTS PAC BN), , (N),S PAC G(N), Ve (N),S PAC A(N), T, S VO(N) STORED INTO T DIRECT COEFFICIENTS PAG D(N), V, (MN), S PAC E(N), V, (N),S STORED INTO T STATE VARIABLES UP-DATING Vp (N)=V, (N) FOR THE NEXT COMPUTATION V, (N) = Temp Vour (N) STORED | Ts INTO T t NEXT BIQUAD | N=N+1 No Yes S-0 OUTPUT SCALING COEFFIECIENT PACETS IIR OUTPUT SAMPLE v | IIR OUTPUT SAMPLE LOADED INT Veu7 AFTER 16-BIT SATURATION (NEW OUTPUT SAMPLE) Vout =T IF GREATER THAN 16-BIT THEN GLAMPED TO 7FFF,, OR 8000 ,, GS-THOMSON TH WickozLecrROMIGS 51/53 7545-24. EPSSTLC7545 XIl- PACKAGE MECHANICAL DATA 44 PINS - PLASTIC GHIP GARRIER (PLCC) B c M Ln | noo ooo 6 214 a 7 Ml sl ql OQ . PMLPCC44 EPS ad A di I | [ZIG tseatng Pane Copknarty) 2 : : Millimeters Inches Dimensions - = Min. Typ. Max. Min. Typ. Max. A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 Cc 3.65 3.7 0.144 0.146 D 42 4.57 0.165 0.180 di 2.59 2.74 0.102 0.108 d2 0.68 0.027 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 F 0.46 0.018 Fl 0.71 0.028 G 0.101 0.004 M 1.16 0.046 M1 1.14 0.045 PLOC44.TBL 52/53 G7 SGS-THOMSON TH MierosLecrronesSTLC7545 XIl - PACKAGE MECHANICAL DATA (continued) 44 PINS - PLASTIC QUAD FLAT PAGK (THIN) (TQFP) A AZ Al H. : Th 7 bar c K Dimensions : Millimeters : Inches Min. Typ. Max. Min. Typ. Max. A 1.60 0.063 Al 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 B 0.30 0.35 0.40 0.012 0.014 0.016 Cc 0.09 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 El 10.00 0.394 E3 8.00 0.315 K 0 (Min.}, 7 (Max.) L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 0.039 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical componentsin life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of IC Components of SGS-THOMSON Microelectronics, conveys a license under the Philips 2 I SGS-THOMSON Microelectronics GROUP OF COMPANIES Patent. Rights to use these components in a PC system, is granted provided that the system conforms to the FC Standard Specifications as defined by Philips. Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. GS-THOMSON TH WickozLecrROMIGS 53/53 PMTQFP44.EPS TOFP444. TBL