11551 new cover Multimedia 23/9/97 5:31 PM Page 2 Semiconductors for Multimedia PC Designer's guide - October 1996 Philips Semiconductors 1 MULTIMEDIA PC DESIGNER'S GUIDE Contents Section 1 2 3 4 5 6 7 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 System level examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 TV, radio and MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Video capture and editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Video conferencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Camera front-ends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Videographics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Review of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Desktop video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Digital video decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Digital video scalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Digital video encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 PCI bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Video analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Video digital-to analog converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Miscellaneous ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Sample analog ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 Television . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Analog TV tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Sound decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Closed caption/teletext decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Digital cable/satellite ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 PC radio modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Multimedia/radio boards with R(B)DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Digital radio systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Compact disc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 CD systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Integrated CD decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 CD-ROM & CD-R/E datapath ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Diode amplification and laser supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Digital servo controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Servo power drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Multimedia PC 1-1 INTRODUCTION 1 8 9 10 11 12 13 Digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 CODECs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Stereo filter DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Low power stereo DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Audio MPEG decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Other audio ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Camera and miscellaneous ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 A/D interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Camera DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Miscellaneous ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Bus ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Universal Serial Bus ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 IEEE 1394-1995 ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Reference/evaluation boards and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Digital video decoder/encoder module system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Demoboards & evaluation kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 General software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 TriMedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 TM-1: the first in a family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Typical TM-1 PC applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 Appendices 1 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 2 Glossary of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 3 Index of type numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 1-2 Multimedia PC INTRODUCTION UNIQUELY QUALIFIED IN PC-BASED MULTIMEDIA SOLUTIONS The Multimedia PC is finally earning its name. First a business and professional tool driven by such things as video editing, video conferencing and office-based applications, the MPC is now invading the home, with new functions such as TV, radio, VCR, phone, newspaper, games, books, picture album and more. Philips Semiconductors is in a uniquely strong position both to satisfy customer needs in this rapidly growing market and provide technology leadership. One of the world's largest semiconductor manufacturers, Philips Semiconductors has in house a vast strength in depth of applied multimedia technology expertise and can draw on the product and market knowledge of a sister consumer electronics division, to offer complete solutions for the MPC. A leader in digital video processing Philips offers a very large range of solutions in digital video. Our families of highly integrated multistandard decoders and encoders offer very high quality performance, for such PC-based applications as video editing and video conferencing. Other ICs offer high performance scaling and many devices in the chipset have on-board colour processing, conversion and filtering functions. And for a truly complete video offering, Philips has video A/D and D/A converters, camera DSPs, single-chip monitor ICs and so on. Exploiting the latest bus technologies Philips is applying their PCI bus expertise in their latest desktop video processing and graphics ICs, to deliver real-time processing and capture of video and graphics in the PC. Outside the PC, Philips is first to the market with a USB transceiver and stand-alone HUB and has USB audio DACs and monitor microcontrollers in development, ideal for low data rate "plug `n' play" multimedia PC devices. And Philips also has ICs for an enhanced version of the IEEE P1394 worldwide multimedia connection standard, allowing it to carry MPEG-2 streams. MPEG decoding As one of the members of MPEG, Philips is playing an active role in developing and refining MPEG compression standards. The depth of Philips expertise is reflected in the quality of its MPEG ICs, which implement the standards in full, delivering excellent decompression quality for both audio and video. Philips has a family of dedicated audio MPEG-1 and MPEG-2 decoders including versions with enhanced error correction for digital radio; and a highly integrated audio/video/graphics MPEG-2 decoder for digital TV applications. TV and radio, digital and analog Analog TV solutions for the PC cover all worldwide standards and, by drawing on their extensive RF expertise and shielding know-how, Philips is the first semiconductor manufacturer to Multimedia PC 1 offer a high quality radio for the PC, including R(B)DS functionality. Recent digital TV and digital radio solutions for the PC draw on technologies and ICs developed for broadcast applications. Solutions for all CD systems As one of the pioneers of CD, Philips today can offer complete system solutions for all the various CD technologies. We have high-speed CD-ROM decoders and a range of highly integrated datapath ICs offering speeds up to 12x for IDE and SCSI applications. Our extensive offer also includes the world's first singlechip CD-Recordable/Erasable interface IC covering both IDE and SCSI systems, offering 8x speed read and 4x speed write. Digital audio for all multimedia needs A world leader in digital audio, Philips' Bitstream technique delivers the highest conversion performance available today, with Continuous Calibration delivering low power, economy solutions. Our range of ADCs/DACs is second to none; we have single-chip sound-channel processing ICs for a number of PC applications; and the first of a leading-edge audio CODEC family offers six-channel digital mixing, on-board audio synthesis and a host of other sound processing functions, making it effectively a single-chip sound card. Next generation programmable multimedia By combining cost-effective advanced microprocessor technology, easy programmability and comprehensive software tools, Philips TriMedia family provides a complete, high performance programmable multimedia solution. At the core is a next-generation DSP/CPU which integrates the power of a DSP with a robust, CPU style software environment, to offer true multimedia processing - the concurrent processing of audio, video, graphics and communications. By combining the power of DSP technology with a breakthrough software architecture which allows programming in familiar high level language, together with an instruction set optimized for multimedia, TriMedia is more than powerful enough to drive the next generation of multimedia products. It is fully supported with extensive software development tools. For more information on TriMedia, see Section 13. Systems and application support - worldwide Philips provides not only a large number of individual ICs, but also many complete chipset and system solutions for a number of MPC applications, all backed by reference designs, demoboards and software. Customer support is available worldwide and there are dedicated MPC groups in the USA (Sunnyvale) and Europe (Hamburg, Germany), each with their own development groups. Extensive applications and design-in support is provided through five Systems Laboratories in Sunnyvale (USA), Eindhoven (the Netherlands), Hamburg (Germany), Southampton (UK) and Taipei (Taiwan). 1-3 2 SYSTEM-LEVEL EXAMPLES Multimedia PC 2-1 SYSTEM-LEVEL EXAMPLES 2 Philips supplies all the ICs, software and system support for virtually any MPC application and some chipset/system examples are shown here. They are not necessarily intended as real-life designs, but to show how Philips ICs fit together to provide all the functions that might be needed, in an add-in card or for integration onto the motherboard. TV, RADIO AND MPEG With just a few ICs, a computer can be turned into a TV to allow video capture for editing, desk top publishing or video conferencing. Philips TV Tuners, available from Philips Components, accept the signal from a cable TV or TV aerial. By adding further elements, radio can be included and with the addition of ICs for MPEG decoding, a multifunction card can be built with TV, radio and MPEG playback from CD-ROM (for Video-CD applications). Closed Caption and Teletext Decoders Philips has a very broad range of ICs for decoding closed caption, teletext or Intercast data sent in the vertical blanking interval (when no active video is transmitted). For data and text extraction the ICs receive the analog composite video signal, locate the horizontal line where the digital data is embedded, recover the clock and extract the data. After error detection and correction, the text data are assembled and stored; the PC is interrupted when a line or page of data is available. A basic (analog) TV board The composite video signal is sent to a video decoder to generate digital YUV images and extract the closed caption or teletext information from the TV signal. The scaler allows manipulation of the YUV image and transmits it, together with the CC/TT information, to the PCI Bus. The composite audio signal from the tuner is decoded by a stereo SAP decoder, while tone control and similar functions are provided by sound processing ICs, after which it is amplified. CV or S Video cable TV or TV antenna FI1236 TV & CABLE TUNER CV SAA7111(A) VIDEO & TEXT DECODER YUV I2C I2 S SAA7146 PCI INTERFACE PCI bus GRAPHIC CONTROLLER Audio TDA9850 STEREO AUDIO DECODER TEA6320 STEREO AUDIO CONTROL TDA1517 STEREO 2x6W AMPLIFIER MSC223 Scaling Scaling may be required in almost any MPC application, often because the video image in the Windows environment will be scaled to an arbitrary size by the user. Also, images are often scaled to reduce the bandwidth when sending data to the hard disk, or the size and format of the image may need to be changed to match the requirements of compression and graphics controller ICs. 2-2 FOR MORE INFORMATION ON.. Cable/terrestrial TV tuners Digital video decoding PCI interfacing SEE PAGE 5-12 4-2 4-18 Scaling 4-8 Audio processing 8-1 CC/teletext decoding 5-6 Multimedia PC SYSTEM-LEVEL EXAMPLES Digital TV board Philips is the first semiconductor manufacturer to supply integrated solutions for both digital cable and satellite systems. The following chipset is ideal for a PC-based digital broadcast solution or DVB/DAVIC cable modem. 2 For more information on Philips Digital Media Broadcast ICs, see Section 5. cable TUNER TDA8046 QAM CABLE DEMODULATOR TUNER TDA8042/43 QPSK SATELLITE DEMODULATION SAA7207 FORWARD ERROR CORRECTION SAA7206 ACCESS CONTROL (DESCRAMBLE) SAA7205 DATA SEPARATOR (DEMUX) SAA7124 VIDEO ENCODER video SAA7201 AUDIO PROCESSING (DECOMPRESS) L TDA1388T AUDIO DAC VIDEO PROCESSING (DECOMPRESS) audio R MSC227 A complete radio/TV and MPEG (video-CD) playback board This board incorporates the basic TV functionality described above, but also includes Philips high performance radio for PCs. An MPEG decoder could also be added, for display of compressed data, often from a CD-ROM or Video-CD. Radio Philips PC FM radio tuner receives the FM signal from a TV or antenna. The tuner produces a stereo signal output, which is Ato-D converted and sent to the PCI bus. Philips also makes ICs for an Astra Digital Radio (ADR) receiver and for a Digital Audio Broadcast (DAB) channel decoder. Video-CD in the PC Video-CDs contain 74 minutes of MPEG-1 compressed audio and video, read from the CD and sent via the ISA port of the PCI bridge to the MPEG decoder for decompressing into digital YUV video and digital I2S audio. The PCI bridge becomes PCI bus master and bursts the digital video image and digital audio sound to any desired memory location in the PC. Decompressed images can also be sent to a TV via a digital video encoder. For CD applications, Philips has high-speed CD decoder ICs and a range of datapath ICs for CD-ROM and CD-Recordable/ Erasable systems. Through a sister division, Philips Key Modules, Philips also offers complete CD engines. Multimedia PC CV or S Video cable TV or TV antenna FI1236 TV & CABLE TUNER CV SAA7111(A) VIDEO DECODER YUV CV MPEG 1, TV and radio in the computer Audio TDA9850 STEREO AUDIO DECODER YUV MPEG 1 A/V DECODER radio 75 antenna SAA7185 VIDEO ENCODER TDA7366 STEREO AUDIO A/D FM RADIO TUNER audio ISA SAA7146 audio BIDIRECTIONAL PCI INTERFACE PCI bus COMMUNIC. LINK RAM CPU RAM FOR MORE INFORMATION ON.. Cable/terrestrial TV tuners CD-ROM GRAPHIC DISPLAY RAM MSC224 SEE PAGE 5-12 Digital video decoding 4-2 Digital video encoding 4-12 Radio systems 6-1 PCI interfacing 4-18 Scaling 4-8 Audio processing 8-1 CD systems 7-1 CC/teletext decoding 5-6 2-3 SYSTEM-LEVEL EXAMPLES VIDEO CAPTURE AND EDITING 2 Computer monitors display "square pixels" with 640 horizontal pixels and 480 vertical pixels. As the display screen has the same aspect ratio of 4 x 3, the 640 x 480 pixels are equally spaced horizontally and vertically. Video communication and compression standards employ the international CCIR 601 digitizing standard, specifying 720 samples during the active portion of the video signal. Philips offers both square-pixel and CCIR-601 compliant decoders. PC buses and video capture/editing architectures Live multimedia capture provides continuous video and audio data streams at very high data rates (more than 20 Mbytes/ second). Data that is not captured is lost and playback which has gaps and interruptions is quite disturbing, so availability of enough bandwidth at the right time is crucial - predictable scheduling and bandwidth allocation on the video bus is thus a major issue. In most consumer applications, audio has the highest priority as any gaps in audio data produces unacceptable "clicks". Video data is secondary, as previous images can be repeated with little noticeable effect if video data is lost. Shared frame buffer architecture for playback The shared frame buffer architecture allows playback of live video and graphics on the computer monitor. If the VGA graphics controller in the graphics card has a digital `video' port, this (de) compress CPU RAM CPU bus CPU allows a low cost videographics system to be built (see example later in this section), but it does not allow video capture. PCI architecture for playback, capture and editing The PCI architecture, with its typical bandwidth of 100 Mbytes/second, is the only architecture allowing live video playback and capture in the PC. It frees the local bus for normal CPU system traffic, with video conducted on the PCI bus. The architecture is a "shared memory" structure, where live images are decoded and scaled by the video capture engine and sent to the desired memory location in the computer. An arbiter manages and distinguishes the real-time importance of each PCI master requesting the bus, increasing the robustness of the PCI bus and its capability to recover from an error. Philips video capture and scaling ICs treat the odd and even fields of interlaced video images independently. In a video editing application, the odd field of the image from the VCR is sent directly to the frame buffer RAM of the graphics controller to monitor incoming images. The even field can be scaled down and sent to the hard disk for storage and editing. This independent odd/even field system is also exploited in video conferencing applications (see next example). FOR MORE INFORMATION ON.. Digital video decoding 4-2 PCI interfacing 4-18 Scaling 4-8 video capture communicate display SAA7110A/ SAA7111(A) VIDEO DECODER CODEC RAM GRAPHICS CONTROLLER RAM SAA7146 SCALER + PCI INTERFACE PCI INTERFACE PCI INTERFACE PCI bus SEE PAGE MSC225 PCI INTERFACE HDISK CD-ROM edit 2-4 Multimedia PC SYSTEM-LEVEL EXAMPLES VIDEO CONFERENCING In video conferencing application, the odd field of the image from the local camera (the `vanity' image) is sent directly to the frame buffer RAM of the graphics controller, to be displayed on the computer monitor. The even field is scaled down and sent to the video conferencing compression engine. SAA7110A SAA7111(A) VIDEO DECODER CV Video conferencing systems are also easily implemented with Philips high power, programmable multimedia processor, TriMedia, described in Section 13. 2 TV or VCR SAA7366 PREAMP + AUDIO A/D microphone Video conference application using a PCI bridge IC The PCI interface/scaler acts as a four way bridge. It receives digital YUV images from the video decoder, scales them and bursts them to the computer PCI bus for local display on the monitor, compression and transmission via a phone line, ISDN line or LAN. When images are received by the computer, it decompresses, scales and/or zooms the images, which are then encoded into baseband or S-video signals for TV display or VCR recording. The PCI bridge also sends and receives digital sound in I2S format; it can interface with an ISA-bus based MPEG-decoder via its DEBI port; and it can read closed caption and teletext data from a video decoder or a dedicated decoding IC. SAA7125 SAA7185B VIDEO ENCODER YUV I2S SAA7146 SCALER + PCI INTERFACE I2S TDA1388T AUDIO D/A + AMP speakers video conference system PCI bus monitor phone line SOFTWARE OR HARDWARE (DE) COMPRESS MODEM GRAPHIC CONTROLLER MSC226 FOR MORE INFORMATION ON.. SEE PAGE Digital video decoding 4-2 Digital video encoding 4-12 PCI interfacing 4-18 Scaling 4-8 Audio processing 8-1 CC/teletext decoding 5-6 Programmable multimedia processors 13-2 CAMERA FRONT-ENDS Philips also makes the video camera DSPs and A/D interfaces needed for a complete video conferencing system. For more information on camera A/D interfacing and DSPs, see Section 9. CCD CORRELATED S/H + AGC ADC TDA8786 SAA8110 CCD DRIVERS TIMING GENERATOR analog CV, S-Video or digital YUV CAMERA DSP MSC228 Multimedia PC 2-5 SYSTEM-LEVEL EXAMPLES VIDEOGRAPHICS 2 FOR MORE INFORMATION ON.. Using the shared frame buffer architecture described under "video editing" allows a low cost solution for the playback of live video and graphics on the computer monitor, provided the VGA controller in the graphics card has a digital `video' port. SAA7112 DECODER + SCALER S or CV inputs MUX, AMP FILTER SEE PAGE Digital video decoding 4-2 Scaling 4-8 Graphics 2-6 TEXT SLICER I2C BUS INTERFACE SDA CHROMA CIRCUIT SCALER, YUV-RGB FIFO YUV SCL GRAPHICS ENGINE BITBLT, CLIPPING video port DISPLAY MEMORY CONTROL FRAME BUFFER MEMORY U, V 2 x A/D CONVERT EXPANSION PORT LUMA CIRCUIT Y Vsync Hsync digitized CV or S-Video SYNCHRONIZATION CLOCK GENERATE U, V Y GRAPHICS & VIDEO ACCEL. VIDEO SCALE YUV-RGB RAMDAC CLOCK SYNTHESIZER MSC229 2-6 Multimedia PC 3 REVIEW OF ICs Multimedia PC 3-1 REVIEW OF ICs SELECTION CHART DESCRIPTION TYPE NUMBER PACKAGE PAGE One Chip Front-end (OCF) SAA7110A PLCC68 4-2, 3 Video Input Processor SAA7111(A) PLCC68 4-2, 4 Desktop video DIGITAL VIDEO DECODERS 3 QFP64 SAA7111A only TQFP64 Decoder with HPS scaler for image port SAA7112 LQFP100 4-2, 5, 9 Digital video decoder and scaler (DESC-Pro) SAA7196 QFP120 4-2, 7, 9 Digital video scaler SAA7186 QFP100 4-9, 10 High Performance Scaler (HPS) SAA7140A/B TQFP128 4-9, 11 EURO-DENC digital video encoder SAA7182/83 PLCC84 4-12, 14 EURO-DENC2 digital video encoder SAA7182A/83A QFP80 4-12, 13 ECO-DENC digital video encoder SAA7124/5 PLCC84 4-12, 15 DIGITAL VIDEO SCALERS DIGITAL VIDEO ENCODERS QFP80 LQFP64 DENC-M6 digital video encoder SAA7184/85B PLCC88 4-12, 16 DENC-M digital video encoder SAA7188A/85 PLCC88 4-12, 16 DENC2 Square pixel digital video encoder SAA7187 PLCC88 4-12, 16 CCIR and square pixel digital encoder with genlock SAA7199B PLCC84 4-12, 17 SAA7146 TQFP208 4-9, 18 Triple RGB 6-bit ADC interface TDA8707 QFP44 4-20 Video analog input interface TDA8708A/B SO28L 4-20, 21 PCI BRIDGES Scaler and PCI bridge (SPCI) IC VIDEO ANALOG-TO-DIGITAL CONVERTERS DIP28 Video analog input interface TDA8709A DIP28 4-20, 22 TDA8709A(T) SO28L 4-20, 22 TDA8758 TQFP48 4-20, 23 TDA8702 DIL16 4-24 TDA8702T SO16 4-24 TDA8712 DIL16 4-24 TDA8712T SO16 4-24 Triple 8-bit video DAC TDA8771A QFP44 4-24, 25 Triple 8-bit video DAC TDA8772(A)H(3/8) QFP44 4-24, 26 Triple 10-bit video DAC TDA8775G LQFP48 4-27 Video Enhancement and D/A processor SAA7165 PLCC44 4-28 Mixer and D/A processor SAA7167(A) TQFP48 4-29 Low power A/D interface VIDEO DIGITAL-TO-ANALOG CONVERTERS 8-bit video DAC 8-bit video DAC 3-2 Multimedia PC REVIEW OF ICs DESCRIPTION TYPE NUMBER PACKAGE PAGE Digital colour space converter (DCSC) SAA7192A PLCC68 4-30 Video and Memory Controller (VMC) SAA7195A QFP160 4-9, 31 Sync. Separator IC for monitors TDA4820T SO8 4-32 4 x 4 video switch matrix TDA8540 DIL20 4-33 TDA8540T TSO20 4-33 MISCELLANEOUS ICS 3 SAMPLE ANALOG ICS Generic multistandard analog decoder Baseband delay line PAL/NTSC analog encoder TDA4655 SDIL24 4-34 TDA4655T SO24 4-34 TDA4665 DIL16 4-35 TDA4665T SO16 4-35 TDA8501 DIL24 4-36 TDA8501T SO24 4-36 SECAM analog encoder TDA8505 DIL32 4-37 Picture signal improvement processor TDA4670 DIL18 4-38 Analog video processor TDA4686 DIL28 4-39 TDA4686WP PLCC28 4-39 TV SOUND DECODERS I2C-bus controlled BTSC stereo/SAP decoder I2C-bus controlled BTSC stereo/SAP decoder and audio processor I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9850 SDIP32 5-2, 3 TDA9850T SO32 5-2, 3 TDA9852 SDIP42 5-2, 4 TDA9855 SHDIL52 5-2, 4 TDA9855WP PLCC68 5-2, 4 TEA5582 DIL20 5-2, 5 Integrated VIP and teletext decoder SAA5246A QFP64, DIL48 5-6 Integrated VIP and teletext decoder with background memory controller SAA5249 SO24, DIL24 5-6 Integrated VIP and teletext decoder SAA5254 QFP64, DIL40 5-6, 7 Integrated VIP and teletext decoder SAA5281 QFP64, SDIL52 5-6 Software for a range of Teletext decoder ICs PC Text - 5-6 Multimedia VBI and FF data acquisition IC SAA5284 QFP44 5-6, 7 Line 21 decoder SAA5252P DIL24 5-8 PLL BTSC stereo decoder CLOSED CAPTION/TELETEXT DECODERS SAA5252T SO24L 5-8 One-page economy teletext/TV microcontroller SAA5290 SDIP52 5-9 Single-chip economy 10 page teletext/TV microcontroller SAA5296ZP/nnn SDIL52 QFP80 SDIL52 5-10 5-10 5-10 SAA5296GP/nnn SAA5299ZP/nnn (EEPROM) DIGITAL CABLE/SATELLITE ICS Range of ICs from Philips Digital Media Broadcast chipset Multimedia PC DMB chipset 5-11 3-3 REVIEW OF ICs DESCRIPTION TYPE NUMBER PACKAGE PAGE Radio PC RADIO MODULES Self-tuned radio TEA5757H/5759H QFP44 6-3 Remote 8-bit I/O expander for I2C-bus PCF8574P/AP DIP16 6-4 PCF8574T/AT SO16 6-4 PCF8574TS SSOP20 6-4 R(B)DS controller CCR921 QFP44 6-5 R(B)DS demodulator SAA6579 DIL16 6-6 SAA6579T SO16 6-6 Stereo radio power amplifier TDA1517P SIL9 8-13 Sound processors TEA632X SDIL32 8-14 TDA632XT SO32 8-14 3 MULTIMEDIA/RADIO BOARDS WITH R(B)DS 5-band graphic equalizer TEA6360 DIL32SHR 8-15 TEA6360T SO32 8-15 - - 6-7, 8 CD-ROM subsystem and system solutions (6x and 8x) ROM 65XXX - 7-2 CD-ROM subsystem and system solutions (12x) ROA 1312/X - 7-3 CD-Recordable subsystem E65400 - 7-3 CD-Recordable data engine D65420 - 7-3 CD-Recordable subsystem and CD-R data engine CDU 2600 - 7-3 ACE (All Compact disc Engine) SAA7348 LQFP100 7-4 10x single-chip digital servo processor and compact disc decoder SAA7370(B)GP QFP64 7-5 Error corrector and host interface SAA7388 QFP80 7-6 High performance CD-ROM controller SAA7385 QFP128 7-6, 7 High speed CD-recordable block decoder/encoder SAA7390 QFP128 7-6, 8 Photodetector amplifiers and laser supply TDA1300T SO24L 7-9 Data amplifier and laser supply TZA1015 SO28 7-10 OQ8868 QFP44 7-11 Digital radio systems Compact Disc CD SYSTEMS INTEGRATED CD DECODERS CD-ROM & CD-R/E DATAPATH ICS DIODE AMPLIFICATION AND LASER SUPPLY DIGITAL SERVO CONTROLLER Digital servo controller 3-4 Multimedia PC REVIEW OF ICs DESCRIPTION TYPE NUMBER PACKAGE PAGE Digital Servo Driver (DSD1) TDA1303T SO24L 7-12 Triple digital servo driver OQ8844 SO20 7-13 Triple digital servo driver SZA1010 SO20 7-13 BTL motor drive circuits TDA7072A DIP8 7-14 TDA7072AT SO8 7-14 TDA7073A DIP16 7-14 TDA7073AT SO16L 7-14 Low power, low voltage stereo CODEC TDA1309H QFP44 8-2 16-bit stereo CODEC with FM synthesis TDA1396 TQFP128 8-3 Single-chip audio processor TDA1548T(Z) SSOP28 8-4 Single-chip audio processor TDA1388T SO28 8-5 TDA1388TZ SSOP28 8-5 TDA1373 QFP64 8-6 Bitstream ADC SAA7360 QFP44 8-7 Bitstream ADC SAA7366 SO24L 8-7, 8 Bitstream/CC filter DAC TDA1305T(AT) SO28 8-9 Noise shaping filter DAC TDA1306T SO24 8-10 Noise shaping filter DAC TDA1386T SO24 8-10 Low power stereo DACs TDA1311A(T) DIL8/SO8 8-11 Low power stereo DACs TDA1387T SO8 8-11 Audio MPEG-1 decoder SAA2500 QFP44 8-12 Audio MPEG-1 decoder for Astra Digital Radio (ADR) SAA2501 QFP44 8-12 Audio MPEG-1 decoder with MPEG-2 stereo capability SAA2502 QFP44 8-12 Stereo radio power amplifier TDA1517P SIL9 8-13 Sound processors TEA6320/1/2/3 TEA6320S DIL32 8-14 TDA6320T SO32 8-14 TEA6360 DIL32SHR 8-15 TEA6360T SO32 8-15 Single DIP8 6-4, 8-16 Dual SO8 6-4, 8-16 SERVO POWER DRIVERS BTL motor drive circuits 3 Digital audio CODECS DSPS General digital I/O input with DSP (GDIO DSP) ADCS STEREO FILTER DACS LOW POWER DACS AUDIO MPEG DECODERS OTHER AUDIO ICS 5-band graphic equalizer Class AB stereo headphone driver Multimedia PC TDA1308T 8-14 3-5 REVIEW OF ICs DESCRIPTION TYPE NUMBER PACKAGE PAGE TDA8706A DIL20 9-2 Camera and miscellaneous ICs A/D INTERFACES 6-bit ADC with multiplexer and clamp 3 TDA8706T SO20L 9-2 10-bit, high speed 3 V ADC TDA8766 LQFP32 9-3 12-bit high speed ADC TDA8767 QFP44 9-4 10-bit A/D interface for camera CCDs TDA8786(A) LQFP48 9-5 8-bit 40 Msps 2.7 - 5.5 V universal ADC TDA8790 SSOP20 9-6 SAA8110 LQFP80 9-7 UAA3201T SO16 9-8 USB transceiver PDIUSBP11 SO14 10-2 USB stand alone hub PDIUSBH11 SDIP32 10-3 Monitor microcontroller with USB plus hub P83C190 SDIP56 10-3 IEEE P1394 serial bus AV link layer controller PDI1394L11 PQFP80 10-4 IEEE P1394 serial bus AV physical layer controller (in development) PDI1394P11 t.b.f. 10-4 CAMERA DSPS Camera DSP MISCELLANEOUS ICS UHF/VHF remote control receiver Bus ICs UNIVERSAL SERIAL BUS ICS IEEE 1394 ICS 3-6 Multimedia PC 4 DESKTOP VIDEO Multimedia PC 4-1 DESKTOP VIDEO 4 DIGITAL VIDEO DECODERS All Philips decoders offer: Support for PAL and NTSC standards with automatic signal detection 8-bit resolution inputs CVBS and S-Video inputs Line-locked clock decoding RTC output to lock encoding to decoding Output 4:2:2 16-bit YUV/YCrCb signals Brightness, Contrast and Saturation and hue control on the output bus PAL delay line PAL and NTSC chroma filtering Peaking and coring filters On-chip clock generation I2C-bus controllable Philips' current range of digital video decoders includes both CCIR-compliant and square-pixel devices, some with on-board scaling features. All decoders are capable of full multistandard operation, with the CCIR-compatible devices supporting all individual sub-standards. All Philips decoders are highly integrated, with many features and extensive functionality included on chip; all recent ICs include on-board ADCs. PAL, NTSC and SECAM signals are colour decoded using Philips unique line-locked clock feature, in which the decoder drives the clock generator to obtain a sampling clock locked to the line frequency of the incoming signal. This ensures excellent picture quality and an orthogonal sampling structure is maintained, even for non-standard inputs such as VCRs. Philips' unique RTC (Real-Time Control) synchronizes encoding and decoding by locking the encoding process to the decoding. This provides accurate and stable colour rendition at the encoder end, even when the signal is non-standard or subject to adverse affects such as noise; it also provides solid decoding of NTSC signals. The 8-bit chrominance signal is fed into a demodulator and two sub-carrier signals are applied from a local oscillator, at a frequency depending on the current colour standard. Output signals from the demodulators are filtered to achieve the desired bandwidth for the colour difference signals. Chroma filters eliminate cross-talk between the chrominance channels in PAL, and between the chrominance and luminance channels (cross-colour) in NTSC. A PAL delay line is implemented to correct for PAL phase errors. The 8-bit luminance signal is fed through a switchable pre-filter. If it is a CVBS signal, it is then passed through a chroma trap filter to eliminate most of the colour carrier signal. High frequency luminance components can be `peaked' in two bandpass filters with programmable transfer characteristics. Further filtering by a coring circuit improves the signal before it is added to the original `unpeaked' signal. Common DC amplification is achieved using a switchable amplifier, necessary because the DC gains are different in the two chroma trap modes. BCS control is then applied to the improved luminance signal before output. Philips digital video decoders CCIR/Square pixel SAA7110A SAA7111 SAA7111A SAA7112 SAA7196 SQP CCIR-601 CCIR-601 CCIR-601 SQP B, G B, G, H, I, M, N B, G, H, I, M, N B, G, H, I, M, N B, G Supported standards PAL NTSC SECAM M M, N M, N M, N M Yes No Yes Yes Yes Outputs formats YUV CCIR RGB 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:1:1 12-bit 4:1:1 12-bit 4:1:1 12-bit 4:1:1 12-bit - - 656 8-bit 656 8-bit 656 8-bit - 16-bit (5-6-5) - 16-bit (5-6-5) 24-bit (8-8-8) 24-bit (8-8-8) 16-bit (5-6-5) 15-bit (5-5-5) 24-bit (8-8-8) 24-bit (8-8-8) No No No No 8-bit scaled CC/Line 21 data slicer Yes Yes Yes Yes VBI data decoder No No No Yes Yes No Scaling features No No No Yes Yes Dual 8-bit video ADC Yes Yes Yes Yes No Expansion port No No No No Bi-directional Refer to page 4-3 4-4 4-4 4-5 4-7 Other mono 4-2 Multimedia PC DESKTOP VIDEO DIGITAL VIDEO DECODERS SAA7110A OCF (One Chip Front-end) SAA7110 ONE CHIP FRONTEND All features listed in overview (page 4-2) plus: Full multistandard decoding including SECAM Six analog inputs with internal video source selectors (six CVBS, three Y/C or a combination) Outputs YUV signals in 12-bit 4:1:1 or 16-bit 4:2:2 Three analog processing channels with analog signal adding of two channels Three built in anti-alias filters Selectable signal (white) peak control On-chip clock generator uses one 26.8 MHz crystal for all standards CHROMINANCE PROCESSING ADC2 AIN32 AIN31 AIN22 AIN21 AIN12 AIN11 ANALOG INPUT CONTROL UVout/8 BRIGHTNESS, CONTRAST, SATURATION CONTROL ANALOG PREPROCESSING ADC1 LUMINANCE PROCESSING I2 C CONTROL SYNCRONISATION Yout/8 CLOCK GENERATION CIRCUIT CLOCK 4 MBE202 I2 C sync signals This state-of-the-art one-chip solution for video input processing provides D/A conversion of CVBS or Y/C analog signals, multistandard decoding and filtering, and digital YUV output for feature processing. After digitization, pre-processing channels perform automatic gain control, clamping and peak-white limiting of the input signal. As a square pixel decoder working on the basis of the TV-2 system, it generates 768 and 640 active pixels/ line in 50 Hz (PAL/SECAM) and 60 Hz (NTSC) environments. QUICK REFERENCE DATA Power supply Total digital supply current 250 mA Total analog supply current 150 mA Total power dissipation (max.) Package Datasheet (12NC) Multimedia PC 5V 1.7 W PLCC68 (SOT188) 9397 750 00368 4-3 DESKTOP VIDEO DIGITAL VIDEO DECODERS SAA7111/SAA7111A Video Input Processor (VIP)/ Enhanced VIP (EVIP) 4 All features listed in overview (page 4-2) plus: Automatic PAL and NTSC decoding (`A' version also decodes SECAM) Four inputs (four CVBS, two Y/C, or one Y/C and two CVBS) with internal source selection Outputs YUV signals in 12-bit 4:1:1, 16-bit 4:2:2, 8-bit 4:2:2, RGB 5:6:5 or RGB 8:8:8 formats Dual processing channels each contain clamp circuit, analog amplifier, anti-aliasing filter and 8-bit CMOS video ADC Fully programmable static gain control for main channels or automatic gain control for selected CVBS or Y/C channel The SAA7111(A) (E)VIP is essentially a CCIR-601 compliant derivative of the SAA7110A. It has an analog front-end including two analog pre-processing channels with A/D conversion and decodes both PAL and NTSC standards. Each channel includes a clamp circuit, to ensure proper clamping. Levels are assigned to the analog input signals and anti-aliasing filters, adapted to the clock frequency using the filter control. Signals can also be peak white limited. The SAA7111A, a low power variant, also accepts SECAM signals and includes SECAM crosscolour reduction. It has a number of additional functions builtin including a VBI (Vertical Blanking Interval) bypass mode. Boundary scan test On-chip line 21 (CC) slicer VBI data decoder (`A' version) Low power `A' version in LQFP is ideal for notebooks, PCMCIA cards, etc. QUICK REFERENCE DATA Power supply 5 V (3.3 V for `A' version) Total digital supply current 130 mA (70 mA) Total analog supply current 70 mA Total power dissipation (max.) Package 1.26 W (0.5 W) PLCC68 (SOT188); QFP64 (SOT393) LQFP64 (SOT314G8) (SAA7111A only) Datasheet (12NC) SAA7111 9397 750 00847 SAA7111A Contact Philips SAA7111 AOUT BYPASS UV AI11 CHROMINANCE CIRCUIT + BRIGHTNESS CONTRAST SATURATION CONTROL AI12 ANALOG PROCESSING C/CVBS AI22 AI21 IICSA Y I2C-BUS INTERFACE SDA SCL I2C-CONTROL GPSW VPO (0 :15) ANALOG CONTROL LUMINANCE CIRCUIT Y/CVBS YUV-to-RGB CONVERSION + OUTPUT FORMATTER UV Y FEIN HREF CLOCK TDI TCK TMS TRSTN TDO Y' TEST CONTROL BLOCK (FOR BOUNDARY SCAN TEST AND SCANTEST) CLOCK GENERATION CIRCUIT SYNCHRONIZATION CIRCUIT POWER-ON CONTROL XTAL XTALI LLC2 CREF LLC RESN MSB795 - 1 VS 4-4 HS VREF RTS0 RTS1 RTCO VSSA0 VDDA0 CE Multimedia PC DESKTOP VIDEO DIGITAL VIDEO DECODERS SAA7112 Decoder with HPS scaler for image port All features listed in overview (page 4-2) plus: Full multistandard decoding including SECAM Six analog inputs with internal video source selectors (six CVBS, two Y/C and two CVBS, or one Y/V and 4 CVBS) Outputs YUV signals in 12-bit 4:1:1, 16-bit 4:2:2, 8-bit 4:2:2 or RGB 5:6:5 format Dual analog processing channels with source selection, anti-aliasing filters, automatic clamp circuit and an 8-bit CMOS video DAC Fully programmable static gain for main channel or AGC on selected Y/CVBS channel 2-D scaler core based on SAA7140B uses phasecorrect interpolation to deliver excellent signal quality, especially on compressed data Arbitrary horizontal and vertical scaling of between 2x (zoom) and down to x1/64 (icon) Two independent programming sets for scaler, allowing definition of two `ranges' per field or frame QUICK REFERENCE DATA On-chip clock generator uses one 32.11 MHz crystal for all standards Versatile VBI decoder, slicer, clock regeneration and byte synchronization Switchable peak white limiting LLC EXPANSION PORT PIN MAPPING D1 OUT CE XOUT XTALI t.b.f. Package LQFP100 (SOT407) Datasheet (12NC) 9397 750 00923 chroma of 16 bit output mode LPB PROG. X PORT INPUT FORMATTER (SELECT) CLOCK GENERATION AND POWER ON CONTROL t.b.f. Total power dissipation (max.) IIC chroma of 16 bit input mode RESON 3.3 V Total digital supply current HOST PORT PIN MAPPING D1 IN RESIN Power supply HDSNSC HPD[7:0] HRWNF HACNSD HADP HCST XREQ XDQ XRH RTCA RTS1 LLC2 RTS0 XPD[7:0] XCLK XRV XTRI RT OUT 4 PROGRAMMING PORT CONTROL from event controller PROGRAMMING REGISTER ARRAY A/B REGISTER MUX SAA7112 CLOCK MULTIPLEXER INLC. TCB SLEEP MODE REGISTER XTAL AI11, AI12 AI21..AI24 DUAL ADC 7111A BASED DIGITAL DECODER 4:2:2 OUTPUT INTERFACE data, clock, H, V, FID and qualifier INPUT ACQ. CONTROL AOUT FIR-FILTER LUMINANCE FIR-FILTER CHROMINANCE PRESCALING LUMINANCE PRESCALING CHROMINANCE 4:2:2 BCS CONTROL LINE FIFO BUFFER VERTICAL SCALING PROCESSOR LINE MEMORY 1H* 16 BIT HORIZONTAL PHASE SCALING LUMINANCE HORIZONTAL PHASE SCALING CHROMINANCE LPB VID. OUT Vref AMCLK ALRCLK ASCLK AXMCLK AUDIO MASTER CLOCK GENERATION AUDIO BIT CLOCK WORD SELECT GENERATION IPD[7:0] FF IP OUT OUTPUT ACQ. CONTROL EVENT CONTROLLER Vref YUV OUTPUT FORMAT VIDEO FIFO 32 x 32 IRH IMAGE PORT PIN MAPPING IRV IDQE ICRQF ITRDY ICLK ITRI 32 TO 8(16) MUX FIFO CONTROL data, clock and reference signals FIFO CONTROL GENERAL PURPOSE TEXTSLICER TXT INTERFACE TEXT FIFO 16 x 32 32 TO 8(16) MUX VIDEO / TEXT ARBITER MSC170 - 1 Multimedia PC 4-5 DESKTOP VIDEO 4 DIGITAL VIDEO DECODERS Field-wise switching between decoder and expansion port input 6-bit phase accuracy with accumulating filter for anti-aliasing Generation of field locked audio Master Clock and an audio serial and left/right (channel) clock signal Bi-directional expansion port, video image port and host port 32-word x 4-byte FIFO for video output data and 16-word x 4 byte FIFO for decoded VBI data The SAA7112 is an IC to capture and scale video images, passed as a digital video stream through the image port of a VGA controller, for display via the VGA frame buffer or for capture to system memory. A very highly integrated device, it combines dual analog pre-processing channels, A/D conversion, clock generation, full multistandard video decoding, high performance scaling and a number of other signal processing functions, all on one chip. BCS control is provided on both decoder and scaler outputs; in addition to the outputs listed, the scaler can output scaled luminance or raw data only. The VBI decoder supports WST, NABST, CC, WSS etc. The bi-directional port has half duplex functionality (D1) to output 8-bit YUV data from the decoder or input to the scaler (e.g. from an MPEG-decoder or video phone CODEC). The video image port is used to interface to the VGA controller and is configurable for master or slave operation, with auxiliary timing and handshake signals, while the host port allows extension of the image port to 16-bit. Discontinuous data streams are supported. The field locked audio clock generation ensures the same number of audio samples associated either with a single field or a set of fields, preventing any loss of synchronization between audio and video during capture or playback. 4-6 Multimedia PC DESKTOP VIDEO DIGITAL VIDEO DECODERS SAA7196 Digital video DEcoder, SCaler (DESC-Pro) All features listed in overview (page 4-2) plus: Multistandard decoder with single CVBS or S-Video input Outputs 16-bit 4:2:2 YUV, RGB 15-bit (5-5-5) and 24-bit (8-8-8), and 8-bit scaled monochrome Programmable luminance peaking for aperture correction Switchable RGB matrix and anti-gamma ROMs Chroma key ( generation) High quality scaling of video pictures down to arbitrary sized windows Maximum 1023 pixels per line and 1023 lines per field The SAA7196 is a highly integrated IC combining digital video decoding functions, scaling and clock generation functions. Monitor controls are incorporated to ensure optimum display. Decoder and scaler parts can operate at different clock frequencies, generated by the single on-chip crystal which also clocks the I2C-bus, allowing both scaler and decoder to be used independently. For a description of the scaling functions, refer to `Scalers' on page 4-8. An external ADC first converts analog video signals to 8-bit digital video data, fed either to one input port for CVBS signals or both input ports for Y/C data (using a second ADC). Other data ports include a 32-bit VRAM port which outputs down-scaled video data to memory and supports different format and operation modes. The 16-bit bi-directional expansion port can be configured to send data to the decoder part of the IC, or accept data for input to the scaler (where it can take clock rate and sync. signals from the external source). Two-dimensional data processing for improved signal quality and compression of scaled video data Horizontal and vertical sync detection for all standards DEBI port (YUV bus) supports data rates of 780 x fH (NTSC) and 944 x fH (PAL/SECAM) in 4:2:2 format Output configurable for 32/24/16-bit video data bus 16-word FIFO register for 32-bit output data Line increment, field sequence and vertical reset control for easy memory interfacing Output can either be in synchronous (transparent) or asynchronous (burst) transfer modes RTCO +5 V CGCE QUICK REFERENCE DATA Power supply CVBS(7-0) GPSW1 GPSW2 SDA SCL PORT AND STATUS REGISTER LQFP120 (SOT349 AA1) Handbook IC22 VCLK Y BRIGHTNESS CONTRAST AND SATURATION CONTROLS UV (BCS) UV(7-0) LUMINANCE DECIMATION FILTER VERTICAL FILTER LINE MEMORY (8 x 384) Y(7-0) RGB MATRIX OUTPUT FORMATTER VRO (31 TO 0); 32-bit VRAM port output RGB or YUV FOLLOWED BY U ANTI-GAMMA ROMs V INTERPOLATOR YUV(15-0) U V CHROMA KEYER OUTPUT FIFO REGISTER PLIN HS, VS HREF SCALE CONTROL SYNCHRONIZATION CLOCK A GENERATOR BUS INTERFACE LLCINB CLOCK B GENERATOR IICSA INCADR HFL VMUX SODD SVS SHREF PQQ clock a CREFINB clock B to scaler and brightness, contrast saturation controls LNQ SAA7196 MSC169 - 1 control and status from scaler part Multimedia PC VOEN BTST Y ARITHMETIC CHROMA DECIMATION FILTER VS clock status I2C-BUS CONTROL 1.5 W Datasheet SYNC LUMINANCE PROCESSOR 170 mA CTST HREF CHROMINANCE PROCESSOR 10 mA Digital supply current Package CGC INPUT INTERFACE Analog supply current Total power dissipation (max.) RESN CHR(7-0) 5V HSY LFCO HCL RTS1 RTS0 XTAL XTALI LLC CREF DIR VS HS YUV (15-0) HREF input/output LLCB LLC2 CREFB 4-7 4 DESKTOP VIDEO Philips currently offers two dedicated scalers, while a number of other devices in our DTV portfolio also incorporate scaling functions including decoders, PCI bridges and a video memory controller. Three levels of scaling performance are available depending on the IC, ranging from High Performance, 2-D phase correct scaling (HPS) down to simple Binary Ratio Scaling (BRS) through pixel and line dropping, offering flexibility to match the specific needs of your application. 4 All Philips' scaler cores offer a minimum of high quality scaling of video pictures down to arbitrary-sized windows. The ICs themselves include a variety of input and output interfaces; all have at least one 16-bit YUV data input port with outputs available either in synchronous (transparent) or asynchronous (burst) transfer modes. DIGITAL VIDEO SCALERS Sample phase information is generated by a phase calculator with an accuracy of 1/64 pixel distance. 2-D scaling HPS (High Performance Scaling) 2-D phase-correct interpolation delivers excellent signal quality, especially on compressed data Horizontal pre-scaling unit filters input 4:4:4 YUV data to reduce the signal bandwidth Phase scaling minimizes the number of phase or amplitude artefacts `Flip' option mirrors input lines Scaling is carried out in three stages: horizontal pre-scaling, vertical scaling and horizontal phase scaling, with the scaling unit receiving timing information from the input ports. The pre-scaling consists of an FIR pre-filter, which reduces signal bandwidth according to the required scale factor to reduce aliasing. As phase-correct horizontal fine scaling is limited to a downscale maximum of x1/4, a sub-sampler is included which improves scaling performance for scale factors from < x1/2 down to icon size, by reducing the incoming pixel count. Two-dimensional data processing improves signal quality and compression of scaled video data Horizontal filtering, handled by two separate decimation filters, reduces artefacts from pixel dropping Signal bandwidth can be reduced in steps between 2-tap and 9-tap Video Processing Unit (VPU) processes vertical luminance data to avoid artefacts caused by line dropping YUV-to-RGB conversion according to CCIR-601 recommendations Although this scaler functions by pixel and line dropping, initial pre-filtering improves signal quality and helps to avoid artefacts. First, filters match the signal characteristics before the pixel decimation stage to reduce artefacts from pixel dropping. Luminance data are fed to a vertical filter consisting of a 384 x 8-bit RAM and an arithmetic block for sub-sampling and interpolation. By vertical processing, video information is preserved even for small scale factors, avoiding artefacts. Chrominance data are interpolated to produce a YUV 4:4:4 data stream before YUVto-RGB conversion. A scale control unit generates reference and gate signals for scaling of the processed video, with the scaling ratio in the horizontal and vertical directions being estimated and used to control the decimation and vertical filtering. Scaled data are then formatted to one of the VRAM port formats before being passed to the FIFO output register. BRS (Binary Ratio Scaling) The input data stream can be vertically downscaled, up to a maximum line length of 768 pixels/line. An ACCU mode can be used for all vertical scales down to icon size (1 to 1/1024), in which the output line qualifier pattern and the sequence length for the line averaging can be defined, with scaling performance improved by weighting the accumulated lines. The resulting amplitude gain of the scaled output signal is then normalized. To preserve signal quality in limited vertical down-scales (1 to x1/2), an LPI mode is used between consecutive lines to generate a new geometric line position. A new output line is then calculated by weighting the samples with the normalized distance to the new geometric position. Horizontal phase-correct scaling then calculates pixels for the geometrically correct orthogonal output pattern, down to x1/4 of the pre-scaled pattern. Phase-correct scaling consists of a filter and arithmetic structure that generates a new phase correct value, minimizing the number of phase or amplitude artefacts. 4-8 Horizontal scaling by pixel dropping and averaging Vertical scaling using line dropping (or line pairs) This simple pixel and line dropping core performs simple scaling down to arbitrary-sized windows. It has very little filtering and is intended only for basic applications. An accumulator, controlled by attenuators to keep pixel values from overflowing, is used to filter the data as it is being scaled down. After scaling, a pixel formatter organizes information from the scaler based on bitdepth and colour space and places pixel information in the right byte lanes, sizing them to the required output format. Philips' SAA7146 PCI bridge IC also has video window occlusion using a software clip mask. Only dedicated scalers are described in this section: other devices with scaling functions are described under other headings. Refer to table on page 4-9. Multimedia PC DEDICATED SCALERS Scaling type PCI BRIDGE/SCALER DECODER/SCALERS VIDEO & MEMORY CONTROLLER SAA7186 SAA7140A/B SAA7146 SAA7196 SAA7112 SAA7195A (VMC) 2-D scaling HPS HPS/BRS 2-D scaling HPS BRS 1023 2047 4095 1023 2047 1023 No Yes Yes No Yes (2x) No 15-bit (5-5-5+ ) 15-bit (5-5-5+ ) 8-bit (3-3-2) pseudo CLUT 15-bit (5-5-5+ ) - 15-bit (5-5-5+ ) 24-bit (8-8-8+ ) 24-bit (8-8-8+ ) 15-bit (5-5-5+ ) 24-bit (8-8-8+ ) Maximum window size Horizontal upscaling (zoom) DESKTOP VIDEO Multimedia PC Table 2: Philips ICs with scaling functions Scaled output formats RGB 16-bit 24-bit (8-8-8+ ) 15-bit (5-5-5) with dither 16-bit (5-6-5) 24-bit (8-8-8+ ) CCIR - - 656 8-bit - - - YUV 16-bit 16-bit 4:2:2 4:4:4 24-bit 16-bit 4:2:2 16-bit 4:2:2 24-bit 4:4:4 12-bit 4:1:1 16-bit 4:2:2 16:2:0 18 bit Indeo 4:2:2 16-bit 12-bit 4:1:1 4:1:1 12-bit 8-bit 2:1:1 4:2:0 6-bit MPEG Other 8-bit mono 8-bit mono 8-bit mono 8-bit mono 8-bit CCIR-656 - 8-bit luminance only FIFO register 16 word 16 word 3 x 128 D word video 16 word 32 word video 160 pixels, 24-bit 16 word decoded VBI Chroma Key ( generation) Yes Yes Anti-gamma corr. Yes Yes Yes Yes No No Expansion port No Yes Dual DEBI Yes Yes No Refer to page 4-10 4-11 4-18 4-7 4-5 4-31 Yes Yes No Yes DIGITAL VIDEO SCALERS 4-9 4 DESKTOP VIDEO DIGITAL VIDEO SCALERS SAA7186 Digital Video Scaler (DVS) Vertical sync. processing by scale control circuit Full picture non-scaled mode Binary or two's-complement UV input and output data Switchable RGB matrix and anti-gamma ROMs TTL-compatible inputs and outputs Outputs 5- and 8-bit RGB, 8-bit YUV or 8-bit monochrome signals The SAA7186 scaler accepts 16-bit YUV data in 4:2:2 format from a number of different multistandard digital video decoders or other similar sources. This is then converted into a unique internal two's-complement data stream for horizontal and vertical filtering and scaling using the 2-D scaling block described in the overview (on page 4-9). Sequential input data is limited to 768 active pixels per line if the vertical filter is active. Specific reference signals support easy memory interfacing. QUICK REFERENCE DATA Power supply 5V Total supply current (max.) 180 mA Total power dissipation (max.) 1W Package QFP100 (SOT317) Datasheet Handbook IC22 Y YIN (7-0) LINE MEMORY (2x8x768) VLCK RGB MATRIX Y VOEN 8 FOLLOWED 8 BY ANTI-GAMMA 8 ROMs U V INPUT DATA BUFFER UVIN (7-0) ARITHMETIC VERTICAL FILTER LUMINANCE DECIMATION FILTER VERTICAL FILTER UV CHROMA DECIMATION FILTER LINE MEMORY (2x8x768) ARITHMETIC 4 2-D data processing improves signal quality and compression of scaled video data 16-bit YUV input data buffer Interlaced and non-interlaced video processing and field control Line memories in Y and UV paths store two lines U INTERPOLATOR V CHROMA KEYER 15 BTST OUTPUT FORMATTER OUTPUT FIFO REGISTER VRO (31 to 0); 32-bit VRAM port output RGB or YUV INCADR HFL HREF LNQ VS SCALE CONTROL HREFD RESN SCL SDA IICSA I 2C CONTROL controls status CLOCK GENERATION SAA7186 MSC201 CREF LLC 4-10 Multimedia PC DESKTOP VIDEO DIGITAL VIDEO SCALERS SAA7140A/B High Performance Scaler (HPS) variant is a 3.3 V low-power version incorporating I2C controllable power saving modes. 2-D phase-correct interpolation delivers excellent signal quality, especially on compressed data DMSD (16-bit YUV input) port, with second bi-directional full duplex expansion port (D1) or 16-bit YUV I/O port The input data stream is formatted according to an internal data representation, depending on which port is selected. If the bidirectional port is used, it is possible to field switch between input ports. Two independent programming sets can be loaded simultaneously, allowing separate scaling and processing functions on two different signals simultaneously. Before scaling, the data is passed through the BCS control. It uses Philips High Performance Scaler core described in the overview on page 4-9. Discontinuous data streams supported Switching between two data sources in two fields BCS control on scaled outputs YUV to RGB conversion including anti-gamma correction Range of YUV/RGB outputs, configurable for 32-, 24-, 16- or 8-bit video data QUICK REFERENCE DATA The SAA7140A is a high performance scaler able both to scale down video pictures to arbitrary-sized windows and upscale horizontally. It can also switch between different processing and scaling functions on two different video fields, from separate sources, making it ideal for applications such as PC-based video conferencing, with a main picture and a vanity picture. The `B' LLCIN PXCIN HIN VIN VIDH (7 to 0) Power supply 5 V (3.3 V for `B' variant) Total supply current t.b.f. Total power dissipation (max.) 750 mW Package LQFP128 (SOT425-1) Datasheet (12NC) VIDL (7 to 0) LLCIO PXCIO HIO 9397 750 00984 VIO FDIO EXPANSION - PORT - INTERFACE reference YIN (7 to 0) UVIN (7 to 0) DMSD port CREF DATA FORMATTER/ REFORMATTER AND REFERENCE SIGNAL GENERATION SCALING UNIT Y Y Y UV UV U V HREF PXO VS ACQUISITION BCS CONTROL VERTICAL PROCESSING HORIZ. PRESCALING LINE MEMORY H Y U ARITHMETIC HORIZ. FINE SCALING V CONTROL V LLC CLK SAA7140 PORT (3 to 0) Y U SCL control V I2C CONTROL SDA status VRO (31 to 0) R HGTV G CSM DITHERING Y-CORRECTION B VSYV OUTPUT FORMATTER OUTPUT FIFO REGISTER FLDV VRAM port PXQV INCADR IICSA HR RESN VCLK Multimedia PC VOEN MSB808 4-11 4 DESKTOP VIDEO DIGITAL VIDEO ENCODERS All Philips encoders offer: Encoding to PAL and NTSC standards with SECAM versions available 13.5 MHz system pixel frequency with 8-bit resolution Controlled rise/fall times of output sync. and blanking Compatible with DIG.TV2 chip family 4 Philips offers one of the most extensive ranges of Digital Video ENcoders (DENCs) currently available, offering a variety of combinations of inputs, outputs, size and functionality to suit all applications. Various chips are CCIR-601, square pixel or dual mode compatible and all accept CCIR-656 (MPEG) input data streams. Some decode PAL and NTSC with full multistandard versions available, and a number offer RGB outputs. One IC offers external genlock to lock encoding to an external source. Most members of the family come in two versions: one with the Macrovision `Pay-per-view' copy protection system (for which a licence is required) and one with the system blocked, for which no licence is required. The basic encoder function consists of subcarrier generation and colour modulation as well as the insertion of user-programmable H/V sync. pulses, with signal filtering according to RS-170-A and CCIR-624 standards. Luminance processing includes gain and offset adjustment with a programmable black level. Chrominance processing includes separate U and V gain adjustment and colour burst insertion, modulation with the subcarrier and a programmable subcarrier frequency. Both interlaced and non-interlaced operation is possible for all standards. Sync/clock generation and D/A conversion are included on-chip. The high feature encoders output CVBS, Y/C and RGB simultaneously, in line with the latest SCART standards. Philips digital video encoders SAA7124/25 SAA7182/83 SAA7182A/83A SAA7184/85B SAA7187 SAA7188A/85 SAA7199B CCIR/Square pixel CCIR CCIR CCIR CCIR SQP CCIR CCIR/SQP Supports SECAM No Yes Yes No No No No - 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:4:4 24-bit Input formats YUV 4:2:216-bit CCIR 656 8-bit RGB - 656 8-bit 656 8-bit 656 8-bit 656 8-bit 4:2:2 16-bit 4:4:4 24-bit 656 8-bit - - - - - - 24-bit Macrovision protection 6.1/ - - /6.1 - /6.1 6.1/ - - 3/ - - Simultaneous outputs CVBS, Y/C, CVBS, Y/C CVBS & Y/C CVBS & Y/C CVBS & Y/C CVBS & Y/C CVBS, Y/C, & RGB & RGB Int./Ext. analog RGB mux No YUV & RGB No Yes No No No No Closed caption Yes Yes Yes Yes Yes Yes No Teletext No Yes Yes No No No No OSD No Yes Yes Yes Yes Yes No Colour comb filter No No No Yes Yes Yes No Colour bar generator Yes Yes Yes Yes Yes Yes No Genlock Advanced Advanced Advanced Advanced Remote Remote On-chip remote remote remote remote I2C interface Yes Yes Yes Yes Yes Yes Yes Microcontroller interface No No No Yes Yes Yes Yes Refer to page 4-14 4-13 4-16 4-16 4-16 4-17 4-12 4-15 Multimedia PC DESKTOP VIDEO DIGITAL VIDEO ENCODERS SAA7182A/83A Encoder EURO-DENC2 All SAA7182/83 features, plus: Monolithic 3.3 V CMOS device with 5 V input stages On-chip analog multiplexing between internal and external RGB signals Line 23 Wide Screen Signalling Encoding RGB output level adjustable by 3 dB (CANAL+ requirement) RGB matrix bypass for analog YUV output (BETACAM) 4 These `A' variants of the SAA7182/83 (see next page) incorporate the same functionality, but also include an on-chip RGB multiplexer which can mix RGB from an external source with internal RGB signals. They also have the capability of loading Wide Screen Signalling data via the I2C-bus and inserting it into Line-23 of 50 Hz systems. QUICK REFERENCE DATA Power supply Digital supply current 3.3 V 5V Analog supply current 3.3 V/5 V t.b.f. t.b.f. t.b.f. LF integral linearity error 2 LSB LF differential linearity error 1 LSB Package PLCC84 (SOT189) QFP80 (SOT318) Datasheet SDA RESN SA SCL CDIR Contact Philips RCV1 TTXRQ XTAL LLC CUR VDDA VrefH RCV2 CREF XTALI I2C-control SECAM PROCESSOR I2C-INTERFACE I2C-control DP(7:0) MP(7:0) OVL(2:0) KEY TTX CbCr I2C-control Y ENCODER I2C-control C I2C-control Y SAA7183A TESTB clock & timing Y DATA MANAGER SYNC/CLOCK OUTPUT INTERFACE A Y C I2C-control VSSA VrefL I2C-control VrefL R G B - PROCESSOR D A CbCr VrefH Multimedia PC CVBS D CUR VDDA Rout Rin Gout Gin Bout Bin MSB793 - 1 4-13 DESKTOP VIDEO DIGITAL VIDEO ENCODERS SAA7182/83 Encoder EURO-DENC 4 Full multistandard digital decoder Accepts 8-bit CCIR-656 with 720 pixels/line or 16-bit YUV input Data are interpolated to 27 MHz, providing 10-bit resolution for CVBS, Y and C data 9-bit resolution for RGB data On-chip YUV to RGB matrix Fast 400 kHz I2C-bus control port Operates in both master and slave modes Three, 10-bit DACs for CVBS and YUV; three 9-bit DACs for RGB The SAA7182/83 EURO-DENC encodes digital YUV video data either to one of the main broadcast standards or to an SVideo or RGB signal, with all signals being available simultaneously. The SAA7183 has the Macrovision Level 6.1 Pay-perView copy protection system embedded on chip; this system is blocked on the SAA7182, so no licence is required to use this IC. QUICK REFERENCE DATA Power supply Digital supply current Analog supply current 90 mA LF integral linearity error 2 LSB LF differential linearity error 1 LSB Package Datasheet (12NC) 4-14 5V 220 mA PLCC84 (SOT189) 9397 750 00324 Multimedia PC DESKTOP VIDEO DIGITAL VIDEO ENCODERS SAA7124/5 Encoder ECO-DENC Encodes NTSC or PAL signals Accepts 8-bit CCIR-656 with 720 pixels/line On-chip YUV to RGB matrix RGB matrix can be bypassed to provide D/Aconverted CbYCr signals One 10-bit DAC for CVBS signals and three 9-bit DACs for separate R, G, and B signals (SCART applications) 4 Simultaneous CVBS and RGB outputs Closed caption encoding The SAA7124/5 ECO-DENC is a low cost (ECOnomy) version of the EURO-DENC (SAA7182/83), without SECAM encoding but available in a smaller package. It encodes NTSC or PAL digital luminance and colour difference signals to a CVBS signal and an RGB signal, or to an S-Video and two CVBS outputs. As with the EURO-DENC encoders, the SAA7124 incorporates the Macrovision Pay-per-view copy protection system level 6.1, which is blocked on the SAA7125. Closed caption encoding is available but there is no teletext function. QUICK REFERENCE DATA Power supply 5V Digital supply current 150 mA Analog supply current 60 mA LF integral linearity error 2 LSB LF differential linearity error Package 1 LSB PLCC84 (SOT189) QFP80 (SOT318-2) LQFP64 (SOT314) Datasheet Multimedia PC Contact Philips 4-15 DESKTOP VIDEO DIGITAL VIDEO ENCODERS DENC2 family of encoders Fast MPU parallel and I2C-bus control ports Outputs CVBS and S-Video signals simultaneously Three, 10-bit DACs running at 27 MHz The SAA7182/3 and SAA7124/5 ICs described in pages 4-13 to 4-15 are enhanced versions of an earlier family of encoders, which is still supported. Offering the same basic functionality as the SAA7182/3 family, they are not as highly featured, including only PAL and NTSC encoding for applications where SECAM is not required, but come in the smaller PLCC68 package. SAA7187 encoder DENC-SQ. A square pixel version of the SAA7188A, offering the same functionality but with no Macrovision system. The MPEG video data port is also replaced by a 24-bit YUV input port. It supports clock frequencies of 24.54 MHz (for 60 Hz systems) and 29.5 MHz (for 50 Hz systems) rather than the single pixel system frequency. MP7 to MP0 VP0 to VP7 VrefH RTCI OVL0 to OVL2 KEY SEL_ED SAA7184/85B encoder DENC-M6. A pin-compatible replacement for the SAA7188A DENC2, the SAA7184 offers the latest version of the Macrovision Pay-per-View copy protection system DATA MANAGER CVBS A OUTPUT INTERFACE ENCODER Y D C VSSA internal control bus RCM1 VrefL clock timing signals SAA7184 RCM2 CONTROL INTERFACE SYNC CLK RCV2 CDIR RCV1 CREF LLC XTAL0 XTALI RESN A0/SDA DTACKN RWN/SCL CSN/SA SEL_MPU MSB913 - 1 DP0 to DP7 4 SAA7188A/85 encoder DENC2-M. The original member of the DENC2 family, this encoder accepts a range of signals, including decoded MPEG-1 video data streams. It has the Macrovision Pay-per-View system, level 3. The SAA7185 is identical to the SAA7188A but with the Macrovision copy protection system blocked. VDDA (rev. 6.1), while the SAA7185B is identical to the SAA7184 but with the Macrovision copy protection system blocked. Encodes NTSC or PAL signals 8-bit CCIR-656 (D1) and 16-bit YUV inputs CUR QUICK REFERENCE DATA SAA7184/85B SAA7187 SAA7188A/85 Power supply 5V 5V 5V Digital supply current 140 mA 175 mA 140 mA Analog supply current 50 mA 50 mA 50 mA LF integral linearity error 2 LSB 2 LSB 2 LSB LF differential linearity error 1 LSB 1 LSB 1 LSB Package PLCC68 (SOT188) PLCC68 (SOT188) PLCC68 (SOT188) Datasheet (12NC) 9397 750 00928 9397 750 00325 9397 750 00944 I2C-bus interface Yes Yes Yes 4-16 Multimedia PC DESKTOP VIDEO DIGITAL VIDEO ENCODERS SAA7199B Encoder with genlock Three 8-bit signal inputs for PAL or NTSC RGB, YUV or indexed colour signals Optional external GENLOCK operation with adjustable horizontal sync. timing and subcarrier phase Stable GENLOCK operation in VCR standard playback mode 3 x 9-bit resolution DACs Three 256 x 8 CLUTs for gamma correction Multi-purpose key for real-time format switching TTL-compatible inputs Autonomous internal blanking Optional still video capture 4 The SAA7199B encodes digital baseband colour/video data into analog CVBS and Y/C signals. Four selectable modes are available: a stand alone mode with horizontal and vertical timings internally generated; a slave mode using external horizontal and vertical timing, with optional real-time information; GENLOCK mode (which requires a clock reference from the SAA7197 external clock generator); and a test mode. Pixel clock and data are line-locked to the horizontal scanning frequency of the video signal. An on-chip conversion matrix provides CCIR601 code-compatible transcoding of RGB and YUV data. QUICK REFERENCE DATA Power supply 5V Total supply current 220 mA LF integral linearity error 1 LSB LF differential linearity error 0.5 LSB Package PLCC84 (SOT189CG) Datasheet Handbook IC22 +5 V +5 V KEY MPK VDDD1 to VDDD3 VrefH V DDA1 to VDDA4 CUR 3 x 8-bit input data PD1(7 to 0)(1) (digital red) PD2(7 to 0)(1) (digital green) C CLUTS INPUT INTERFACE ENCODER MATRIX 3x 256 x 8 RTCI TRIPLE DACs Y OUTPUT BUFFERS outputs to monitor/TV PD3(7 to 0)(1) (digital blue) CVBS VSSA internal control bus CVBS0(7 to 0) VrefL LDV SAA7199B STATUS REGISTER SDA I 2 C-bus SCL XTALO I 2 C-BUS CONTROL SYNC PROCESSING CONTROL INTERFACE CLOCK INTERFACE XTALI RTCI RESET GPSW A1 A0 HCL CS R/W D(7 to 0) LFCO HSY HSN SLT VSN/CSYN CLKSEL CLKO CREF CB CLKIN LLC PIXCLK MSC200 to/from microcontroller Multimedia PC 4-17 DESKTOP VIDEO The PCI-bus is virtually the de-facto replacement for the old ISA-bus. Its high speed and bandwidth and its operation as a multi-speed bus, together with its burst mode, make it ideal in desktop video applications where large volumes of data have to SAA7146 PCI BRIDGES be quickly moved around the PC for real-time processing and display. Philips PCI bridge IC includes scaling functions and a range of ports for interfacing flexibility. QUICK REFERENCE DATA Power supply Multimedia bridge with scaler and PCI 4 Master read/write and slave PCI 2.1 interface DMA access for audio and video data onto the PCI bus Support for full bandwidth high speed PCI transfers and PCI burst mode RPS (Register Programming Sequencer), allowing loading of pre-defined programming sets under I2C-bus control Dual D1 interface supports bi-directional, full duplex, two channel, full D1 (CCIR-656) standards 3 x 128 D word Video FIFO with overflow detection and parity check Scaling functions include display of arbitrary-sized windows and electronic zooming, and conversion between sample schemes 2-D phase-correct interpolation delivers excellent signal quality, especially on compressed data (HPS) Bi-directional Binary Ratio Scaler (BRS) can convert between full-size video (50 or 60 Hz) and CIF/QCIF Processing of 4095 active samples per line and active lines per frame Programmable RGB and YUV outputs include packed and planar formats for local display and compression Virtual memory management unit (4 MB per DMA channel) Brightness, contrast and saturation control and Chroma Key generation On-chip colour space matrix, dithering and gamma correction Supports rectangle overlay and bit mask clipping 4-18 Core I/O pad 5V 3.3 V Total supply current t.b.f. PCI clock frequency 33 MHz I2S clock frequency Total power dissipation (max.) Package Datasheet 12.5 MHz t.b.f. TQFP208 (SOT316A1) Contact Philips One of Philips' most integrated and highly featured ICs, the SAA7146 interfaces desktop video functions to the PCI bus and includes a range of interfaces to provide flexible connection to a large number of video and audio ICs. It also includes internal Binary Ratio Scaling (BRS) and two-dimensional High Performance Scaling (HPS) functions similar to those in the SAA7140A/B, so is ideal for many applications requiring realtime desktop video processing. For more information on the BRS or HPS scaling functions, refer to the `Scalers' section (page 4-8). The SAA7146 includes a YUV 4:2:2 video input port which can be configured in two ways. Firstly, it can accept 8-bit time-multiplexed bi-directional full duplex YUV data in accordance with CCIR-656 standards (D1 video), with sync signals encoded in the input data stream or brought in on separate sync. inputs. These sync pins can be used as outputs when external synchronization to the input source is required. Secondly, it can behave as a 16-bit port, for backwards compatibility with the DMSD2 standard, in which Y luminance data are on one 8-bit port and the U and V chrominance data are multiplexed on a second 8-bit port. This DSMD2 mode is compatible with other 16-bit decoder devices in the DTV chipset such as the SAA7110A. After scaling, the signal can be output in various programmable RGB and YUV formats and can be dithered for low bit-rate formats. A second YUV video channel bypasses the HPS and connects the real-time video interface with the PCI interface through FIFO and DMA control. This video bypass channel offers the same BRS features as the SAA7146. VBI data and test signals can be also be bypassed without processing. The FIFO has overflow detection and `graceful' recovery. Multimedia PC DESKTOP VIDEO PCI BRIDGES The DEBI (Data Expansion Bus Interface) has parallel modes for system set-up and programming of peripheral multimedia devices further down the chain. It is also optimized to transport compressed MPEG/JPEG data to and from peripheral ICs to the PCI system. The DEBI is connected to the PCI by single instruction direct access and via a data DMA channel for streaming data. dual D1 or 16bit YUV SAA7146 I/O Both PCI master and slave modes support 32-bit transfers at a maximum clock rate of 33 MHz. To increase bus performance, they can handle fast back-to-back transfers. Video signal flow to and from the PCI bus is controlled by three video DMA channels, with the channel definition supporting the typical video data structure (hierarchy) of pixels, lines, fields and frames. In slave mode, access only to the programmable registers and configuration space is provided. Audio signal flow is controlled by four audio DMA channels. The digital audio serial interface is I2S compatible and supports the connection of up to four devices. Multimedia PC I2C DATA EXPANSION BUS INTERFACE REAL TIME VIDEO INTERFACE BINARY RATIO SCALER HIGH PERFORMANCE 2-DIMENSIONAL SCALER SERIAL I2S AUDIO INTERFACE I2S I2 C MASTER 4 PCI interface, FIFOs and DMA controls MSB799 PCI local bus 4-19 DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS All Philips ADCs offer: Sampling rates of at least 32 MHz Binary or two's-complement 3-state TTL outputs TTL-compatible digital inputs and outputs High SNR ratio over large analog input frequency range Internal reference voltage regulator No sample-and-hold circuit required 4 Many ICs in the Philips DeskTop Video chipset include onboard ADCs. Philips also has available a number of specialized stand-alone ADCs which include a range of integrated signal conditioning functions. PHILIPS VIDEO ADCS TDA8707 TDA8708A/B TDA8709A TDA8758 ADC resolution 6-bit 8-bit 8-bit 8-bit Variable pre-amplifier No No Yes No AGC No Yes No Yes* Clamp functions Yes Yes Yes Yes Input selector circuit No Yes No Yes * only on luminance channel TDA8707 CLREF CLP CLK Triple RGB 6-bit ADC interface Triple ADC with 6-bit resolution Sampling rate up to 35 MHz Internal clamping functions Low power dissipation INR CLAMPING CIRCUIT 6-BIT ADC R0 to R5 6 ING The TDA8707 CMOS low power ADC converts RGB analog inputs into 6-bit binary coded digital words. It incorporates three A/D converters using the full-flash method; each has an internal clamping circuit. Internal buffers are provided to drive the A/D converter inputs. BUFFER BUFFER CLAMPING CIRCUIT 6-BIT ADC G0 to G5 6 TDA8707 INB BUFFER CLAMPING CIRCUIT 6-BIT ADC B0 to B5 6 CREFH CREFL MSC207 SLT QUICK REFERENCE DATA Power supply Analog supply current Digital supply current 5 mA Typical DC integral linear error 0.35 LSB Typical power dissipation 335 mW Package Datasheet (12NC) 4-20 5V 60 mA QFP44 (SOT307-2) 9397 750 00605 Multimedia PC DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS TDA8708A/B Video analog input interface Clamp and AGC functions for CVBS and Y signals Input selector circuit White peak control The TDA8708A/B provides a simple interface for decoding video signals and can be configured to operate in two modes. Mode 1, which enables fast recovery of the sync pulses in the decoder circuit, is used when video signals are weak and it only adjusts the AGC amplifier gain roughly. If the sync period or rear porch pulses become indistinct, the TDA8708 automatically switches to Mode 2, where the digital output of the ADC is compared to the internal digital reference levels. Both chips provide white peak control in Mode 1 and the `A' variant also has this function in Mode 2. 4 QUICK REFERENCE DATA Power supply 5V Analog supply current 37 mA Digital supply current 24 mA Typical DC integral linear error 1 LSB SNR (effective bits at 4.43 MHz) 7.5 Total power dissipation Package 365 mW TDA8708A/B DIP28 (SOT117-1) TDA8708AT/BT SO28L (SOT136-1) video input selection bit 0 video input selection bit 1 analog voltage output Datasheet (12NC) TDA8708A 9397 734 20011 Datasheet (12NC) TDA8708B 9397 734 80011 ADC input clock input decoupling input TTL outputs V CCO (+ 5 V) VIDEO AMPLIFIER output format/ chip enable (3-state input) video input 0 video input 1 INPUT SELECTOR AMP. 8 - bit ADC video input 2 clamp capacitor connection AGC capacitor connection TDA8708A/B AGC & CLAMP LOGIC & MODE SELECTION peak level current resistor input TTL OUTPUTS D0 to D7 PEAK LEVEL DIGITAL COMPARATOR BLACK LEVEL DIGITAL COMPARATOR SYNC LEVEL DIGITAL COMPARATOR MSC191 sync level sync pulse Multimedia PC black level sync pulse 4-21 DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS TDA8709A Video analog input interface Low level AC clock inputs and outputs Three selectable video inputs Variable gain pre-amplifier with clamp function 4 An analog input interface for video signal processing, the TDA8709A includes an input selector to choose one out of three video signals. A video pre-amplifier has external gain control and a clamp function which can be switched between digital `16' for RGB signals and digital `128' for chrominance or colour difference signals. QUICK REFERENCE DATA Power supply 5V Analog supply current 40 mA Digital supply current 24 mA Typical DC integral linear error 1 LSB SNR (effective bits at 4.43 MHz) 7.5 Total power dissipation Package 380 mW TDA8709A DIP28 (SOT117-1) TDA8709AT SO28L (SOT136-1) Datasheet (12NC) video input selection bit 0 video input selection bit 1 analog voltage output ADC input clock input decoupling input 9397 734 60011 TTL outputs V CCO (+ 5 V) VIDEO AMPLIFIER video input 0 video input 1 INPUT SELECTOR AMP. fast output chip enable 8 - bit ADC video input 2 clamp capacitor connection gain control input TDA8709A TTL OUTPUTS D0 to D7 CLAMP LEVEL "16" DIGITAL COMPARATOR CLAMP LOGIC CLAMP LEVEL "128" DIGITAL COMPARATOR output format selection MSC190 clamp level selection 4-22 clamp pulse Multimedia PC DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS TDA8758 Low power A/D interface Peak white enable input Input selector circuit for 1-of-5 video inputs Clamp and AGC functions for Y/CVBS channel Clamp function for C channel The TDA8758 is a low power, dual ADC interface providing a simple interface between CVBS or S-Video signals and a digital colour decoder, processing either 1-of-2 Y/C or 1-of-3 CVBS input signals. All analog signals are digitally clamped with a fast pre-charge on clamp and AGC for start-up. An ADC interface is provided on the Y/CVBS channel. 4 QUICK REFERENCE DATA Power supply 5V Analog supply current 55 mA Digital supply current 24 mA Typical DC integral linear error 0.75 LSB Crosstalk between Y and C channels -56 dB SNR (effective bits at 4.43 MHz) 7.0 (x2) Total power dissipation 485 mW Package LQFP48 (SOT313-2) Datasheet (12NC) SEL2 CCLPC ANOUTC CLAMP LEVEL 128 CHROM2 9397 750 00606 ADC TTL 8 C7 to C0 CHROM1 COMPARATOR OFC TDA8758 CVBS3 TIMING GENERATOR INPUT SELECTOR CLK OFY COMPARATORS Y2/CVBS2 AGC & CLAMP 64 ADC Y1/CVBS1 TTL 8 Y7 to Y0 MSC208 SEL1 PWE GATE A C CLPY GATE B Multimedia PC CAGC ANOUTY 4-23 DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS Many ICs in the Philips DeskTop Video chipset include onboard DACs - for example, all video encoders have 9- or 10-bit DACs on board. In addition to a number of dedicated video DACs, Philips also offers a highly integrated mixer/DA processor which mixes encoded and external RGB signals, and a video enhancement processor/converter. 4 PHILIPS VIDEO DACS TDA8702 TDA8712 TDA8771A TDA8772(A)H(3/8) TDA8775G Sampling rate 30 MHz 50 MHz 35 MHz 35 MHz/85 MHz 50 MHz TTL-compatible inputs Yes Yes Yes Yes Yes Resolution 8-bit 8-bit 8-bit 8-bit 10-bit TDA8702/TDA8712 8-bit video DACs Sampling rate up to 30 MHz (TDA8702) or 50 MHz (TDA8712) Two complementary analog outputs Internal input resistor Internal 75 output load REFERENCE CURRENT GENERATOR TDA8702 TDA8712 CURRENT GENERATORS 8 data (D7 - D0) (TTL) DATA INPUT INTERFACE DATA LATCHES CURRENT SWITCHES CURRENT TO VOLTAGE CONVERSION V V CLK MSC209 Internal reference voltage regulator No deglitching circuit required QUICK REFERENCE DATA Power supply 5V Analog supply current 26 mA Digital supply current 23 mA DC integral non-linearity 0.5 LSB DC differential non-linearity 0.5 LSB Total power dissipation Package 250 mW TDA8702/TDA8712 TDA8702T/TDA8712T Datasheet 4-24 DIL16(SOT38) SO16 (SOT162) TDA8702 Handbooks IC22, IC02 TDA8712 9397 734 70011 Multimedia PC DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS TDA8771A Triple 8-bit video DAC RED digital inputs (bits R0 to R3) Triple DAC with sampling rate up to 35 MHz Large output voltage range 1 k output load Internal reference voltage regulator No deglitching circuit required clock input 4 LSB DECODER TDA8771A RED digital inputs (bits R4 to R7) 4 reference current input (I REF ) MSB DECODER RESISTOR STRING GREEN digital inputs (bits G0 to G3) RED analog output 4 The three DACs in the TDA8771A are based on resistor string architecture with integrated output buffers, with the voltage output range determined by an internal reference source. 4 LSB DECODER GREEN digital inputs (bits G4 to G7) 4 MSB DECODER RESISTOR STRING BLUE digital inputs (bits B0 to B3) GREEN analog output 4 LSB DECODER BLUE digital inputs (bits B4 to B7) 4 MSB DECODER RESISTOR STRING BLUE analog output BANDGAP REFERENCE MSC155 - 1 reference voltage decoupling input (VREF ) QUICK REFERENCE DATA Power supply Total analog supply current Total digital supply current DC integral non-linearity DC differential non-linearity Total power dissipation Package Datasheet Multimedia PC 5V 33 mA 7 mA 0.5 LSB 0.25 LSB 200 mW QFP44 (SOT307-2) 9397 750 00591 4-25 DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS TDA8772(A)H(3/8) RED digital inputs (bits R0 to R3) Triple 8-bit video DAC TDA8772A 1 V output range with 75 load Internal reference voltage regulator No deglitching circuit required 4 Triple DAC with sample rates up to 35 MHz or 85 MHz Sync. & blank control inputs Independent clock input for each DAC RED digital inputs (bits R4 to R7) 4 MSB DECODER GREEN digital inputs (bits G0 to G3) These triple 8-bit DACs convert digital input signals to analog output signals with conversion rates up to 35 MHz (for the `H/3' variants) and 85 MHz (for the `H/8' variants). The `A' versions have a blank control input on the green channel only. The three DACs in the TDA8772 are based on resistor string architecture with integrated output buffers, with the voltage output range determined by an internal reference source. GREEN digital inputs (bits G4 to G7) BLANK control input SYNC control input LSB DECODER RED clock input RESISTOR STRING RED analog output 4 4 MSB DECODER BLUE digital inputs (bits B0 to B3) BLUE digital inputs (bits B4 to B7) reference current input (I REFB ) 4 LSB DECODER GREEN clock input RESISTOR STRING GREEN analog output 4 4 CONTROL REGISTER MSB DECODER LSB DECODER BLUE clock input RESISTOR STRING BLUE analog output reference current input for internal reference (I REFA ) BANDGAP REFERENCE MSC159 - 1 reference voltage decoupling input (V REF ) QUICK REFERENCE DATA TDA8772(A)H/3 TDA8772(A)H/8 Power supply 5V 5V Total analog supply current 65 mA 65 mA Total digital supply current 7 mA 16 mA DC integral non-linearity 0.5 LSB 0.75 LSB DC differential non-linearity 0.25 LSB 0.5 LSB Maximum clock frequency 35 MHz 85 MHz Total power dissipation 260 mW 310 mW Package QFP44 (SOT307B) QFP44 (SOT307B) Datasheet (12NC) 9397 750 00029 9397 750 00029 4-26 Multimedia PC DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS TDA8775G Triple 10-bit video DAC red digital inputs (bits R0 to R3) 4 TDA8775 10-bit resolution Sampling rate up to 50 MHz (normal mode, 37.5 load) or 35 MHz (low power mode, 150 load) Triple DACs based on internal current source architecture with selector for normal or lowpower mode 0.66 V output range Sync. & blank control inputs Internal reference voltage regulator No deglitching circuit required red digital inputs (bits R4 to R9) 6 MSB DECODER green digital inputs (bits G0 to G3) LSB DECODER CLK CURRENT SOURCE OUTR 4 LSB DECODER green digital inputs (bits G4 to G9) 6 4 MSB DECODER blue digital inputs (bits B0 to B3) CURRENT SOURCE OUTG 4 LSB DECODER blue digital inputs (bits B4 to B9) BLANK control input SYNC control input 6 MSB DECODER CONTROL REGISTER CURRENT SOURCE OUTB CURRENT REFERENCE MSC215 SLT reference current decoupling input (Iref) QUICK REFERENCE DATA Power supply 5V Total analog supply current 64 mA (RL= 37.5 ) Total digital supply current 15 mA (RL= 37.5 ) 16 mA (RL= 150 ) 10 mA (RL= 150 ) DC integral non-linearity DC differential non-linearity Maximum clock frequency 1 LSB 0.5 LSB 50 MHz (RL= 37.5 ) 35 MHz (RL= 150 ) Total power dissipation 385 mW (RL= 37.5 ) 130 mW (RL= 150 ) Package Datasheet (12 NC) Multimedia PC LQFP48 (SOT313-2) 9397 750 01021 4-27 DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS SAA7165 Video Enhancement and D/A processor (VEDA2) Digital Colour Transient Improvement (DCTI) increases colour transition sharpness 16-bit parallel input for 4:1:1 and 4:2:2 YUV data Separate DACs with 9-bit resolution on Y signals and 8-bit resolution on U and V signals Line-locked data clock with maximum sampling rate of 32 MHz 8-bit luminance and multiplexed colour difference formats with optional 7-bit format Microcontroller input supports various clock and pixel rates Controllable peaking of luminance signal and coring stage with controllable threshold eliminates noise Interpolation filter increases data rate in chrominance path 1 V output range with 75 load No external adjustments required 4 The highly integrated SAA7165 upsamples and interpolates YUV signals before D/A conversion and includes colour transient improvement and noise reduction. The input format is first checked to ensure the right interpolation filter is used and is then formatted into the internal processing format. Peaking of the Y signal compensates for several bandwidth reductions in external pre-processing, providing increased sharpness. The coring stage suppresses small high frequency signal components generated by the bandpass gain to reduce noise disturbances, with the remaining high frequency peaking component available for weighted addition after coring. The chrominance interpolation filter consists of various filter stages, multiplexers and de-multiplexers, increasing the data rate by a factor of 2 or 4. After the DCTI stage, which improves the transition behaviour of the UV colour difference signals, the signals are D/A converted using resistor chains with low impedance output buffers. QUICK REFERENCE DATA Power supply 5V Total supply current t.b.f. DC integral non-linearity 1 LSB DC differential non-linearity 0.5 LSB Total power dissipation t.b.f. Package PLCC44 (SOT187) Datasheet Handbook IC22 CUR Y7 to Y0 8 Y FORMATTER PEAKING AND CORING 8 CY Y DAC 3 DATA SWITCH data clock U UV FORMATTER INTERPOLATION FILTER DCTI (B - Y) DAC 2 V MC LLC HREF Y REFLY YUV-bus UV7 to UV0 VDDA4 REFLUV CUV TIMING CONTROL DAC 1 (R - Y) RESET SCL I2C-bus SDA I2C-BUS CONTROL TEST CONTROL SAA7165 MSC202 4-28 Multimedia PC DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS SAA7167(A) Crefh Bin Gin Rin Mixer and D/A processor (MDAC) Three analog mixers blend DAC output with external RGB signals High speed triple 8-bit DACs Two's-complement or binary offset input format Keying control block supports pseudo-colour, highcolour and true-colour input modes YUV-RGB colour space conversion according to CCIR-601 standard Voltage output amplifiers for each of the RGB channels MIXER OPAMP Rout MIXER OPAMP Gout MIXER OPAMP Bout YUV7 to YUV0 UV7 to UV0 REFORMATTER YUV TO RGB MATRIX 8-BIT DAC (3x) MUX HREF SDA SCL I2C-BUS CONTROL CLOCK GENERATOR SAA7167 KEYING CONTROL RESN MSB914 VCLK PCLK EXTKEY P7 to P0 This mixed-mode IC converts digital YUV video data to analog RGB video and mixes it with external analog RGB input from another source, usually the VGA graphics board, allowing the display of video in a window on the PC monitor. This is an essential function in many desktop video applications such as video conferencing or Video-CD playback. Input YUV information is processed through the video data path. First the reformatter demultiplexes the various YUV formats (4:1:1, 4:2:2, 2:1:1) into the standard internal data format of 4:4:4. After digital colour space conversion from YUV to RGB, identical triple 8-bit DACs designed with voltage-drive architecture (one for each of the RGB channels), provide highspeed data conversion either at 50 MHz or 100 MHz (`A' version). The chip will also accept RGB 5:6:5 input passed directly to these DACs. Mixers, controlled by the keying control block, blend the signals with external RGB. Internal level shifters and amplifiers match the external analog inputs with the output level of the DACs and each final RGB output is then buffered with a built-in voltage output amplifier, so it can be used for direct driving of an 150 load. QUICK REFERENCE DATA Power supply Total supply current (Vclk= 50 MHz) DC integral non-linearity 1 LSB DC differential non-linearity 1 LSB Total power dissipation Package Datasheet (12NC) Multimedia PC 5V 100 mA t.b.f. TQFP48 9397 750 00416 4-29 4 DESKTOP VIDEO MISCELLANEOUS ICs SAA7192A FORMATTER Digital Colour Space Converter (DCSC) 4 CCIR-601 compliant conversion matrix Input formatter with multiplexer, Y-delay line and Cr/Cb interpolating filters Gamma correction with on-board VLUTs Y DELAY DATAIN1 DATAIN2 MATRIX MULTIPLEXER Cr AND Cb FILTER DATAIN3 HREF Matched pipeline delay line on horizontal reference signal PIPELINE DELAY LINE SAA7192A VIDEO LOOK-UP TABLES DATAOUT1 VIDEO LOOK-UP TABLES DATAOUT2 VIDEO LOOK-UP TABLES DATAOUT3 HREF_OUT I2C-BUS RECEIVER MSC214 I2C-bus ADDRESS The SAA7192A DCSC is a digital matrix for transforming 16-/24-bit digital input signals into an RGB 24-bit format in accordance with CCIR-601 recommendations. Accepting the various input formats from a digital multistandard decoder, it provides a constant propagation delay and has a maximum data rate of 16 MHz. The matched pipeline delay line permits the HREF signal to be synchronized with the video data at the output. QUICK REFERENCE DATA Power supply 5V I2C-bus interface Yes Total supply current Total power dissipation (max.) Package 150 mA 1.5 W PLCC68 (SOT18-8AA, AGA, CGS) Datasheet 4-30 Handbook IC22 Multimedia PC DESKTOP VIDEO MISCELLANEOUS ICs SAA7195A Video and Memory Controller (VMC) VDY (7:0) VDC (7:0) VIDEO DATA PATH (VDP): FILTER, SCALING, VLUTs, MATRIX CHROMA KEY sync signals video clock Accepts multi-standard 15/16-bit YUV and RGB video signals in CCIR-601/656 input video formats Frame grabber for image capture Real-time scan rate signal conversions (both interlaced and non-interlaced) Control signals for colour and chroma keying FIFO RD (23:01) MUX VRAM/ DRAM video data SAA7195A ACQUISITION CONTROL address VRAM CONTROL RAM-Ctrl chroma key DISPLAY CONTROL PC-INTERFACE COLOUR KEYING video select MBE203 AD(23:01) Ctrl display clock Decimation and interpolation filters to reduce conversion errors Range of on-chip video processing functions Luminance and chrominance filters to adapt bandwidth and data rate Brightness Contrast Saturation control on YUV output bus graphics syncs pixel clock graphic data 4 Variety of YUV output formats Display resolution up to 1024 x 1024 pixels Combining several functions on one chip, the SAA7195A provides signal filtering, formatting, scaling and video buffering functions, as well as controlling video memories and providing an interface to the PC bus. Supporting any number of VRAMs between two and twelve, the memory controller can handle a range of simple to high-end applications. By using real-time transfer it can store a complete 4:2:2 format PAL field in a single VRAM bank (4 VRAMs, each 256k x 4-bit). Video processing functions include horizontal filtering, a simple arbitrary downscaling compatibility using pixel/line dropping and a continuous squeeze, zoom panning and scrolling function. YUV output can be merged with RGB for windowing, or encoded to CVBS or Y/C signals. QUICK REFERENCE DATA Power supply I2C-bus interface Total supply current Total power dissipation (max.) Package Datasheet Multimedia PC 5V No 260 mA (@ fclk = 32 MHz) 2W QFP160 (SOT322B-1) Contact Philips 4-31 DESKTOP VIDEO MISCELLANEOUS ICs TDA4820T composite sync vertical sync COMPOSITE SYNC OUTPUT VERTICAL SYNC OUTPUT COMPOSITE SYNC SLICING VERTICALSLICING & INTEGRATION AMPLIFIER & BLACK LEVEL 50% PEAK SYNC VOLTAGE Sync separator IC for monitors 4 Positive video input signals, capacitive-coupled Operates with non-standard video signals Video amplifier with black level clamping Generation of composite sync slicing level at 50% of peak sync voltage Generation of vertical sync slicing level at 40% of peak sync voltage Vertical sync separator with double slope integrator Delay time of vertical output determined by external resistor Output stages for vertical and horizontal sync TDA4820T MSC198 C2 C3 220 nF 220 nF positive CVBS signal R1 QUICK REFERENCE DATA Power supply Typical supply current Vsync (p-p) Vertical sync output Composite sync output (max.) Total power dissipation (typ.) 4-32 12 V 8 mA 50 - 500 mV 10 V 10 V 150 mW Package SO8 (SOT96A) Datasheet Handbook IC22 Multimedia PC DESKTOP VIDEO MISCELLANEOUS ICs TDA8540(T) VCC(D0,1) VCC(D2,3) SWITCH MATRIX 4 x 4 video switch matrix S-Video or CVBS processing 3-state switches for all channels Selectable gain for video channels Sub-address facility Auxiliary audio outputs for audio switching System expansion up to 7 devices (28 sources) Static short-circuit proof outputs ESD protection IN3 PEAKCLAMP GAIN DRIVER 3 OUT3 IN2 PEAKCLAMP GAIN DRIVER 2 OUT2 IN1 PEAKCLAMP/ BIAS GAIN DRIVER 1 OUT1 IN0 PEAKCLAMP/ BIAS GAIN DRIVER 0 OUT0 2 CL0 to CL1 4 4 DECODER 1 OF 4 DECODER 1 OF 4 4 DECODER 1 OF 4 4 DECODER 1 OF 4 G0 to G3 4 EN0 to EN3 4 TDA8540 VCC DGND 2 2 2 SUPPLY 2 D1 I 2 C RECEIVER D0 AGND power reset MSC216 Primarily designed for switching between composite video signals, four input lines allow switching between two S-Video or four CVBS signals. Each of the four outputs can be set to a high impedance state, permitting parallel connection to several devices. Controlled via the I2C-bus, 3-bits of the I2C address can be selected via sub-address input pins, providing for parallel operation of 7 devices. Control options include clamping input signals to their negative peak (top sync); selecting a gain factor of 1x or 2x for the output; individually connecting output to input; setting impedance state of outputs individually; and controlling two binary output data lines for switching accompanying sound signals. S0 S1 S2 SCL SDA QUICK REFERENCE DATA Power supply 8V Typical supply current Crosstalk attenuation between channels Total power dissipation (max.) Package Datasheet Multimedia PC 20 mA 70 dB 750 mW TDA8540 DIL20 (SOT146E) TDA8540T SO20 (SOT163A) Handbook IC22 4-33 4 DESKTOP VIDEO SAMPLE ANALOG ICs Sample analog ICs Although digital systems are the driving force behind video processing on the desktop PC, analog systems are still dominant in broadcast and will be for the immediate future. Philips, with vast experience in TV and video applications, has a diverse range of analog chips that could be used in the front-end of desktop video applications. The following ICs are just a small selection from this range; for more details, refer to the `TV designer's guide' and the `Satellite and terrestrial TV front-end designer's guide'. 4 TDA4655 HUE Generic multistandard analog decoder chroma Automatic recognition of broadcast standard No adjustments required Reduced external components PAL / NTSC OSCILLATOR DIVIDER PLL HUE - CTRL SERVICE ACC PAL / NTSC DEMODULATOR TDA4655 BLANKING COLOURKILLER BUFFER SECAM DEMODULATOR DEEMPHASIS Low voltage and low power dissipation Not all time constraints integrated (ACC, SECAM de-emphasis) 2 fsc - (R-Y) - (B-Y) PAL / SECAM PAL SECAM NTSC3.5 NTSC4.4 The TDA4655 is an integrated, full multistandard analog colour decoder with negative colour difference output signals, designed to operate with Philips' integrated baseband delay line (TDA4665). An on-board PLL generates a reference clock signal at twice the colour carrier frequency and is available to drive external devices such as a PAL comb filter. The IC can distinguish both NTSC 3.5 and NTSC 4.3 colour carrier frequencies automatically. SYSTEM CONTROL NTSC STANDARD SCANNING IDENT STANDARD SELECTION PULSE PROCESSING BANDGAP REFERENCE SANDCASTLE DETECTOR SSC MSC203 VP QUICK REFERENCE DATA Power supply 8V Typical supply current Total power dissipation Package Datasheet 4-34 31 mA 248 mW TDA4655 SDIL24 (SOT234) TDA4655T SO24 (SOT137A) Handbook IC02 Multimedia PC DESKTOP VIDEO SAMPLE ANALOG ICs TDA4665 Baseband delay line Multistandard baseband delay line circuit Two comb filters, using switched-capacitors for one line delay time (64 s) Adjustment-free application No crosstalk between SECAM colour carriers Clamping of AC-coupled input signals 4 Addition of delayed and non-delayed output signals NTSC comb filtering to suppress cross-colour distortion The TDA4665 is an integrated baseband delay line circuit with one delay line suitable for decoders with both positive and negative colour difference signal outputs. It includes output buffer amplifiers on-chip. QUICK REFERENCE DATA Power supply (analog and digital) 5V Total supply current 5.9 mA Total power dissipation 30 mW Package TDA4665 DIL16 (SOT38-4) TDA4665T SO16 (SOT109A) Datasheet (12NC) (R-Y) SIGNAL CLAMPING LINE MEMORY colour-difference input signals (B-Y) SAMPLEAND-HOLD (R-Y) LP pre-amplifiers addition output stages buffers SIGNAL CLAMPING LINE MEMORY sandcastle pulse input 9397 750 00381 SANDCASTLE DETECTOR FREQUENCY PHASE DETECTOR SAMPLEAND-HOLD 3 MHz shifting clock colour-difference output signals (B-Y) LP TDA4665 DIVIDER BY 192 LP 6 MHz CCO DIVIDER BY 2 MSC221 Multimedia PC 4-35 DESKTOP VIDEO SAMPLE ANALOG ICs TDA8501 PAL/NTSC analog encoder 4 Alignment free modulators for PAL and NTSC Chrominance processing via a range of integrated alignment-free filters Operates with either internal free running oscillator or external sub-carrier signal RGB and YUV input signal paths with multiplexing for insertion of teletext/OSD Fast switching between RGB and YUV inputs CSYNC PAL / NTSC (f H /2) TDA8501 PULSE SHAPER ADDER OSC DL LPF MODULATOR BUFFER BPF R G B ADDER MATRIX Y out notch CVBS out BUFFER switch MGA462 Y U V chroma out Sync separator circuit and pulse shaper for on-chip generation of timing signals Y + sync, C and CVBS outputs Signal amplitudes are correct for 75 driving via an external emitter follower This highly integrated analog PAL/NTSC encoder converts RGB or YUV signals to PAL or NTSC broadcast standards. RGB signals are connected to a matrix which outputs YUV, via clamping and line blanking circuits and if selected, the U, V matrix output signals can be routed to low pass filters, and the Y signal to the adder where it is combined with the sync pulse. Signals are routed through a PAL/NTSC selection switch, as the filter/modulator stages operate in different modes depending on the standard. External Y and -U, -V signals can also be fed directly to the switch and multiplexed with the generated YUV signals. The -3 dB nominal frequency response levels for the low pass filters are 1.35 MHz for PAL and 1.1 MHz for NTSC. Processing of chrominance signals includes low frequency filtering; then, after signal modulation, a blanker blocks the signal during the sync period to avoid signal distortion from the control loop. QUICK REFERENCE DATA Power supply 5V Typical supply current Chrominance crosstalk -60 dB Total power dissipation 200 mW Package Datasheet 4-36 40 mA TDA8501 DIL24 (SOT234AH2) TDA8501T SO24 (SOT137AH1) Handbook IC02 Multimedia PC DESKTOP VIDEO SAMPLE ANALOG ICs TDA8505 SECAM analog encoder Alignment free integrated filters Reference oscillators locked to the line frequency CSYNC fH /2 sandcastle Vident RGB and YUV input signal paths with multiplexing for insertion of teletext/OSD Oscillators can be crystal controlled Colour kill and vertical identification modes Sync separator circuit and pulse shaper for on-chip generation of timing signals Sandcastle output for transcoding applications Y + sync, C and CVBS outputs TIMING AND REF. FREQ. GENERATOR TDA8505 FRAME IDENT GAIN LIMITER PHASE DET FM MODULATOR PHASE DET LPF R G B FILTER + BLANKING Csync MATRIX 4 + switch CVBS MGA463 Y U V DL The TDA8505 is a SECAM variant of the TDA8501 encoder incorporating many of the same functions. It cannot use an external sub-carrier signal and requires a single adjustment. QUICK REFERENCE DATA Power supply Total analog supply current Total digital supply current Total power dissipation Package Datasheet Multimedia PC 5V 39 mA 4 mA 215 mW DIL32 Handbook IC02 4-37 DESKTOP VIDEO SAMPLE ANALOG ICs TDA4670 Picture signal improvement processor SDA SCL 4 Luminance signal delay from 20 ns up to 1100 ns (minimum step 45 ns) Colour transient improvement (CTI) reduces colour difference transient times to those of high frequency luminance signals Aperture correction Luminance peaking in 4 steps 2.6 or 5 MHz peaking centre frequency with -3, 0, +3 and +6 dB peaking Noise reduction by coring AUTOMATIC DELAY TIME CORRECTION TDA4670 TDA4671 I 2 C - BUS RECEIVER VARIABLE DELAY 20 TO 1155 ns IN 45 ns STEPS Y APERTURE CORRECTION CORING STAGE DEGREE OF PEAKING - (R-Y) or (R-Y) Y (td) - (R-Y) or (R-Y) TRANSIENT DETECTOR sandcastle pulse SANDCASTLE PULSE DETECTOR HIGH PASS FILTER SWITCH DRIVER STORAGE CAPACITORS TRANSIENT DETECTOR - (B-Y) or (B-Y) - (B-Y) or (B-Y) MBA805 - 1 Handles negative and positive colour difference signals 5 or 12 V sandcastle input pulse synchronizes timing pulse generation Automatic luminance signal delay correction Luminance and colour difference input signal clamping with capacitor coupling The TDA4670 processes luminance and colour difference signals to improve picture quality. Colour transients are improved on the chrominance signal; the luminance signal is delayed and it can also be improved by peaking and noise reduction. QUICK REFERENCE DATA Power supply Typical supply current Total power dissipation (max.) Package Datasheet 4-38 5V 41 mA 0.97 W DIL18 (SOT102) Handbook IC02 Multimedia PC DESKTOP VIDEO SAMPLE ANALOG ICs TDA4686(WP) Analog video processor Intended for double line frequency applications (100/120 Hz) Luminance/negative colour difference signal interface Black level clamping of colour difference, luminance and RGB input signals with capacitorcoupling DC level storage Two analog RGB inputs with BCS control Same RGB output black levels for Y/C and RGB input signals Full multistandard RGB matrix with fast switching between standards BCS and peak white adjustments Timing pulse generation from a 2- or 3-level sandcastle pulse Two switch-on delays prevent discoloration before steady-state operation Clamped output or automatic cut-off with picture tube leakage current compensation Peak drive and average beam current limiting Emitter follower RGB output stages hue control voltage (to NTSC decoder) SDA I2C-bus controlled outputs for hue-adjust of NTSC decoders No delay of clamping pulse A luminance and colour difference interface for video processing in TV receivers, the TDA4686's primary function is to process the luminance and chrominance signals from a colour decoder. It accepts two RGB source signals, from a SCART connector or an OSD generator and outputs RGB signals to drive video output stages. All parameters are fully I2C-bus controlled. Additional members in this device family offer different types and degrees of white level control and the range includes an IC for use with standard line frequency applications. There is also a version with additional on-chip control. QUICK REFERENCE DATA Power supply 8V Total supply current 60 mA Luminance input (peak-to-peak) 0.45 V Power dissipation 1.2 W TDA4686 TDA4686WP Package 1.0 W TDA4686 DIL28 (SOT117) TDA4686WP PLCC28 (SOT261CG) Datasheet Handbook IC22 vertcal flyback pulse HUE CONTROL I 2 C - BUS RECEIVER TDA4685, TDA4686 TDA4687, TDA4688 SCL SANDCASTLE PULSE DETECTOR sandcastle pulse 1 st AND 2 nd SWITCH ON DELAYS TIMING GENERATOR leakage and cut-off current feedback CUT - OFF COMPARATORS LEAKAGE STORAGE FSW 1 R1 G1 B1 Y (VBS) - (R-Y) - (B-Y) FSW 2 R2 G2 B2 SAT. CONTROL PAL/SECAM, R NTSC G RGB B MATRIX FAST SIGNAL SWITCHES, BLANKING R CONTRAST G CONTROL B BRIGHTNISS CONTROL, BLANKING PEAK DRIVE AND PDL AVERAGE BEAM CURRENT LIMITING WHITE LEVEL CONTROL PEAK DRIVE LIMITER CUT - OFF CONTROL R G B OUTPUT STAGES CUT - OFF STORAGE R G B to video output stages MBA800 - 2 average beam current Multimedia PC PEAK DRIVE STORAGE 4-39 4 5 TELEVISION Multimedia PC 5-1 TELEVISION ANALOG TV TUNERS/SOUND DECODERS ANALOG TV TUNERS VHF/UHF off-air TV and cable tuners 50 to 850 MHz PLL-controlled tuning Tuning and control via I2C bus RTMA M and N system Baseband video and stereo sound output FCC radiation, signal handling, immunity compliant TYPE NUMBER COUNTRY Fl1236 USA CONNECTOR F or M Fl1236J Japan F or M Fl1246 UK/Ireland IEC Fl1256 France IEC Fl1216 Rest of Europe IEC These tuners, available from Philips Components, integrate into Philips Semiconductors desktop video chipset to provide a complete solution for display of TV in the PC environment, either full screen or within a window. 5 Sound Decoders The MTS (Multichannel Sound Modulation) stereo sound from the tuner contains the Left and Right sound in the 50 to 15,000 Hz band. A pilot tone is transmitted at 15,734 Hz, and the L-R signal is modulated on a 31,468 Hz carrier. The Second Audio Program (SAP) sound channel allows broadcasts in two languages and is modulated on a 78,670 Hz subcarrier. The stereo decoder locks its PLL to the pilot tone and extracts the left, right and SAP sound signals. These ICs are a representative selection from a larger family, described in more detail in the TV designer's guide. PHILIPS SOUND DECODERS TDA9850 TDA9852 TDA9855 TEA5582* Stereo decoder type BTSC/SAP BTSC/SAP BTSC/SAP BTSC DBX noise reduction Yes Yes Yes No Adjustable input level Yes Yes Yes No via I2C-bus No Yes No No 60 dB output No No No Yes at audio signal zero crossing Mute control Yes Yes Yes No Interface for external noise reduction circuits No Yes No No Independent channel volume control No Yes Yes No Automatic volume level control No Yes Yes No Loudness characteristic linked to volume control No Yes Yes No Tone (bass and treble) control No No Yes No Sub-woofer or surround output No No Yes No Selector for external source (line in) No Yes Yes Yes I2C-bus transceiver Yes Yes Yes No *The older TEA5582 has no DBX decoder, so no licence is required to use this IC, as is the case with the TDA985x family. The licence can be obtained from THAT Corporation. 5-2 Multimedia PC TELEVISION SOUND DECODERS TDA9850 I2C-bus controlled BTSC stereo/SAP decoder Selectable DBX decoded outputs include stereo, mono, SAP Additional SAP output without DBX but including de-emphasis Automatically tuned integrated filters Composite input noise detector with selectable thresholds for stereo and SAP off The TDA9850 is a bipolar integrated BTSC stereo/SAP decoder and DBX expander for TV, VCR and multimedia applications. Incorporating a stereo pilot PLL and ceramic resonator circuit, it provides automatic I2C adjustment of stereo channel separation with two selectable pilot thresholds and automatic pilot cancellation, providing quasi-alignment free operation. All filter functions necessary for stereo and SAP demodulation and part of the DBX filter circuits are provided on-chip using transconductor circuits, with the required accuracy obtained by an automatic filter alignment circuit. 5 ceramic resonator L+R L - BSAP STEREO DECODER DEMATRIX + MODE SELECT stereo OUTL mono SAP to OUTR audio processing DE-EMPHASIS SAP without DBX TDA9850 composite baseband input INPUT LEVEL ADJUST SAP DEMODULATOR NOISE DETECTOR STEREO/SAP SWITCH DBX STEREO ADJUST LOGIC, I2C TRANSCEIVER MAD MSB647 SDA SCL CL CR Multimedia PC 5-3 TELEVISION SOUND DECODERS TDA9852/55 I2C-bus controlled BTSC stereo/SAP decoder and audio processor The TDA9852 and TDA9855 are enhanced versions of the TDA9850. Incorporating the same stereo, SAP and DBX functions, they also include a hi-fi audio processor providing an extensive range of audio processing features, as well as a processor for producing linear stereo, pseudo stereo, spatial stereo and forced mono effects. The TDA9852 has an additional interface for external noise reduction circuits and offers I2C-bus mute control; while the TDA9855 includes tone control (independent bass and treble) and a sub-woofer or surround sound output with its own volume control. Refer to the table for details. 5 QUICK REFERENCE DATA TDA9850 TDA9852/55 Power supply 9V 8.5 V Supply current 58 mA 75 mA 60 dB 60 dB - 94 dB SNR line out (mono) audio section Channel separation Stereo > 25 dB > 25 dB SAP/dual sound > 70 dB > 70 dB Bandwidth Stereo 50 Hz to 10 kHz 50 Hz to 11 kHz 50 Hz to 8 kHz 50 Hz to 8 kHz Total harmonic distortion 0.2% 0.2% Package TDA9850: SDIP32 (SOT232-1) TDA9852: SDIP42 (SOT270-1) Mono, dual sound/SAP TDA9850T: SO32 (SOT287-1) TDA9855: SHDIL52 (SOT247AH) TDA9855WP: PLCC68 (SOT188CG) Datasheet (12NC) 9397 750 00176 TDA9852: 9397 750 00706 TDA9855: Handbook IC22 EIR ceramic resonator LOR LIR AUTOMATIC VOLUME AND LEVEL CONTROL STEREO DECODER comp INPUT LEVEL ADJUST SAP DEMODULATOR VIR STEREO/ SAP SWITCH DBX DEMATRIX + LINEOUT SELECT INPUT SELECT STEREO ADJUST LOL EFFECTS LOGIC, I2C TRANSCEIVER VOLUME RIGHT LOUDNESS CONTROL TDA9855 VOLUME LEFT LOUDNESS CONTROL VIL LIL BASS RIGHT CONTROL TREBLE RIGHT CONTROL ZERO CROSSING SUBWOOFER MATRIX, VOLUME SURROUND BASS LEFT CONTROL TREBLE LEFT CONTROL OUTR OUTS OUTL MSB648 MAD SDA SCL EIL 5-4 Multimedia PC TELEVISION SOUND DECODERS TEA5582 PLL BTSC stereo decoder QUICK REFERENCE DATA Power supply 7 V to 16 V Automatic mono/stereo switching via pilot presence detector LED driver for stereo indicator Smooth mono/stereo control Total current consumption (typ.) with no LED driver Matrix and two amplifiers for left and right output signals Source selector for switching between internal MUX signal and external signals External de-emphasis control 6 dB attenuation of (L-R) with respect to (L+R) prior to matrix Total power dissipation (max.) 19 mA THD (at VO = 600 mV) 0.3 % Channel separation 28 dB SNR (bandwidth IEC 79) 82 dB 160 mW Package DIL20 (SOT146) Datasheet Handbook IC02 5 An integrated phase-locked loop (PLL) stereo decoder, the TEA5582 is primarily designed for low cost stereo decoding in low- to medium-range applications. It accepts either a low impedance current input to the MUX, or can be switched to accept an external input. The de-emphasis and the amplifier gain can be set with external passive components. It has full ESD protection. VP phase detector PHASE DETECTOR STABILIZER VCO left de-emphasis VOLTAGE CONTROLLED OSCILLATOR FREQUENCY DIVIDER left channel input 2 left AMP fH VOLTAGE CONTROLLED OSCILLATOR ON/OFF SWITCH TEA5582 2fH fH fH Vo left AMP (L+R) MUX VOLTAGE-TOCURRENT CONVERTER AMP x1 SYNCHRONOUS DEMODULATOR AMP CONVERTER input 1 left mute MATRIX input 1 right AMP 2fH AMP SMS CONTROL x1 (L-R) (L-R) Vo right fH +Vref PILOT-CANCEL PILOT PRESENCE DETECTOR MONO/STEREO SWITCH LED DRIVER AMP right channel input 2 right MSC222 source selector Multimedia PC pilot presence detector smooth mono/stereo control LED driver right de-emphasis (L-R) de-emphasis 5-5 TELEVISION 5 CLOSED CAPTION/TELETEXT DECODERS Philips has a range of teletext decoders applicable to the multimedia PC market. The choice of decoder will depend on a number of issues including page access time, language support, cost, package and whether to use a single chip or decoder/RAM solution. These `multimedia' decoders are described below and on the following pages is a selection of ICs from Philips full range of teletext, closed caption and line 21 decoders. PC Text teletext software Multimedia teletext decoders All Philips multimedia decoders offer: I2C bus control by a bus master such as the SAA7146 Simple application, requiring very few external components Similar register maps Support by the PC Text teletext software RF Intelligent page acquisition and caching Level 1.5 teletext Teletext functions accessible using any programming language capable of calling functions from Windows DLLs Teletext window class usable as main window or as a control Supports a range of teletext devices Optional Fastext support C and Visual Basic demonstration application The PC Text software consists of a number of Windows (3.1, 3.11 and `95) DLLs and a window class, allowing quick development of Teletext applications on PCs using a compatible teletext decoder. It allows a single teletext device to be used by more than one application simultaneously. The acquisition software makes intelligent use of multichannel teletext devices to acquire and cache pages the user is likely to want next, ensuring minimum delay. With the SAA5246A or SAA5281, it provides caching of up to 30 pages. PC Text provides full language coverage for Western Europe and can be extended to cover all WST areas. COLOR DECODER/ SCALER TUNER CVBS TELETEXT DECODER I2C PCI BUS MASTER PCI Bus MSC234 SAA5246A SAA5249 SAA5254 SAA5281 8 (external) 500 (external) 1 (internal) 8 (internal) Acquisition channels 4 1 1 4 Language/region All WST By region By region All WST Features External 8 x 8 K SRAM Single-chip teletext decoder Single-chip decoder with On-chip 8 x 8 k No. of pages for page storage with data slicer and on-chip 8 x 1.1 k RAM; RAM; supports acquisition display driver supports Fastext/FLOF Fastext/FLOF and TOP Package QFP64, DIL48 SO24, DIL24 QFP64, DIL40 QFP64, SDIL52 Datasheet Handbook IC02 Handbook IC02 Handbook IC02 Handbook IC02 5-6 Multimedia PC TELEVISION CLOSED CAPTION/TELETEXT DECODERS SAA5284 VDDA Multimedia VBI and FF data acquisition IC CVBS0 High performance multistandard data slicer Intercast and DataCast PDC (packet 30 and 31) compatible Supports 525 line teletext (USWST, NABTS and MOJI) and 625 line teletext (EuroWST and ChinaCCST) Supports European and American Closed Captioning Supports Wide Screen Signalling (WSS) and Video Programming Selection (VPS) data User programmable data format 2 kbyte data cache CVBS1 Iref black VSSA VDDD VSSD RESET VPOin[7...6] LLC2 HREF LLC DMACK WR (1) WR (1) DMARQ C8[1...0] ANALOG SWITCH INT PACKET BUFFER AND FRONT END CONTROL REGISTERS ANALOGUE VIDEO TO DATA BYTE CONVERTOR (DATA DEMODULAT OR) OSCILLATOR AND TIMING MULTI STANDARD HOST INTERFACE (INTEL, MOTOROLA, DIGITAL VIDEO) RDY (1) SEL[1...0] DENB A[2...0] D[7...0] PACKET FILTERING (e.g. WST PACKETS 30/31) (1) (1) FIFO I 2C INTERFACE 400 kHz SLAVE SDA SCL PACKET BUFFER RAM, 2KBYTE (45 PACKETS) MSC233 OSCOUT OSCGND OSCIN TEST0 TEST1 5 Choice of clock frequencies (direct-in clock or crystal oscillator) Parallel, Motorola, Intel, I2C and digital video bus interfaces Data type selectable on individual video lines, with VBI and FF modes Programmable interrupt, DMA or polling driven Optimized for EMC The SAA5284 is a Vertical Blanking Interval (VBI) and Full Field (FF) video acquisition IC tailored specifically for PC addin cards, motherboards and set-top boxes. It supports all common teletext and closed caption formats and will filter packets 30 and 31 WST/NABTS; it also has scope for accepting as yet unspecified formats. A very highly integrated IC, it incorporates all the necessary data slicing, interfaces, data filtering and control logic, so requires very few external components for design-in. Controlled via the parallel interface or the I2C-bus, it can output data via the digital video bus when a parallel interface is not available. QUICK REFERENCE DATA Power supply 5V Supply current t.b.f. Typical sync amplitude Crystal frequency Package Datasheet Multimedia PC 0.3 V 12, 13.5, 15, 16 MHz QFP44 Contact Philips 5-7 TELEVISION CLOSED CAPTION/TELETEXT DECODERS SAA5252 V H Line 21 decoder RGBREF DISPLAY TIMING OSCIN `Stand-alone' or I2C-bus controlled line 21 decoder On-chip display RAM allowing full page Text mode Enhanced character display modes OSCILLATOR OSCGND Full colour captions Automatic handling of Field 2 data Automatic selection of (1H, 1V), (2H, 1V) and (2H, 2V) scan modes Onboard OSD facility using character generator CHARACTER ROM ADDRESSING OSCOUT SAA5252 BLAN CHARACTER GENERATOR CODE INTERPRETER AND ADDRESSING R ROUNDING ITALICS AND RGB MULTIPLEXOR G B BLANIN RIN GIN PAGE RAM BIN DR BLACK IREF CVBS SYNC SEPARATOR AND ACQUISITION TIMING ADC DATA DETECTOR I2C INTERFACE SERIAL/ PARALLEL AND PARITY SDA SCL CONTROL MSC189 2 I C/DC 5 The SAA5252 is a single-chip line 21 decoder that will acquire, decode and display line 21 Closed Captioning data from a 525-line CVBS signal. Normal and line progressive scan modes are supported; it has an RGB interface for standard colour decoder ICs and RGB inputs which support signals from external OSD ICs. The displayed characters are defined on a 5 x 12 matrix within a 7 x 13 window, allowing one blank pixel either side and a pixel row above. It has video, text and caption display modes. QUICK REFERENCE DATA Power supply 5V Supply current 30 mA I2C-bus interface Yes CVBS sync. amplitude 0.3 V CVBS video amplitude Package Datasheet 5-8 1V SAA5252P DIL24 (SOT101) SAA5252T SO24L (SOT137-1) Handbook IC22 Multimedia PC TELEVISION CLOSED CAPTION/TELETEXT DECODERS SAA5290 One-page economy teletext/TV microcontroller Complete single-chip one-page teletext decoder and TV microcontroller Supports Western European, Eastern European, Turkish, Cyrillic, Arabic and Thai languages Double size, double width and double height character capability for OSD Enhanced display features including meshing and shadowing Separate display and acquisition timing for increased flexibility 525 and 625 line display synchronization BLACK IREF VSYNC CVBS0 CVBS1 TELETEXT ACQUISITION DATA SLICER DISPLAY TIMING HSYNC FRAME R, G, B ACQUISITION TIMING PAGE RAM VDS DISPLAY COR XTALIN XTALOUT SAA5290 OSC OSCGND 16K8 ROM RESET 80C51 CPU 256x8 RAM TEXT I/FACE data addr ADC PWM TIMER/ CTRS/I 2C int PORT 3 PORT 2 PORT 1 PORT 0 P3.0-P3.4/ ADC0-2 P2.0-P2.7/ PWM P1.0-P1.7/INT0,IN T1, T0, T1, SDA, SCL P0.0-P0.7 MSC205 5 Standby mode through power-down of teletext and analog hardware Direct driving of LEDs 80C51 compatible microcontroller 16 kbytes masked ROM 256 bytes on-chip RAM Six 6-bit PWMs and one 14-bit precision PWM 4-bit DAC and comparator with 3-input multiplexer, providing 3 successive approximation software ADCs Master and slave bit-level I2C-bus This IC is a single-chip one-page economy teletext decoder and TV microcontroller. It decodes 625-line based WST (World System Teletext) transmissions and provides a range of TV control and OSD functions. The teletext decoder is derived from a single page teletext decoder and static RAM is included on-chip to hold one complete page of teletext for decoding/storage. Interrupt logic 0 is triggered on rising and falling edges, allowing pulse-width measurement for remote control decoding. The microcontroller is an industry standard 80C51 device and the SAA5290 is available as a mask-programmed ROM version or as a Flash EEPROM version in a multichip package, for product development. QUICK REFERENCE DATA Power supply 25 mA Analog supply current 35 mA Teletext supply current Crystal frequency Package Datasheet Multimedia PC 5V Microcontroller supply current 20 mA 12 MHz SDIP52 (SOT247-1) Handbook IC02 5-9 TELEVISION CLOSED CAPTION/TELETEXT DECODERS SAA5296 BLACK IREF VSYNC Single-chip economy 10 page teletext/TV microcontroller CVBS0 CVBS1 TELETEXT ACQUISITION DATA SLICER DISPLAY TIMING HSYNC FRAME R, G, B 10-PAGE RAM ACQUISITION TIMING VDS DISPLAY COR 5 Complete multistandard teletext decoder and TV controller chip RGB interface to standard colour decoder Supports video and scan related sync. modes Single crystal oscillator for teletext decoder, microcontroller and display Ten page (10240 x 8) on-board teletext and OSD memory Handles Western and Eastern European, and Turkish, Cyrillic, Arabic and Thai languages 260 characters in mask programmed ROM Acquisition and decoding of VPS data (EBU PDC System A) Double size, width and height capability for OSD Enhanced display features and automatic detection of Fastext Colour palette with 8 colours for both foreground and background. 80C51 compatible microcontroller with 32 kbytes mask programmed ROM and 768 bytes RAM Eight 6-bit PWMs and one 14-bit PWM for tuning control Four ADCs implemented as an 8-bit DAC and comparator with 4 multiplexed outputs As a combined, single-chip economy ten page TV teletext decoder and controller IC, the SAA5296 is intended to provide the central control mechanism in a TV receiver. It will decode 625 and 525 line based WST transmissions and provides tuner control functions and OSD facilities. The teletext decoder is a derivative of the IVT1.1X and the TV microcontroller is based on an industry standard 80C51. A ten page static RAM module is incorporated on-chip as memory for both teletext and OSD functions. Information regarding teletext signal quality, whether it is 625 or 525 line broadcast and which language variant is in use can all be read via the I2C interface. Packet 26 data is handled by dedicated hardware. There are two versions of this chip, either with Flash EEPROM in a multichp package for software development or mask programmed ROM. SAA5296 XTALIN XTALOUT OSCILLATOR OSCGND 32 K x 8 ROM 256 x 8 RAM ANALOG-TODIGITAL CONVERTER PULSE WIDTH MODULATOR 512 x 8 AUX RAM data RESET 8051 CPU address INT PORT 3 PORT 2 P3.0 to P3.4 P2.0 to P2.7 INT TIMER/ CTRS/ I 2 C PORT 1 PORT 0 P1.0 to P1.7 P0.0 to P0.7 MSB591 - 1 EXTENDED TYPE NO. VERSION PACKAGE SAA5296ZP/nnn ROM SAA5296GP/nnn Int./ext. ROM QFP80 (SOT318) SAA5499ZP/nnn EEPROM SDIL52 (SOT247) SDIL52 (SOT247) QUICK REFERENCE DATA Power supply Supply current Supply current (standby text) Clock frequency Datasheet 5-10 TEXT INTERFACE 5V 115 mA 30 mA 12 MHz Handbook IC22 Multimedia PC TELEVISION DIGITAL CABLE/SATELLITE ICs Digital Broadcasting by cable and satellite is one of today's most significant technologies. Philips' integrated chipset is not only ideal for a highly-featured DVB set-top box or a DVB/DAVIC cable modem, but is also ready for building into TVs, DVD players and PCs. We are ideally placed to give our customers a clear lead, as the only semiconductor and component manufacturer that can supply a completely integrated system solution, for both cable and satellite systems. By drawing on our vast audio and video experience in both analog and digital fields, we provide a complete, single supplier solution, allowing you to reach the market very quickly. Philips is actively involved in defining standards for these markets and we fully support the DVB and DAVIC standards. For the cable modem market, Philips intends to support both IEEE802.14 and the Cable Labs standards as they develop. 5 Receiver Input Satellite channel OUTDOOR UNIT TUNER QPSK CONTROLLER MULTISWITCH QPSK DEMODULATOR FEC Satellite front-end Cable front-end Signal access and control MPEG decoding DESCRAMBLER AUDIO DEMULTIPLEXER VIDEO RISC PROCESSOR GRAPHICS Output AUDIO DAC VIDEO ENCODER R/F MODULATOR MSB999 CABLE TUNER I/F AMPLIFIER/ CONVERTER QAM DEMODULATOR CARD READER INTERFACE FEC I/F demodulation Multimedia PC Cable channel 5-11 TELEVISION DIGITAL CABLE/SATELLITE ICs SATELLITE TDA8040 TDA8043 QPSK demodulator One-chip satellite channel decoder (ADC/QPSK/FEC) 5 Quadrature accuracy optimized for digital television Low crosstalk between I and Q channels High input sensitivity Internal voltage stabilizer for the VCO ensures good shift performance The demodulator amplifies the received RF signals in a high gain amplifier and mixes them with two LO signals, 90 out of phase, generated using an internal Voltage Controlled Oscillator (VCO) and frequency divider. The resulting Inphase (I) and Quadrature (Q) signals are buffered separately to drive external low pass filters used for baseband filtering and then amplified. Handles QPSK and BPSK modulation schemes Accepts variable symbol rates at up to 32 Msymbols/s 35%/50% roll-off Nyquist filter and A/D converters built-in Programmable loop filters provide for internal clock recovery and AGC loops No external loops This is a one-chip, DVB compliant demodulator with Viterbi/Reed-Solomon decoding for Forward Error Correction, with de-interleaver and descrambler. TDA8041 TDA8705(A) QPSK demodulator controller Dual ADC Operates with low SNR applications Handles up to 30 Msymbols/s On-board DACs and op-amps provide high flexibility for loop time constraints The QDMC TDA8041H is designed specifically to work with the QDM and generates all the control signals needed to demodulate QPSK (and BPSK) signals. TDA8042 UHF QPSK demodulator Symbol rates up to 45 Msymbols/s AGC detector and amplifier with a 21 dB control range Phase accuracy to less than two degrees; typically one degree The TDA8042 is an enhanced version of the TDA8040, handling QPSK modulated RF signals from 350 MHz to 650 MHz and with an on-chip 0 and 90 phase shifter. 5-12 2 times 6-bit resolution High SNR over a large analog input frequency range TTL output Two separated inputs (AC-coupling) TTL-compatible digital inputs Low level AC clock input signal allowed Internal reference voltage regulator Low analog input capacitance with no buffer amplifier needed No sample-and-hold circuit required The TDA8705 and TDA8705A are 6-bit high-speed dual ADCs. Converting two analog input signals into two 6-bit binary-coded words they are designed for DBS (Direct Broadcast Satellite) QPSK satellite video applications. Both ICs interface directly to the TDA8040 and all-digital demodulators for DVB or other DBS systems. The TDA8705 has a maximum sampling rate of 40 MHz with an effective SNR of 5.8 bits at 10 MHz full-scale input; the TDA8705A has a maximum sampling rate of 80 MHz with an effective SNR of 5.5 bits at 20 MHz full-scale input. Multimedia PC TELEVISION DIGITAL CABLE/SATELLITE ICs CABLE SYSTEMS TDA8761A TDA9819 9-bit ADC IF amplifier/converter and TV-VIF Maximum sample rate of 30 MHz In-Range (IR) tri-state TTL output High Signal-to-Noise Ratio (SNR) and low power dissipation TTL-compatible inputs and outputs No buffer amplifier is required No external sample-and-hold circuit needed Optimized for digital video, the TDA8761A is a 9-bit converter with high linearity, delivering the conversion accuracy needed in 256 QAM demodulation for all symbol frequencies. It is guaranteed for no missing codes. IF down conversion mixer with internal and external AGC for DTV Complete analog VIF including AGC and AFC Multistandard VIF stage handles positively and negatively modulated signals Sound IF stages process FM standards and L-standard AM sound demodulation Processing of NICAM L sound carrier Provides Vision IF (VIF) and sound IF signal processing with a single reference Phase Locked Loop (PLL) demodulator, combined with the signal stages for IF processing to the DVB standard. TDA8790 TDA8046H 8-bit 40 Msps 2.7 - 5.5 V universal ADC Multi-mode QAM demodulator 8-bit resolution with sample rates up to 40 MHz Supports 4, 16, 32, 64 and 256 modulation schemes Operates between 2.7 V and 5.5 V DC sampling allowed Integral 15% or 20% roll-off Half-Nyquist filter Compensation for offset between I and Q branches CMOS/TTL-compatible digital inputs and outputs High Signal-to-Noise Ratio (SNR) and low power dissipation No buffer amplifier is required No external sample-and-hold circuit needed The TDA8790 is a low-power, low-cost universal CMOS ADC for video and general purpose applications which includes a sleep mode to reduce device power consumption when inactive down to 4 mW. It is suitable for QPSK applications and when used with the TDA8046 QAM demodulator, provides a cost effective 64 QAM system solution. (For 256 QAM, use the TDA8761A described above.) Multimedia PC Decision Feedback Equalizer produces constellation diagram with no training sequence required Four de-mapping schemes, including an 8-bit parallel format suitable for FEC Variable symbol rates with external hardware support Broadly similar in function to the TDA8045, this enhanced digital demodulator covers both European and USA standards. From the ADC, the TDA8046H accepts TTL-compatible signals and processes them to I and Q baseband signals. Digital control values for coarse AGC are derived and converted onchip to analog control currents; these are feed back via a loop filter using an op-amp, which gives flexibility in selection of the PLL loop time constraints. The same basic scheme is also used for the clock and carrier recovery. The equalizer function, implemented with a T-spaced 12- or 14-taps adaptive filter with feedback, produces a `clean' constellation diagram, which is fed to the output formatter. 5-13 5 TELEVISION DIGITAL CABLE/SATELLITE ICs SIGNAL ACCESS AND CONTROL SAA7201 SAA7206 MPEG-2 decoder with graphics DVB compliant descrambler 5 Decoding of video data in MPEG-2 PES, MPEG-1 packet or ES format using less than 2 Mbit of DRAM On-board vertical and horizontal scaling functions and a range of trick modes Layer-1 and layer-2 MPEG audio decoding supporting mono, stereo, surround sound and dual channel modes On-chip audio de-emphasis, volume control and programmable channel mixing From 16 Mbit, a minimum 1.2 Mbit is memory available for graphics Multiple graphics boxes with background loading, fast switching scrolling and fading Support for direct bitmaps or bitmaps coded to DVB region-based graphics standards The SAA7206 descrambles MPEG-2 signals in line with the European DVB Super Descrambler Mechanism algorithm. A parser separates MPEG-2 compliant transport streams and routes them on to the main descrambler block. With the adoption of the MPEG-2 compression standard in the broadcasting world, Philips has developed a highly integrated multistandard MPEG-2 decoder specifically for broadcast applications. It handles audio and video MPEG-2 streams and also includes DVB graphics and OSD capability. SAA7205 MPEG-2 transport and demultiplexer SAA7207H Reed/Solomon decoder On-board teletext filter compatible with TXT input the SAA7183 video encoder High speed filter allows output of entire transport packets or packet payloads On-chip clock generation for interfacing to the descrambler Works on its own on non-scrambled signals Descrambles MPEG-2 Transport Stream (TS) or Packetized Elementary Stream (PES) signals Descrambler includes stream and block decipher modules, with PID and CW banks Conditional access data is retrieved and passed to the microcontroller On-chip C interface with memory mapped I/O Handles DVB compliant R/S code Automatic synchronization of bytes, blocks and frames De-interleaving according to a convolutional scheme High throughput R/S decoder block with three fully pipelined hardware computation units On-board error correction Energy dispersal de-scrambling algorithm Six quasi-bi-directional ports and an I2C-bus interface This IC provides Forward Error Correction for cable systems. An input data stream, interpreted as non byte-aligned, is passed to the synchronization block. This interprets a byte stream in fixed length blocks of 204 bytes starting with a synchronization byte, and both de-interleaving and Reed/Solomon decoding are based on this block structure. After descrambling, this IC demultiplexes a broadcast signal. A parser separates MPEG-2 compliant transport streams which, after error handling, are routed to audio and video filters with decoder specific interfaces, and the system microcontroller. 5-14 Multimedia PC 6 RADIO Multimedia PC 6-1 RADIO PC RADIO MODULES The OM560x family of FM tuner modules has been designed to operate in the harsh electrical environment of a PC and deliver high quality stereo radio reception. Shielded for use in the PC, they meet the FCC requirements on radiation. These tuner modules comprise a core self-tuned radio, an amplifier and a bus converter which enables I2C-bus or STR control and provides three additional I/O control lines. Three modules are available to meet various international frequency and connector requirements. A number of complete reference boards are also available using these modules, covering a basic tuner board, a multimedia board including sound processing and an enhanced multimedia board with R(B)DS functionality. FM RECEIVER FE 75 aerial IF AMP/DET MPX LINE AMPLIFIER TDA1308T TEA5757H R line output L SYNTH. MPX OM5604 BUS CONVERTOR PCF8574T (optional) 3 I/Os MSB942 IIC-bus or STR-pins 6 QUICK REFERENCE DATA OM5604 OM5606 OM5608 Region USA Europe Japan Frequency 87.5 to 108 MHz 87.5 to 108 MHz 76 to 90 MHz Connector F-connector IEC F-connector Datasheet 9397 750 00352 9397 750 00352 9397 750 00358 Software The processing power available in the PC environment allows designers to model the user interface on that of a high specification music system. To simplify the design task, Philips has designed reference software and can supply a number of sample programs including application programs for DOS and Windows, and a test program. Software is supplied as Pascal source code. User interface functions such as step, search and so on, and control of communications through the I2C-bus, are handled through the software. The software displays and controls all sound functions including volume, bass and treble, source selection and mute, balance (left/right and front/rear) and display of the R(B)DS information. Up to 99 pre-set channels are available, which can also be set manually, giving the user a wide choice of configurations. It is also possible to search for only those stations that play a particular style of music, either by manual tuning or automatically scanning for particular R(B)DS codes. 6-2 Multimedia PC RADIO PC RADIO MODULES TEA5757H/5759H RECEIVER Self-tuned radio Combined tuning synthesizer and radio Unique analog fast-tuning algorithm typically identifies 40 stations within 20 s High signal-to-noise ratio Automatic fine tuning to counter signal drift Local/DX switching TUNING AM VCO AM AFC AM CHANNEL INTERFACE LEVEL V/I A/D level FM AFC FM CHANNEL bus DIGITAL CONTROL & TUNING FUNCTION FM VCO MPXin ref. osc. Sout DET. Cloop FM STEREO DECODER SDS TEA5757H STABILIZER MSB961 L Stop detection circuit and microcontroller bus interface on-chip audio R The TEA5757H is a highly integrated single-chip, self-tuned radio covering AM (LW, MW and SW) and stereo FM broadcasts and is available in versions covering European/USA (87.5 to 108 MHz) and Japanese (76 to 91 MHz) frequencies. The chip uses Philips' unique fast-tuning algorithm which increases tuning speed the greater the distance to the desired frequency. Once the tuner has defined the VCO frequency of a channel within a set window, when that station is selected the chip fine tunes the signal using the quality of the received signal as a reference, to lock the receiver to that frequency. The system then goes into a power saving stand-by mode and if at any time the quality of the signal weakens, then the chip wakes up and finetunes itself once more, using the previously set VCO frequency. Local/DX switching ensures reception is not overpowered when tuned to strong local transmitters. 6 QUICK REFERENCE DATA Power supply Static Tuning Supply current Total harmonic distortion 15 mA FM 16 mA 71 dB AM 55 V FM 1.2 V AM 0.8% FM MPX channel separation Total power dissipation (max.) Package Datasheet (12NC) Multimedia PC 12 V AM SNR RF sensitivity 2.1 to 12 V 0.3% 30 dB 250 mW QFP44 (SOT307) 9397 750 00557 6-3 RADIO PC RADIO MODULES TDA1308T Class AB stereo headphone driver The TDA1308T is a high performance integrated class AB headphone driver providing a high SNR and slew rate, combined with low distortion. Its low power consumption and small size make it ideal for MPC audio applications. This IC is described in detail in the `Digital audio' section, on page 8-16. PCF8574A INTERRUPT LOGIC INT 6 Remote 8-bit I/O expander for I2C-bus LP FILTER PCF8574 A0 A1 I2C-bus to parallel port expander 8-bit remote I/O port for the I2C-bus Up to three additional control lines Open-drain interrupt output Low standby current consumption of 10 A maximum Latched outputs with high current drive capability for direct driving of LEDs A2 SCL SDA INPUT FILTER I 2 C BUS CONTROL SHIFT REGISTER 8 BIT P0 to P7 I/O PORTS WRITE pulse VDD READ pulse POWER-ON RESET MSC192 The optional PCF8574A provides general purpose I/O expansion for most microcontrollers via the two-line bidirectional bus (I2C), allowing I2C or STR control of the tuner module. It includes an 8-bit quasi-bidirectional port and an I2C interface. An interrupt signal can be sent on a dedicated line to the microcontroller, allowing the remote I/O to inform the microcontroller if there is incoming data, without using the I2C-bus. QUICK REFERENCE DATA Power supply 2.5 to 6 V Typical supply current 40 A Typical standby current 2.5 A Power-on reset value (max.) Total power dissipation (max.) Package 6-4 400 mW PCF8574P/AP DIP16 (SOT38-1) PCF8574T/AT SO16 (SOT162-1) PCF8574TS Datasheet 2.4 V SSOP20 (SOT226-1) Handbook IC22 Multimedia PC RADIO Philips has an extensive range of complementary ICs for building complete multimedia sound cards with in-built radio, reducing design time and simplifying complete system design. Very few external components are needed for PC systems based on the OM560x family of modules. MULTIMEDIA/RADIO BOARDS WITH R(B)DS CCR921 R(B)DS DECODER SAA6579 RDS DEMODULATOR OM5604 FM MULTIMEDIA MODULE 75 aerial I2C-bus Philips offers two multifunction, multimedia radio reference boards. Both include a sound processor, which can also accept input from a CD-ROM drive, as well as a graphic equalizer and power amplifier. The second also offers R(B)DS functionality. These boards are intended as design examples; Philips has a great range of other audio processing ICs, allowing customers to build a variety of multimedia audio boards with various functionalities. CD-ROM sound line input TDA1517P POWER AMPLIFIER TEA6320 SOUND PROCESSOR ISA-BUS INTERFACE power output line output TEA6360 5 BAND EQUALIZER MULTIMEDIA FM-RADIO CARD MSB943 CCR921 I2 C 6 R(B)DS controller CTRQN RDDA Supports all R(B)DS group types All decoded R(B)DS data plus status information available via I2C-bus R(B)DS information available for processing by the PC in real-time Data buffering (up to 700 ms), allows instant access and `intelligent' searching on specific R(B)DS data Fast synchronization with block type A search signals from RDS/RBDS demodulator DAVN RDCL CCR921 OSCI additional outputs RESET SYNC TP TA M/S I 2C-CLOCK I 2 C-address A0 A1 I2 C-DATA MSC120 Error processing with correction status for every block The CCR921 is an 80C51 C with intelligent RDA data decoding and pre-processing software incorporating automatic error detection and correction. It accepts R(B)DS data and converts it into tuning and display information. The microcontroller handles decoding of all R(B)DS codes under I2C-bus control, after which all R(B)DS data is present within the serial interface protocol. As an I2C slave, no multimaster bus is required. QUICK REFERENCE DATA Power supply Typical supply current I2C-bus interface Oscillator frequency Package Datasheet Multimedia PC 5V 24 mA Yes 8.664 MHz QFP44 Contact Philips 6-5 RADIO MULTIMEDIA/RADIO BOARDS WITH R(B)DS SAA6579 +5 V R(B)DS demodulator 6 2nd order anti-aliasing filter 8th order 57 kHz bandpass filter separates R(B)DS data from the MPX signal Reconstruction filter (2nd order) 57 kHz subcarrier regenerated by a Costas Loop PLL RDCL signal (RDS clock) recovered by a second PLL with lock on biphase data rate Biphase symbol decoder with integrate and dump functions Pre-amplifier and comparator with automatic offset compensation Signal quality detector CMOS-level digital outputs Subcarrier output OSCI MUX MPX signal 57 kHz BANDPASS (8th ORDER) ANTIALIASING FILTER OSCILLATOR AND DIVIDER RECONSTRUCTION FILTER V OSCO DDD QUALITY BIT GENERATOR QUAL DIFFERENTIAL DECODER RDDA SCOUT SAA6579(T) CIN +5 V CLOCKED COMPARATOR VDDA V ref BIPHASE SYMBOL DECODER COSTAS LOOP VARIABLE AND FIXED DIVIDER VP1 REFERENCE VOLTAGE RDCL CLOCK REGENERATION AND SYNC TEST LOGIC AND OUTPUT SELECTOR SWITCH VSSA TSTLD TEST T57 VSSD MSC204 After digitization, the radio signal is synchronously demodulated to recover the biphase data symbols, which are further processed in an integrate and dump circuit which generates the RDDA (RDS Data) signal. The data signal RDDA and the regenerated clock signal RDCL are provided as outputs for further processing by a suitable decoder (or microcomputer) such as the CCR921. The operation of the SAA6579 is in accordance with the CENELEC EN 50067 standard. The boards are completed with the following ICs: TDA1517P stereo radio power amplifier. A stereo, singleended audio amplifier delivering 2 x 6 W per channel for driving passive speakers. TEA6320/1/2/3 sound processors. A family of sound processors and audio control circuits, providing digital control via the I2C bus of various sound parameters. TEA6360 5-band graphic equalizer. The TEA6360 5-band stereo graphic equalizer is an I2C-bus controlled tone processor for applications such as radios, TVs and music centres with Dolby noise reduction. QUICK REFERENCE DATA Power supply 5V Total supply current 6 mA Minimum R(B)DS input amplitude (RMS) Oscillator frequency Package SAA6579 SAA6579T Datasheet 6-6 1V 4.332/8.664 MHz DIL16 (SOT38GG6) SO16 (SOT162A) Handbook IC01 Multimedia PC RADIO DIGITAL RADIO SYSTEMS Astra Digital Radio The ADR system uses the ISO/IEC 11172-3 MPEG-1 layer-II international standard, more commonly known as Musicam, for the digital encoding/decoding of audio signals for transmission over their satellite network. Digital transmission allows provision of CD quality sound and ADR will provide two services to their customers, at the moment primarily in Germany but likely to be extended to other countries. These are a `free-to-air' service for public and private radio stations, and a subscription-based DMX (Digital Music Express) service, offering 60 different channels at the moment, to be extended to 120 thematic channels. SAA2530 SAA2502 The SAA2530 has been designed specifically to handle and decrypt ADR/DMX transmissions and it performs all the demodulation and decoding functions required for the processing of the full frequency range of ADR SIF input signals. For details of the SAA2502 and others in the SAA250x family of MPEG decoders, please refer to the Digital Audio section, page 8-12. The first IC in Philips' 2nd generation of MPEG decoders (the SAA2502) and an ADR specific demodulator and decoder chip (the SAA2530) are the only chips required for demodulation, decoding and audio processing of both formats of ADR signals. 6 It provides QPSK demodulation and de-interleaving of the ancillary data. After pre-processing, this allows for display of programme-related information, auxiliary data and R(B)DS information. A full ADR system would also include a card reader and verifier IC to check for the relevant subscription information for the pay-radio service. The SAA2530 includes an 8-bit A/D converter and gain controlled amplifier, and performs the synchronization of MPEG-1 layer-II data, which can then be passed on to the SAA2502 interface. A number of additional features are available with this chip such as Viterbi and differential decoding, depuncturing and descrambling, and FEC functions. It has interfaces for both I2C and L3-bus control. ADR DEMODULATION, DECODING & AUDIO PROCESSING L SATELLITE TUNER MPEG SAA2530 R SAA2502 I2S-bus SPDIF LNB POWER REMOTE CONTROL TRANSCEIVER PUSH BUTTONS AND DISPLAYS ancillary data MICROCONTROLLER CARD READER AND ELECTRONICS MSC027 Multimedia PC 6-7 RADIO DIGITAL RADIO SYSTEMS Digital Audio Broadcast channel decoder The Musicam encoding system used in ADR will also be used for the European Digital Audio Broadcasting standard, and Philips has a first generation DAB chipset. The DAB channel decoder contains all the key components for the Eureka-147 DAB system, supporting DAB modules I, II and III and all the main features of the EBU ETSI draft prETS 300 401. It provides real-time processing of the FIC (Fast Information Channel) and up to six service components, with error protection for both audio and data services. The channel decoder includes three main ICs: a differential demodulator and DSP interface (FADIC), a program selector (SIVIC) and the SAA2501 MPEG-1 or SAA2502 MPEG-2 audio source decoder. The whole chipset is suitable for small DAB receivers. FADIC SIVIC Differential demodulator and DSP interface Program selector 6 Input symbol buffering Frequency transposition Decoding of FIC (Fast Information Channel) and up to six service components 256-, 512- or 2048-point complex FFT Differential demodulation Metric generation 8-bit parallel input and output interfaces 16-bit parallel control interface 4-bit soft decision Viterbi decoding 320 kB decoding capacity 432 unit deinterleaving capacity Error flag generated by re-encoding CRC syndrome calculation on each FIB 4-bit parallel input and serial output (DAB3) interfaces 256 K x 4 DRAM and L3 microcontroller interface The FADIC is frame independent and operates on a symbol basis. It processes each symbol in the baseband frame in an identical manner. The SIVIC performs service selection, frequency and time-deinterleaving, and Viterbi decoding. SAA250X DIGITAL MODULE TUNER MODULE Audio source decoders For details of the SAA250x family of audio MPEG decoders, please refer to the Digital Audio section, page 8-12. RAM TUNER IF FADIC SIVIC SAA2501 or SAA2502 I2S CONTROL DSP MSB960 user interface 6-8 Multimedia PC 7 COMPACT DISC Multimedia PC 7-1 COMPACT DISC CD SYSTEMS As one of the pioneers of CD technology, Philips IC and system solution offering for CD-audio, CD-ROM, CD-Recordable, CD-i, Video-CD and other CD systems is so large, it is impossible to cover in detail in this document. Some key ICs and systems for CD-ROM/CD-recordable MPC applications are described here; for a full round up, please refer to the separate CD Designer's Guide (12NC 9398 750 00952). CD SYSTEMS Philips makes a number of complete CD-ROM and CDRecordable system solutions, including all the ICs and components needed to design a complete drive. Available from Philips Key Modules, comprehensive starter-kits include a fully operational sample, and all the technical documentation and software. They are guaranteed to meet specification, so are a valuable tool for simplifying design-in for manufacturers, reducing both costs and time-to-market. The systems themselves are in fact capable of higher performance than those published in the starter kit specifications so with careful optimization, drive manufacturers can easily differentiate their products in a highly competitive market. ROM 65XXX 7 6x and 8x CD-ROM system solutions ROM 65XXX are families of subsystems and complete, predeveloped system solutions for economy 6x and 8x, and highend 8x CD-ROM drives. The high performance 8x solutions are based around the ROM 65300 subsystem, a pre-developed CD-ROM engine optimized to deliver an average sustained data rate of 1200 kbytes/s, 115 ms seek time and 140 ms access time. It uses a fast, low power CD decoder IC with sophisticated error correction specifically for CD-ROM systems. Its specially developed mechanism features a brushless disc motor optimized for high speed operation, delivering long lifetime and high reliability. Available in a tray-type loader, which also has special suspension units to provide the extra damping and disc clamping required for sustained high performance 8x operation, the complete engine is designed for installation in a 5.25" half-height disk bay. For fast radial access, the sledge transmission has ultra-high ratio gearing, controlled by an adjustment-free servo system. The servo processor uses an FTC (Fast Track Count) algorithm optimized for high speed performance and has other features such as enhanced tracking capabilities and automatic initialization. The engine also includes the diode amplifier and laser supply which, by being incorporated onto the sledge of the CDM mechanism, improves the SNR as the diode currents are converted to HF signals close to the source. 7-2 A pre-programmed, masked microcontroller is available, handling all the servo and decoding functions and offering a comprehensive control interface to reduce design effort further. The system also includes a serial control interface (S2B) with serial digital data output for further processing by a CD-ROM block decoder. The ROM 65200 subsystem for economy 8x systems is similar, but uses a different loader/mechanism; the ROM 65100 is a 6x subsystem. All three subsystems are also available as complete system solutions, including either the SAA7388 (see page 7-6) or SAA7385 (see page 7-7) block decoder/controller ICs, for IDE and SCSI versions respectively. ROM 65300 CD-ROM ENGINE LO9585/88 COMPACT DISC DECODER OQ8875 DIODE AMPLIFIER & LASER SUPPLY CDM12.10 3-BEAM MECHANISM WITH BRUSHLESS MOTOR OQ8868 LO9585/88 DIGITAL SERVO CONTROLLER COMPACT DISC DECODER audio L/R BA5934 L1270 CD LOADER DIGITAL SERVO DRIVERS TDA7072A CDT6xx S2B bus MICRO CONTROLLER SERVO DRIVER MSC301 Multimedia PC COMPACT DISC CD SYSTEMS ROA 1312 CD-ROM system solution Philips latest CD-ROM solution is capable of 12x operation, achieving an average sustained data transfer rate of 1800 kbytes/s, 110 ms seek time and 120-135 ms access time. This exceptional performance is achieved using the SAA7348 All Compact disc Engine (ACE), which combines CD decoding, servo-processing and microcontroller functions all on one chip (see next page). It also has a completely new tray loader and mechanism, dust tight and vibration free, specially developed for operation at these very high speeds. As with the ROM 65XXX systems, the engine is available in both IDE and SCSI system solution versions. TDA1545 audio L/R OQ8875 DA CONVERTOR DIODE AMPLIFIER & LASER SUPPLY I2S SAA7388GP SAA7348 ACE1 ROM1312 3-BEAM MECHANISM WITH BRUSHLESS MOTOR DECODER DIGITAL SERVO CONTROLLER V4 S2B bus BLOCKDECODER INTERFACE (ELM) + EXTERNAL 1 MB DRAM I2C bus ROM1312 CD LOADER IDE-bus with ATAPI commands POWER AMPLIFIER MICRO CONTROLLER MOTOR CONTROL + MOTOR DRIVER MSC297 ROM1312 CD-ROM SUB-SYSTEM CD-RECORDABLE SYSTEMS LO9585 Based on the CDU 2600 CD-R subsystem, the CDU Data Engine forms the basis for a complete data CD-R drive, delivering 2x speed recording and playback at up to 6x speed, with a fast access time of <300 ms at 6x operation. digital output COMPACT DISC ENCODER R . . . W subcode TDA1371HP serial data input serial data output TDA1372HP SIGNAL PROCESSOR COMPACT DISC ENCODER subcode input CDM2600 The Recorder CDU 2600 subsystem provides all the basic functions for a CD-Recordable application. It incorporates a CDencoder and decoder and a dedicated tray-type CD loader, fully pre-wired with a simple interface and incorporating all the special suspension and clamping features required for recordable applications. A dedicated pre-programmed microcontroller ensures reliable operation and provides a versatile interface; it handles all servo, calibration and laser control functions during read, write and access operations, as well as controlling CDdecoding/encoding operations. The subsystem can also be used in audio applications. 3-BEAM MECHANISM CDL2600 57SZA1010T OQ8845T DIGITAL SERVO DRIVERS DIGITAL SERVO CONTROLLER LO9600 DECICATED MICRO CONTROLLER serial user interface CD LOADER MSC300 The Data Engine incorporates the high performance SAA7390 CD-R controller and host interface IC, providing both SCSI and ATAPI solutions (see page 7-8). A complete CD-R drive built around the CDU 2600 will fit into a standard 5.25" drive. Also available is the Recorder E65400 and its derivative Data Engine (D65420), which provides 2x speed write and 4x speed read. Multimedia PC 7-3 7 COMPACT DISC INTEGRATED CD DECODERS SAA7348 ACE (All Compact disc Engine) ROM SAA7348 7 CPU CORE High speed (up to 12x) integrated CD-engine All standard decoder functions implemented digitally on-chip Built-in access procedure RAM TELE QCLV Radial and focus servo loop with automatic closed loop gain Sledge motor servo loop with pulsed sledge support Lock-to-disc mode Low focus noise SFR DECODER SERIAL RAM RAM ROM PLA REGs SERIAL SERVO HFin Audio data peak level detection Full error correction strategy (t = 2 and e = 4) PLL LFin MSC232 2-4 times oversampling integrated digital filter including fs mode FIFO overflow concealment for rotational shock resistance Kill interface for DAC deactivation during digital silence EBU interface handles audio and data S2B serial interface with host controller The SAA7348 is a highly integrated IC incorporating the functionality of a CD decoder and digital servo driver. In addition, a large part of the glue logic from the ROM65000 CD-engine family has also been integrated to minimize external component count. Although developed primarily for high speed CD-ROM applications, its very high level of integration makes the SAA7348 ideal for a wide range of other CD applications. The high speed servo includes four current input ADCs for focus and two for the radial signals. A comparator input for the Fast Track Count signal is available to achieve high performance jumping. There are two subcode interfaces: the V4 and the EIAJ set. Audio functions include de-emphasis as well as the KILL function and there is a mono output selection. An audio output clock for Bitstream-CC DACs is provided and the audio serial data interface can be set to I2S or EIAJ mode. The decoder can address 16 programmable registers. Control is via an internal micro supporting external memory, or via an external micro. QUICK REFERENCE DATA Power supply I/O pads 3.3 V 5V Analog supply current t.b.f. Digital supply current t.b.f. Package Datasheet 7-4 Core LQFP100 (SOT407-1) Contact Philips Multimedia PC COMPACT DISC INTEGRATED CD DECODERS CD7: SAA7370(B)GP 10x single-chip digital servo processor and compact disc decoder VRL R1,2 VRH D1 to D4 IREFT ADC PREPROCESSING CONTROL FUNCTION RA OUTPUT STAGES VREF GENERATOR FO SL All standard decoder functions implemented digitally Multi-speed decoder with up to 10x playback speeds Full error correction strategy; t = 2 (C1 frames) and e = 4 (C2 frames) Full EIAJ CP-2401 CD-graphics interface 8 frame FIFO overflow concealment for rotational shock resistance Digital audio (EBU) interface provides 32-bit word, IEC958-format biphasemark outputs 2 to 4 times oversampling digital filter, including fs mode Audio data peak level detection Kill interface for DAC deactivation during digital silence Diode signal pre-processing Focus, radial and sledge-motor servo loop Three-line serial interface via microcontroller Fast radial jump or access procedure Low focus noise Automatic closed loop gain control available for focus and radial loops Radial jumps at up to 80 kHz (or 160 kHz `B' version) V4 interface provides subcode data in a similar format to RS232 All ICs in the CD7 family combine the functions of a CD decoder and digital servo processor. They have all the control and start-up procedures found in previous Philips' systems and also including a number of high-level functions such as automatic error handling, automatic sequencers, timer interrupts, and high-level status and interfaces for the decoder and interrupts. SCL SDA RAB MICROPROCESSOR INTERFACE CONTROL PART LDON SAA7370BGP SILD DIGITAL PLL HFIN HFREF ISLICE IREF TEST1 to TEST3 MOTOR CONTROL FRONT END EFM DEMODULATOR ERROR CORRECTOR TEST AUDIO PROCESSOR CRIN CL16 CFLG FLAGS SRAM SELPLL CROUT MOTO1,2 TIMING C2FAIL RAM ADDRESSER CL11 CL4 EBU INTERFACE SBSY SFSY SUBCODE PROCESSOR SUB PEAK DETECT RCK STATUS DECODER MICROPROCESSOR INTERFACE SCLK SERIAL DATA INTERFACE VERSATILE PINS INTERFACE DOBM KILL WCLK DATA EF RESET MSB918 V1,V2 V3 to V5 KILL 7 Signals from the photo-detector in a two-stage three-beam compact disc system are first A-to-D converted and then processed into separate decoder and focus-servo loop signals, for input to the IC's servo control. The decoder signals are then conditioned using logic circuits to obtain control signals. A normalized focus error signal is produced, used to provide extra protection for track-loss generation, drop out detection and the focus start-up procedure. This provides optimum system performance and as the chip automatically adjusts conditioning levels, the need for external factory adjustments is removed. The chip includes a lock-to-disc or CAV (Constant Angular Velocity) mode for playback of discs whose input data-rates vary from the inside to the outside of the disc. It supports pulsed sledge signals and can perform radial jumps; during long jumps the fast radial actuator is dampened electronically. The `B' variant includes an on-chip clock multiplier allowing crystals of 8.4672 MHz and 16.9344 MHz to be used. Both focus and radial control loops can be controlled automatically for short periods, such as at the start of a new disc. QUICK REFERENCE DATA Power supply Total supply current Package Datasheet Multimedia PC 5V 49 mA QFP64 (SOT393-1) Contact Philips 7-5 COMPACT DISC CD-ROM & CD-R/E DATAPATH ICS Philips SAA738x is a family of IDE/SCSI CD-ROM block decoders/interfaces ICs for high speed drives, while the SAA7390 is the first CD-recordable/erasable interface IC to support both ATAPI and SCSI systems. All offer real-time third level error correction and detection and CRC checking of mode 1 (CD-ROM) and mode 2 form 1 (CD-i) sectors. ATAPI/SCSI Data rates Transfer burst rate Max. external memory SAA7388 SAA7385 SAA7390 ATAPI SCSI-2 ATAPI/SCSI 8x read, 4x write up to 12x up to 12x 11.1 Mbytes/s 10 Mbytes/s 16.9 Mbytes/s 16 Mbits DRAM 256 kbytes or 4 Mbyte DRAM 128 kbytes SRAM 1 Mbyte DRAM Error corrector and host interface (up to 12x) RA16/CAS RA15/RAS RWE SYN RD0 to RD7 DMACK DA1 CRIN DA2/EJECT HOST INTERFACE OSCILLATOR CROUT CS2/SELRQ IOCS16 MSB911 - 1 HD8 to HD15 The SAA7388 is a block decoder and buffer manager for up to 12x CD-ROM applications, simultaneously performing input data buffering, error correction and host data transfer. Input data to the CD-DSP interface is programmable as I2S or EIAJ format and is first synchronized, before being decoded and written to the buffer memory, which can hold one full data sector. The error corrector performs two pass correction in real time in 9-bit, 4096 byte words before an EDC (Electronic Data Check) is performed. Sector header and sub-header are then written to the header registers and the microcontroller reads the decoder status, header information and sector start address. MEMORY MANAGER RESET HD0 to HD7 SRAM CACHE IRQ/EOP/HFBC All ATAPI registers are present in the hardware Supports Q-W subcode buffering, de-interleaving and correction Compatible with the Sanyo LC89510, Oak OTI-012 and IDE/ATA/ATAPI hard disk interfaces RA6 to RA14 P INTERFACE SCRST/STEN INT DMARQ/DTEN RA0 to RA5 SCL IORDY/WAIT/HFBLB TEST ERROR CORRECTOR SDA HRD Corrects two errors per symbol with erasure correction 36-kbit erco buffer RAM 12 byte command and status FIFOs HWR Host transfer burst rate of 11.1 Mbytes/s DA0/CMD CS1/HEN 7 DECODER SERIAL INTERFACE SAA7388 TEST1, 2 SFSY SAA7388 C2PO Yes DATA Yes WS Yes No BCK No Dedicated S2B UART interface SUB Yes RCK Supports Q-W subcode under software control and with the use of a RAM test executed by the microcontroller, the SAA7380/88 can work with partially defective dynamic memory units. QUICK REFERENCE DATA Data transfer between the decoders and an external microcontroller, usually an 8051 derivative, is handled via a Motorola SPI-based interface, which can be programmed for Sanyo, Oak or ATA compatibility. Mapping of the external memory is Power supply Total supply current Package Datasheet (12NC) 7-6 5 V (3.3 V) 60 mA QFP80 (SOT318-2) 9397 750 00808 Multimedia PC COMPACT DISC CD-ROM & CD-R/E DATAPATH ICS SAA7385 256k x 8 DRAM High performance CD-ROM controller (up to 12x) NCR53CF94 equivalent SCSI-2 controller allows operation at up to 10 Mbytes/s Single transfers of up to 16 Mbytes SCAM (SCSI Configuration AutoMatically) function for plug and play 48 mA on-chip SCSI drivers BUFFER MANAGER data subcode DATA CONVERTOR & SUBCODE UART LAYERED ERROR CORRECTOR BUFFER MAPPER 53CF94 SCSI data CD DECODER subcode MICROCONTROLLER INTERFACE SAA7385 DSIC DSP 80C32 MICROCONTROLLER DEBUG UART MSB908 Front-end interface includes a block decoder, a sector sequencer, a 212 ms watchdog timer and a subcode interface 80C32 microcontroller with 256 x 8 scratchpad SRAM Three timer/event counters Red book audio pass through Input clock synthesizer 64k x 8 ROM The SAA7385 CD-ROM controller incorporates a SCSI-2 controller, microcontroller and all the necessary front-end interface logic to provide a single-chip, high performance digital solution for up to 12x speed systems. 7 The SCSI controller is software compatible with previous members of the 53C90 family. It has a high speed 16-bit DMA interface to the DRAM buffer manager, which has ten level arbitration logic and uses page mode access for high speed error correction and SCSI data transfer. Third level error corrections are automatically written to the DRAM frame buffer. The microcontroller has a programmable full duplex serial channel and eight general purpose I/O pins, and all control registers can be mapped into the 80C32s special function memory space. All error correction is handled by dedicated hardware, significantly reducing microcontroller workload. QUICK REFERENCE DATA Power supply Total supply current Package Datasheet (12NC) Multimedia PC 5V t.b.f. QFP128 9397 750 00917 7-7 COMPACT DISC CD-ROM & CD-R/E DATAPATH ICS SAA7390 256K x 8 or 4M x 8 DRAM BUFFER High speed CD-recordable block decoder/encoder BUFFER MANAGER data subcode data 7 Generic interface with 16.9 Mbytes/s transfer for external SCSI or ATAPI hosts Incorporates all digital electronics to connect a CD-65 based decoder to a host. Designed for 8x read and 4x write speeds Third level error correction and third layer ECC syndrome calculation Third layer encode/decode and buffer management Block oriented host transfers Supports 256 KB, 1 MB or 4 MB of 70 ns low-cost DRAM C-flag interface provides an absolute time stamp CD DECODER subcode c-flag BASIC ENGINE DATA CONVERTER & SUB-CODE UART LAYERED ERROR CORRECTOR WRITE I/F ENCODE BUFFER MAPPER GENERIC EXTERNAL INTERFACE SCSI or ATAPI interface MICROCONTROLLER INTERFACE SAA7390 S2B UART MSB889 80C32 MICROCONTROLLER 128K x 8 ROM Ten level arbitration logic in buffer manager Authoring software available The SAA7390 CD-recordable/erasable controller chip provides a data path from the host to the CDCEP (CD encoder) for CDR/E operation in both SCSI and ATAPI systems. It combines the interface logic, decoding/encoding and other sophisticated functions required for complete CD-R/E applications. In has on-board 80C32 microcontroller and 53CF90B or 53CF92A/B fast SCSI processor interfaces (which may also use an ATAPI processor), needed to provide full block encode and decode functions. The on-board block decoder function accepts parallel data from the buffer manager, serializes it, calculates the CRC and third-level ECC parity bytes when necessary and outputs them to the CDCEP using a special data clock. An ASSS (Automatic Sector Size Select) function checks the sub-header of Mode 2 data to determine the length of data blocks stored within the memory buffer, with the rest of the frame data loaded into the 3 kbyte buffer. This sector buffer supports a number of data block sizes including Red Book audio, fixed length sectors, and yellow and green book modes and forms. QUICK REFERENCE DATA Power supply Total supply current Package Datasheet (12NC) 7-8 5V t.b.f. QFP128 9397 750 00942 Multimedia PC COMPACT DISC DIODE AMPLIFICATION & LASER SUPPLY TDA1300T Photodetector amplifiers and laser supply Six input buffer amplifiers with low pass filtering and virtually no offset HF data amplifier with a high- or low-gain mode Fully automatic laser control including stabilisation and on/off switch with separate supply for power reduction Optimized interconnection between the pick-up detector and digital servo processor Adjustable laser bandwidth and laser switch-on current slope N- and p- sub laser monitor Built-in equalizers provide single/double speed switching `on-the-fly' Constant laser output regardless of ageing Small outline package allows close mounting to photo-diodes on the CD mechanism I6 I5 I4 I3 I2 I1 I6in I5in I4in I3in I2in I1in 6 1.5x 5 1.5x 4 1.5x 3 1.5x 2 1.5x 1 1.5x Id6out O6 Id5out O5 Id4out O4 Id3out O3 Id2out O2 Id1out O1 TDA1300T Icsin -4 I/V HG RFE LS ADJ MI VDD IADJ (N-sub) or (P-sub) RF VDDL Vmon (N-sub) or Imon Vgap OTA ILO LO (P-sub) VDD SUPPLY This IC derives filtered currents for tracking, focus control and the HF data signal for the CD decoder. They can be used with a wide variety of 3-beam/sledge optics with p- and n-sub lasers with single or double Foucault focus error detectors. LDON ON/OFF GND CL MSC187 QUICK REFERENCE DATA Power supply Diode current amplification (typ.) Equalization delay time Laser supply output current (max.) Package Datasheet (12NC) Multimedia PC 3.0 to 5.5 V 1.55 320 ns 100 mA SO24L 9397 750 00441 7-9 7 COMPACT DISC DIODE AMPLIFICATION & LASER SUPPLY TZA1015 VDDLF Data amplifier and laser supply (H-DALAS) 7 Six voltage-input buffer amplifiers with low pass filtering and virtually no offset Universal photodiode IC interface using internal conversion resistors Broadband RF data amplifier designed for sustained 16x data rates (up to 18x max) Selectable RF gain for CD-Rewritable/CD-ROM applications Programmable RF/FTC gain for optimal dynamic range and playability Radial error signal for fast track counting Fully automatic laser control including stabilization and an on/off switch, plus a separate supply for power efficiency VCOM VDDRF GND LF AND RF SUPPLY + S6 + S5 + D4 + D3 + D2 + D1 Vref - x O6 - x O5 - x O4 - x O3 - x O2 - x O1 GSE GARF I/V TZA1015 VDDL MI Vgop I/V LO I/V Automatic monitor diode polarity selection (n-sub/p-sub) Adjustable laser bandwidth and laser switch-on current slope using external capacitor Protection circuit to prevent laser damage due to supply-voltage dip Optimized interconnection between data amplifier and Philips' digital servo/decoder circuits LDON MSC302 This data amplifier and laser supply circuit is designed to provide system flexibility and an optimal interface to Philips' current input servo-decoders. The RF amplifier has a programmable bandwidth, allowing the IC to be used in CD audio or CDROM systems with up to 16x sustained data rates. A programmable RF gain and a gain switch to select CD or CD-R/E systems provides optimal playability. QUICK REFERENCE DATA Power supply channel matching (max.) -3 dB bandwidth 80 kHz RF amplifier -3 dB bandwidth 40 MHz max flatness delay 0.9 ns max output current -100 mA Laser supply Package Datasheet 7-10 5V LF amplifier 1% FS p-type monitor input 0.15 V n-type monitor output VDD - 0.15 V SO28 (SOT136) Contact Philips Multimedia PC COMPACT DISC DIGITAL SERVO CONTROLLER OQ8868 Digital servo controller (DSIC-S) VDDD SIDA/SDA DA SICL/SCL CDID COMM SILD RAB ENIIC Focus, radial and sledge servo loop Built-in access procedure Sophisticated track loss detection mechanism Automatic focus start-up procedure and in-lock indication (incl. fast focus restart) Automatic gain control for the complete focus and radial loop Defect and shock detectors Flexible system oscillator Extended radial error signal Automatic initialization and jump procedure for radial servo Automatic offset and gain control for radial error Single/double Foucault and astigmatic focusing The highly integrated OQ8868 digital servo controller is optimized for CD-ROM applications, providing all servo functions for two-stage CD-systems except the spindle motor control. It accepts diode currents and drives various power stages, and the servo loops are very low noise. It can be tailored to the requirements of a broad range of CD-systems by adjusting the servo characteristics via the fast three-wire serial interface. RSTI NS SL NS FO NS RA FTC VDDA D1 ANALOG-TO-DIGITAL CONVERTER D2 ANALOG-TO-DIGITAL CONVERTER D3 ANALOG-TO-DIGITAL CONVERTER D4 ANALOG-TO-DIGITAL CONVERTER S1 ANALOG-TO-DIGITAL CONVERTER S2 ANALOG-TO-DIGITAL CONVERTER XTLR ANALOG-TO-DIGITAL CONVERTER RP CONTROL MONITOR TL FOK LDO RSTO VSSA OTD ERROR DETECTION DEFI VrefH VrefL XTALO XTALI TEST1 INTREQ DEFO REFERENCE CLKO OSCILATOR OQ8868 TEST TEST2 MSC212 VSSD QUICK REFERENCE DATA Power supply Analog supply current 5 mA Digital supply current 17 mA Maximum quiescent current 10 A Package Datasheet (12NC) Multimedia PC 5V QFP44 (SOT307-2) 9397 750 00785 7-11 7 COMPACT DISC SERVO POWER DRIVERS TDA1303T Digital Servo Driver (DSD1) VDDD1 VDDD2 EN TC notch filters Optimized low-power, low-voltage IC for 3-beam, 2-stage CD optics Three gain-stabilized class-D amplifiers On-board laser-diode SMPS minimizes power losses during DC-to-DC conversion Continuous gain control compensates for battery voltage fluctuations Battery voltage indication Output resistance <4 Suppression of idle switching SLEDGE DRIVER OSL(pos) FOCUS DRIVER OFO(pos) RADIAL DRIVER ORA(pos) OSL(neg) SL OUTPUT DRIVER CONTROL FO OFO(neg) RA CLK VDDA ADC Vctrl SILO BATTERY VOLTAGE INDICATOR ORA(neg) SIDA SICL TDA1303T enable Vref SWITCHED-MODE POWER CONTROL LASER DRIVER Vol VIs MSC220 The TDA1303T provides three identical output driver functions; the amplifiers receive PDM signals from the servo controller (integrated into the CD7 CD-decoder ICs) and process them for the radial tracking and focus actuators, and the sledge motor. It is suitable for portable applications. VSS1 VSS2 7 QUICK REFERENCE DATA Power supply 1 mA Digital supply current (stabilized) 1 mA Package Datasheet 7-12 5V Analog supply current (stabilized) SO24L (SOT137-1) Handbook IC01 Multimedia PC COMPACT DISC SERVO POWER DRIVERS OQ8844/SZA1010 VDDD VDDR VDDF VDDS Triple digital servo driver (DSD2/DSD3) RAC Three, 1-bit class-D actuator drivers for focus, radial and sledge Separate power supply pins for all drivers Built-in high efficiency digital notch filters Enable input for focus/radial and sledge drivers Differential output for all drivers DIGITAL NOTCH FILTER END STAGE H-BRIDGE RA+ DIGITAL NOTCH FILTER END STAGE H-BRIDGE FO+ DIGITAL NOTCH FILTER END STAGE H-BRIDGE RA+ SZA1010 FOC SLC CLI EN1 EN2 FO+ SL+ SL+ CONTROL MSC299 Integrating class-D power drivers specifically designed for digital servo applications allows these digital servo drivers to deliver much higher efficiency than conventional analog drivers. It also produces very highly integrated ICs, reducing the number of external components required for a complete digital servo loop. The SZA1010 is the successor to the OQ8844, offering additional features such as a radial tri-state selection pin for the radial output drive and the ability to handle clock frequencies up to 10 MHz. VSSD VSSR tristate VSSS/VSSF 7 QUICK REFERENCE DATA OQ8844 SZA1010 Power supply (all driver pins) 5V 5V 4.1 4 Actuator driver (max. bridge resistance) Focus Radial 4.6 4 Sledge 3.1 2 Focus 250 mA 250 mA Radial 250 mA 250 mA Sledge 560 mA 560 mA Input clock frequency (typ.) 4.2336 MHz 10 MHz Package SO20 (SOT163-1) SO20 (SOT163-1) Datasheet (12NC) 9397 750 00471 Contact Philips Supply current (max.) Multimedia PC 7-13 COMPACT DISC SERVO POWER DRIVERS TDA7072A(T)/73A(T) I + i BTL motor drive circuits positive input 1 Single BTL and dual BTL versions BTL configuration allows bi-directional direct currents to be fed to the loads Very high slew rate negative input 1 I - i negative output 1 SHORT - CIRCUIT AND THERMAL PROTECTION TDA7073A TDA7073AT High output current (0.6 A) Suitable for handling PWM signals up to 176 kHz Short circuit and thermal protection, with ESD protection on all pins Single 3 V to 18 V power supply positive output 1 I - i positive input 2 negative output 2 negative input 2 I + i positive output 2 The TDA7072A(T) and TDA7073A(T) ICs are respectively single and dual Bridge-Tied Load (BTL) CD servo power drivers, receiving control signals from the servo controller (integrated into the CD7 CD-decoder ICs) and processing them for the radial tracking and focus actuators, and the sledge and disc drive motors. They have a very low output offset voltage and built-in MCL protection, and are suitable for headphone applications. MSC196 7 QUICK REFERENCE DATA TDA7072A(T) TDA7073A(T) Power supply 5V 5V Total quiescent current 4 mA 8 mA Input bias current 100 nA 100 nA Slew rate 12 12 Cut-off frequency 1.5 MHz 1.5 MHz TDA707xA DIP8 DIP16 TDA707xAT SO8 SO16L Handbook IC01 Handbook IC01 Package Datasheet 7-14 Multimedia PC DIGITAL AUDIO 8 Multimedia PC 8-1 DIGITAL AUDIO CODECs TDA1309H tal up-sample filter, partly IIR and partly FIR, with a virtually linear phase response up to 15 kHz. Low power, low voltage stereo CODEC Low voltage (2.7 V), low power CODEC Bitstream ADC and bitstream/CC DAC Separate power down modes on both ADC and DAC allow power reduction when either section is not in use and the loop through function bypasses the ADC/DAC and filtering for analog recording/playback, further reducing consumption. 16- and 18-bit I2S-bus and LSB fixed formats are supported. Separate power down modes for ADC and DAC Integrated high-pass filter to cancel DC offset (ADC) Analog loop through function QUICK REFERENCE DATA 256 fs system clock frequency for ADC and DAC 192 fs, 256 fs and 384 fs DAC clock frequencies Power supply 3V ADC Analog supply current 8 mA Digital de-emphasis (DAC) Multiple digital I/O formats Digital supply current 0.2 mA Typical THD at 0 dB -85 dB Overload detector enabling automatic recording level adjustment (ADC) DAC requires only one capacitor for analog postfiltering SNR DAC 95 dB Analog supply current 3.5 mA Digital supply current 0.2 mA Typical THD at 0 dB -85 dB SNR 8 99 dB (104 dB with 18-bit input) The TDA1309H combines a bitstream ADC sampling stereo left and right channels simultaneously, with a bitstream/CC DAC to provide a low power, low voltage stereo CODEC for portable digital equipment with recording and playback functions. The ADC uses a serial IIR filter to produce a fairly linear phase response up to 15 kHz. The DAC section includes a digi- Total power dissipation (max.) ADC 72 mW DAC Package 84 mW QFP44 (SOT307-1) Datasheet (12NC) 9397 750 00879 analog input SYSCLK MODE1 TEST1 analog output MODE0 CLKEDOE DE-EMPH TEST0 MODE2 BAIL BAOL VRP DADEM VRN MODE SELECT ADC DACL VOUTL DAC TDA1309H I REF CURRENT DIGITAL INTERFACE DIGITAL FILTER DIGITAL INTERFACE DIGITAL FILTER DAREF Vm I dec Vm ADREF ADC BAIR DAC BAOR VSS-10 OVLOAD ADWS ADENB ADSDA ADBCK ANLPTR ADPON DABCK DAPON DAWS DASDA DACR V OUTR MSB206 - 1 analog output analog input 8-2 Multimedia PC DIGITAL AUDIO CODECs TDA1396 16-bit stereo CODEC with FM synthesis 16-bit Bitstream AD/DA converter Six channel MPC3 compatible digital mixer, with full digital mixing on all audio channels Full duplex operation with different input and output sample rates Six stereo input channels (three analog and three digital) Allows recording and playback mixing to be handled separately Integrated digital FM synthesis emulation and Philips Incredible Sound 3D enhancement Full stereo I/O at sample rates from 3.6 kHz to 55 kHz in infinite steps Built-in interfaces for MIDI MPU-401, joystick, wave table synthesis and OPLx Sample rate conversion on all digital inputs and outputs Preamplifier with AGC for direct microphone input 24 mA ISA-bus drive capability 16-bit ISA address decode Type `F' DMA timing Power management Supports IMA ADPCM, A-Law and -Law compression and decompression microphone I/O PROCESSING FOR ANALOG AND DIGITAL SIGNALS line in CD-ROM TDA1396 6-CHANNEL DIGITAL MIXER D/A OUTPUT CONVERSION 3 ANALOG IN 2 DIGITAL IN 1 DIGITAL OUT DIGITAL IN FM SYNTHESIZER ISA INTERFACE WITH PLUG & PLAY COMPATIBILITY REGISTERS DIGITAL IN DIGITAL OUT 2 INPUT SAMPLE RATE CONVERTERS GAME SOUND BLASTER 16 WINDOWS SOUND SYSTEM ISA 3D ENHANCED SOUND GAME VOLUME MIDI I/O line out VOLUME AND TONE MIDI INTERFACE JOYSTICK AND VOLUME UP/DOWN INTERFACE MICRO CONTROLLER 1 INPUT AND 1 OUTPUT SAMPLE RATE CONVERTER MSC230 As a 16-bit true stereo audio CODEC, the TDA1396 is a highly integrated and cost effective digital audio solution for PC soundcard, notebook and motherboard applications. Using Philips' patented Bitstream technology, it delivers a dynamic range and level of audio performance that enables the recording and playback of high quality stereo music. The TDA1396 is fully compatible with all current PC standards including Soundblaster and Windows (both 3.1x and `95) Sound System. It includes a `Plug and Play' interface supporting up to six logical devices and has a built in game port with quad timer. It also supports host software acoustic echo cancellation. QUICK REFERENCE DATA Power supply Core & analog I/O Supply current 3.3 V 5V 5V 180 mA 10 mA THD + noise (0 dB) -85 dB SNR 90 dBA Package Datasheet (12NC) Multimedia PC 3.3 V TQFP128 (SOT425-1) 9397 750 00894 8-3 8 DIGITAL AUDIO DSPs TDA1548T(Z) IF1 IF2 Single-chip audio processor 8 Incorporates DACs, digital de-emphasis filters, volume and tone control, and a headphone amplifier Accepts up to 20-bit serial input in I2S or LSB-justified format Up to 128 times oversampling Cascaded 4-stage digital filter incorporates 2-stage FIR filter and linear interpolator Noise-shaping filter delivers excellent THD and noise figures Two separate dynamic ranges for the bass boost filter Soft mute No zero crossing distortion Master and slave operation WS BCK MUTE SERIAL DATA INPUT DEEM VOLUME AND SOUND CONTROL VOLUME CONTROL SYSCLK DATA SOFT MUTE CONTROL TIMING AD3S ADVC ADBB CLSEL ADTR SOUND CONTROL 1 FS V DDA FILTER STAGE 1 2 FS MODE0 OP FILTER STAGE 2 MODE1 ADREF 4 FS LINEAR INTERPOLATOR 8 FS 8 x OVERSAMPLING (SAMPLE-AND-HOLD) IOL RCONV1 1 nF GND 8 x OVERSAMPLING (SAMPLE-AND-HOLD) 2nd ORDER NOISE SHAPER 2nd ORDER NOISE SHAPER DATA ENCODER DATA ENCODER 16 (4-bit) CALIBRATED CURRENT SOURCES 16 (4-bit) CALIBRATED CURRENT SOURCES LEFT OUTPUT SWITCHES RIGHT OUTPUT SWITCHES 2.2 k C EXT1 VOL OP1 VDDO V REF IOR R CONV2 1 nF C EXT2 2.2 k VOR OP1 REFERENCE SOURCE 16 (4-bit) CALIBRATED CURRENT SINKS 16 (4-bit) CALIBRATED CURRENT SINKS 1 F OP3 GND TDA1548T GND V COM Designed as a single-chip solution for all sound functions in CD, MD and DCC personal stereo players, the TDA1548T family of Bitstream/CC DACs also provides a complete sound channel processing solution for multimedia PC applications and dual-purpose CD-ROM drives. A selectable flat frequency response allows the headphone outputs to be used as line outputs for driving speakers and its design means no bulky DC blocking capacitors are needed in CD-ROM headphone driver applications. With its low operating voltage and small package, it is particularly suited to portable battery powered equipment, including notebook PCs. MSB470 - 1 QUICK REFERENCE DATA Power supply Supply current SNR Selectable system clock THD + N at 0 dB Digital de-emphasis filter Total power dissipation (max.) Package Datasheet (12NC) 8-4 3V 16 mA 95 dB 64, 256 and 384 fs -85 dB 44.1 kHz 50 mW SSOP28 9397 750 00773 Multimedia PC DIGITAL AUDIO DSPs TDA1388T/M IF1 IF2 DATA Single-chip audio processor WS BCK ACP SERIAL DATA INPUT CHANNEL INTERCHANGE SYSCLK TIMING DSP functions cover independent L & R volume control, bass and treble boost, and de-emphasis I2S and LSB input formats Stereo line out with microprocessor-controlled volume Stereo headphone output with potentiometer volume control High linearity, wide dynamic range and low distortion The single-chip TDA1388 highly-integrated Bitstream/CC filter-DAC offers many sound processing functions, providing a complete sound reproduction solution in CD-ROM applications. It requires no analog postfilter and can be controlled by static pins or by microcontroller interface. SYSSEL APPL2 DE-EMPHASIS VOLUME CONTROL FEATURE CONTROL UNIT BASS BOOST AND TREBLE APPL1 SOFT MUTE FILTER STAGE 1 + 2 APPL0 4fs SAMPLE-AND-HOLD 16 x OVERSAMPLING TDA1388 RCONV1 VDDA 64fs 2nd-ORDER NOISE SHAPER DATA ENCODER DATA ENCODER 16 (4-BIT) CALIBRATED CURRENT SOURCES 16 (4-BIT) CALIBRATED CURRENT SOURCES FILTCL VOL 2nd-ORDER NOISE SHAPER 16 (4-BIT) CALIBRATED CURRENT SINKS FILTCR RCONV2 - RIGHT OUTPUT SWITCHES LEFT OUTPUT SWITCHES + On-chip filtering, DACs, postfiltering and buffering CD-ROM sound path features include separate L & R soft mute, bilingual and monaural modes, channel interchange or combinations - REFERENCE SOURCE VOR + 16 (4-BIT) CALIBRATED CURRENT SINKS Vref + HPINL + REFERENCE SOURCE - - 30 k HPINR 30 k 30 k 30 k MSC210 HPOUTR HPOUTL 8 QUICK REFERENCE DATA Power supply 5V Supply current 22 mA SNR 95 dBA Dynamic range 95 dB THD + N -85 dB line out -65 dB headphone output Total power dissipation Package 110 mW TDA1388T TDA1388TM Datasheet (12NC) Multimedia PC SO28 (SOT136-1) SSOP28 (SOT341-1) 9397 750 00516 8-5 DIGITAL AUDIO DSPs TDA1373 General digital I/O input with DSP (GDIN DSP) QUICK REFERENCE DATA Power supply 5V Total supply current 166 mA Maximum output sample frequency Standard and 4-times over-sampled outputs 8-bit gain/attenuation control THD + N `Psycho-acoustic' noise shaper effectively eliminates quantization noise Audio outputs soft-muted during loop acquisition Total power dissipation (max.) 8 BS CUS 16-bit data USER STATUS EXTRACTION U LD DA MICROCONTROLLER INTERFACE -95 dB QFP64 Datasheet (12NC) CL -113 dB 830 mW Package CEN MU EM 20-bit data 55 kHz XTLI XTLO CLI 9397 750 00927 CL01 CL02 CL03 CL04 X-TAL OSCILLATOR 128fo 256fo 384fo The TDA1373H General Digital Input IC greatly simplifies the interconnection of digital audio systems using different data formats and sample rates. With the variety of professional and consumer data formats in use, the high performance and exceptional level of integrated functionality makes this chip ideal for professional quality sound mixing and recording equipment, universal digital speaker systems, DCC and DAT recorders, digital amplifiers and jitter killers. On-chip Bitstream inputs and filters for use with external Bitstream ADCs/DACs allows the simple building of high performance Bitstream CODECs. Up or down sample rate conversion over a wide range of sample rates with no loss of quality Digital PLL with adaptive bandwidth for effective jitter-free operation Fast and automatic detection and locking to the input sampling rate, with continuous tracking Dedicated sub-code processing for CD ON-chip CS (consumer) and/or UC (professional) demodulation and buffering IEC958 compatible decoder (for recording to CD) with output sample rate tracking the input Converts I2S, Japanese or IEC958 input formats to I2S or Japanese output formats 768fo PV LOCK IEC 958 DECODER SA C DI1D CLOCK SHOP CHANNEL STATUS EXTRACTION WS PO DI1O MM1 GENERAL CONTROL DI1 DI1S DATA SLICER DI2 PHASE DETECTOR LOOP FILTER HOLD FSL VCO MM0 64fo 4x UPSAMPLING FIFO 16 x UPSAMPLING VARIABLE HOLD DO2 DO2D I2 S OUT DO2W DO2C DSO TST1 TST2 RST DNI AIL AIR 32 x DOWNSAMPLING 4x DOWNSAMPLING stereo DO1D 2 I S OUT DO1 DO1W DO1C IN-BAND NOISE SHAPER TDA1373H FO AO DI2 ATTENUATOR BITSTREAM DIGITAL FILTER AOL1 DAC OUTPUT I 2S OUT AOR1 CLD HOLD I 2S IN MSB468 - 1 FOD FOC FOW DI2D DI2W DI2C 8-6 Multimedia PC DIGITAL AUDIO ADCs Philips ADCs for MPC digital audio applications offer: Fully differential ADC using 3rd order Sigma-Delta modulation Single-ended stereo inputs Uncommitted input buffer for filtering and pre-scaling Four stage digital decimation filters Up to 128 times oversampling Switchable high-pass filter to remove DC offsets Sampling rates between 18 and 53 kHz Master or slave operation SAA7360 SAA7366 Anti-aliasing suppression > -93 dB > -60 dB Typical THD + N at 0 dB -90 dB -80 dB 256 fs 11.2896 MHz 12.288 MHz 512 fs Crystal frequency 22.5792 MHz - Dynamic range 93 dB 90 dB In-band ripple < 0.0002 dB Outputs < 0.1 dB 16- or 18-bit I2S Two pseudo I2S 18-bit I2S One pseudo I2S format formats SAA7360 QUICK REFERENCE DATA Power supply Bitstream ADC 5V Analog supply current 39 mA Digital supply current The SAA7360 is a very high performance ADC designed for digital playback systems such as digital amplifiers, CD-recordable and DCC. The decimation filters deliver high anti-aliasing suppression and very low in-band ripple. BAOL BBOL BAIL NINL PINL 410 mW Package QFP44 (SOT205A) Datasheet (12NC) DIOL DCKO XIN 9397 750 00081 XOUT XSYS1 XSYS2 TIMING AND CONTROL SDM V refL 43 mA Total power dissipation FSEL 128f s V refL VDACN WSEL MUX VDACP TSEL VDDAT VSSAT ODF1 TIMING V refL 1st DECIMATION FILTER STAGE 8f s 2nd DECIMATION FILTER STAGE fs HIGHPASS FILTER ODF2 OUTPUT INTERFACE SWSO SCKO V ref V refR SDO SWSI I ref MUX I ref SCKI 128f s BAIR 26 CEN SAA7360 SDM RESET V refR V refR TEST2 MSC217 BAOR Multimedia PC BBOR NINR PINR DSEL DIOR HPEN TEST1 8-7 8 DIGITAL AUDIO ADCs SAA7366 Bitstream ADC Integrated buffers for simple interfacing to analog inputs 4 flexible serial interface modes Overload detection of digital signal -1 dB amplitude Standby mode Based on the SAA7360 and with the basic ADC features, the SAA7366 has been designed for ease of application, minimal board area and low cost. An economy ADC with a digital section that can operate down to 3.4 V, it can be used for the digital acquisition of analog audio signals from CD-recordable drives and is particularly suitable for portable systems such as DCC and DAT players. QUICK REFERENCE DATA Analog supply voltage 5V Digital supply voltage 3.4 to 5.5 V Analog supply current 13 mA Digital supply current 56 mA Total power dissipation 345 mW Standby power consumption 325 W Package SO24L (SOT137A) Datasheet Handbook IC22 8 VREFR operational amplifier 10 k BIR 3 k VDACN I REF 1 pF CKIN DECIMATION FILTER TIMING GENERATOR SIGMADELTA MODULATOR STAGE 2 STAGE 1 COMB 3 HALF-BAND FILTERS FILTER OVLD SAA7366 1 pF BOL 10 k operational amplifier HIGH-PASS FILTER 3 k 10 k REFERENCE VOLTAGE GENERATOR SDO SERIAL OUTPUT INTERFACE operational amplifier SWS SCK VREFL 8-8 STD CLOCK GENERATION AND CONTROL 3 k REFERENCE CURRENT GENERATOR 3 k BIL REFERENCE VOLTAGE GENERATOR SIGMADELTA MODULATOR VDACP TEST1 operational amplifier 10 k BOR TEST2 HPEN SLAVE SFOR MSC206 Multimedia PC DIGITAL AUDIO STEREO FILTER DACs TDA1305T(AT) Bitstream/CC filter DAC ATSB CKSL1,2 Cascaded 4-stage digital filter incorporating 2-stage FIR (Finite Impulse Response) filter, linear interpolation and sample and hold circuit -12 dB fixed attenuation on volume control Soft mute and noise shaping No zero crossing distortion Digital de-emphasis filter for 32, 44.1 and 48 kHz sampling rates I2S or `S' 1fs serial input formats at 16-, 18- or 20-bits 128 times oversampling at 256 x fs; 96 times at 384 x fs The TDA1305T(AT) are BCC (Bitstream/ContinuousCalibration) filter-DACs which use Philips' Bitstream conversion technique for optimum audio performance at low signal levels, and the power-saving CC technique on larger signals. DATA DSMB MUSB CKSL1 BCK L TIMING X OUT CDEC R TEST1 CKSL2 X IN FIR FILTER (TDA1305) IIR FILTER (TDA1306) SERIAL DATA INPUT WS DEEM2 DEEM1 16 f s 6 x OVERSAMPLING (SAMPLE & HOLD) TEST2 L TDA1305T(AT) R 96 f s 2nd - ORDER NOISE SHAPING ENCODING AND OUTPUT SWITCHING FILTER V OL FILTER 16 (4 - BIT) CURRENT SOURCES 16 (4 - BIT) CURRENT SOURCES 16 (4 - BIT) CURRENT SINKS 16 (4 - BIT) CURRENT SINKS V OR Vref REFERENCE SOURCE MSC197 8 QUICK REFERENCE DATA Power supply Supply current Full scale output voltage SNR Typical THD at 0 dB Total power dissipation (typ.) Package Datasheet (12NC) Multimedia PC 3.4 to 5.5 V 42 mA 1.5 V 110 dB -90 dB 210 mW SO28 (SOT136-1) 9397 750 00517 8-9 DIGITAL AUDIO STEREO FILTER DACs TDA1306T/TDA1386T CKSL1 Noise shaping filter DAC DATA WS 8 Cascaded 4-stage digital filter incorporating IIR filter stage -12 dB fixed attenuation on volume control Soft mute and noise shaping Variable volume control via microcontroller interface No zero crossing distortion Digital de-emphasis filter at 44.1 kHz sampling rate I2S or `S' 1fs serial input formats at 16-, 18- or 20-bits 4 times oversampling BCK SERIAL DATA INPUT 4 x f s DIGITAL UP - SAMPLE CKSL2 TIMING TEST1 TEST2 NOISE SHAPER NOISE SHAPER RIGHT OUTPUT SWITCHES RIGHT OUTPUT SWITCHES MODE CONTROL FILTCR APPL APP0 APP1 APP2 APP3 FILTCR RCONV1 RCONV2 3 k VOL SYSCLK FILTER AND FEATURES OP1 3 k CC DIVIDER TDA1306T TDA1386T CC DIVIDER OP1 VOR VREF VSSA REFERENCE SOURCE MSB204 - 2 Selectable system clock 256 fs or 384 fs (TDA1306T only) TDA1305T pin compatible (TDA1306T only) The TDA1306T/86T dual Bitstream/CC-DACs are a low-cost alternative to the TDA1305T. With their up-sampling filter and noise shaping, they require only simple 1st-order analog post-filtering. Two on-board operational amplifiers convert the digitalto-analog current to an output voltage. QUICK REFERENCE DATA TDA1306T TDA1386T Power supply 5V 5V I2C-bus No No Typical THD at 0 dB -70 dB -70 dB Typical SNR 110 dB 108 dB RMS full scale output 1.1 V 1.1 V Package SO24 (SOT137-1) SO24 (SOT137-1) Datasheet Handbook IC22 9397 750 00518 8-10 controlled Multimedia PC DIGITAL AUDIO LOW POWER STEREO DACs TDA1311A(T)/TDA1387T Low power consumption Space saving SO8 package Input format compatible with time multiplexed, two's complement and TTL 18.4 MHz clock frequency Wide operating temperature range (-40 C to +85 C) Wide dynamic range (16-bit resolution) Single supply rail Output current and bias current proportional to supply voltage Fast settling allows 2x , 4x and 8x oversampling (serial input) or double speed operation at 4x oversampling No crossing distortion V OL I/V LEFT INPUT REGISTER RIGHT INPUT REGISTER LEFT OUTPUT REGISTER RIGHT OUTPUT REGISTER LEFT BIT SWITCHES RIGHT BIT SWITCHES I OR 11 - BIT PASSIVE DIVIDER 32 (3 - BIT) CALIBRATED CURRENT SOURCES 32 (3 - BIT) CALIBRATED CURRENT SOURCES 1 CALIBRATED SPARE SOURCE 1 CALIBRATED SPARE SOURCE 11 - BIT PASSIVE DIVIDER REFERENCE SOURCE BCK CONTROL AND TIMING WS DATA TDA1311A(AT) V DD MBA858 - 1 V DD V OL LEFT INPUT REGISTER RIGHT INPUT REGISTER LEFT OUTPUT REGISTER RIGHT OUTPUT REGISTER LEFT BIT SWITCHES RIGHT BIT SWITCHES These DACs use the CC technique, where the largest bitcurrents are repeatedly generated by a single current reference source. This duplication is based upon internal charge storage principle, providing an accuracy insensitive to ageing, temperature matching and process variations. The accuracy of the intrinsic high coarse current combined with a symmetrical offset decoding principle eliminates zero-crossing distortion and ensures high quality reproduction. Together with their low power and small packages, they are ideal for MPC applications, especially portables and notebooks. Versions are available with either current output (TDA1387T) or voltage output (TDA1311A(T)). IDR 11 - BIT PASSIVE DIVIDER 32 (3 - BIT) CALIBRATED CURRENT SOURCES 32 (3 - BIT) CALIBRATED CURRENT SOURCES WS DATA V OR 1 CALIBRATED SPARE SOURCE 1 CALIBRATED SPARE SOURCE 11 - BIT PASSIVE DIVIDER REFERENCE SOURCE BCK OP2 I BR I ref R ref CONTROL AND TIMING TDA1387T V DD MSC188 8 QUICK REFERENCE DATA TDA1311A/AT TDA1387T Power supply 5V 5 V (min. 3 V) Supply current 3.4 mA 5.5 mA Input format `S', up to 4 x fs I2S up to 4 x fs Output 2V 1.0 mA Typical THD + N at 0 dB -68 dB -88 dB Typical SNR 92 dB 98 dB Package V ref OP1 I BL Typical power dissipation V OR I/V I OL @5 V 17 mW 27.5 mW @3 V - 10 mW DIL8 (SOT97DE8) SO8 (SOT96-1) SO8 (SOT96AE3) Datasheet (12NC) Multimedia PC 9397 750 00532 9397 750 00519 8-11 DIGITAL AUDIO AUDIO MPEG DECODERS SAA2500 FAMILY SAA2500 Supports all MPEG-1 layer-I and layer-II audio modes Supports all MPEG-1 bit rates and sample frequencies with fully automatic switching L3 microcontroller interface All features of SAA2500, plus: Decodes error-protection schemes in Digital Audio Broadcast (DAB) and Astra Digital Radio (ADR) broadcasts Burst mode data input Programmable variable bit output precision (16-, 18-, 20- or 22-bit) Integrated audio post processing for control of signal level and inter-channel crosstalk De-multiplexing of ancillary data in input bitstream Sample clock switching and on-chip clock generation Automatic digital de-emphasis of decoded audio signal Error concealment Low power consumption 8 SAA2501 The SAA2500 family was developed for a range of broadcast digital audio applications including digital radio. All three chips have the same base features as the SAA2500 and can operate in master and slave modes. The SAA2501 has additional error handling for DAB and ADR applications; the SAA2502 is a second generation, high feature general purpose MPEG-2 decoder supporting both layer-I and layer-II of the MPEG-1 standard as well as meeting all requirements for a stereo MPEG-2 decoder. Fully compatible with Eureka-147 specifications Demultiplexing of Program Associated Data (PAD) in the input data stream SAA2502 All features of SAA2500, plus: MPEG-2 compatible stereo output Supports low sample frequencies (16, 22.05 and 24 kHz) with CRC correction of scale factors Handles byte- and non-byte-aligned input data IEC958 digital output Programmable automatic internal dynamic range compression algorithm Output formats include I2S, SPDIF and 256 (or more) oversampled analog stereo PC MCLKIN MCLKOUT X22OUT X22IN L3MODE DIVIDER REF-CLK PHASE COMPARATOR CLOCK GENERATOR DECODING CONTROL L3/I 2C CLOCK L3DATA/I2 CDATA FSCLKIN FSCLKOUT URDA/STOP CDSCL/CDMCL CDSEF/CDMEF analog right DEQUANTIZATION CDS/CDM DAC analog left I/P PROCESSOR SD SYNTHESIS CDSWA/CDMWS SPDIF ENCODER CDSSY SAA2502H TC1 TC0 TD1 TD0 TCK TMS TRST WS SCK SPDIF RESET QUICK REFERENCE DATA SAA2500 SAA2501 Power supply 5V 5V 5V I2S interface Yes Yes Yes I2C-bus controlled No No Yes Package QFP44 (SOT307-2) QFP44 QFP44 Datasheet Handbook IC01 9397 746 40011 Contact Philips 8-12 MSB515 SAA2502 Multimedia PC DIGITAL AUDIO Philips extensive range of audio devices also includes general audio processing ICs such as faders, graphic equalizers, amplifiers etc. A few examples are included here; for details on the full range, please refer to the data handbooks IC01 (`Semiconductors OTHER AUDIO ICs for radio and audio systems'). Information on audio ICs for specific application areas can be found in the appropriate Designer's guide (refer to Appendix 1 for a list of these guides). TDA1517P stand-by switch 100 F Stereo radio power amplifier Fixed 20 dB closed loop voltage gain and high output power Stereo channel balance within 1 dB Mute/standby switch Good ripple rejection input reference voltage VP 100 nF 2200 F internal 1/2 V P TDA1517 220 nF 60 k 60 k input 1 220 nF input 2 MSB261 - 1 1000 F No switch ON/OFF clicks Built-in protection against load dump, AC/DC short circuit to ground or supply, reverse polarity, adverse temperature conditions, ESD and SOAR 1000 F This stereo, single-ended audio amplifier delivers 2 x 6 W per channel for driving passive speakers. The mute/standby switch requires a very low current to switch between the two conditions and uses less than 100 A when in standby. 8 QUICK REFERENCE DATA Power supply 14.4 V Typical supply current 40 mA Power output Supply voltage ripple rejection Channel separation (min.) Multimedia PC 2x6W 48 mA 40 dB Package SIL9 (SOT110B) Datasheet Handbook IC01 8-13 DIGITAL AUDIO OTHER AUDIO ICs TEA6320/1/2/3 Sound processors Source selector for four stereo and one mono input Interface to an equalizer and noise reduction circuits Control of bass and treble, volume level, balance and fader Fast mute switching at zero signal crossing via IC pin or I2C bus 106 dB volume control range; maximum gain 20 dB Wide dynamic range with low noise and distortion Line out to drive active speakers QUICK REFERENCE DATA (TEA6320(T)) Power supply 8.5 V Typical supply current 26 mA I2C-bus interface Yes SNR 105 dB THD 8 This family of sound processors and audio control circuits provide digital control via the I2C bus of various sound parameters. The source selector selects input from the OM560x radio module, line in and CD-ROM audio input. The hardware mute function is particularly useful for applications using R(B)DS as the zero crossing mute avoids modulation plops during changing presets and/or sources (i.e. traffic announcement during cassette playback). It also includes a loudness characteristic automatically controlled with the volume (and the TDA6322T/23T also include loudness control with the bass and treble). All functions can be fully I2C-bus controlled. 0.1% Ripple rejection 76 dB Channel separation 96 dB (80 dB for TDA6322/23) Package TDA6320 SDIL32 TDA6320T SO32 Datasheet (12NC) TEA6320 9397 750 00533 TEA6321 9397 750 00534 TEA6322 9397 750 00535 TEA6323 9397 750 00536 left output front rear SOURCE SELECTOR audio left BASS LEFT TEA6320T VOLUME 1 LOUDNESS + / - 15 dB TREBLE LEFT + / - 12 dB MUTE & ZERO CROSS DETECTOR VOLUME 2, LEFT BASS FADER + G = 0...+55 dB G = 20...-31 dB audio right POWER SUPPLY VOLUME 2, RIGHT BASS FADER I 2 C-BUS BASS RIGHT TREBLE RIGHT MGA526 SDA SCL front rear right output 8-14 Multimedia PC DIGITAL AUDIO OTHER AUDIO ICs TEA6360 5-band graphic equalizer Fully I2C-bus controlled monolithic integrated 5-band stereo equalizer circuit Five filters for each channel Centre frequency, bandwidth and maximum boost/cut defined by external components Variable, quasi-constant or constant Q-factor selectable via I2C software Defeat mode for linear frequency response and optimum noise performance All stages DC coupled Two different programmable module addresses QUICK REFERENCE DATA I2C-bus The TEA6360 5-band stereo graphic equalizer is an controlled tone processor for applications such as radios, TVs and music centres with Dolby noise reduction. It also offers the possibility of sound control as well as equalization of sound pressure behaviour for different rooms or loudspeakers. It has 5 stereo pairs of constant bandwidth boost/cut bandpass filters, each centred on a different frequency. The control range (12 dB for example) of each stereo pair is divided into five steps (2.4 dB in this case) with one extra step for the linear position. Overall DC gain is 0 dB, so offset voltages are not amplified. Power supply 8.5 V Typical supply current 24.5 mA Frequency range 0 to 20 kHz SNR 98 dB THD (max.) 1.0% Typical crosstalk attenuation 75 dB Ripple rejection 70 dB Package TEA6360 DIL32SHR (SOT232) TEA6360T SO32 (SOT287) Datasheet Handbook IC01 output right MAD input right 2.95 kHz input left 12 kHz 790 Hz 205 Hz 59 Hz TEA6360 I 2 C-BUS CONTROL MSC218 SDA Multimedia PC SCL output left 8-15 8 DIGITAL AUDIO OTHER AUDIO ICs TDA1308T VSS VDD Class AB stereo headphone driver INA Large output voltage swing No switch ON/OFF clicks INA INB Excellent power supply ripple rejection Short circuit resistance Low power consumption OUTA INB OUTB TDA1308T MSB207 The TDA1308T is a high performance integrated class AB headphone driver providing a high SNR and slew rate, combined with low distortion. Its low power consumption and small size make it ideal for MPC audio applications. 8 QUICK REFERENCE DATA Power supply Single 5 V (3 to 7 V) Dual 2.5 V ( 1.5 to 3.5 V) Supply current 3 mA SNR 110 dB Typical THD + N at 0 dB -70 dB Power supply ripple rejection Channel separation 70 dB Maximum output power Package 60 mW Single Dual Datasheet 8-16 90 dB DIP8 (SOT97-1) SO8 (SOT96-1) Handbook IC01 Multimedia PC CAMERA & MISCELLANEOUS ICs 9 Multimedia PC 9-1 CAMERA AND MISCELLANEOUS ICs A/D INTERFACES TDA8706A VCLPR VCLPB VCLPG CLK 6-bit ADC with multiplexer and clamp D5 CLAMP CLP 6-bit resolution 5.8 effective bits at 4.43 MHz input D4 D3 RED 6-BIT ADC MULTIPLEXER Maximum conversion frequency 40 MHz Binary tri-state CMOS outputs D2 digital voltage outputs GREEN D1 BLUE CMOS OUTPUTS CMOS-compatible digital inputs R, G and B clamps on code 0 D0 TDA8706A VDDA Luminance and colour difference clamps Internal reference voltage REGULATOR MSC211 SR SG SB VRB select inputs The TDA8706A is a 6-bit ADC with three analog multiplexed inputs. An analog clamp on code 0 is provided for RGB processing and the clamping level can also be adjusted externally up to code 20. It can also be used as a single 6-bit ADC. 9 QUICK REFERENCE DATA Power supply 7 mA Digital supply current 5 mA Integral non-linearity 0.25 LSB Differential non-linearity 0.20 LSB Total power dissipation @ 3 V Package Datasheet (12NC) 9-2 2.7 to 5 V Analog supply current 36 mW SSOP24 (SOT340-1) 9397 750 00991 Multimedia PC CAMERA AND MISCELLANEOUS ICs A/D INTERFACES TDA8766 voltage reference CE 10-bit high speed 3 V ADC Sampling rate up to 20 MHz with 10-bit resolution DC sampling allowed High SNR over a large analog input frequency range (9.3 effective bits at 1.0 MHz full scale input at 20 MHz) In-range tri-state CMOS output analog input HIGH - SPEED 10 - BIT A/D CONVERTER LATCHES TTL OUTPUT STAGES output reference TDA8766 CLK CLOCK DRIVER OVERFLOW/ UNDERFLOW LATCH D9 - D0 (tristate) CMOS OUTPUT STAGE overflow/ underflow MGC785 CMOS/TTL-compatible inputs and outputs Power saving standby mode External voltage reference regulator Low analog input capacitance and no buffer amplifier required No sample and hold circuit required A high speed 3V ADC, the high resolution TDA8766 is ideal for professional video and more general applications. A standby mode allows the reduction of the devices power consumption down to 4 mA. 9 QUICK REFERENCE DATA Power supply 3.3 V Analog supply current 9 mA Digital supply current Integral non-linearity Differential non-linearity SNR 0.9 LSB 60 dB Typ. THD at 0 dB -63 dB Total power dissipation (typ.) 66 mW Package Datasheet (12NC) Multimedia PC 8 mA 2 LSB LQFP32 (SOT401-1) 9397 750 00746 9-3 CAMERA AND MISCELLANEOUS ICs A/D INTERFACES TDA8767 CLK TC OE D11 12-bit high speed ADC MSB CLOCK DRIVER D10 TDA8767 D9 Vref 12-bit resolution with sampling rates up to 30 MHz Guaranteed for no missing codes Binary or two's-complement CMOS outputs All digital inputs and outputs are CMOS compatible In-range CMOS output D8 D7 AMP D6 CMOS OUTPUTS D5 data outputs D4 VI ANALOG-TO-DIGITAL CONVERTER VI LATCHES D3 D2 sampleand-hold D1 D0 SH LSB VCCO 3 V to 5 V CMOS-compatible digital outputs Differential clock input IN-RANGE LATCH CMOS OUTPUT IR MSC195 Differential or single analog input No external sample and hold circuit or buffer amplifier required The TDA8767 is a bipolar 12-bit high speed ADC for imaging and a wide range of other applications. A sine wave clock input signal is allowed and it has an external amplitude range control. Three versions are available with different maximum clock frequencies (10, 20 and 30 MHz). 9 QUICK REFERENCE DATA Power supply 40 mA Digital supply current 22 mA Integral non-linearity 3 LSB Differential non-linearity 0.75 LSB Total power dissipation 335 mW Package Datasheet (12NC) 9-4 5V Analog supply current QFP44 (SOT307-2) 9397 750 00889 Multimedia PC CAMERA AND MISCELLANEOUS ICs A/D INTERFACES TDA8786(A) IN2 IN1 CDSP2 CDSP1 TRACKAND-HOLD TRACKAND-HOLD TRACKAND-HOLD TRACKAND-HOLD CLPCDS CLK OE 10-bit A/D interface for camera CCDs TRACKAND-HOLD Minimum 18 MHz sampling frequency AGC gain from 3.5 dB to 33.5 dB in 0.1 dB steps Soft clipper for white compression (starting from 40% of input signal) Fully programmable via 3-wire serial interface Low power consumption of typically 400 mW, with standby-modes available on individual blocks +6 dB fixed gain analog output for analog iris control 8-bit DAC; 10-bit DAC for analog settings TTL compatible inputs; TTL and CMOS compatible outputs Small LQFP48 package CLOCK GENERATOR D9 D8 CLAMP D7 CLAMP TDA8786 TDA8786A D6 +6 dB AMPOUT D5 PBK OUTPUTS BUFFER 10-BIT ADC SOFT CLIPPER AGCOUT D4 AGC CLPOPB D3 OPTICAL BLACK CLAMP PBIN PREBLANKING 9-BIT DAC D2 VCCA1 4-BIT DAC D1 PBOUT ADCIN D0 10-BIT DAC CLPADC 8-BIT DAC REGULATOR CLAMP OFDOUT SERIAL INTERFACE MSC213 DACOUT Vref The TDA8786 is a 10-bit A/D converter and interface for CCD digital video cameras. A highly-integrated IC, it includes CDS, AGC, soft-clipper, preblanking and a reference regulator onchip. The `A' version has the control pulse active LOW. Digital outputs operate from 2.5 V to 5 V. VRB VRT DEC2 STDBY SEN SDATA DEC1 SCLK 9 QUICK REFERENCE DATA Power supply Analog supply current Digital supply current 15 mA Integral non-linearity 2 LSB Differential non-linearity CDS output amplifier gain AGC dynamic range Total power dissipation Package Datasheet (12NC) Multimedia PC 5V 67 mA 0.9 LSB 6 dB 30 dB 400 mW LQFP48 (SOT313-2) 9397 750 00846 9-5 CAMERA AND MISCELLANEOUS ICs A/D INTERFACES TDA8790 CLK 1 8-bit 40 Msps 2.7 to 5.5 V universal ADC CLOCK DRIVER SLEEP TDA8790 V RT 8-bit resolution with sampling rate up to 40 MHz Operates between 2.7 V and 5.5 V DC sampling allowed CMOS/TTL-compatible digital inputs and outputs D7 D6 RLAD analog voltage input VI ANALOG -TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS D4 D3 V RM External voltage reference regulator data outputs D2 D1 D0 Low power dissipation and sleep mode High SNR (7.3 effective bits at 4.43 MHz full scale input) Low analog input capacitance and no buffer amplifier required No external sample-and-hold circuit needed MSB D5 VRB LSB VDDO MSC156 The TDA8790 is a low-power, low-cost universal CMOS ADC for video and general purpose applications which includes a sleep mode to reduces device power consumption when inactive down to 4 mW. 9 QUICK REFERENCE DATA Power supply 3.3 V Analog supply current 4 mA Digital supply current Integral non-linearity Differential non-linearity SNR 0.5 LSB 47 dB Typ. THD at 0 dB -50 dB Total power dissipation 30 mW Package Datasheet (12NC) 9-6 5 mA 0.75 LSB SSOP20 (SOT266-1) 9397 750 00677 Multimedia PC CAMERA AND MISCELLANEOUS ICs CAMERA DSP SAA8110 Camera DSP The SAA8110 is a high precision DSP for video camera applications including desktop video (video conferencing, video capture), observation and videophone. It supports several types of CCD including PAL, NTSC and CIF (progressive and interlaced). On-board RGB processing functions include a colourspace conversion matrix to YUV, black offset, knee and gamma; Y processing includes contour processing and noise reduction; and UV processing include white clip, false colour correction and noise reduction. It also includes an SMPS pulse generator and control DAC. Mosaic CCD to Y/C encoder 9- or 10-bit input (10-bit internal processing) Horizontal resolution of up to 800 pixels/line White balance control Black offset pre-processing (including optical black offset control) RGB separation RGB and YUV signal processing functions CIF, DTV2 and D1 digital output formats On-board PAL/NTSC encoder and 9-bit DACs for analog output Measurement engine prepared for auto-exposure, auto-focus and auto-white balance features VH reference and window timing I2C or SNERT serial interface Mode control including power management QUICK REFERENCE DATA Power supply 3 V or 5 V Analog supply current 50 mA Digital supply current 100 mA Typical power dissipation 900 mW @ 5 V/14.3 MHz Package LQFP80 (SOT315) I2C-bus controlled Yes Datasheet Contact Philips 9 8 SAA8110 Y-PROCESSING 10 CCD_IN OFFSET PREPROCESSING RGB SEPARATION RGB PROCESSING 3 2 RGB TO YUV 3 UV-PROCESSING CLK1 MEASUREMENT ENGINE CLK2 DIGITAL OUTPUT FORMATTER 8 ANALOG OUTPUT PREPROCESSING (INCL. PAL/NTSC ENCODER) V-DACS. 2 Y(UV) UV VS, HREF FIOUT LCC CREF (PXQ) VDAC_OUT VDAC_REF XOSC_IN XOSC_OUT PMC 3 T(0,1, 2) TEST CONTROL ADDITIONAL FUNCTIONS (e.g. SMPS PULSE GENERATOR, CONTROL DACs) 2 CDAC_OUT CDAC_REF Multimedia PC VH-REFERENCE WINDOW TIMING AND CONTROL SERIAL INTERFACE 3 SMP P(1, 0) STROBE SCLK SDATA SIS MSC316 VD HD FI AO/SN_RES SDA SCL/SN_DA A1/SN_DA 9-7 CAMERA AND MISCELLANEOUS ICs MISCELLANEOUS ICs UAA3201T UHF/VHF remote control receiver Oscillator with external SAW resonator Wide frequency range and high sensitivity Low power consumption Superheterodyne architecture IF filter bandwidth determined by application Low cost solution The UAA3201T is a fully integrated single-chip receiver, primarily intended for use in VHF and UHF remote control systems employing direct AM Return-to-Zero (RZ) Amplitude Shift Keying (ASK) modulation. It can be used for RF remote control applications such as keyless entry and wireless mouse. The RF signal is fed directly into the mixer stage, where it is reduced to a nominal 500 kHz IF signal by the SAWRcontrolled oscillator. The IF signal is then amplified and passed through a 5th order elliptical low-pass filter. Filter output is demodulated by a limiting amplifier that rectifies the incoming IF signal and after further filtering, the output signal is limited by a comparator. QUICK REFERENCE DATA Power supply 3.5 V to 6 V Supply current 3.4 mA Sensitivity -105 dBm Receiver turn-on time 10 ms 1600 (50 load) Typical loaded Q (SAWR) 9 Package SO16 (SOT109-1) Datasheet (12NC) FA VEM MXIN LIN VCC LFB 9397 750 00136 CPC data output CPO LIMITER BUFFER COMPARATOR MIXER IF AMP BUFFER VCC Vref MON 9-8 MOP BAND GAP REFERENCE UAA3201T OSCILLATOR SAWR CPB CPA MSC199 Multimedia PC BUS ICs 10 Multimedia PC 10-1 BUS ICs UNIVERSAL SERIAL BUS ICs PDIUSBP11 OE# SPEED VMO VPO USB transceiver D- D+ RCV Complies with Universal Serial Bus Specification v1.0 Fully compatible with the VHDL `Serial Interface Engine' Digital inputs and outputs to transmit and receive USB data Supports high (12 Mbits/s) and low (1.5 Mbits/s) speed data transmission Samples available in SSOP and TSSOP packages VP VM MSC235 The PDIUSBP11 is a single-chip generic USB transceiver, designed to work with the Serial Interface Engine and application interface in a USB peripheral or hub design. It allows either 3.3 V or 5 V programmable and standard logic devices to interface with the Physical layer of the USB, so is well suited for USB peripherals using ASIC or programmable logic. The gated inputs are decoded by the host, which also drives the outputs from the serial interface engine. Applications include keyboards, mice, monitors (control and hub), digital speakers, joysticks and telecommunications. 10 QUICK REFERENCE DATA Power supply Supply current 3.3 V (5 V tolerant) High speed 10 mA Low speed 2 mA Quiescent supply current Supply current in Suspend (max.) Total power dissipation Package Datasheet 10-2 330 A 65 A t.b.f. SO14 (SOT108-1) Contact Philips Multimedia PC BUS ICs UNIVERSAL SERIAL BUS ICs PDIUSBH11 UPSTREAM PORT USB stand-alone hub Complies with Universal Serial Bus Specification v1.0 Four downstream ports with per packet connectivity; one upstream port Hub plus embedded function with two endpoints Integrated memory for hub and function PHILIPS SIE HUB CONTROLLER FIFO HUB REPEATER DOWNSTREAM PORT2 DOWNSTREAM PORT3 DOWNSTREAM PORT4 EMBEDDED PORT (I2C) DOWNSTREAM PORT5 MSC246 Generates and checks CRC values Asynchronous transmit/receive FIFOs Versatile I2C-bus host and function interface Automatic USB protocol handling Full USB power management support including suspend and wake-up modes QUICK REFERENCE DATA Power supply Philips' USB stand-alone hub with embedded function provides USB functionality and USB expandability to a PC peripheral. The modular approach used to implement a hub and embedded function allows the device to be used with either a dedicated low cost microcontroller or an existing controller with a modified version of the software. Control of the PDIUSBH11 is via a serial I2C-bus slave interface, which also allows initialization, configuration and USB data retrieval or set-up. Supply current Quiescent supply current Supply current in suspend (max.) DC input voltage (max.) Total power dissipation (max.) Package Datasheet 3.3 V t.b.f. 330 A 65 A 5.5 V t.b.f. SDIP32 Contact Philips 10 Other USB ICs In addition to these devices, Philips has other ICs with USB functionality in development. These include the P83C190 monitor microcontroller which includes a USB bus interface and hub and the UDA1321T audio DAC, a CMOS bitstream DAC for USB compliant devices. Multimedia PC 10-3 BUS ICs IEEE 1394-1995 ICs PDI1394L11 1394 AV link layer controller AVCLK CYCLOUT AVDATA[7:0] CYCLIN AVFSYNCOUT IEEE 1394-1995 compliant link layer controller Embedded audio/video layer interface A/V layer interface compatible with various MPEG-2 and DVC codecs Application data packetization complies with proposed IEC 1883 specification 80C51 or MC68xx compatible byte-wide host interface 3.3 V supply with all inputs 5 V tolerant The PDI1394L11 is Philips' Audio/Video link layer controller for the high speed IEEE-1394 Serial Bus, designed to pack and unpack real-time application data packets for transmission using isochronous data transfers. A microcontroller interface allows for internal register configuration as well as performing asynchronous data transfers. AVFSYNCIN AVSYNC AVVALID AV LAYER TRANSMITTER AND RECEIVER 5kB BUFFER MEMORY (ISOC & ASYNC PACKETS) CTL0 CTL1 LREQ AVERR1 ISO_N AVERR0 SCLK AVENDPCK PDI1394L11 HIF A[8:0] HIF D[7:0] HIF WR_N HIF RD_N 8-BIT HOST INTERFACE ASYNCH TRANSMITTER AND RECEIVER HIF CS_N CONTROL AND STATUS REGISTERS RESET_N HIF INT_N MSC243 QUICK REFERENCE DATA Power supply Supply current Clock The link layer provides an interface between the physical layer, the host controller and connected devices. (Note: IEC 1883 is a Specification of Digital Interface for Consumer Electronic Audio/Video Equipment.) D[0:7] LINK CORE Total power dissipation (max.) Package Datasheet 3.3 V t.b.f. 49.978 MHz t.b.f. QFP80 (SOT318-C5) Contact Philips PDI1394P11 1394 AV physical layer controller 10 IEEE 1394-1995 compliant physical layer controller Data transfers at up to 200 Mbits/s Industry standard Link/Physical interface (connects to any link controller) 3 ports 3.3 V supply The PDI1394P11 is an Audio/Video physical layer controller for the IEEE-1394 Serial Bus. It is in development, with availability scheduled for available first quarter 1997. 10-4 Multimedia PC REFERENCE/ EVALUATION BOARDS AND SOFTWARE 11 Multimedia PC 11-1 REFERENCE/EVALUATION BOARDS & SOFTWARE As well as individual ICs, Philips provides a number of evaluation and demonstration boards, complete with software, developed in Philips Semiconductors - Systems Laboratories (PS-SLs). These boards are invaluable tools which allow customers to assess an IC's functionality and performance, and provide a reference for real-world designs. Philips also still supports a number of boards for older ICs and has a number of new boards in development. Boards are supported by two general software tools, the Desktop Video Debugger and Universal Register Toolset and most have their own dedicated software modules. There are also extensive application notes, user manuals, and hardware and software descriptions. DEMOBOARDS TYPE NUMBER Digital video decoder module DECMOD01 This page Digital video encoder module ENCMOD02 This page SAA7183 demoboard DTV7183 Page 11-3 SAA7146 demoboard DPC7146 Page 11-4 SAA7140 demoboard DPC7140 Page 11-8 MPEG-1 video playback evaluation kit DPC7131 Page 11-9 SAA7167 demoboard DPC7167 Page 11-10 Digital video decoder/encoder module system To simplify the task of demonstrating and evaluating Philips' extensive range of digital video encoder and decoder ICs, as well as significantly reduce the costs involved, Philips Semiconductors has developed a modular system which can be configured for a number of devices and packages, removing the need for individual PCBs. This modular concept, which evolved from the DTV7183 demoboard (described on next page), was designed to allow simple, cost-effective assessment of different video decoders and encoders, regardless of the package footprint. Encoder and decoder modules can be connected together directly, to test basic encoding/decoding quality and functionality. They can also be operated stand-alone, or as front- or back-ends for customized applications and other Philips demoboards. 11 DECODER/ENCODER MODULES Digital video decoder module The digital decoder module accepts SAA7110(A) and SAA7111(A) decoders (see pages 4-3, 4) in either PLCC68 or LQFP64 packages. Input to the board is through two RCA jacks for CVBS signals or a DIN connector for S-Video. Digital output is fed to the YUV feature connector and resistors can be used to suppress any high frequency ringing due to long wires. The resistor/capacitor set-up has to be altered only for the low voltage (3.3 V) SAA7111A decoder. A third order crystal is used for the SAA7110(A) and SAA7111. 11-2 MORE INFORMATION Digital video encoder module The encoder module accepts PLCC84, QFP80 and LQFP64 packages, allowing for insertion of the SAA7182/83, SAA7182A/ 83A or SAA7124/25 encoders (see page 4-12). A 26-pin YUVfeature connector is used for the digital input, which can be in CCIR-656 (D1) or 16-bit YUV (for the SAA7182(A)/ 83(A)) formats. DAC output is passed through analog post-filters to the connectors. Filters are assigned to the connectors depending on signal type and the DAC signals are routed via jumpers, to adapt to the different output modes of the SAA7124/25. Jumpers also allow the module to be configured for the OSD signals and RGB inputs of the SAA7182A/83A family, and for switching between the S-Video and RGB modes of the SAA7124/25. Boards are available individually, each with its own software which interfaces with the I2C-bus via a printer port adapter. Documentation includes a manual explaining the overall concept and individual user manuals. Microcontroller module Each of the modules has a socket for an I2C-bus EEPROM, used for storing initialization data and for a future microcontroller module. Although developed initially as an aid to evaluating and demonstrating ICs in applications where there is no processing power (e.g. set-top box applications), the microcontroller module will provide additional flexibility in testing in PC applications. Multimedia PC REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS DTV7183 SAA7183 demoboard This basic board is used by customers to evaluate two crucial functions in the field of desktop video - encoding and decoding - and it can be used either as a stand-alone board, or as an extension for other demoboards. The board accepts an analog input video signal, digitizes and decodes it into YUV data and then passes it via the digital YUV bus to the encoder, where the signal is reconstructed and converted back to an analog output video signal. For evaluation, the customer can plug in either the SAA7110(A) or SAA7111(A) ICs (see pages 4-3 and 4-4), which offer complete multistandard one-chip decoding. Both have on-chip A/D conversion, filtering, clock generation and decoding of CVBS and S-Video signals, for PAL and NTSC standards (and SECAM if the appropriate derivative is chosen). The SAA7110 is a square-pixel decoder; the SAA7111 is CCIR-601 compliant. analog inputs (CVBS, S-video) YUV FEATURE CONNECTOR DIGITAL COLOR DECODER digital YUV bus SAA7110 SAA7111 MICROCONTROLLER DTV7183 DIGITAL COLOR ENCODER SAA7185 SAA7187 SAA7188A DIGITAL COLOR ENCODER SAA7182 SAA7183 analog outputs (CVBS, S-video) analog outputs (CVBS, S-video, RGB) DEMOBOARD MSB912 There are two sockets for Philips' encoder IC family (see Video encoders section, pages 4-14 to 4-17). If the SAA7110(A) decoder is used, then normally its square pixel equivalent encoder is inserted, the SAA7187; if decoding is handled by the SAA7111(A), then any of Philips' CCIR-601-compliant ICs (SAA7182(A)/83(A), SAA7184/85B or SAA7185/88A) can be used. They output CVBS, and/or S-Video and RGB, depending on the encoder chosen. The board also includes a YUV feature connector. There is also space for an optional microcontroller, which allows direct I2C-bus control of the encoders and decoders. It provides eight different I2C-bus set-ups and requires no knowledge of I2C-bus programming or control registers, for simple demonstration. If the microcontroller option is not used, a separate I2C-bus control program is used to drive the DTV7183 board, requiring an I2C-bus cable connection. A number of operation modes are possible. First, direct decoderto-encoder for basic decoding/encoding evaluation. YUV-toencoder mode allows digital YUV data to be fed directly onto the bus for encoding, by-passing the decoders. The board can also be set up in Encoder Master mode and a Pattern Generator mode is available when the board is operating stand-alone, to demonstrate the high quality of the reconstructed video output signal. Real-Time Control This board also shows very clearly the advantages of a unique Philips' development, RTC (Real-Time Control). This process synchronizes encoding and decoding by locking the encoding process to the decoding. This provides accurate and stable colour rendition at the encoder end, even when the signal is non-standard or subject to adverse affects such as noise; it also provides solid decoding of NTSC signals. 11 Multimedia PC 11-3 REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS DPC7146 SAA7146 demoboard The DPC7146 is a 4-layer PCB, including several Philips audio and video processing ICs, with a number of interfaces and connectors. Its primary chip is the SAA7146 which, with its wide range of interfaces, allows the board to be used as a base for developing a number of applications, such as video-conferencing, as well as AC-3 playback and MPEG-2 codecs. It also features the SAA7111A video decoder, TDA1309T audio codec, PCF8598E EEPROM, and the SAA7185B video encoder and TDA1308 headphone driver for video and audio output. Philips is committed to three communications standards: IEEE 1394-1995 for external multimedia peripherals; the PCI bus as the backbone in the PC; and the USB for general PC and low data rate peripherals. In general, it is expected that all peripherals will in the future be connected via one of these buses. This board lies at the core of Philips PCI multimedia strategy and is a complete silicon and software demonstration environment. For multimedia over PCI, at the heart of Philips' solution is the SAA7146 Multimedia PCI and Bridge Scaler IC. It has many on-board interfaces, supporting video and audio inputs/outputs via the PCI interface, and has a high performance scaler core similar to that in the SAA7140. Hardware The central element of the board is the SAA7146. It is controlled via the PCI bus and data on the board can be uploaded from the EEPROM, as required in the PCI specification. It has two D1 video ports, giving it the capability for simultaneous capture and playback of video. The TSL audio I/O engines can be arbitrarily mapped onto five Serial Data (SD) lines and five Word Select (WS) lines. The DEBI port can be configured for either a 16-bit ISA bus format or Motorola-style bus, where the data bandwidth is about double that of the standard PC ISA bus. Additional functionality is provided through GPIO (General Purpose I/O) and multi-master I2C bus interfaces. As PCI bus master, it can send data from local video and audio sources and the general data interface to its main memory, or it can request data from memory. Data streams are handled locally by powerful control engines which operate autonomously, offloading the data control workload from the CPU and enabling real-time control. Two Register Programming Sequencer (RPS) engines, in combination the Local Event Management, can control almost all data streams independently of the CPU. Two Time Slot List (TSL) engines provide enhanced audio features. AUDIO uP e.g. PENTIUM VIDEO proc. -bus SAA7146 uP DEVICES L2 I2C DEVICES 11 CONTROL + BRIDGE MEM D PCI-bus ISA-bus PCI to SCSI HD ISA MOUSE KEYBOARD PCI to SCSI VGA to SCSI HD MEM MSC236 Philips multimedia - PCI architecture 11-4 Multimedia PC REFERENCE/EVALUATION BOARDS & SOFTWARE audio R/L TDA1309 AUDIO audio R/L D1B AUDIO PROCESSING D1B_SY CVBS Y chroma I2C bus DEMOBOARDS S1 D1D S2 D1D_SY Y chroma VIDEO ENCODER S4 S5 D1A INSERT# SAA7111A VIDEO DECODER SAA7184 D1A_SY PCI-BRIDGE SAA7146 D1A S3 D1A_SY S6 ALE XAD(0 to 15) VMI L HA(0 to 3) CONNECTOR XAD(0 to 7) ISA(0 to 4) GPIO(0 to3) AUDIO XAD(8 to 16) VMI D1C D1C_SY X MSC303 PCI-bus Other major functional blocks are: * Video front-end: this consists of the SAA7111A multistandard video decoder (see page 4-4), I2C bus interface, and CVBS and S-Video connectors. Alternatively, the SAA7111 or SAA7110 may be used (see pages 4-3 and 4-4). This block provides colour decoded video streams from a CVBS or S-Video source to one of the two video inputs to the SAA7146 in 16-bit 4:2:2 format. Control of the decoder is via the I2C interface and the standard set-up uses the PCI Bridge as the I2C-bus master. Video data can be fed directly to the SAA7146 and in addition to the video signals, the S-Video connector features I2C bus connectivity. An external tuner module could be added to the front-end. * Video back-end: video playback uses the SAA7185B decoder (see page 4-16) and a standard application uses Direct Mode (DM), where video data are fed directly to the encoder. For additional functionality, the SAA7146 supports line and field memory access via VMI connectors, using additional Line Memory Mode or Field Memory Mode modules. Encoded video signals are available as CVBS or S-Video signals. * Audio codec: the TDA1309T Bitstream audio codec (see page 8-2) provides independent analog audio I/O to the board. Stereo signal capture is handled through the earphone connector, using the ADC in the TDA1309T, with the sample rate controlled using the appropriate clock signal. Audio out- Multimedia PC put uses the DAC in the TDA1309T, after which the signal is amplified using the TDA1308 headphone amplifier (see page 8-16) and then passed to the earphone connector. Additional connectors allow for the connection of Philips audio evaluation boards using, for example, the TDA1548 audio processor (see page 8-4). The audio clock is generated by an independent crystal. * DEBI port: this behaves effectively as a high-speed ISA bus interface and can be used to connect an ISA-based MPEG decoder or, in principle, any other ISA device. It can also operate as an interface to a Motorola-style bus. When combined with the Local Event Management and the RPS functionality, this makes the board very flexible. * VMI connectors: these connectors allow additional boards to be connected and provide access to most video, audio and DEBI data signals. * Power supply: the power supply for the board is split into two different sections. The 12 V supply of the PCI edge connector is used to generate the decoupled 5 V supply for the video decoder, encoder and analog audio supply. The PCI edge connector 5 V supply is used as a general 5 V supply and for the 3.3 V supply of the SAA7146. This splitting decouples all sections from the main DC supply and supports local decoupling of functional blocks, resulting in very low noise content in the video signals. 11-5 11 REFERENCE/EVALUATION BOARDS & SOFTWARE Software Developed to assist customers' software application and driver development and reduce time-to-market, the software kit provides developers with a high level interface via a Hardware Application Layer (HAL), consisting of two DLLs (for the SAA7146 and the decoder). Virtual device drivers (VxD) are included along with a debug utility, as well as a register editor and universal I2C transceiver (described under `General Software' at the end of this section). The kit also has demonstration drivers for audio and video capture, closed captioning, and a sample application with source code. All HAL drivers can be accessed directly, so PCI bus handling and other functions can be performed through the Application Layer. The software capture drivers are designed for Microsoft's Video for Windows architecture, and are modular and expandable. The 16-bit version will be available in Q3/96 for Windows '95 and Windows 3.x, while the full 32-bit version for Windows '95 and Windows NT will be available by the end of 1996. * Dynamic class library: contains all of the classes required to control the DPC7146 demoboard covering video, audio, closed captioning/teletext, I/O, memory and utilities. * DMSD46.DLL: this DLL provides a generic class that abstracts the specific details of Philips' decoders used with the DEMOBOARDS SAA7146, including controls for the SAA7111 and SAA7110. It allows the user to query and modify the input format, video format standard and colour settings used by the decoder. * DENC46.DLL: this DLL provides a generic class that abstracts the specific details of Philips' encoders used with the SAA7146, including controls for the SAA7185B and SAA7184 (with Macrovision option). It allows the user to query and modify the output format, video format standard and colour settings used by the encoder. * Virtual device driver: the SAA714x VxD performs kernel level operations and is responsible for providing services to the DLLs, including allocating physically contiguous, locked memory and providing an interface to Microsoftis Virtual Memory Manager (VMM) and other virtual drivers for the DLLs. The VxD operates in protected mode. * Video capture device driver: this device driver provides lowlevel video capture services for Windows multimedia applications. Featuring real-time video capture, video preview (displayed by host) and video overlay (video data directly bus mastered over the PCI bus to the VGA frame buffer), it provides an interface for the user to select the image size and capture format. Utilizing PCI configuration information, and DCI for Windows 3.1 or Direct Draw for Windows '95, this VIDEO / AUDIO CAPTURE APPLICATION (VfW) AVI CAPTURE (AVICAP.DLL) ,,,,,,, ,,,,,, ,,,,,,, ,,,,,, ,,,,,,, ,,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,,,, ,,, ,, ,, ,,,,,,, ,,,,,,,,, MICROSOFT VIDEO (MSVIDEO.DLL) SAA7146 SAMPLE APPLICATION (SMPL46.EXE) VIDEO CAPTURE DRIVER (VCAP46.DLL) application interface 11 DMSD46 (DLL) SAA7146 DYNAMIC CLASS LIBRARY (SAA7146.DLL) DENC46 (DLL) VxD hardware interface PCI-bus MSC237 SAA7146 APPLICATION BOARD OEM appl. Philips Semiconductors Microsoft 11-6 Multimedia PC REFERENCE/EVALUATION BOARDS & SOFTWARE driver can determine information about the VGA board, frame buffer, video format and occluded video regions. Any number of occlusions are possible; the driver ensures continuous video updates of non-occluded regions and commands the SAA7146 not to write occluded pixels to the frame buffer in the overlay mode. The clip mask is implemented using a pixel map, which provides the flexibility to determine the shape, position and number of occluded regions. * Audio capture device driver: this driver supports a configurable capture buffer size and is capable of capturing 16-bit stereo audio in an AVI file. * Debug utility: with its simple graphical user interface, it allows the user to identify quickly all PCI devices in the system, view the configuration information, view and edit PCI memory registers, select and execute macros, and access other devices connected to the PCI bridge via DEBI and I2C interfaces. Sample application A C++ for Windows based sample application is provided which exploits the "function of inheritance", in that the functionality of a process can be passed on to a child process. This allows a DEMOBOARDS customer to adapt the supplied sample very easily to a specific application - code can be simply modified at high level (the sample APIs) and functionality will be retained. This allows very easy product differentiation and quick times-to-market, the two most critical factors for success. The application demonstrates windowed display of live video from a PC-top video camera or broadcast, which is freely scaled as the size of the window is changed by the user. It demonstrates video overlay using a clip mask, capture and storage of a video image to system memory, and closed captioning processing. A feature is in development which will display odd fields in real time, with simultaneous capture of even fields, as required in some video conference applications. The RPS feature allows loading of different set-ups. This could be used, for example, to alter the scaling factor after an event such as a V-sync or H-sync signal, enabling the display of video at two different locations simultaneously or the creation of special effects. There is also a VBI mode for Intercast systems and an audio capture and playback mode. 11 Multimedia PC 11-7 REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS DPC7140 SAA7140 demoboard The DPC7140 demoboard features Philips' High Performance Scaler IC, the SAA7140 (see page 4-11) and has two main application areas. The first is for Multimedia PCs, where the video display output is merged with the graphics display at the computer monitor using the SAA7167 Mix-DAC (see page 4-29), to provide video in a window. The second uses a digital video encoder for digital television applications. The board also can be used to evaluate the very high quality of the High Performance Scaler core. It allows a direct contrast between simple scaling by pixel and line dropping, used by the SAA7195A (see page 4-31), which can produce artefacts, and the high performance scaling of the SAA7140, which produces high quality scaled images even down to icon size. Hardware The DPC7140 demoboard is a 16-bit ISA-bus based PC add-in card. An SAA7111 or SAA7110A (see pages 4-4 and 4-3) digital multistandard video decoder is used as the video front-end. This converts analog video input from the CVBS or S-Video connectors to a digital signal and delivers the control signal and the line-locked clock. The SAA7140 then up- or down-scales the video images before passing them to the SAA7195A, which performs scan rate conversion from TV to graphics display. Output is either a merged video and RGB signal using the SAA7167 Mix-DAC, or a reconstructed video signal from the SAA7183 encoder (see page 4-14), depending on the application. As well as the video input connectors, there is an I2C-bus interface and a YUV expansion connector which allows access to the digital YUV data bus. There is also a control connector for the OSD function of the SAA7183 and a video output connection, as well as analog RGB VGA input and output connections. Software The software is a demonstration application covering input source selection, video attribute control and colour keying functions, as well as the scaling and zooming functions, and it includes all low level drivers. It operates under Windows 3.1 (or higher) and provides a number of simple dialogue boxes for editing video parameters, described as follows: * Configuration: used to set the I/O address of the DPC7140 board * Video overlay: places the video in a window and stretches it to fit, unless altered under the Video Location control. * Video source: for selecting the video input connector and video source, which sets the PLL lock-time for the decoder. The HPS expansion port is used with applications which feed direct video streams to the device, such as MPEG ICs. * Video attributes: for control of input video BCS and luminance. * Video location: used for manual selection of the size of the video within a window and setting scale and zoom factors independently, for both the horizontal and vertical axes. * Miscellaneous: for adjusting display offset (which allows for timing differences depending on the VGA card), scaling via the SAA7140 or SAA7195A, freezing/unfreezing the video, horizontal mirror and selecting the format for the video memory. key control RGB input MIX-DAC 11 CVBS S-video VIDEO FRONT-END SAA7110 or SAA7111 EXPANSION CONNECTOR VGA FEATURE CONNECTOR HIGH PERF. SCALER SAA7140A AND OPT. LINE-MEMORY VIDEO MEMORY CONTROLLER SAA7167 RGB output VRAM BANK SAA7195A CVBS S-video EURO-DENC DPC7140 HIGH PERFORMANCE SCALER BOARD PC ISA bus interface SAA7182/ SAA7183 RGB output MSB909 11-8 Multimedia PC REFERENCE/EVALUATION BOARDS & SOFTWARE EVALUATION KIT DPC7131 MPEG-1 video playback evaluation kit This board is an MPEG-1 technology demonstrator using the SAA7131A FMPEG-1 decoder (not commercially available). It particular, it shows its capability for synchronous processing of audio and video data streams in a number of application modes. In general, all of these application modes support slow motion, scan, still picture operation and frame grabbing for further processing. The SAA7131A reads MPEG-1 data from hard disk or CDROM through its ISA-bus interface. After decompression, the signal is passed to the SAA7182/83 encoder (see page 4-14), outputting CVBS, S-video or RGB for display on a TV or PC monitor. Audio data is handled through the TDA1305 dual audio DAC (see page 8-9) and the TDA1308 stereo headphone driver (see page 8-16). Decompressed data can also be written back onto the ISA bus for further processing or hard disk storage. For maximum flexibility, this board includes a digital multistandard decoder, either the SAA7110A or the SAA7111 (see pages 4-3 and 4-4), the SAA7195A Video Memory Controller (see page 4-31) with VRAM, and the SAA7167 Mix-DAC (see page 4-29). The decoder digitizes and decodes multistandard CVBS or S-Video signals from broadcast sources, cameras or VCRs. Signal filtering, formatting, scaling and video buffering functions are handled by the SAA7195A, which also provides an interface to the PC bus. Finally, the SAA7167 Mix-DAC takes digital video data, converts it into the analog domain and merges it with analog RGB signals from the VGA feature connector, for display of video signals in a window. Several video modes can then be demonstrated (in all cases audio is output through the TDA1305 and TDA1308): * MPEG direct TV output mode. MPEG data from the ISAbus is decoded in the SAA7131A; video is displayed directly on a TV through the SAA7182/83 encoders. * Expansion connector mode. This is essentially the same, but uses the expansion connector to take MPEG-decoded data off the board for further processing on another board - scaling, using Philips SAA7140 high performance scaler, for example - or to a PCI bridge scaler (SAA7146). * Cost-effective VGA slave mode MPEG overlay. MPEG data from the ISA-bus is decoded in the SAA7131A; video is sent through the SAA7167 where it is converted to analog RGB and overlaid with the system VGA data as master, and displayed on the PC monitor. * Normal MPEG overlay mode. In this advanced video playback mode, decompressed video data is fed through the SAA7195A, which provides more flexibility for up and downscaling and positioning the window on the PC monitor. * Genlocked mode. This capability is suitable for simultaneous handling of video sources. The SAA7131A decodes the MPEG data as described, while the SAA7110A/SAA7111 decodes an input video signal. The SAA7110A/SAA7111 is the master and displays a full screen picture, overlaid with the MPEG video (or you can toggle between full screen live video and MPEG video). * Genlocked MPEG/TV overlay mode. A high-end solution for simultaneous handling of MPEG data and video. Similar to the above example, it also uses the odd/even frame storage capability of the SAA7195A so that a live video signal and the MPEG video can both be displayed together in a window on the PC. This evaluation kit includes the board, driver software for Windows MCI and DOS OMI along with debugging and demonstration software with a sample Video-CD. For completeness, it also has full hardware and software documentation, ORCAD, layout, Gerber and Aperture files, and a device list and even a VGA feature connector and RGB cables. MPEG DEMOBOARD EXPANSION CONNECTOR CVBS S-video VIDEO FRONT-END SAA7110 or SAA7111 DRAM VGA FEATURE CONNECTOR VIDEO MEMORY CONTROLLER DPC7131 11 key control RGB input VRAM BANK MIX-DAC MUX SAA7167 RGB output SAA7195A PC ISA bus interface CVBS S-video EURO-DENC FMPEG audio SAA7131 DAC audio SAA7182/ SAA7183 RGB output PC ISA bus interface MSB910 Multimedia PC 11-9 REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS DPC7167 SAA7167 Demoboard This ISA-bus based PC add-on card provides a platform for developing applications which capture live video for playback at a later time. Although the board is primarily intended as a base for an image capture, storage and graphics overlay board, audio ICs can easily be integrated for real world multimedia applications. can be saved for future playback, compression or editing. Various software compression routines are provided. The driver has components for device set-up, system configuration and debugging. There is also extensive user control of video parameters such as video format; image format, size, overlay and display characteristics such as BCS; video source and so on. Video images can be played back using either the Media Player or through the VidEdit tool. The DPC7167 front-end has an SAA7110 or SAA7111 (see page 4-2) digital multistandard decoder which digitizes and decodes CVBS and S-Video signals. It also includes an SAA7195A Video Memory Controller (see page 4-31) and 4 Mbit of VRAM, providing image storage, video buffering and simple scaling functions. An ISA-bus interface and a feature connector allow analog RGB signals to be fed through to the SAA7167 Mix-DAC (see page 4-14), for mixing of processed image data with separate analog RGB signals, for example for video overlay in a window. Evaluation board A suite of video capture software is provided, developed with the Video for Windows 1.1 Software Development Kit. This includes a video capture (VidCap) driver which allows the user to freeze and capture single and multiple frames. It also allows capture of live video streams and generation of AVI files, which An evaluation board for the SAA7112 (see page 4-2) is in development. The SAA7112 is a single-chip decoder/scaler offering essentially the combined functionality of the SAA7111A and SAA7140 with an image port for direct interfacing to VGA controllers. This functionality is described in a combined Application Note AN96053. SAA7112 I2C 2M-BIT VRAM CVBS 11 SAA7110 SAA7195A MUX SAA7167 2M-BIT VRAM ISA INTERFACE FEATURE CONNECTOR analog RGB MSC238 ISA-bus 11-10 GRAPHIC SUBSYSTEM Multimedia PC REFERENCE/EVALUATION BOARDS & SOFTWARE GENERAL SOFTWARE DESKTOP VIDEO DEBUGGER KIT UNIVERSAL REGISTER TOOLSET This software is designed to accompany all DTV demoboards and allows designers to set-up and evaluate individual ICs on a board. It provides an interface to the ICs at register level, allowing the register contents of each IC to be displayed and modified in a separate window. Register settings can be saved and restored from disk. The kit essentially provides standard low-level I2C driver support and as such, can even be used outside the DTV environment. The Universal Register Toolset (URT) was developed to reduce the effort required to create the software needed to support new devices, such as debuggers, sample applications, etc. This cuts the time and cost for generating a working version of a complete new software application and allows quicker and more costeffective updates. The kit consists of a number of tools running on a standard IBM PC under Microsoft Windows (3.1, 3.11 and '95). During installation, the I2C-bus master must be configured, which can either be the SAA7146 PCI bridge and Scaler (see page 4-9, 18), the SAA7195A Video Memory Controller (see page 4-9, 31) or a line printer port adapter, if installed. Board builder This powerful tool allows designers to build their own test boards for testing, verification or evaluation (a board in this case being a group of ICs accessed together in an application). Standard set-up files are provided for all Philips MPC ICs, which load the IC registers with start-up values. Initialization can be manual for each IC, or can be performed automatically for all ICs through the DTV shell, in which case you use the board builder to create a board initialization file. Standard IC set-up files can be used directly for board evaluation or modified as required. They can also be overwritten with user defined files. An example board file is provided with the software, which can be modified to create board files without using the board builder. DTV shell The DTV shell is a type of file manager, providing access to one program (normally a register view) for each IC. It is used to load a board set-up file (created manually or using the board builder), which in fact simply provides links to the executables, making it easier for users to modify them. All executables for a board setup are displayed as icons. Other modules The kit includes a Register View function, which allows viewing and modifying of individual IC registers. If an I2C device has no register view executable, one can be created with the Universal I2C Transceiver. There is also an I2C Status Viewer. Two specific Overlay Windows for the SAA7195A and for the SAA7195A/SAA7140 provide easy access to these device registers - as the window is scaled and re-sized, the registers are updated automatically. A VRAM I/O Access utility enables simple transfer of files to and from VRAM and VLUTs and a Picture Converter tool allows translation of captured images between various video formats. An MCI Media Player is also included which, unlike the standard Windows player, can be used to send individual MCI commands from a command line. Multimedia PC The approach is based on allowing the user to work with logical rather than absolute values and register addresses. The URT allows the application engineer to define details of a chip in a specially-developed language, in a description file. From this, the URT compiler automatically generates a stand-alone Visual BASIC application which allows IC data manipulation at the logical level, allowing programming by simply changing logical register names. Description files can easily be modified. The Toolset provides an interface between PC application software and devices, handling the complex task of converting low level data structures into readable formats. The appearance of the program can be visually modified with the Visual BASIC development system, which requires no knowledge of BASIC itself. The URT also includes a `C' interface which a systems programmer can use in more complex work-benches, to design a software module without knowing all the register mappings and value assignments of the device. Additional modules can be designed as a Visual BASIC add-in (OCX), which can then be incorporated into the automatically generated work-benches. The general approach is valid for all bus systems and specific bus drivers are provided (I2C, PCI, etc.). The URT supports single and multiple device sessions. As a consequence, the hardware developer need not be familiar with a specific Windows-related programming language or the Windows system design when adapting tools for a new or modified IC. Similarly, a programmer creating a new user interface for an existing device will not need to know all the details of the IC at low level - the whole approach is aimed at ensuring simple applicability to new targets for anyone familiar with the target hardware functionality. It is a genuinely universal tool, supporting any device controlled using registers. DEVICE DEFINITION FILE MACRO FILE URT-COMPILER HEADER IDF URD APPLICATION URT.DLL URD BUS DRIVER DEVICE MSC240 11-11 11 REFERENCE/EVALUATION BOARDS & SOFTWARE The URT structure Logical values are used in a hardware specification to describe a device. However, for programming purposes a logical value may cover several physical registers and a register might represent two logical values, depending on the value being read/written. This can lead to software errors which are very difficult to trace. First a Device Definition File is created, describing the device in terms of registers, RAM areas and logical groups. This can be done manually using a text editor or using the provided Device Definition development tool, which includes aids such as syntax highlighting and a menu system to access URT components such as the compiler. From this, the URT compiler creates an Internal Definition File, read by the main URT DLL, which acts as an interface between the application and the driver for the bus in use. The bus driver DLLs can be accessed by the URT DLL and the URD (Universal Register Debugger), and are responsible for transferring read/write commands to the device. APPLICATION ENGINEER END USER URD WORK BENCH GENERAL SOFTWARE The URT DLL also creates `C' header files from the Device Definition Files. These contain definitions of registers and their values, and entry points for the functions offered by the URT DLL, which can be used by `C' applications. Special support such as automatic Form generation is provided for MS Visual BASIC, offering a graphical user interface and a visual representation of some registers and macros, to make prototyping as fast and simple as possible for developers not familiar with more advanced programming. A detailed definition of the low level interface is provided to allow users to add their own low level drivers, written in C++, without having to recompile the DLL. A number of OCX controls will be added for special functions such as a Window Overlay, Frame Grabber, etc. The URT DLL is provided in a 16-bit version for Windows 3.x and 32-bit for Windows '95 and NT. APPLICATION ENGINEER SYSTEM PROGRAMMER APPLICATION ENGINEER OCX DEVICE DEFINITION FILE VISUAL BASIC 11 URT-DLL BUS DRIVER DLLs INTERNAL DEFINITION FILE URT-COMPILER application creation change notification usage application path DEVICES device definition path MSC239 11-12 Multimedia PC MONITORS 12 Multimedia PC 12-1 MONITORS Philips complete solutions Philips has a vast array of specially designed or optimized ICs for monitors, as well as a full range of discrete components. You can source everything you need from Philips to build a monitor, ranging from small, cost-effective PC monitors, through larger and more highly featured displays for more demanding PC applications, up to large workstation or CAD/CAM monitors. Most ICs are I2C-bus controlled, which allows simple control of the whole system, cutting design time and allowing quick automatic factory adjustment of many functions. Only a very brief summary of the main ICs and discrete semiconductors for core monitor functions are given here. For a more detailed review, please refer to the quick selection guide `Semiconductors for Monitors' (12NC 9397 750 01004); full details are in the separate `Monitors Designer's guide', which is in preparation. Philips Semiconductors devices for other functions in a monitor, such as audio for multimedia monitors, are covered both in this guide and in other Designer's guides (see Appendix 1 on Documentation); Philips can also provide other devices for a complete solution, such as power supply controllers; and other monitor components such as the picture tube, deflection units, line transformers and so on are all available from Philips Components. VIDEO PRE-AMP RGB VIDEO OUTPUT AMPLIFIERS brightness uniformity I2C-bus VECTOR PROCESSOR factory test & calibration H/V sync OSD DDC control MICROCONTROLLER EEPROM 12 int USB bus MULTIPLE DACs dynamic convergence VERTICAL DEFLECTION H/V eht HORIZONTAL DEFLECTION DEFLECTION PROCESSOR control USB HUB LCD DISPLAY POWER SUPPLY MSC219 Typical high-end monitor configuration with vector processing option for dynamic convergence 12-2 Multimedia PC MONITORS Deflection controllers Philips has a large range of sync processors, with a wide range of functionalities and integration levels, reflecting the evolution of market technology and suitable for many types of monitor. The products are grouped into families for 14", 15" and 17" models. Currently, Philips highly integrated TDA4855/58 autosync devices represent the state-of-the-art. The next generation TDA4853/54 devices are already in design: they are based around a complete I2C-bus control concept which addresses the merging PC/TV market and also include features such as Moire cancellation and extensive integrated geometry control functions. The TDA4855/54 include dynamic focus capability on chip, while the TDA4858/53 are intended for markets segments which do not require dynamic focus. Together with the TDA488X video controller family and TDA486X booster family, they form a complete and powerful solution for PC monitors. SYNC PROCESSORS TDA4855 TDA4858 TDA4854 TDA4853 Max. hor. frequency (kHz) (autosync) 30 to 100 30 to 100 15 to 130 15 to 130 Vert. freq. range (Hz) (autosync) 40 to 110 40 to 110 40 to 160 40 to 160 VGA mode yes no no no E-W parabola generator yes yes yes yes TV/VCR mode no no yes yes Geometry controls external external on-chip on-chip I2C Adjustments DC DC I2C Supply voltage (V) 9.2 to 16 9.2 to 16 9.2 to 16 9.2 to 16 Package SDIP32 SDIP32 SDIP32 SDIP32 Vertical boosters Video controller As for the deflection controllers, Philips vertical booster product family is divided into a low cost range, suitable for the highly competitive market for monitors up to 15"; and a range for high performance monitors of 17" and above. Two broad design types are available: standard half-bridge circuits and highly innovative full bridge solutions. The full bridge, a design unique to Philips, has a very high level of integration, although it is does have a higher power dissipation. The vertical boosters are DCcoupled to the deflection controller, eliminating the need for bulky blocking capacitors and keeping the circuit free from bounce during mode changes. Philips has an excellent product offer for the low-end market segment, with its TDA4882/84, 85 MHz ICs. These have a higher integration level than most competitive products and also include greyscale tracking, which ensures colour remains constant as the user adjusts brightness and contrast. The new TDA4885 has a range of innovative features such as gain modulation, which delivers a uniform brightness across the entire screen, compensating for light fall-off from the centre to the edges of picture tubes (which is highly disturbing to viewers). It is fully I2C bus controlled, which reduces the number of wires between the main board and video board, making designs more tolerant of EMI disturbances. VIDEO PRE-AMPLIFIERS TDA4882 TDA4884 TDA4885 Bandwidth (MHz) 85 85 150 (note 3) Number of channels 3 3 3 Gain, brightness and contrast control DC (note 1) DC (note 2) I2C Gain modulation no no yes Greyscale tracking yes yes yes Output stage can drive discretes can drive discretes universal Supply voltage (V) 8 8 8 Package DIL20 DIL20 SDIP32 12 Notes 1 Brightness control on-chip, two gain controls 2 Brightness control via grid 1, three gain controls 3 Pixel rate Multimedia PC 12-3 MONITORS Vector processor Memories, OSD and LCD display drivers Philips has in test a vector processor offering a range of functions including a correction waveform generator specifically for colour monitors. It has two correction channels with current outputs and the waveform generator tracks with picture width and height, and is independent of scan frequency. It offers 3 x 3 point alignment with one channel and, by adding both channels, quasi 5 x 5 point alignment. Waveform alignment can be I2C-bus controlled. As part of its complete monitors solution, Philips has an OSD circuit which can display 128 characters (from ROM) in a 12 x 16 matrix, offering a variety of colour background modes. LCD display drivers include segment and dot-matrix types. Segment drivers can drive 24 to 96 or 40 to 160 segments; matrix drivers offer either 18 x 16 or 32 x 60 dots (rows x columns). Non-volatile memories run from 128 x 8-bit serial access, up to 2048 x 8. Multiple DACs Discrete semiconductors Philips multiple DACs are a simple and cost-effective single-chip solution for various monitor applications, for example for RGB gain and cut-off or for a range of geometry parameters. Of course discrete semiconductors play a major role in monitor design and function and Philips is one of the world's major discrete semiconductor manufacturers. MULTIPLE DACS TDA8444 TDA8447 Number of DACs 8 8 Resolution (bits) 6 8 Output voltage range (V) 0.1 to VP - 0.5 0.4 to VP - 0.8 I2C-bus yes yes Supply voltage (V) 10.8 to 13.2 4.5 to 8.8 Package DIP16, SO16L, SO20 DIP16 Microcontrollers Philips offers more 80C51 derivative microcontrollers than any other supplier and this includes an exceptionally broad offer of microcontrollers dedicated to monitor applications. For deflection, rectification and EHT generation, Philips has extensive ranges of fast soft recovery controlled avalanche rectifiers, ultra fast low-loss controlled avalanche rectifiers, high voltage soft recovery rectifiers and damper diodes, all available in a number of voltage, current and power specification combinations. Similarly, Philips has power transistors for horizontal deflection output stages, ranging from devices for 14" SVGA 38 kHz monitors, up to 17", 64 kHz and 82 kHz monitors. Other discrete semiconductors for monitors include video output amplifier transistors and modules, transistors for the modules' input buffer stages and PowerMOSFETs for Scorrection capacitor/mode switching. Versions are available with 4 K ROM, up to devices offering a maximum of 64 K Flash EPROM, while RAM options extend from 128 K up to 512 K. Devices are available with a range of analog PWM outputs, on-board ADCs and full-duplex UARTs, and some versions have up to 48 I/O lines. All have at least two timer/counters and a watchdog timer that enables fail-safe recovery. More advanced controllers also include on-board DACs and a number of dedicated functions such as composite sync separation, auto-sync detection and DDC1/DDC2 support. The very latest also includes a USB-bus interface and HUB. For details of the HUB, refer to Bus ICs in Section 10. 12 12-4 Multimedia PC TRIMEDIA 13 Multimedia PC 13-1 TRIMEDIA PROGRAMMABLE MULTIMEDIA PROCESSORS In the multimedia market, some trends are clearly definable. Individual media functions are evolving in graphics, audio, video and communications and as they develop, they are being combined to create true multimedia applications - ones which are highly realistic and truly interactive. This demands an integrated approach with high performance, concurrent processing of multiple data types and while programmable DSPs can provide the power, they have been complex to program, using assembly language. By combining cost-effective advanced microprocessor technology, easy programmability and comprehensive software tools, Philips TriMedia family of programmable multimedia processors provides the answer. ROBUST SOFTWARE ENVIRONMENT PROGRAMMABLE DSP: high performance, VLIW architecture multifunctional hardware compiler & tools RTOS integrated multimedia functions multimedia applications libraries MSC193 TRIMEDIA SOLUTION combines DSP performance with CPU software video At the core of the TriMedia chip is a DSP/CPU, which integrates the power of a DSP with a high performance VLIW architecture, with robust, CPU style development environment. It is fully programmable in high-level C and C++ languages on UNIX and PC platforms and by allowing the developer to work in a familiar language, product development, testing, fine-tuning and optimization of software libraries becomes quick and efficient. Graphics Audio Video 2D mono still 3D VR stereo Indeo Communications wavetable MPEG-1 LAN WAN waveguide MPEG-2 wireless macrotrend: combination of media functions PROGRAMMABLE DSP microtrend: evolution of media functions Entertainment/Education Settop TV Video conferencing audio graphics communications With an instruction set optimized for multimedia operations and its highly parallelized architecture, at 100 MHz TriMedia yields a peak performance of 4 billion operations per second. With this astonishing performance, its ease of programmability and with the advanced algorithms for audio, video, graphics, fax/modem, telephony and video conferencing available, TriMedia reduces time to market for OEMs. Unlike other multimedia processors, the TriMedia TM-1 DSP/CPU offers an open development environment. By not forcing developers into a proprietary architecture and allowing them to work in a familiar, open and easily programmable environment, they can minimize the time-to-market for new, high performance multimedia applications for the PC and consumer markets. Philips fully expects TriMedia to become the industry standard for multimedia applications. MSC244 13 13-2 Multimedia PC TRIMEDIA PARTNERING FOR OPEN MULTIMEDIA DEVELOPMENT As part of its strategy of providing an open platform which will drive the development of new, innovative multimedia applications, the TriMedia Group is developing relationships with a growing list of Independent Software Vendors (ISVs). These partnerships will result in continuous innovation in advanced software libraries to meet evolving needs, driving the multimedia applications market to the next level. The first development partnership is with InVision Interactive, Inc., a leader in digital audio technology. Their software will enable the first processor in the TriMedia family, the TM-1, to deliver virtually all the capabilities of a fully compliant General MIDI synthesizer (see below for a broad look at the TM-1 chip). These new capabilities are in addition to TriMedia's support of Microsoft's DirectX API, including the direct sound interface, enabling TM-1 to play powerful sound effects and 3D positional audio. Thus, TM-1 can transform a desktop computer into a powerful musical instrument without the need for a sound card. These libraries will be available to TriMedia customers, so that they can develop state-of-the-art audio capabilities for their multimedia applications. TM-1: THE FIRST IN A FAMILY The TM-1 family is a complete processing environment for high-performance multimedia applications ranging from lowcost, single-purpose systems such as video phones to re-programmable, multi-purpose plug-in cards for PCs. Controlled by a small real-time OS kernel running on the VLIW core and using a variety of open or proprietary multimedia algorithms, TM-1 easily implements popular multimedia standards such as MPEG-1 and MPEG-2. With its CPU, high-bandwidth internal bus and internal busmastering DMA peripherals, TM-1 is tailored for use in PCbased real-time multimedia applications. It provides the low cost and chip count of a special-purpose, embedded solution, combined with the re-programmability of a general-purpose processor. To give an indication of the power of this technology, using a cycle-accurate simulator to evaluate a mixed multimedia application of decoding MPEG-1 data at 30 fps with superimposed texture mapped 3D graphics, at 100 MHz the TriMedia-1 con- SDRAM video CCIR-601/656 YUV 4:2:2 VIDEO DMA IN VLD COPROCESSOR HIGHWAY serial digital audio ADC AUDIO DMA IN VIDEO DMA OUT DAC AUDIO DMA OUT TIMERS video CCIR-601/656 YUV 4:2:2 synchronous serial i/f for V.34 / ISDN SYNC. SERIAL I/F I$ DSPCPU CORE IMAGE COPROCESSOR SCALING COLOUR CONVERSION D$ JTAG I 2C PCI MASTER / SLAVE BRIDGE MSB932 PCI local bus sumes only 22% of the available processor cycles and 12% of the memory bandwidth. The main functional blocks in TM-1 are the microprocessor core itself, a memory interface for SDRAM (Synchronous DRAM) and peripheral I/O blocks for interfacing with multimedia data streams. All interfaces are glueless and include CCIR-601 compliant Video-in and Video-out units, and Audioin and Audio-out units which require only an ADC and DAC respectively. Both audio and video units are programmable, offering a high degree of user-customization. TriMedia includes a PCI interface for communications with the host PC and a V.34/ISDN interface providing remote communication support or interfacing to a network. It also includes accelerators for video scaling interpolation and variable length decoding for smooth flow of video in an unlimited number of arbitrarily overlapped windows. Other TM-1 derivatives will have varying interface sets targeted at different applications. All TM-1 solutions will be software compatible at C/C++ source-code level, allowing Philips to strike the optimum balance between cost and performance for all the chips in the family. Engineering samples of the TM-1 are currently shipping to Early Access Program (EAP) customers with volume shipments expected by the first quarter of 1997, at a pricing level compatible with consumer electronics applications. 13 Multimedia PC 13-3 TRIMEDIA TYPICAL TM-1 PC APPLICATIONS PC-based MPEG video compression In this case, a camera chip or other source supplying uncompressed 8-bit 4:2:2 YUV video data is connected directly to the TM-1's video-in unit, which samples and demultiplexes the Y, U and V data, storing it in separate SDRAM areas. When a complete video frame has been read it interrupts the TM-1 CPU, which compresses the video data using a powerful set of data-parallel software operations and writes it to another SDRAM area. The compressed video data can now be sent to a host system over the PCI bus, for archival on local mass storage, or it could be transferred by the host over a network such as ISDN. Alternatively, the data could be sent to a remote system using the integrated V.34 interface, creating a video phone or video conferencing system. The TM-1 CPU could also encrypt the compressed data before transmission, for security. SDRAM SAA7111 TM-1 SAA7366T PCI 80 x 86 SCSI CONTR. HDD PCI-bus PCI MSC241 Video decompression in a PC One typical application for TM-1 is in a video-decompression card in a PC. The PC operating system hands the TM-1 card a pointer to compressed video data in the PC's memory. The TM-1 CPU fetches data from the compressed video stream via the PCI bus, decompresses frames from the video stream (possibly aided by the variable-length decoder unit) and places them into local TM-1 SDRAM. When a frame is ready for display, the TM-1 CPU issues a display command to the image coprocessor, which fetches the decompressed frame and transfers it over the PCI bus to the frame buffer, in the PC's video display card (or in system memory if the PC uses a Unified Memory Architecture). video in CVBS SAA7111 VIDEO DECODER + SCALER YUV YUV SAA7185B VIDEO ENCODER TV or VCR microphone SAA7366 PREAMP + AUDIO A/D I2S I 2S TM-1 TRIMEDIA (DE) COMPRESSOR ISDN phone line ISDN RECEIVER TDA1388T AUDIO D/A + AMP ISDN TRANSMITTER speakers ISDN phone line PCI bus monitor Video conferencing TriMedia easily implements a PC-based video conferencing system: with its dedicated communications, image and VLD coprocessing units, the TM-1 further relieves the computer of compression/decompression and communication tasks. GRAPHIC CONTROLLER MSC231 13 13-4 Multimedia PC APPENDICES A Multimedia PC A-1 APPENDICES APPENDIX 1 DOCUMENTATION Separate data sheets OQ8844 OQ8868 SAA2501 SAA7110A SAA7111 SAA7112 SAA7140A/B SAA7167(A) SAA7182/83 SAA7184/85B SAA7187 SAA7188A/85 SAA7360 SAA7385 SAA7388 SAA7390 TDA1300T TDA1305T(AT) TDA1309H TDA1311A(T) TDA1373 TDA1386T TDA1387T TDA1388T(Z) TDA1396 TDA1548T(Z) TDA4665 TDA8706A TDA8707 TDA8708A TDA8708B TDA8709A TDA8712 TDA8758 TDA8766 TDA8767 TDA8771 TDA8772(A)H(3/8) TDA8775G TDA8786(A) TDA8790 TDA9850 TDA9852 TEA5757H/5759H TEA6320 TEA6321 TEA6322 TEA6323 UAA3201T Triple digital servo driver Digital servo controller Audio MPEG-1 decoder for Astra Digital Radio (ADR) One Chip Front-end (OCF) Video Input Processor Decoder with HPS scaler for image port High Performance Scaler (HPS) Mixer and D/A processor EURO-DENC digital video encoder DENC-M6 digital video encoder DENC2 Square pixel digital video encoder DENC-M digital video encoder Bitstream ADC High performance CD-ROM controller Error corrector and host interface High speed CD-recordable block decoder/encoder Photodetector amplifiers and laser supply Bitstream/CC filter DAC Low power, low voltage stereo CODEC Low power stereo DACs General digital I/O input with DSP (GDIO DSP) Noise shaping filter DAC Low power stereo DACs Single-chip audio processor 16-bit stereo CODEC with FM synthesis Single-chip audio processor Baseband delay line Video Enhancement and D/A processor Triple RGB 6-bit ADC interface 6-bit ADC with multiplexer and clamp Video analog input interface Video analog input interface 8-bit video DAC Low power A/D interface 10-bit, high speed 3 V ADC 12-bit high speed ADC Triple 8-bit video DAC Triple 8-bit video DAC Triple 10-bit video DAC 10-bit A/D interface for camera CCDs 8-bit 40 Msps 2.7 - 5.5 V universal ADC I2C-bus controlled BTSC stereo/SAP decoder I2C-bus controlled BTSC stereo/SAP decoder & audio processor Self-tuned radio Sound processor Sound processor Sound processor Sound processor UHF/VHF remote control receiver 9397 750 00471 9397 750 00785 9397 746 40011 9397 750 00368 9397 750 00847 9397 750 00923 9397 750 00984 9397 750 00416 9397 750 00324 9397 750 00928 9397 750 00325 9397 750 00944 9397 750 00081 9397 750 00917 9397 750 00808 9397 750 00942 9397 750 00441 9397 750 00517 9397 750 00879 9397 750 00532 9397 750 00927 9397 750 00518 9397 750 00519 9397 750 00516 9397 750 00894 9397 750 00773 9397 750 00381 9397 750 00991 9397 750 00605 9397 734 20011 9397 734 80011 9397 734 60011 9397 734 70011 9397 750 00606 9397 750 00746 9397 750 00889 9397 750 00591 9397 750 00029 9397 750 01021 9397 750 00846 9397 750 00677 9397 750 00176 9397 750 00706 9397 750 00557 9397 750 00533 9397 750 00534 9397 750 00535 9397 750 00536 9397 750 00136 A A-2 Multimedia PC APPENDICES APPENDIX 1 ICs covered in data handbooks PCF8574A SAA2500 SAA5246A SAA5249 SAA5252 SAA5254 SAA5281 SAA5290 SAA5296 SAA6579 SAA7146 SAA7165 SAA7186 SAA7192A SAA7196 SAA7199B SAA7366 TDA1303T TDA1306T TDA1308T TDA1517P TDA4655 TDA4670 TDA4686(WP) TDA4820T TDA7072A(T) TDA7073A(T) TDA8501 TDA8505 TDA8540(T) TDA8702 TDA9855 TEA5582 TEA6360 Remote 8-bit I/O expander for I2C-bus Audio MPEG-1 decoder Integrated VIP and teletext decoder Integrated VIP and teletext decoder with background memory controller Line 21 decoder Integrated VIP and teletext decoder Integrated VIP and teletext decoder One-page economy teletext/TV microcontroller Single-chip economy 10 page teletext/TV microcontroller R(B)DS demodulator Scaler and PCI bridge (SPCI) IC Video Enhancement and D/A processor Digital video scaler Digital colour space converter (DCSC) Digital video decoder and scaler (DESC-Pro) CCIR and square pixel digital encoder with genlock Bitstream ADC Digital Servo Driver (DSD1) Noise shaping filter DAC Class AB stereo headphone driver Stereo radio power amplifier Generic multistandard analog decoder Picture signal improvement processor Analog video processor Sync. Separator IC for monitors BTL motor drive circuits BTL motor drive circuits PAL/NTSC analog encoder SECAM analog encoder 4 x 4 video switch matrix 8-bit video DAC I2C-bus controlled BTSC stereo/SAP decoder and audio processor PLL BTSC stereo decoder 5-band graphic equalizer Handbook IC22 Handbook IC01 Handbook IC02 Handbook IC02 Handbook IC02 Handbook IC02 Handbook IC02 Handbook IC02 Handbook IC02 Handbook IC01 Handbook IC22 Handbook IC22 Handbook IC22 Handbook IC22 Handbook IC22 Handbook IC22 Handbook IC22 Handbook IC01 Handbook IC22 Handbook IC01 Handbook IC01 Handbook IC02 Handbook IC22 Handbook IC22 Handbook IC22 Handbook IC01 Handbook IC01 Handbook IC02 Handbook IC02 Handbook IC22 Handbook IC22 Handbook IC22 Handbook IC02 Handbook IC01 A Multimedia PC A-3 APPENDICES APPENDIX 1 Other information on ICs There is preliminary technical information available on the following ICs: contact your local Philips sales office for more information or refer to the Philips WWW home page. CCR921 CDU 2600 D65420 E65400 P83C190 PDI1394L11 PDI1394P11 PDIUSBH11 PDIUSBP11 ROA1312/X ROM 65XXX SAA2502 SAA5284 SAA7111A SAA7124/5 SAA7182A/83A SAA7195A SAA7348 SAA7370(B)GP SAA8110 SZA1010 TZA1015 R(B)DS controller CD-Recorder subsystem and CD-R data engine CD-Recordable data engine CD-Recordable subsystem Monitor microcontroller with USB plus hub IEEE P1394 serial bus AV link layer controller IEEE P1394 serial bus AV physical layer controller (in development) USB stand alone hub USB transceiver CD-ROM subsystem and system solution (12x) CD-ROM subsystems and system solutions (6x and 8x) Audio MPEG-1 decoder with MPEG-2 stereo capability Multimedia VBI and FF data acquisition IC Enhanced Video Input Processor ECO-DENC digital video encoder EURO-DENC2 digital video encoder Video and Memory Controller (VMC) ACE (All Compact disc Engine) 10x single-chip digital servo processor and compact disc decoder Camera DSP Triple digital servo driver Data amplifier and laser supply Application notes AN9312 AN95014, AN94036 AN95056 AN96053 AN96054 AN96055 AN96063 TDA1305T SAA2500/1 User's Manual DPC7167 Demo Board High Performance Scaler SAA7140A(/B) SAA7146 Software Development Kit Digital Video Decoder/Encoder Module System DPC7146 Demonstration Board User Manual User manuals UM95009 UM9601 UM9603 UM960XX DTV7183 Demonstration Board V0.3 DPC7140 Demonstration Software DPC7146 Evaluation Board V1.0 DPC7140 Demo Board V0.1 A A-4 Multimedia PC APPENDICES APPENDIX 1 Data handbooks IC01 IC02 IC22 IC12 Semiconductors for radio and audio systems Semiconductors for television and video systems Desktop video I2C peripherals 9398 652 93011 (new) 9398 750 00074 9397 750 00141 9397 750 00306 Linecards Digital video decoders linecard Digital video encoders linecard Video <-> PCI bridges 9397 750 00621 (new) 9397 750 00622 (new) 9397 750 00624 Other relevant designer's guides Audio data converters and miscellaneous digital audio ICs designer's guide Compact Disc designer's guide Digital Media Broadcast designer's guide Multimedia ICs selection guide Portable and home hi-fi/radio designer's guide Terrestrial and satellite TV front-ends designer's guide TV designer's guide 9397 750 00151 9398 750 00952 (new) 9397 750 00727 9397 750 00286 (new) 9397 750 00907 9397 750 00147 9397 750 00148 CD-ROMs Desktop Video 9397 750 00644 A Multimedia PC A-5 APPENDICES APPENDIX 2 GLOSSARY OF ABBREVIATIONS C ACC ACCU ADC ADPCM ADR AGC AM API ASIC ASK ASSS ATAPI AVI BCC BCS BER BIOS BITBLT BRS CAS CAV CC CC CCD CCIR A CD CD-i CDM CD-R CD-R/E CIF CLUT CMOS CODEC CPU CRC CRT CTI CVBS DAB DAC DAT DAVIC DCC DCT DCTI DEBI DENC DIN DLL A-6 Microcontroller Automatic Clamp Control Accumulator Analog-to-Digital Converter Adaptive Differential Pulse Code Modulation Astra Digital Radio Automatic Gain Control Amplitude Modulation Application Program Interface Application Specific Integrated Circuit Amplitude Shift Keying Automatic Sector Size Select AT - Additional Packet Interface Audio-Video Interleave Bitstream/Continuous-Calibration Brightness, Contrast and Saturation Bit Error Ratio Basic Input/Output System BIT-BLock Transfer Binary Ratio Scaler Column Address Select Constant Angular Velocity Continuous-Calibration Closed Caption Charge-Coupled Device Comite Consultatif International des Radiocommunication Compact Disc Compact Disc - Interactive Compact Disc Mechanism Compact Disc Recordable Compact Disc - Recordable/Erasable Common Interchange Format Colour Look-Up Table Complementary Metal Oxide Semiconductor COder-DECoder Central Processing Unit Cyclic Redundancy Check Cathode Ray Tube Colour Transient Improvement Composite Video Baseband Signal Digital Audio Broadcast Digital-to-Analog Converter Digital Audio Tape Digital Audio VIdeo Council Digital Compact Cassette Discrete Cosine Transformation Digital Colour Transient Improvement Dynamic Expansion Bus Interface Digital ENCoder Deutches Institut fur Normung Dynamic Link Library DM DMA DMSD DMX DRAM DSP DTV DVB DVS EAP EBU EDC EEPROM EHT EIAJ EMC EMI EPLD EPROM ESD FCC FF FIC FIFO FIR FM FMM FMV FPGA FTC GUI HAL HPS I2C I2S IDE IEC IEEE IIR ISA ISDN ISO ISV JPEG LCD LED LMM LUT MCI MD MIDI Direct Mode Direct Memory Access Digital Multi-Standard Decoder Digital Music Express Dynamic Random Access Memory Digital Signal Processing DeskTop Video Digital Video Broadcast Digital Video Scaler Early Access Program European Broadcasting Union Electronic Data Check Electrically Erasable Programmable Read Only Memory Extra High Tension Electronic Indentity Association Japan ElectroMagnetic Compatibility ElectroMagnetic Interference Electronically Programmable Logic Device Erasable Programmable Read Only Memory Electro-Static Discharge Federal Communications Commission Full Field Fast Information Channel First In, First Out Finite Impulse Response Frequency Modulation Field Memory Mode Full Motion Video Fast Programmable Logic Array Fast Track Control Graphical User Interface Hardware Application Layer High Performance Scaler Inter-IC Inter-IC Sound Integrated Drive Electronics International Electrotechnical Commission Institute of Electronic and Electrical Engineers Infinite Impulse Response Industrial Standard Architecture Integrated Services Digital Network International Standardization Organization Independent Software Vendor Joint Photography Experts Group Liquid Crystal Display Light Emitting Diode Line Memory Mode Look-Up Table Media Control Interface Music Disc Music Instrument Digital Interface Multimedia PC APPENDICES MPC MPEG MTS MUSICAM MUX NABTS NTSC OCF OCX OMI OSD PAD PAL PCB PCI PCMCIA PDM PES PLL PS-SL PWM QCIF QPSK R(B)DS RAMDAC RAS RCA RDCL RDDA RF RPS RTC RZ SAP SCAM SCSI SDRAM SECAM SIF SMPS SNR SOAR SPDIF SPI SRAM STN STR SVGA Multimedia Personal Computer Motion Picture Expert Group Multichannel Sound Modulation Masking pattern adapted Universal Subband Integrated Coding And Multiplexing Multiplexer North American Broadcasting Teletext Specifications National Television Standards Committee One-Chip Front-end OLE Custom Control Open Messaging Interface On-Screen Display Program Associated Data Phase Alternate Line Printed Circuit Board Peripheral Component Interconnect Personal Computer Memory Card International Association Pulse Density Modulation Packetized Elementary Stream Phase-Locked Loop Philips Semiconductors - Systems Laboratory Pulse Width Modulation Quarter Common Interchange Format Quadrature Phase Shift Keying Radio (Broadcast) Data Signals Ramdom Access Memory Digital-to-Analog Converter Row Address Select Radio Corporation of America R(B)DS CLock R(B)DS DAta Radio Frequency Register Programming Sequencer Real-Time Control Return-to-Zero Second Audio Program SCSI Configuration AutoMatically Small Computer Systems Interface Synchronous DRAM SEquential Colour And Memory Source Input Format Switched Mode Power Supply Signal-to-Noise Ratio Safe Operating Arena Sony-Philips Digital Interface Arena Serial Peripheral Interface Static Random Access Memory Super Twisted Nematic Sychronous Transmitter/Receiver Super Video Graphics Array Multimedia PC APPENDIX 2 TFT THD TOP TTL UHF URD URT USB USWST VBI VBR VCO VGA VHDL VHSIC VHF VLD VLIW VLUT VMC VMM VoD VPS VPU VRAM WSS WST Thin Film Transistor Total Harmonic Distortion Technical/Office Protocol Transistor Transistor Logic Ultra High Frequency Universal Register Debugger Universal Register Toolset Universal Serial Bus United States World Service Teletext Vertical Blanking Interval Variable Bit Rate Voltage Controlled Oscillator Video Graphics Array VHSIC Hardware Description Language Very high speed IC Very High Frequency Variable Length Decoder Very Long Instruction Word Video Look-Up Table Video and Memory Controller Virtual Memory Manager Video on Demand Video Programming Selection Video Processing Unit Video Random Access Memory Wide Screen Signalling World System Teletext A A-7 APPENDICES APPENDIX 3 INDEX OF TYPE NUMBERS A TYPE NUMBER DESCRIPTION PAGE CCR921 R(B)DS controller 6-5 CDU 2600 CD-Recordable subsystem and CD-R data engine 7-3 DMB chipset Range of ICs from Philips Digital Media Broadcast chipset 5-11 D65420 CD-Recordable data engine 7-3 E65400 CD-Recordable subsystem 7-3 OQ8844 Triple digital servo driver 7-13 OQ8868 Digital servo controller 7-11 PC Text Software for a range of Teletext decoder ICs 5-6 PCF8574A Remote 8-bit I/O expander for I2C-bus 6-4 PDI1394L11 IEEE P1394 serial bus AV link layer controller 10-4 PDI1394P11 IEEE P1394 serial bus AV physical layer controller 10-4 PDIUSBP11 USB transceiver 10-2 PDIUSBH11 USB stand alone hub 10-3 P83C190 Monitor microcontroller with USB plus hub 10-3 ROA 1312 CD-ROM subsystem and system solutions (12x) 7-3 ROM 65XXX CD-ROM subsystem and system solutions (6x and 8x) 7-2 SAA2500 Audio MPEG-1 decoder 8-12 SAA2501 Audio MPEG-1 decoder for Astra Digital Radio (ADR) 8-12 SAA2502 Audio MPEG-1 decoder with MPEG-2 stereo capability 8-12 SAA5246A Integrated VIP and teletext decoder 5-6 SAA5249 Integrated VIP and teletext decoder with background memory controller 5-6 SAA5252 Line 21 decoder 5-8 SAA5254 Integrated VIP and teletext decoder 5-6, 7 SAA5281 Integrated VIP and teletext decoder 5-6 SAA5284 Multimedia VBI and FF data acquisition IC 5-6, 7 SAA5290 One-page economy teletext/TV microcontroller 5-9 SAA5296 Single-chip economy 10 page teletext/TV microcontroller 5-10 SAA6579 R(B)DS demodulator 6-6 SAA7110A One Chip Front-end (OCF) 4-2, 3 SAA7111(A) Video Input Processor 4-2, 4 SAA7112 Decoder with HPS scaler for image port 4-2, 5, 9 SAA7124/5 DENC-N digital video encoder 4-12, 15 SAA7140A/B High Performance Scaler (HPS) 4-9, 11 SAA7146 Scaler and PCI bridge (SPCI) IC 4-9, 18 SAA7165 Video Enhancement and D/A processor 4-28 SAA7167(A) Mixer and D/A processor 4-29 SAA7182/83 EURO-DENC digital video encoder 4-12,14 SAA7182A/83A EURO-DENC2 digital video encoder 4-12, 13 SAA7184/85B DENC-M6 digital video encoder 4-12, 16 SAA7186 Digital video scaler 4-9, 10 SAA7187 DENC2 Square pixel digital video encoder 4-12, 16 SAA7188A/85 DENC-M digital video encoder 4-12, 16 SAA7192A Digital colour space converter (DCSC) 4-30 SAA7195A Video and Memory Controller (VMC) 4-9, 31 SAA7196 Digital video decoder and scaler (DESC-Pro) 4-2, 7, 9 A-8 Multimedia PC APPENDICES APPENDIX 3 TYPE NUMBER DESCRIPTION PAGE SAA7199B CCIR and square pixel digital encoder with genlock 4-12, 17 SAA7348 ACE (All Compact disc Engine) 7-4 SAA7360 Bitstream ADC 8-7 SAA7366 Bitstream ADC 8-7, 8 SAA7370(B)GP 10x single-chip digital servo processor and compact disc decoder 7-5 SAA7385 High performance CD-ROM controller 7-6, 7 SAA7388 Error corrector and host interface 7-6 SAA7390 High speed CD-recordable block decoder/encoder 7-6, 8 SAA8110 Camera DSP 9-7 SZA1010 Triple digital servo driver 7-13 TDA1300T Photodetector amplifiers and laser supply 7-9 TDA1303T Digital Servo Driver (DSD1) 7-12 TDA1305T(AT) Bitstream/CC filter DAC 8-9 TDA1306T Noise shaping filter DAC 8-10 TDA1308T Class AB stereo headphone driver 6-4, 8-16 TDA1309H Low power, low voltage stereo CODEC 8-2 TDA1311A(T) Low power stereo DACs 8-11 TDA1373 General digital I/O input with DSP (GDIO DSP) 8-6 TDA1386T Noise shaping filter DAC 8-10 TDA1387T Low power stereo DACs 8-11 TDA1388T(Z) Single-chip audio processor 8-5 TDA1396 16-bit stereo CODEC with FM synthesis 8-3 TDA1517P Stereo radio power amplifier 8-13 TDA1548T(Z) Single-chip audio processor 8-4 TDA4655 Generic multistandard analog decoder 4-34 TDA4665 Baseband delay line 4-35 TDA4670 Picture signal improvement processor 4-38 TDA4686(WP) Analog video processor 4-39 TDA4820T Sync. Separator IC for monitors 4-32 TDA7072A(T) BTL motor drive circuits 7-14 TDA7073A(T) BTL motor drive circuits 7-14 TDA8501 PAL/NTSC analog encoder 4-36 TDA8505 SECAM analog encoder 4-37 TDA8540(T) 4 x 4 video switch matrix 4-33 TDA8702 8-bit video DAC 4-24 TDA8706A 6-bit ADC with multiplexer and clamp 9-2 TDA8707 Triple RGB 6-bit ADC interface 4-20 TDA8708A/B Video analog input interface 4-20, 21 TDA8709A Video analog input interface 4-20, 22 TDA8712 8-bit video DAC 4-24 TDA8758 Low power A/D interface 4-20, 23 TDA8766 10-bit, high speed 3 V ADC 9-3 TDA8767 12-bit high speed ADC 9-4 TDA8771A Triple 8-bit video DAC 4-24, 25 TDA8772(A)H(3/8) Triple 8-bit video DAC 4-24, 26 TDA8775G Triple 10-bit video DAC 4-24, 27 TDA8786(A) 10-bit A/D interface for camera CCDs 9-5 Multimedia PC A-9 A APPENDICES APPENDIX 3 TYPE NUMBER DESCRIPTION PAGE TDA8790 8-bit 40 Msps 2.7 - 5.5 V universal ADC 9-6 TDA9850 I2C-bus 5-2, 3 TDA9852 I2C-bus controlled BTSC stereo/SAP decoder and audio processor 5-2, 4 TDA9855 I2C-bus controlled BTSC stereo/SAP decoder and audio processor 5-2, 4 TEA5582 PLL BTSC stereo decoder 5-2, 5 TEA5757H/5759H Self-tuned radio 6-3 TEA6320/1/2/3 Sound processors 8-14 TEA6360 5-band graphic equalizer 8-15 TZA1015 Data amplifier and laser supply 7-10 UAA3201T UHF/VHF remote control receiver 9-8 controlled BTSC stereo/SAP decoder A A-10 Multimedia PC