Multimedia PC - Philips Semiconductors / NXP Semiconductors

Philips

Semiconductors

Designer’s guide - October 1996

Multimedia PC

Semiconductors for

11551 new cover Multimedia 23/9/97 5:31 PM Page 2

1
Multimedia PC
MULTIMEDIA PC DESIGNER’S GUIDE 
Contents
Section Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2 System level examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
TV, radio and MPEG  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Video capture and editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Video conferencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Camera front-ends  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Videographics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
3 Review of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
4 Desktop video  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Digital video decoders  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Digital video scalers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Digital video encoders  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
PCI bridges  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Video analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Video digital-to analog converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Miscellaneous ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Sample analog ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
5 Television  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Analog TV tuners  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Sound decoders  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Closed caption/teletext decoders  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Digital cable/satellite ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
6 Radio  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
PC radio modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Multimedia/radio boards with R(B)DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Digital radio systems  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
7 Compact disc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
CD systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Integrated CD decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
CD-ROM & CD-R/E datapath ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Diode amplification and laser supply  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Digital servo controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Servo power drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
1-1

Multimedia PC
INTRODUCTION
1-2
1
8 Digital audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
CODECs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
DSPs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
ADCs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Stereo filter DACs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Low power stereo DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Audio MPEG decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Other audio ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
9 Camera and miscellaneous ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
A/D interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Camera DSP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Miscellaneous ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
10 Bus ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Universal Serial Bus ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
IEEE 1394-1995 ICs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
11 Reference/evaluation boards and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Digital video decoder/encoder module system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Demoboards & evaluation kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
General software  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
12 Monitors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
13 TriMedia  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
TM-1: the first in a family  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Typical TM-1 PC applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Appendices
1 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
2 Glossary of abbreviations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
3 Index of type numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

Multimedia PC

INTRODUCTION

1-3

The Multimedia PC is finally earning its name. First a business

and professional tool driven by such things as video editing,

video conferencing and office-based applications, the MPC is

now invading the home, with new functions such as TV, radio,

VCR, phone, newspaper, games, books, picture album and

more.

Philips Semiconductors is in a uniquely strong position both to

satisfy customer needs in this rapidly growing market and

provide technology leadership. One of the world’s largest semi-

conductor manufacturers, Philips Semiconductors has in house a

vast strength in depth of applied multimedia technology exper-

tise and can draw on the product and market knowledge of a sis-

ter consumer electronics division, to offer complete solutions for

the MPC.

A leader in digital video processing

Philips offers a very large range of solutions in digital video. Our

families of highly integrated multistandard decoders and

encoders offer very high quality performance, for such PC-based

applications as video editing and video conferencing. Other ICs

offer high performance scaling and many devices in the chipset

have on-board colour processing, conversion and filtering func-

tions. And for a truly complete video offering, Philips has video

A/D and D/A converters, camera DSPs, single-chip monitor ICs

and so on.

Exploiting the latest bus technologies

Philips is applying their PCI bus expertise in their latest desktop

video processing and graphics ICs, to deliver real-time process-

ing and capture of video and graphics in the PC. Outside the

PC, Philips is first to the market with a USB transceiver and

stand-alone HUB and has USB audio DACs and monitor

microcontrollers in development, ideal for low data rate “plug

‘n’ play” multimedia PC devices. And Philips also has ICs for an

enhanced version of the IEEE P1394 worldwide multimedia

connection standard, allowing it to carry MPEG-2 streams.

MPEG decoding

As one of the members of MPEG, Philips is playing an active

role in developing and refining MPEG compression standards.

The depth of Philips expertise is reflected in the quality of its

MPEG ICs, which implement the standards in full, delivering

excellent decompression quality for both audio and video.

Philips has a family of dedicated audio MPEG-1 and MPEG-2

decoders including versions with enhanced error correction for

digital radio; and a highly integrated audio/video/graphics

MPEG-2 decoder for digital TV applications.

TV and radio, digital and analog

Analog TV solutions for the PC cover all worldwide standards

and, by drawing on their extensive RF expertise and shielding

know-how, Philips is the first semiconductor manufacturer to

offer a high quality radio for the PC, including R(B)DS func-

tionality. Recent digital TV and digital radio solutions for the

PC draw on technologies and ICs developed for broadcast appli-

cations.

Solutions for all CD systems

As one of the pioneers of CD, Philips today can offer complete

system solutions for all the various CD technologies. We have

high-speed CD-ROM decoders and a range of highly integrated

datapath ICs offering speeds up to 12×for IDE and SCSI appli-

cations. Our extensive offer also includes the world's first single-

chip CD-Recordable/Erasable interface IC covering both IDE

and SCSI systems, offering 8×speed read and 4×speed write.

Digital audio for all multimedia needs

A world leader in digital audio, Philips' Bitstream technique

delivers the highest conversion performance available today,

with Continuous Calibration delivering low power, economy

solutions. Our range of ADCs/DACs is second to none; we have

single-chip sound-channel processing ICs for a number of PC

applications; and the first of a leading-edge audio CODEC fam-

ily offers six-channel digital mixing, on-board audio synthesis

and a host of other sound processing functions, making it effec-

tively a single-chip sound card.

Next generation programmable multimedia

By combining cost-effective advanced microprocessor technolo-

gy, easy programmability and comprehensive software tools,

Philips TriMedia family provides a complete, high performance

programmable multimedia solution. At the core is a next-genera-

tion DSP/CPU which integrates the power of a DSP with a

robust, CPU style software environment, to offer true multi-

media processing – the concurrent processing of audio, video,

graphics and communications. By combining the power of DSP

technology with a breakthrough software architecture which

allows programming in familiar high level language, together

with an instruction set optimized for multimedia, TriMedia is

more than powerful enough to drive the next generation of mul-

timedia products. It is fully supported with extensive software

development tools. For more information on TriMedia, see

Section 13.

Systems and application support – worldwide

Philips provides not only a large number of individual ICs, but

also many complete chipset and system solutions for a number

of MPC applications, all backed by reference designs,

demoboards and software. Customer support is available world-

wide and there are dedicated MPC groups in the USA

(Sunnyvale) and Europe (Hamburg, Germany), each with their

own development groups. Extensive applications and design-in

support is provided through five Systems Laboratories in

Sunnyvale (USA), Eindhoven (the Netherlands), Hamburg

(Germany), Southampton (UK) and Taipei (Taiwan).

UNIQUELY QUALIFIED IN PC-BASED MULTIMEDIA SOLUTIONS

2-1

Multimedia PC

SYSTEM-LEVEL

EXAMPLES

SYSTEM-LEVEL

EXAMPLES

2-2

Multimedia PC

Philips supplies all the ICs, software and system support for vir-

tually any MPC application and some chipset/system examples

are shown here. They are not necessarily intended as real-life

designs, but to show how Philips ICs fit together to provide all

the functions that might be needed, in an add-in card or for

integration onto the motherboard.

TV, RADIO AND MPEG

With just a few ICs, a computer can be turned into a TV to

allow video capture for editing, desk top publishing or video

conferencing. Philips TV Tuners, available from Philips

Components, accept the signal from a cable TV or TV aerial. By

adding further elements, radio can be included and with the

addition of ICs for MPEG decoding, a multifunction card can

be built with TV, radio and MPEG playback from CD-ROM

(for Video-CD applications).

A basic (analog) TV board

The composite video signal is sent to a video decoder to generate

digital YUV images and extract the closed caption or teletext

information from the TV signal. The scaler allows manipulation

of the YUV image and transmits it, together with the CC/TT

information, to the PCI Bus. The composite audio signal from

the tuner is decoded by a stereo SAP decoder, while tone control

and similar functions are provided by sound processing ICs,

after which it is amplified.

Scaling

Scaling may be required in almost any MPC application, often

because the video image in the Windows environment will be

scaled to an arbitrary size by the user. Also, images are often

scaled to reduce the bandwidth when sending data to the hard

disk, or the size and format of the image may need to be

changed to match the requirements of compression and graphics

controller ICs.

SYSTEM-LEVEL EXAMPLES

MSC223

CV or S Video

Audio

SAA7111(A)

VIDEO &

TEXT

DECODER

FI1236

TV & CABLE

TUNER

TDA9850

STEREO

AUDIO

DECODER

SAA7146

PCI

INTERFACE

GRAPHIC

CONTROLLER

TEA6320

STEREO

AUDIO

CONTROL

TDA1517

STEREO

2 x 6 W

AMPLIFIER

cable TV or

TV antenna

YUV PCI

bus

I2C

I2S

FOR MORE INFORMATION ON.. SEE PAGE

Cable/terrestrial TV tuners 5-12

Digital video decoding 4-2

PCI interfacing 4-18

Scaling 4-8

Audio processing 8-1

CC/teletext decoding 5-6

Closed Caption and Teletext Decoders

Philips has a very broad range of ICs for decoding closed cap-

tion, teletext or Intercast data sent in the vertical blanking inter-

val (when no active video is transmitted). For data and text

extraction the ICs receive the analog composite video signal,

locate the horizontal line where the digital data is embedded,

recover the clock and extract the data. After error detection and

correction, the text data are assembled and stored; the PC is

interrupted when a line or page of data is available.

2-3

Multimedia PC

Digital TV board

Philips is the first semiconductor manufacturer to supply inte-

grated solutions for both digital cable and satellite systems. The

following chipset is ideal for a PC-based digital broadcast solu-

tion or DVB/DAVIC cable modem.

For more information on Philips Digital Media Broadcast ICs,

see Section 5.

MSC227

TDA8046

QAM

CABLE

DEMODULATOR

TUNERcable

TUNER TDA8042/43

QPSK SATELLITE

DEMODULATION

SAA7207

FORWARD

ERROR

CORRECTION

AUDIO

PROCESSING

(DECOMPRESS)

VIDEO

PROCESSING

(DECOMPRESS)

SAA7205

DATA

SEPARATOR

(DEMUX)

SAA7206

ACCESS

CONTROL

(DESCRAMBLE)

SAA7124

VIDEO

ENCODER video

TDA1388T

AUDIO DAC

SAA7201 L

audio

SYSTEM-LEVEL EXAMPLES

A complete radio/TV and MPEG (video-CD)

playback board

This board incorporates the basic TV functionality described

above, but also includes Philips high performance radio for PCs.

An MPEG decoder could also be added, for display of com-

pressed data, often from a CD-ROM or Video-CD.

Radio

Philips PC FM radio tuner receives the FM signal from a TV or

antenna. The tuner produces a stereo signal output, which is A-

to-D converted and sent to the PCI bus. Philips also makes ICs

for an Astra Digital Radio (ADR) receiver and for a Digital

Audio Broadcast (DAB) channel decoder.

Video-CD in the PC

Video-CDs contain 74 minutes of MPEG-1 compressed audio

and video, read from the CD and sent via the ISA port of the

PCI bridge to the MPEG decoder for decompressing into digital

YUV video and digital I2S audio. The PCI bridge becomes PCI

bus master and bursts the digital video image and digital audio

sound to any desired memory location in the PC. Decompressed

images can also be sent to a TV via a digital video encoder.

For CD applications, Philips has high-speed CD decoder ICs

and a range of datapath ICs for CD-ROM and CD-Recordable/

Erasable systems. Through a sister division, Philips Key

Modules, Philips also offers complete CD engines.

MSC224

CV or S Video CV

YUV

YUV CV

ISA

audio

Audio

SAA7111(A)

VIDEO

DECODER

FI1236

TV & CABLE

TUNER

TDA9850

STEREO

AUDIO

DECODER

SAA7185

VIDEO

ENCODER

TDA7366

STEREO

AUDIO A/D

MPEG 1 A/V

DECODER

MPEG 1, TV and radio

in the computer

SAA7146

BIDIRECTIONAL

PCI

INTERFACE

RADIO

TUNER

cable TV or

TV antenna

radio 75 Ω

antenna

PCI bus

GRAPHIC

DISPLAY

RAM

CD-ROM

CPU

RAM

COMMUNIC.

LINK

RAM

audio

FOR MORE INFORMATION ON.. SEE PAGE

Cable/terrestrial TV tuners 5-12

Digital video decoding 4-2

Digital video encoding 4-12

Radio systems 6-1

PCI interfacing 4-18

Scaling 4-8

Audio processing 8-1

CD systems 7-1

CC/teletext decoding 5-6

2-4

Multimedia PC

VIDEO CAPTURE AND EDITING

Computer monitors display “square pixels” with 640 horizontal

pixels and 480 vertical pixels. As the display screen has the same

aspect ratio of 4 ×3, the 640 ×480 pixels are equally spaced

horizontally and vertically. Video communication and compres-

sion standards employ the international CCIR 601 digitizing

standard, specifying 720 samples during the active portion of the

video signal. Philips offers both square-pixel and CCIR-601

compliant decoders.

PC buses and video capture/editing

architectures

Live multimedia capture provides continuous video and audio

data streams at very high data rates (more than 20 Mbytes/

second). Data that is not captured is lost and playback which has

gaps and interruptions is quite disturbing, so availability of

enough bandwidth at the right time is crucial - predictable

scheduling and bandwidth allocation on the video bus is thus a

major issue.

In most consumer applications, audio has the highest priority as

any gaps in audio data produces unacceptable “clicks”. Video

data is secondary, as previous images can be repeated with little

noticeable effect if video data is lost.

Shared frame buffer architecture for playback

The shared frame buffer architecture allows playback of live

video and graphics on the computer monitor. If the VGA graph-

ics controller in the graphics card has a digital ‘video’ port, this

SYSTEM-LEVEL EXAMPLES

MSC225

CPU

CPU bus

RAM

(de) compress video capture communicate display

SAA7110A/

SAA7111(A)

VIDEO

DECODER

SAA7146

SCALER +

PCI INTERFACE

PCI

INTERFACE

PCI bus

HDISK

CD-ROM

edit

CODEC

RAM

PCI

INTERFACE

GRAPHICS

CONTROLLER

RAM

PCI

INTERFACE

allows a low cost videographics system to be built (see example

later in this section), but it does not allow video capture.

PCI architecture for playback, capture and editing

The PCI architecture, with its typical bandwidth of

100 Mbytes/second, is the only architecture allowing live video

playback and capture in the PC. It frees the local bus for normal

CPU system traffic, with video conducted on the PCI bus. The

architecture is a “shared memory” structure, where live images

are decoded and scaled by the video capture engine and sent to

the desired memory location in the computer. An arbiter man-

ages and distinguishes the real-time importance of each PCI

master requesting the bus, increasing the robustness of the PCI

bus and its capability to recover from an error.

Philips video capture and scaling ICs treat the odd and even

fields of interlaced video images independently. In a video edit-

ing application, the odd field of the image from the VCR is sent

directly to the frame buffer RAM of the graphics controller to

monitor incoming images. The even field can be scaled down

and sent to the hard disk for storage and editing. This indepen-

dent odd/even field system is also exploited in video conferenc-

ing applications (see next example).

FOR MORE INFORMATION ON.. SEE PAGE

Digital video decoding 4-2

PCI interfacing 4-18

Scaling 4-8

2-5

Multimedia PC

VIDEO CONFERENCING

In video conferencing application, the odd field of the image

from the local camera (the ‘vanity’ image) is sent directly to the

frame buffer RAM of the graphics controller, to be displayed on

the computer monitor. The even field is scaled down and sent to

the video conferencing compression engine.

Video conference application using a PCI

bridge IC

The PCI interface/scaler acts as a four way bridge. It receives

digital YUV images from the video decoder, scales them and

bursts them to the computer PCI bus for local display on the

monitor, compression and transmission via a phone line, ISDN

line or LAN. When images are received by the computer, it

decompresses, scales and/or zooms the images, which are then

encoded into baseband or S-video signals for TV display or

VCR recording. The PCI bridge also sends and receives digital

sound in I2S format; it can interface with an ISA-bus based

MPEG-decoder via its DEBI port; and it can read closed caption

and teletext data from a video decoder or a dedicated decoding

IC.

Video conferencing systems are also easily implemented with

Philips high power, programmable multimedia processor,

TriMedia, described in Section 13.

MSC226

SAA7110A

SAA7111(A)

VIDEO

DECODER

SAA7366

PREAMP +

AUDIO A/D

SAA7125

SAA7185B

VIDEO

ENCODER

TDA1388T

AUDIO D/A

+ AMP

SAA7146

SCALER +

PCI

INTERFACE

TV or VCR

speakers

monitor

YUV

I2S I2S

video conference

system

PCI bus

microphone

phone line GRAPHIC

CONTROLLER

SOFTWARE OR

HARDWARE

(DE) COMPRESS

MODEM

FOR MORE INFORMATION ON.. SEE PAGE

Digital video decoding 4-2

Digital video encoding 4-12

PCI interfacing 4-18

Scaling 4-8

Audio processing 8-1

CC/teletext decoding 5-6

Programmable multimedia processors 13-2

CAMERA FRONT-ENDS

Philips also makes the video camera DSPs and A/D interfaces

needed for a complete video conferencing system.

For more information on camera A/D interfacing and DSPs, see

Section 9.

MSC228

CORRELATED

S/H + AGC

TIMING

GENERATOR

CCD

DRIVERS CAMERA

DSP

analog CV,

S-Video or

digital YUV

ADC

TDA8786

SAA8110

SYSTEM-LEVEL EXAMPLES

2-6

Multimedia PC

SYSTEM-LEVEL EXAMPLES

MSC229

TEXT

SLICER

SAA7112

DECODER

+ SCALER

SDA

SCL

U, V

YUV

GRAPHICS

& VIDEO

ACCEL.

video port

CHROMA

CIRCUIT

LUMA

CIRCUIT

digitized CV

or S-Video

S or CV

inputs

Vsync

Hsync

2 x A/D

CONVERT

SYNCHRO-

NIZATION

I2C BUS

INTERFACE GRAPHICS ENGINE

BITBLT, CLIPPING

DISPLAY

MEMORY

CONTROL

FRAME

BUFFER

MEMORY

VIDEO SCALE

YUV-RGB

RAMDAC

CLOCK

SYNTHESIZER

SCALER,

YUV-RGB

FIFO

EXPANSION

PORT

CLOCK

GENERATE

MUX, AMP

FILTER

VIDEOGRAPHICS

Using the shared frame buffer architecture described under

“video editing” allows a low cost solution for the playback of live

video and graphics on the computer monitor, provided the VGA

controller in the graphics card has a digital ‘video’ port.

FOR MORE INFORMATION ON.. SEE PAGE

Digital video decoding 4-2

Scaling 4-8

Graphics 2-6

Multimedia PC 3-1

REVIEW OF

ICs

REVIEW OF

ICs

3-2
3
Multimedia PC
SELECTION CHART
DESCRIPTION TYPE NUMBER PACKAGE PAGE
Desktop video
DIGITAL VIDEO DECODERS
One Chip Front-end (OCF) SAA7110A  PLCC68 4-2, 3
Video Input Processor SAA7111(A)  PLCC68 4-2, 4
QFP64 
SAA7111A only TQFP64
Decoder with HPS scaler for image port SAA7112  LQFP100 4-2, 5, 9
Digital video decoder and scaler (DESC-Pro) SAA7196  QFP120 4-2, 7, 9
DIGITAL VIDEO SCALERS
Digital video scaler SAA7186  QFP100 4-9, 10
High Performance Scaler (HPS) SAA7140A/B  TQFP128 4-9, 11
DIGITAL VIDEO ENCODERS
EURO-DENC digital video encoder SAA7182/83  PLCC84 4-12, 14
EURO-DENC2 digital video encoder SAA7182A/83A  QFP80 4-12, 13
ECO-DENC digital video encoder SAA7124/5  PLCC84 4-12, 15
QFP80
LQFP64
DENC-M6 digital video encoder SAA7184/85B PLCC88 4-12, 16
DENC-M digital video encoder SAA7188A/85 PLCC88 4-12, 16
DENC2 Square pixel digital video encoder SAA7187 PLCC88 4-12, 16
CCIR and square pixel digital encoder with genlock SAA7199B PLCC84 4-12, 17
PCI BRIDGES
Scaler and PCI bridge (SPCI) IC SAA7146 TQFP208 4-9, 18
VIDEO ANALOG-TO-DIGITAL CONVERTERS
Triple RGB 6-bit ADC interface TDA8707 QFP44 4-20
Video analog input interface TDA8708A/B SO28L 4-20, 21
DIP28
Video analog input interface TDA8709A DIP28 4-20, 22
TDA8709A(T) SO28L 4-20, 22
Low power A/D interface TDA8758  TQFP48 4-20, 23
VIDEO DIGITAL-TO-ANALOG CONVERTERS
8-bit video DAC TDA8702 DIL16 4-24
TDA8702T SO16 4-24
8-bit video DAC TDA8712 DIL16 4-24
TDA8712T SO16 4-24
Triple 8-bit video DAC TDA8771A  QFP44 4-24, 25
Triple 8-bit video DAC TDA8772(A)H(3/8)  QFP44 4-24, 26
Triple 10-bit video DAC TDA8775G LQFP48 4-27
Video Enhancement and D/A processor SAA7165  PLCC44 4-28
Mixer and D/A processor SAA7167(A)  TQFP48 4-29
REVIEW OF ICs

3-3
Multimedia PC
3
DESCRIPTION TYPE NUMBER PACKAGE PAGE
MISCELLANEOUS ICS
Digital colour space converter (DCSC) SAA7192A  PLCC68 4-30
Video and Memory Controller (VMC) SAA7195A QFP160 4-9, 31
Sync. Separator IC for monitors TDA4820T  SO8 4-32
4 ×4 video switch matrix TDA8540 DIL20 4-33
TDA8540T TSO20 4-33
SAMPLE ANALOG ICS
Generic multistandard analog decoder TDA4655 SDIL24 4-34
TDA4655T  SO24 4-34
Baseband delay line TDA4665 DIL16 4-35
TDA4665T  SO16 4-35
PAL/NTSC analog encoder TDA8501 DIL24 4-36
TDA8501T  SO24 4-36
SECAM analog encoder TDA8505 DIL32 4-37
Picture signal improvement processor TDA4670 DIL18 4-38
Analog video processor TDA4686 DIL28 4-39
TDA4686WP PLCC28 4-39
TV
SOUND DECODERS
I2C-bus controlled BTSC stereo/SAP decoder TDA9850 SDIP32 5-2, 3
TDA9850T SO32 5-2, 3
I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9852 SDIP42 5-2, 4
I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 SHDIL52 5-2, 4
TDA9855WP PLCC68 5-2, 4
PLL BTSC stereo decoder TEA5582  DIL20 5-2, 5
CLOSED CAPTION/TELETEXT DECODERS
Integrated VIP and teletext decoder SAA5246A QFP64, DIL48 5-6
Integrated VIP and teletext decoder with background memory controller SAA5249 SO24, DIL24 5-6
Integrated VIP and teletext decoder SAA5254 QFP64, DIL40 5-6, 7
Integrated VIP and teletext decoder SAA5281 QFP64, SDIL52 5-6
Software for a range of Teletext decoder ICs  PC Text – 5-6
Multimedia VBI and FF data acquisition IC SAA5284 QFP44 5-6, 7
Line 21 decoder SAA5252P DIL24 5-8
SAA5252T SO24L 5-8
One-page economy teletext/TV microcontroller SAA5290 SDIP52 5-9
Single-chip economy 10 page teletext/TV microcontroller SAA5296ZP/nnn  SDIL52 5-10
SAA5296GP/nnn  QFP80 5-10
SAA5299ZP/nnn  SDIL52 5-10
(EEPROM)
DIGITAL CABLE/SATELLITE ICS
Range of ICs from Philips Digital Media Broadcast chipset DMB chipset 5-11
REVIEW OF ICs

3-4
3
Multimedia PC
REVIEW OF ICs
DESCRIPTION TYPE NUMBER PACKAGE PAGE
Radio
PC RADIO MODULES
Self-tuned radio TEA5757H/5759H  QFP44 6-3
Remote 8-bit I/O expander for I2C-bus PCF8574P/AP DIP16 6-4
PCF8574T/AT SO16 6-4
PCF8574TS SSOP20 6-4
MULTIMEDIA/RADIO BOARDS WITH R(B)DS
R(B)DS controller CCR921 QFP44 6-5
R(B)DS demodulator SAA6579 DIL16 6-6
SAA6579T SO16 6-6
Stereo radio power amplifier TDA1517P  SIL9 8-13
Sound processors TEA632X SDIL32  8-14
TDA632XT SO32 8-14
5-band graphic equalizer TEA6360 DIL32SHR 8-15
TEA6360T SO32 8-15
Digital radio systems – – 6-7, 8
Compact Disc
CD SYSTEMS
CD-ROM subsystem and system solutions (6×and 8×) ROM 65XXX  – 7-2
CD-ROM subsystem and system solutions (12×) ROA 1312/X – 7-3
CD-Recordable subsystem E65400 – 7-3
CD-Recordable data engine D65420 – 7-3
CD-Recordable subsystem and CD-R data engine CDU 2600 – 7-3
INTEGRATED CD DECODERS
ACE (All Compact disc Engine) SAA7348 LQFP100 7-4
10×single-chip digital servo processor and compact disc decoder SAA7370(B)GP  QFP64 7-5
CD-ROM & CD-R/E DATAPATH ICS
Error corrector and host interface SAA7388  QFP80 7-6
High performance CD-ROM controller SAA7385 QFP128 7-6, 7
High speed CD-recordable block decoder/encoder SAA7390  QFP128 7-6, 8
DIODE AMPLIFICATION AND LASER SUPPLY
Photodetector amplifiers and laser supply TDA1300T SO24L 7-9
Data amplifier and laser supply TZA1015 SO28 7-10
DIGITAL SERVO CONTROLLER
Digital servo controller OQ8868 QFP44 7-11

3-5
Multimedia PC
3
DESCRIPTION TYPE NUMBER PACKAGE PAGE
SERVO POWER DRIVERS
Digital Servo Driver (DSD1) TDA1303T  SO24L 7-12
Triple digital servo driver OQ8844 SO20 7-13
Triple digital servo driver SZA1010 SO20 7-13
BTL motor drive circuits TDA7072A DIP8 7-14
TDA7072AT SO8 7-14
BTL motor drive circuits TDA7073A DIP16  7-14
TDA7073AT SO16L 7-14
Digital audio
CODECS
Low power, low voltage stereo CODEC TDA1309H  QFP44 8-2
16-bit stereo CODEC with FM synthesis TDA1396  TQFP128 8-3
DSPS
Single-chip audio processor TDA1548T(Z)  SSOP28 8-4
Single-chip audio processor TDA1388T SO28 8-5
TDA1388TZ  SSOP28 8-5
General digital I/O input with DSP (GDIO DSP) TDA1373  QFP64 8-6
ADCS
Bitstream ADC SAA7360  QFP44 8-7
Bitstream ADC SAA7366  SO24L 8-7, 8
STEREO FILTER DACS
Bitstream/CC filter DAC TDA1305T(AT)  SO28 8-9
Noise shaping filter DAC TDA1306T SO24 8-10
Noise shaping filter DAC TDA1386T  SO24 8-10
LOW POWER DACS
Low power stereo DACs TDA1311A(T) DIL8/SO8 8-11
Low power stereo DACs TDA1387T SO8 8-11
AUDIO MPEG DECODERS
Audio MPEG-1 decoder SAA2500  QFP44 8-12
Audio MPEG-1 decoder for Astra Digital Radio (ADR) SAA2501 QFP44 8-12
Audio MPEG-1 decoder with MPEG-2 stereo capability SAA2502 QFP44 8-12
OTHER AUDIO ICS
Stereo radio power amplifier TDA1517P  SIL9 8-13
Sound processors TEA6320/1/2/3 8-14
TEA6320S DIL32  8-14
TDA6320T SO32 8-14
5-band graphic equalizer TEA6360 DIL32SHR 8-15
TEA6360T SO32 8-15
Class AB stereo headphone driver TDA1308T  Single  DIP8 6-4, 8-16
Dual SO8 6-4, 8-16
REVIEW OF ICs

3-6
3
Multimedia PC
DESCRIPTION TYPE NUMBER PACKAGE PAGE
Camera and miscellaneous ICs
A/D INTERFACES
6-bit ADC with multiplexer and clamp TDA8706A  DIL20 9-2
TDA8706T SO20L 9-2
10-bit, high speed 3 V ADC TDA8766  LQFP32 9-3
12-bit high speed ADC TDA8767 QFP44 9-4
10-bit A/D interface for camera CCDs TDA8786(A)  LQFP48 9-5
8-bit 40 Msps 2.7 - 5.5 V universal ADC TDA8790 SSOP20 9-6
CAMERA DSPS
Camera DSP SAA8110 LQFP80 9-7
MISCELLANEOUS ICS
UHF/VHF remote control receiver UAA3201T  SO16 9-8
Bus ICs
UNIVERSAL SERIAL BUS ICS
USB transceiver PDIUSBP11 SO14 10-2
USB stand alone hub PDIUSBH11 SDIP32 10-3
Monitor microcontroller with USB plus hub P83C190 SDIP56 10-3
IEEE 1394 ICS
IEEE P1394 serial bus AV link layer controller PDI1394L11 PQFP80 10-4
IEEE P1394 serial bus AV physical layer controller (in development) PDI1394P11 t.b.f. 10-4
REVIEW OF ICs

4-1

Multimedia PC

DESKTOP VIDEO

4-2 Multimedia PC

All Philips decoders offer:

■Support for PAL and NTSC standards with

automatic signal detection

■8-bit resolution inputs

■CVBS and S-Video inputs

■Line-locked clock decoding

■RTC output to lock encoding to decoding

■Output 4:2:2 16-bit YUV/YCrCb signals

■Brightness, Contrast and Saturation and hue

control on the output bus

■PAL delay line

■PAL and NTSC chroma filtering

■Peaking and coring filters

■On-chip clock generation

■I2C-bus controllable

DIGITAL VIDEO DECODERS

the line frequency of the incoming signal. This ensures excellent

picture quality and an orthogonal sampling structure is main-

tained, even for non-standard inputs such as VCRs.

Philips’ unique RTC (Real-Time Control) synchronizes encod-

ing and decoding by locking the encoding process to the decod-

ing. This provides accurate and stable colour rendition at the

encoder end, even when the signal is non-standard or subject to

adverse affects such as noise; it also provides solid decoding of

NTSC signals.

The 8-bit chrominance signal is fed into a demodulator and two

sub-carrier signals are applied from a local oscillator, at a fre-

quency depending on the current colour standard. Output sig-

nals from the demodulators are filtered to achieve the desired

bandwidth for the colour difference signals. Chroma filters elimi-

nate cross-talk between the chrominance channels in PAL, and

between the chrominance and luminance channels (cross-colour)

in NTSC. A PAL delay line is implemented to correct for PAL

phase errors.

The 8-bit luminance signal is fed through a switchable pre-filter.

If it is a CVBS signal, it is then passed through a chroma trap fil-

ter to eliminate most of the colour carrier signal. High frequency

luminance components can be ‘peaked’ in two bandpass filters

with programmable transfer characteristics. Further filtering by a

coring circuit improves the signal before it is added to the origi-

nal ‘unpeaked’ signal. Common DC amplification is achieved

using a switchable amplifier, necessary because the DC gains are

different in the two chroma trap modes. BCS control is then

applied to the improved luminance signal before output.

Philips’ current range of digital video decoders includes both

CCIR-compliant and square-pixel devices, some with on-board

scaling features. All decoders are capable of full multistandard

operation, with the CCIR-compatible devices supporting all

individual sub-standards. All Philips decoders are highly integrat-

ed, with many features and extensive functionality included on

chip; all recent ICs include on-board ADCs.

PAL, NTSC and SECAM signals are colour decoded using

Philips unique line-locked clock feature, in which the decoder

drives the clock generator to obtain a sampling clock locked to

Philips digital video decoders

SAA7110A SAA7111 SAA7111A SAA7112 SAA7196

CCIR/Square pixel SQP CCIR-601 CCIR-601 CCIR-601 SQP

Supported standards

PAL B, G B, G, H, I, M, N B, G, H, I, M, N B, G, H, I, M, N B, G

NTSC M M, N M, N M, N M

SECAM Yes No Yes Yes Yes

Outputs formats

YUV 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit

4:1:1 12-bit 4:1:1 12-bit 4:1:1 12-bit 4:1:1 12-bit –

CCIR – 656 8-bit 656 8-bit 656 8-bit –

RGB – 16-bit (5-6-5) 16-bit (5-6-5) 16-bit (5-6-5) 15-bit (5-5-5)

24-bit (8-8-8) 24-bit (8-8-8) 24-bit (8-8-8) 24-bit (8-8-8)

Other No No No No 8-bit scaled

mono

CC/Line 21 data slicer Yes Yes Yes Yes No

VBI data decoder No No Yes Yes No

Scaling features No No No Yes Yes

Dual 8-bit video ADC Yes Yes Yes Yes No

Expansion port No No No No Bi-directional

Refer to page 4-3 4-4 4-4 4-5 4-7

4-3

Multimedia PC

SAA7110A

QUICK REFERENCE DATA

Power supply 5 V

Total digital supply current 250 mA

Total analog supply current 150 mA

Total power dissipation (max.) 1.7 W

Package PLCC68 (SOT188)

Datasheet (12NC) 9397 750 00368

DESKTOP VIDEO DIGITAL VIDEO DECODERS

OCF (One Chip Front-end)

All features listed in overview (page 4-2) plus:

■Full multistandard decoding including SECAM

■Six analog inputs with internal video source selec-

tors (six CVBS, three Y/C or a combination)

■Outputs YUV signals in 12-bit 4:1:1 or 16-bit 4:2:2

■Three analog processing channels with analog

signal adding of two channels

■Three built in anti-alias filters

■Selectable signal (white) peak control

■On-chip clock generator uses one 26.8 MHz crystal

for all standards

This state-of-the-art one-chip solution for video input processing

provides D/A conversion of CVBS or Y/C analog signals, multi-

standard decoding and filtering, and digital YUV output for fea-

ture processing. After digitization, pre-processing channels per-

form automatic gain control, clamping and peak-white limiting

of the input signal. As a square pixel decoder working on the

basis of the TV-2 system, it generates 768 and 640 active pixels/

line in 50 Hz (PAL/SECAM) and 60 Hz (NTSC) environments.

MBE202

ANALOG

PRE-

PROCESSING

AIN32

AIN31

AIN22

AIN21

AIN12

AIN11

I C

CONTROL

ADC2

ADC1

CHROMINANCE

PROCESSING

LUMINANCE

PROCESSING

SYNCRONISATION

ANALOG

INPUT

CONTROL

I C

2sync signals

BRIGHTNESS,

CONTRAST,

SATURATION

CONTROL

SAA7110 ONE CHIP FRONTEND

CLOCK

GENERATION

CIRCUIT

UVout/8

Yout/8

CLOCK

4-4

Multimedia PC

Video Input Processor (VIP)/

Enhanced VIP (EVIP)

All features listed in overview (page 4-2) plus:

■Automatic PAL and NTSC decoding (‘A’ version

also decodes SECAM)

■Four inputs (four CVBS, two Y/C, or one Y/C and

two CVBS) with internal source selection

■Outputs YUV signals in 12-bit 4:1:1, 16-bit 4:2:2,

8-bit 4:2:2, RGB 5:6:5 or RGB 8:8:8 formats

■Dual processing channels each contain clamp

circuit, analog amplifier, anti-aliasing filter and 8-bit

CMOS video ADC

■Fully programmable static gain control for main

channels or automatic gain control for selected

CVBS or Y/C channel

■Boundary scan test

■On-chip line 21 (CC) slicer

■VBI data decoder (‘A’ version)

■Low power ‘A’ version in LQFP is ideal for note-

books, PCMCIA cards, etc.

DESKTOP VIDEO DIGITAL VIDEO DECODERS

SAA7111/SAA7111A

QUICK REFERENCE DATA

Power supply 5 V (3.3 V for ‘A’ version)

Total digital supply current 130 mA (70 mA)

Total analog supply current 70 mA

Total power dissipation (max.) 1.26 W (0.5 W)

Package PLCC68 (SOT188);

QFP64 (SOT393)

(SAA7111A only) LQFP64 (SOT314G8)

Datasheet (12NC) SAA7111 9397 750 00847

SAA7111A Contact Philips

MSB795 - 1

CHROMINANCE CIRCUIT

BRIGHTNESS

CONTRAST

SATURATION

CONTROL

C/CVBS

BYPASS

I2C-BUS

INTERFACE

Y/CVBS UV

YUV-to-RGB

CONVERSION

OUTPUT

FORMATTER

CLOCK

GENERATION

CIRCUIT

POWER-ON

CONTROL

CLOCK

ANALOG

PROCESSING

ANALOG

CONTROL

TEST

CONTROL

BLOCK

(FOR

BOUNDARY SCAN

TEST AND

SCANTEST)

LUMINANCE

CIRCUIT

SYNCHRONIZATION

CIRCUIT

I2C-CONTROL

XTAL

XTALI

LLC2

CREF

LLC

RESN

FEIN

HREF

VPO (0 :15)

GPSW

SCL

IICSA

SDA

VSSA0 CEVDDA0

RTCORTS1RTS0VREFHSVS

AOUT

AI11

AI12

AI22

AI21

TDI

TCK

TMS

TRSTN

TDO

SAA7111

The SAA7111(A) (E)VIP is essentially a CCIR-601 compliant

derivative of the SAA7110A. It has an analog front-end includ-

ing two analog pre-processing channels with A/D conversion

and decodes both PAL and NTSC standards. Each channel

includes a clamp circuit, to ensure proper clamping. Levels are

assigned to the analog input signals and anti-aliasing filters,

adapted to the clock frequency using the filter control. Signals

can also be peak white limited. The SAA7111A, a low power

variant, also accepts SECAM signals and includes SECAM cross-

colour reduction. It has a number of additional functions built-

in including a VBI (Vertical Blanking Interval) bypass mode.

4-5

Multimedia PC

Decoder with HPS scaler for image port

All features listed in overview (page 4-2) plus:

■Full multistandard decoding including SECAM

■Six analog inputs with internal video source selec-

tors (six CVBS, two Y/C and two CVBS, or one

Y/V and 4 CVBS)

■Outputs YUV signals in 12-bit 4:1:1, 16-bit 4:2:2,

8-bit 4:2:2 or RGB 5:6:5 format

■Dual analog processing channels with source selec-

tion, anti-aliasing filters, automatic clamp circuit

and an 8-bit CMOS video DAC

■Fully programmable static gain for main channel

or AGC on selected Y/CVBS channel

■On-chip clock generator uses one 32.11 MHz

crystal for all standards

■Versatile VBI decoder, slicer, clock regeneration

and byte synchronization

■Switchable peak white limiting

SAA7112

■2-D scaler core based on SAA7140B uses phase-

correct interpolation to deliver excellent signal

quality, especially on compressed data

■Arbitrary horizontal and vertical scaling of

between 2×(zoom) and down to ×1/64 (icon)

■Two independent programming sets for scaler,

allowing definition of two ‘ranges’ per field or

frame

HORIZONTAL

PHASE SCALING

LUMINANCE

INPUT

ACQ.

CONTROL

4:2:2

OUTPUT

INTERFACE

4:2:2

BCS

CONTROL

LINE

FIFO

BUFFER

OUTPUT

ACQ.

CONTROL

YUV

OUTPUT

FORMAT

VIDEO FIFO

32 × 32

TEXT FIFO

16 × 32

GENERAL

PURPOSE

TEXTSLICER

TXT

INTERFACE

data, clock

and reference

signals

data, clock, H,

V, FID and

qualifier

VIDEO / TEXT

ARBITER

FIFO CONTROL

HOST PORT PIN MAPPINGEXPANSION PORT PIN MAPPING

HADP

SAA7112

IIC

Vref

PROGRAMMING

PORT CONTROL

D1 IND1 OUT

RT OUT

SLEEP MODE REGISTER

PROGRAMMING

ARRAY

A/B

MUX

CLOCK MULTIPLEXER

INLC. TCB

EVENT

CONTROLLER

FIFO CONTROL

32 TO 8(16)

MUX

OUT

LPB

VID.

OUT

IPD[7:0]

IRH

IRV

IDQE

ICRQF

ITRDY

ICLK

ITRI

MSC170 - 1

IMAGE

PORT

MAPPING

32 TO 8(16)

MUX

VERTICAL

SCALING

PROCESSOR

LINE

MEMORY

1H* 16 BIT

HORIZONTAL

PHASE SCALING

CHROMINANCE

FIR-FILTER

LUMINANCE

FIR-FILTER

CHROMINANCE

PRESCALING

LUMINANCE

PRESCALING

CHROMINANCE

HCST

chroma of 16 bit output mode

from event

controller

chroma of

16 bit

input mode

HRWNF HACNSD

HDSNSC HPD[7:0]

XCLK

X PORT INPUT

FORMATTER

(SELECT)

RTS1

RTCALLC RTS0

LLC2 XRV XTRI

XDQ XRH

XPD[7:0] XREQ

LPB

PROG.

AI11, AI12

AI21..AI24

AOUT

DUAL

ADC

AUDIO

MASTER

CLOCK

GENERATION

AUDIO BIT

CLOCK WORD

SELECT

GENERATION

7111A

BASED

DIGITAL

DECODER

AMCLK

ASCLK

ALRCLK

AXMCLK

RESIN

RESON

XOUT

XTALI

XTAL

CLOCK

GENERATION

AND

POWER ON

CONTROL

DESKTOP VIDEO DIGITAL VIDEO DECODERS

QUICK REFERENCE DATA

Power supply 3.3 V

Total digital supply current t.b.f.

Total power dissipation (max.) t.b.f.

Package LQFP100 (SOT407)

Datasheet (12NC) 9397 750 00923

4-6

Multimedia PC

■Field-wise switching between decoder and expan-

sion port input

■6-bit phase accuracy with accumulating filter for

anti-aliasing

■Generation of field locked audio Master Clock and

an audio serial and left/right (channel) clock signal

■Bi-directional expansion port, video image port

and host port

■32-word × 4-byte FIFO for video output data and

16-word ×4 byte FIFO for decoded VBI data

The SAA7112 is an IC to capture and scale video images, passed

as a digital video stream through the image port of a VGA con-

troller, for display via the VGA frame buffer or for capture to

system memory. A very highly integrated device, it combines

dual analog pre-processing channels, A/D conversion, clock gen-

eration, full multistandard video decoding, high performance

scaling and a number of other signal processing functions, all on

one chip. BCS control is provided on both decoder and scaler

outputs; in addition to the outputs listed, the scaler can output

scaled luminance or raw data only. The VBI decoder supports

WST, NABST, CC, WSS etc.

The bi-directional port has half duplex functionality (D1) to

output 8-bit YUV data from the decoder or input to the scaler

(e.g. from an MPEG-decoder or video phone CODEC). The

video image port is used to interface to the VGA controller and

is configurable for master or slave operation, with auxiliary tim-

ing and handshake signals, while the host port allows extension

of the image port to 16-bit. Discontinuous data streams are sup-

ported.

The field locked audio clock generation ensures the same num-

ber of audio samples associated either with a single field or a set

of fields, preventing any loss of synchronization between audio

and video during capture or playback.

DESKTOP VIDEO DIGITAL VIDEO DECODERS

4-7

Multimedia PC

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 10 mA

Digital supply current 170 mA

Total power dissipation (max.) 1.5 W

Package LQFP120 (SOT349 AA1)

Datasheet Handbook IC22

SAA7196

Digital video DEcoder, SCaler (DESC-Pro)

All features listed in overview (page 4-2) plus:

■Multistandard decoder with single CVBS or

S-Video input

■Outputs 16-bit 4:2:2 YUV, RGB 15-bit (5-5-5) and

24-bit (8-8-8), and 8-bit scaled monochrome

■Programmable luminance peaking for aperture

correction

■Switchable RGB matrix and anti-gamma ROMs

■Chroma key (α generation)

■High quality scaling of video pictures down to

arbitrary sized windows

■Maximum 1023 pixels per line and 1023 lines per

field

■Two-dimensional data processing for improved

signal quality and compression of scaled video data

■Horizontal and vertical sync detection for all

standards

■DEBI port (YUV bus) supports data rates of

780 ×fH(NTSC) and 944 ×fH(PAL/SECAM) in

4:2:2 format

■Output configurable for 32/24/16-bit video data bus

■16-word FIFO register for 32-bit output data

■Line increment, field sequence and vertical reset

control for easy memory interfacing

■Output can either be in synchronous (transparent)

or asynchronous (burst) transfer modes

The SAA7196 is a highly integrated IC combining digital video

decoding functions, scaling and clock generation functions.

Monitor controls are incorporated to ensure optimum display.

Decoder and scaler parts can operate at different clock frequen-

cies, generated by the single on-chip crystal which also clocks the

I2C-bus, allowing both scaler and decoder to be used indepen-

dently. For a description of the scaling functions, refer to

‘Scalers’ on page 4-8.

An external ADC first converts analog video signals to 8-bit dig-

ital video data, fed either to one input port for CVBS signals or

both input ports for Y/C data (using a second ADC). Other data

ports include a 32-bit VRAM port which outputs down-scaled

video data to memory and supports different format and opera-

tion modes. The 16-bit bi-directional expansion port can be

configured to send data to the decoder part of the IC, or accept

data for input to the scaler (where it can take clock rate and

sync. signals from the external source).

CHROMINANCE PROCESSOR

SCALE CONTROL

SYNCHRONIZATION

clock clock a

RESN

GPSW1

GPSW2

SDA

SCL

HSY LFCO RTS1 RTS0 XTAL XTALI

HCL

+5 V

IICSA

CHR(7-0)

CVBS(7-0)

control and

status from

scaler part

status

SYNC

PLIN

HREF

YUV(15-0)

UV(7-0)

Y(7-0)

HS, VS

LUMINANCE

PROCESSOR

INPUT

INTERFACE

I2C-BUS

CONTROL

PORT AND

STATUS

CLOCK A

GENERATOR

CHROMA

DECIMATION

FILTER

INTERPOLATOR CHROMA

KEYER

RGB

MATRIX

FOLLOWED

ANTI-GAMMA

ROMs

OUTPUT

FORMATTER

OUTPUT

FIFO

BRIGHTNESS

CONTRAST

AND

SATURATION

CONTROLS

(BCS)

CLOCK B

GENERATOR

BUS INTERFACE CREFINB clock B

to scaler and

brightness,

contrast

saturation

controls

LLCINB

CGC

CREFLLC

VERTICAL FILTER

CTSTCGCE

RTCO

LUMINANCE

DECIMATION

FILTER LINE

MEMORY

(8 × 384)

ARITHMETIC

VCLKVOEN

INCADR

HFL

VMUX

SODD

SVS

PQQ

SHREF

BTST

SAA7196

LLC2DIR LLCB

CREFB

HREF

YUV (15-0)

input/output

VRO (31 TO 0);

32-bit VRAM

port output

RGB or YUV

LNQ

MSC169 - 1

DESKTOP VIDEO DIGITAL VIDEO DECODERS

4-8

Multimedia PC

Philips currently offers two dedicated scalers, while a number of

other devices in our DTV portfolio also incorporate scaling

functions including decoders, PCI bridges and a video memory

controller. Three levels of scaling performance are available

depending on the IC, ranging from High Performance, 2-D

phase correct scaling (HPS) down to simple Binary Ratio

Scaling (BRS) through pixel and line dropping, offering flexibili-

ty to match the specific needs of your application.

All Philips’ scaler cores offer a minimum of high quality scaling

of video pictures down to arbitrary-sized windows. The ICs

themselves include a variety of input and output interfaces; all

have at least one 16-bit YUV data input port with outputs avail-

able either in synchronous (transparent) or asynchronous (burst)

transfer modes.

HPS (High Performance Scaling)

■2-D phase-correct interpolation delivers excellent

signal quality, especially on compressed data

■Horizontal pre-scaling unit filters input 4:4:4 YUV

data to reduce the signal bandwidth

■Phase scaling minimizes the number of phase or

amplitude artefacts

■‘Flip’ option mirrors input lines

Scaling is carried out in three stages: horizontal pre-scaling, ver-

tical scaling and horizontal phase scaling, with the scaling unit

receiving timing information from the input ports. The pre-scal-

ing consists of an FIR pre-filter, which reduces signal bandwidth

according to the required scale factor to reduce aliasing. As

phase-correct horizontal fine scaling is limited to a downscale

maximum of ×1/4, a sub-sampler is included which improves

scaling performance for scale factors from < ×1/2down to icon

size, by reducing the incoming pixel count.

The input data stream can be vertically downscaled, up to a

maximum line length of 768 pixels/line. An ACCU mode can

be used for all vertical scales down to icon size (1 to 1/1024), in

which the output line qualifier pattern and the sequence length

for the line averaging can be defined, with scaling performance

improved by weighting the accumulated lines. The resulting

amplitude gain of the scaled output signal is then normalized.

To preserve signal quality in limited vertical down-scales (1 to

×1/2), an LPI mode is used between consecutive lines to generate

a new geometric line position. A new output line is then calcu-

lated by weighting the samples with the normalized distance to

the new geometric position.

Horizontal phase-correct scaling then calculates pixels for the

geometrically correct orthogonal output pattern, down to ×1/4of

the pre-scaled pattern. Phase-correct scaling consists of a filter

and arithmetic structure that generates a new phase correct

value, minimizing the number of phase or amplitude artefacts.

Sample phase information is generated by a phase calculator

with an accuracy of 1/64 pixel distance.

2-D scaling

■Two-dimensional data processing improves signal

quality and compression of scaled video data

■Horizontal filtering, handled by two separate deci-

mation filters, reduces artefacts from pixel

dropping

■Signal bandwidth can be reduced in steps between

2-tap and 9-tap

■Video Processing Unit (VPU) processes vertical

luminance data to avoid artefacts caused by line

dropping

■YUV-to-RGB conversion according to CCIR-601

recommendations

Although this scaler functions by pixel and line dropping, initial

pre-filtering improves signal quality and helps to avoid artefacts.

First, filters match the signal characteristics before the pixel deci-

mation stage to reduce artefacts from pixel dropping. Lumi-

nance data are fed to a vertical filter consisting of a 384 x8-bit

RAM and an arithmetic block for sub-sampling and interpola-

tion. By vertical processing, video information is preserved even

for small scale factors, avoiding artefacts. Chrominance data are

interpolated to produce a YUV 4:4:4 data stream before YUV-

to-RGB conversion. A scale control unit generates reference and

gate signals for scaling of the processed video, with the scaling

ratio in the horizontal and vertical directions being estimated

and used to control the decimation and vertical filtering. Scaled

data are then formatted to one of the VRAM port formats

before being passed to the FIFO output register.

BRS (Binary Ratio Scaling)

■Horizontal scaling by pixel dropping and averaging

■Vertical scaling using line dropping (or line pairs)

This simple pixel and line dropping core performs simple scaling

down to arbitrary-sized windows. It has very little filtering and is

intended only for basic applications. An accumulator, controlled

by attenuators to keep pixel values from overflowing, is used to

filter the data as it is being scaled down. After scaling, a pixel

formatter organizes information from the scaler based on bit-

depth and colour space and places pixel information in the right

byte lanes, sizing them to the required output format. Philips

’

SAA7146 PCI bridge IC also has video window occlusion using

a software clip mask.

Only dedicated scalers are described in this section: other devices

with scaling functions are described under other headings. Refer

to table on page 4-9.

DESKTOP VIDEO DIGITAL VIDEO SCALERS

4-9

Multimedia PC

DESKTOP VIDEO DIGITAL VIDEO SCALERS

Table 2: Philips ICs with scaling functions

DEDICATED SCALERS PCI BRIDGE/SCALER DECODER/SCALERS

VIDEO & MEMORY CONTROLLER

SAA7186 SAA7140A/B SAA7146 SAA7196 SAA7112 SAA7195A (VMC)

Scaling type 2-D scaling HPS HPS/BRS 2-D scaling HPS BRS

Maximum window

size 1023 2047 4095 1023 2047 1023

Horizontal upscaling

(zoom) No Yes Yes No Yes (2×)No

Scaled output formats

RGB 15-bit (5-5-5+ α) 15-bit (5-5-5+ α) 8-bit (3-3-2) pseudo CLUT 15-bit (5-5-5+ α) – 15-bit (5-5-5+ α)

24-bit (8-8-8+ α) 24-bit (8-8-8+ α) 15-bit (5-5-5+ α) 24-bit (8-8-8+ α) 16-bit

15-bit (5-5-5) with dither 24-bit (8-8-8+ α)

16-bit (5-6-5)

24-bit (8-8-8+ α)

CCIR – – 656 8-bit – – –

YUV 16-bit 16-bit 4:2:2 4:4:4 24-bit 16-bit 4:2:2 16-bit 4:2:2 24-bit 4:4:4

16:2:0 18 bit Indeo 12-bit 4:1:1 16-bit 4:2:2

4:2:2 16-bit 12-bit 4:1:1

4:1:1 12-bit 8-bit 2:1:1

4:2:0 6-bit MPEG

Other 8-bit mono 8-bit mono 8-bit mono 8-bit mono 8-bit CCIR-656 –

8-bit luminance only

FIFO register 16 word 16 word 3 × 128 D word video 16 word 32 word video 160 pixels, 24-bit

16 word decoded VBI

Chroma Key

(α generation) Yes Yes Yes Yes No Yes

Anti-gamma corr. Yes Yes Yes Yes No No

Expansion port No Yes Dual DEBI Yes Yes No

Refer to page 4-10 4-11 4-18 4-7 4-5 4-31

4-10

Multimedia PC

Digital Video Scaler (DVS)

■2-D data processing improves signal quality and

compression of scaled video data

■16-bit YUV input data buffer

■Interlaced and non-interlaced video processing and

field control

■Line memories in Y and UV paths store two lines

■Vertical sync. processing by scale control circuit

■Full picture non-scaled mode

■Binary or two’s-complement UV input and output

data

■Switchable RGB matrix and anti-gamma ROMs

■TTL-compatible inputs and outputs

■Outputs 5- and 8-bit RGB, 8-bit YUV or 8-bit

monochrome signals

The SAA7186 scaler accepts 16-bit YUV data in 4:2:2 format

from a number of different multistandard digital video decoders

or other similar sources. This is then converted into a unique

internal two’s-complement data stream for horizontal and verti-

cal filtering and scaling using the 2-D scaling block described in

the overview (on page 4-9). Sequential input data is limited to

768 active pixels per line if the vertical filter is active. Specific

reference signals support easy memory interfacing.

QUICK REFERENCE DATA

Power supply 5 V

Total supply current (max.) 180 mA

Total power dissipation (max.) 1 W

Package QFP100 (SOT317)

Datasheet Handbook IC22

SAA7186

DESKTOP VIDEO DIGITAL VIDEO SCALERS

SAA7186

SCALE CONTROL

I C

CONTROL

VERTICAL FILTER

INTERPOLATOR

VRO (31 to 0);

MSC201

INPUT

DATA

BUFFER

LUMINANCE

DECIMATION

FILTER

CHROMA

DECIMATION

FILTER

ARITHMETIC

LINE

MEMORY

(2x8x768)

VERTICAL FILTER

ARITHMETIC

LINE

MEMORY

(2x8x768)

RGB

MATRIX

FOLLOWED

ANTI-GAMMA

ROMs

CHROMA

KEYER

OUTPUT

FORMATTER

OUTPUT

FIFO

2CLOCK

GENERATION

SDA

SCL

IICSA

CREF

RESN

UVIN

(7-0)

YIN

(7-0)

VLCK

VOEN

BTST

INCADR

HFL

HREF

32-bit VRAM

port output

RGB or YUV

controls

status

LNQ

HREFD

LLC

4-11

Multimedia PC

High Performance Scaler (HPS)

■2-D phase-correct interpolation delivers excellent

signal quality, especially on compressed data

■DMSD (16-bit YUV input) port, with second

bi-directional full duplex expansion port (D1) or

16-bit YUV I/O port

■Discontinuous data streams supported

■Switching between two data sources in two fields

■BCS control on scaled outputs

■YUV to RGB conversion including anti-gamma

correction

■Range of YUV/RGB outputs, configurable for 32-,

24-, 16- or 8-bit video data

The SAA7140A is a high performance scaler able both to scale

down video pictures to arbitrary-sized windows and upscale hor-

izontally. It can also switch between different processing and

scaling functions on two different video fields, from separate

sources, making it ideal for applications such as PC-based video

conferencing, with a main picture and a vanity picture. The ‘B’

SAA7140A/B

MSB808

DATA

FORMATTER/

REFORMATTER

AND

REFERENCE

SIGNAL

GENERATION

reference

ACQUI-

SITION

PXO

YIN

(7 to 0)

UVIN

(7 to 0)

CREF

HREF

LLC

DMSD

port BCS

CONTROL

VHORIZ.

PRE-

SCALING

LINE

MEMORY

CONTROL

ARITHMETIC

SCALING UNIT

VERTICAL PROCESSING

HORIZ.

FINE

SCALING

EXPANSION - PORT - INTERFACE

OUTPUT FORMATTER

OUTPUT FIFO REGISTER

VRO

(31 to 0)

HGTV

VSYV

FLDV

PXQV

INCADR

VRAM

port

CSM

DITHERING

Y-CORRECTION

VCLK VOEN

I2C CONTROL

PORT (3 to 0)

SCL

SDA

IICSA

RESN

control

status

VIDH

(7 to 0) VIDL

(7 to 0) LLCIO PXCIO HIO VIO FDIOVINHINPXCINLLCIN

SAA7140

CLK

QUICK REFERENCE DATA

Power supply 5 V (3.3 V for ‘B’ variant)

Total supply current t.b.f.

Total power dissipation (max.) 750 mW

Package LQFP128 (SOT425-1)

Datasheet (12NC) 9397 750 00984

DESKTOP VIDEO DIGITAL VIDEO SCALERS

variant is a 3.3 V low-power version incorporating I2C control-

lable power saving modes.

The input data stream is formatted according to an internal data

representation, depending on which port is selected. If the bi-

directional port is used, it is possible to field switch between

input ports. Two independent programming sets can be loaded

simultaneously, allowing separate scaling and processing func-

tions on two different signals simultaneously. Before scaling, the

data is passed through the BCS control. It uses Philips High

Performance Scaler core described in the overview on page 4-9.

4-12

Multimedia PC

DESKTOP VIDEO DIGITAL VIDEO ENCODERS

All Philips encoders offer:

■Encoding to PAL and NTSC standards with

SECAM versions available

■13.5 MHz system pixel frequency with 8-bit

resolution

■Controlled rise/fall times of output sync. and

blanking

■Compatible with DIG.TV2 chip family

Philips offers one of the most extensive ranges of Digital Video

ENcoders (DENCs) currently available, offering a variety of

combinations of inputs, outputs, size and functionality to suit all

applications. Various chips are CCIR-601, square pixel or dual

mode compatible and all accept CCIR-656 (MPEG) input data

streams. Some decode PAL and NTSC with full multistandard

versions available, and a number offer RGB outputs. One IC

offers external genlock to lock encoding to an external source.

Most members of the family come in two versions: one with the

Macrovision ‘Pay-per-view’ copy protection system (for which a

licence is required) and one with the system blocked, for which

no licence is required.

The basic encoder function consists of subcarrier generation and

colour modulation as well as the insertion of user-programmable

H/V sync. pulses, with signal filtering according to RS-170-A

and CCIR-624 standards. Luminance processing includes gain

and offset adjustment with a programmable black level.

Chrominance processing includes separate U and V gain adjust-

ment and colour burst insertion, modulation with the subcarrier

and a programmable subcarrier frequency. Both interlaced and

non-interlaced operation is possible for all standards. Sync/clock

generation and D/A conversion are included on-chip. The high

feature encoders output CVBS, Y/C and RGB simultaneously,

in line with the latest SCART standards.

Philips digital video encoders

SAA7124/25 SAA7182/83 SAA7182A/83A SAA7184/85B SAA7187 SAA7188A/85 SAA7199B

CCIR/Square pixel CCIR CCIR CCIR CCIR SQP CCIR CCIR/SQP

Supports SECAM No Yes Yes No No No No

Input formats

YUV – 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:2:2 16-bit 4:4:4 24-bit 4:2:2 16-bit

4:2:216-bit 4:4:4 24-bit

CCIR 656 8-bit 656 8-bit 656 8-bit 656 8-bit 656 8-bit 656 8-bit –

RGB – – – – – – 24-bit

Macrovision protection 6.1/ – – /6.1 – /6.1 6.1/ – – 3/ – –

Simultaneous outputs CVBS, Y/C, CVBS, Y/C, CVBS, Y/C CVBS & Y/C CVBS & Y/C CVBS & Y/C CVBS & Y/C

YUV & RGB & RGB & RGB

Int./Ext. analog RGB muxNo No Yes No No No No

Closed caption Yes Yes Yes Yes Yes Yes No

Teletext No Yes Yes No No No No

OSD No Yes Yes Yes Yes Yes No

Colour comb filter No No No Yes Yes Yes No

Colour bar generator Yes Yes Yes Yes Yes Yes No

Genlock Advanced Advanced Advanced Advanced Remote Remote On-chip

remote remote remote remote

I2C interface Yes Yes Yes Yes Yes Yes Yes

Microcontroller interfaceNo No No Yes Yes Yes Yes

Refer to page 4-15 4-14 4-13 4-16 4-16 4-16 4-17

4-13

Multimedia PC

DESKTOP VIDEO DIGITAL VIDEO ENCODERS

MSB793 - 1

RCV1

RCV2

TTXRQ

CREF

XTAL

XTALI LLC

SYNC/CLOCK

clock & timing

CDIR

SECAM

PROCESSOR

OUTPUT

INTERFACE

ENCODER

CbCr

DATA

MANAGER

I2C-INTERFACE

RESN SCL

SDA SA

R G B - PROCESSOR

I2C-control

I2C-controlI2C-controlI2C-control

I2C-control I2C-control

I2C-control

CbCr

VrefH VDDA

CUR

CVBS

TESTB

VSSA

VrefL

Rout

Bout

Gout

Gin

Bin

Rin

VrefH VDDA

CUR

DP(7:0)

MP(7:0)

OVL(2:0)

KEY

TTX

SAA7183A

QUICK REFERENCE DATA

Power supply 3.3 V/5 V

Digital supply current 3.3 V t.b.f.

5 V t.b.f.

Analog supply current t.b.f.

LF integral linearity error ±2 LSB

LF differential linearity error ±1 LSB

Package PLCC84 (SOT189)

QFP80 (SOT318)

Datasheet Contact Philips

SAA7182A/83A

Encoder EURO-DENC2

All SAA7182/83 features, plus:

■Monolithic 3.3 V CMOS device with 5 V input

stages

■On-chip analog multiplexing between internal and

external RGB signals

■Line 23 Wide Screen Signalling Encoding

■RGB output level adjustable by 3 dB

(CANAL+ requirement)

■RGB matrix bypass for analog YUV output

(BETACAM)

These ‘A’ variants of the SAA7182/83 (see next page) incorpo-

rate the same functionality, but also include an on-chip RGB

multiplexer which can mix RGB from an external source with

internal RGB signals. They also have the capability of loading

Wide Screen Signalling data via the I2C-bus and inserting it into

Line-23 of 50 Hz systems.

4-14

Multimedia PC

DESKTOP VIDEO DIGITAL VIDEO ENCODERS

SAA7182/83

Encoder EURO-DENC

■Full multistandard digital decoder

■Accepts 8-bit CCIR-656 with 720 pixels/line or

16-bit YUV input

■Data are interpolated to 27 MHz, providing 10-bit

resolution for CVBS, Y and C data

■9-bit resolution for RGB data

■On-chip YUV to RGB matrix

■Fast 400 kHz I2C-bus control port

■Operates in both master and slave modes

■Three, 10-bit DACs for CVBS and YUV; three 9-bit

DACs for RGB

The SAA7182/83 EURO-DENC encodes digital YUV video

data either to one of the main broadcast standards or to an S-

Video or RGB signal, with all signals being available simultane-

ously. The SAA7183 has the Macrovision Level 6.1 Pay-per-

View copy protection system embedded on chip; this system is

blocked on the SAA7182, so no licence is required to use this

IC.

QUICK REFERENCE DATA

Power supply 5 V

Digital supply current 220 mA

Analog supply current 90 mA

LF integral linearity error ±2 LSB

LF differential linearity error ±1 LSB

Package PLCC84 (SOT189)

Datasheet (12NC) 9397 750 00324

4-15

Multimedia PC

SAA7124/5

Encoder ECO-DENC

■Encodes NTSC or PAL signals

■Accepts 8-bit CCIR-656 with 720 pixels/line

■On-chip YUV to RGB matrix

■RGB matrix can be bypassed to provide D/A-

converted CbYCr signals

■One 10-bit DAC for CVBS signals and three 9-bit

DACs for separate R, G, and B signals (SCART

applications)

■Simultaneous CVBS and RGB outputs

■Closed caption encoding

The SAA7124/5 ECO-DENC is a low cost (ECOnomy) version

of the EURO-DENC (SAA7182/83), without SECAM encod-

ing but available in a smaller package. It encodes NTSC or PAL

digital luminance and colour difference signals to a CVBS signal

and an RGB signal, or to an S-Video and two CVBS outputs. As

with the EURO-DENC encoders, the SAA7124 incorporates

the Macrovision Pay-per-view copy protection system level 6.1,

which is blocked on the SAA7125. Closed caption encoding is

available but there is no teletext function.

QUICK REFERENCE DATA

Power supply 5 V

Digital supply current 150 mA

Analog supply current 60 mA

LF integral linearity error ±2 LSB

LF differential linearity error ±1 LSB

Package PLCC84 (SOT189)

QFP80 (SOT318-2)

LQFP64 (SOT314)

Datasheet Contact Philips

DESKTOP VIDEO DIGITAL VIDEO ENCODERS

4-16 Multimedia PC

DESKTOP VIDEO DIGITAL VIDEO ENCODERS

DENC2 family of encoders

■Encodes NTSC or PAL signals

■8-bit CCIR-656 (D1) and 16-bit YUV inputs

■Fast MPU parallel and I2C-bus control ports

■Outputs CVBS and S-Video signals simultaneously

■Three, 10-bit DACs running at 27 MHz

The SAA7182/3 and SAA7124/5 ICs described in pages 4-13 to

4-15 are enhanced versions of an earlier family of encoders,

which is still supported. Offering the same basic functionality as

the SAA7182/3 family, they are not as highly featured, including

only PAL and NTSC encoding for applications where SECAM

is not required, but come in the smaller PLCC68 package.

SAA7184/85B encoder DENC-M6. A pin-compatible replace-

ment for the SAA7188A DENC2, the SAA7184 offers the latest

version of the Macrovision Pay-per-View copy protection system

CONTROL

INTERFACE

internal control bus

clock timing signals

SYNC

CLK

RTCI

VrefH

VDDA

SAA7184

MP7 to MP0

VP0 to VP7

SEL_MPU

CSN/SA

DP0 to DP7

KEY

SEL_ED

OVL0 to OVL2

RCM1

RCM2

RWN/SCL

A0/SDA

DTACKN

RESN

XTALI

XTAL0

LLC

CREF

CDIR

RCV1

RCV2

CVBS

CUR

VSSA

VrefL

MSB913 - 1

DATA

MANAGER ENCODER OUTPUT

INTERFACE

QUICK REFERENCE DATA SAA7184/85B SAA7187 SAA7188A/85

Power supply 5 V 5 V 5 V

Digital supply current 140 mA 175 mA 140 mA

Analog supply current 50 mA 50 mA 50 mA

LF integral linearity error ± 2 LSB ± 2 LSB ± 2 LSB

LF differential linearity error ± 1 LSB ± 1 LSB ± 1 LSB

Package PLCC68 (SOT188) PLCC68 (SOT188) PLCC68 (SOT188)

Datasheet (12NC) 9397 750 00928 9397 750 00325 9397 750 00944

I2C-bus interface Yes Yes Yes

(rev. 6.1), while the SAA7185B is identical to the SAA7184 but

with the Macrovision copy protection system blocked.

SAA7188A/85 encoder DENC2-M. The original member of the

DENC2 family, this encoder accepts a range of signals, includ-

ing decoded MPEG-1 video data streams. It has the

Macrovision Pay-per-View system, level 3. The SAA7185 is

identical to the SAA7188A but with the Macrovision copy pro-

tection system blocked.

SAA7187 encoder DENC-SQ. A square pixel version of the

SAA7188A, offering the same functionality but with no

Macrovision system. The MPEG video data port is also replaced

by a 24-bit YUV input port. It supports clock frequencies of

24.54 MHz (for 60 Hz systems) and 29.5 MHz (for 50 Hz sys-

tems) rather than the single pixel system frequency.

4-17

Multimedia PC

Encoder with genlock

■Three 8-bit signal inputs for PAL or NTSC RGB,

YUV or indexed colour signals

■Optional external GENLOCK operation with

adjustable horizontal sync. timing and subcarrier

phase

■Stable GENLOCK operation in VCR standard play-

back mode

■3 ×9-bit resolution DACs

■Three 256 ×8 CLUTs for gamma correction

■Multi-purpose key for real-time format switching

■TTL-compatible inputs

■Autonomous internal blanking

■Optional still video capture

The SAA7199B encodes digital baseband colour/video data into

analog CVBS and Y/C signals. Four selectable modes are avail-

able: a stand alone mode with horizontal and vertical timings

internally generated; a slave mode using external horizontal and

vertical timing, with optional real-time information; GEN-

LOCK mode (which requires a clock reference from the

SAA7197 external clock generator); and a test mode. Pixel clock

and data are line-locked to the horizontal scanning frequency of

the video signal. An on-chip conversion matrix provides CCIR-

601 code-compatible transcoding of RGB and YUV data.

SAA7199B

DESKTOP VIDEO DIGITAL VIDEO ENCODERS

SDA

SCL

SAA7199B

I C-BUS

CONTROL

STATUS

TRIPLE

DACs

OUTPUT

BUFFERS

CREF

LLC

XTALI

XTALO

VSSA

VDDA1

CVBS0(7 to 0)

HCL HSY HSN

LFCO

MSC200

+5 V

GPSW

CONTROL INTERFACE SYNC PROCESSING CLOCK INTERFACE

SLT

VSN/CSYN CB

PIXCLK CLKIN

CLKO

CLKSEL

RESET CS

R/W

A0 A1

CLUTS

3×

256 × 8

INPUT

INTERFACE ENCODER

MATRIX

D(7 to 0)

internal control bus

CVBS

outputs to

monitor/TV

CUR to VDDA4

+5 V

DDD1 DDD3

to V KEY

PD2(7 to 0)(1)

PD1(7 to 0)(1)

PD3(7 to 0)(1)

(digital red)

(digital green)

(digital blue)

LDV VrefL

VrefH

3 × 8-bit input data

I C-bus

MPK

to/from microcontroller

RTCI

QUICK REFERENCE DATA

Power supply 5 V

Total supply current 220 mA

LF integral linearity error ±1 LSB

LF differential linearity error ± 0.5 LSB

Package PLCC84 (SOT189CG)

Datasheet Handbook IC22

4-18 Multimedia PC

The PCI-bus is virtually the de-facto replacement for the old

ISA-bus. Its high speed and bandwidth and its operation as a

multi-speed bus, together with its burst mode, make it ideal in

desktop video applications where large volumes of data have to

DESKTOP VIDEO PCI BRIDGES

SAA7146

Multimedia bridge with scaler and PCI

■Master read/write and slave PCI 2.1 interface

■DMA access for audio and video data onto the

PCI bus

■Support for full bandwidth high speed PCI

transfers and PCI burst mode

■RPS (Register Programming Sequencer), allowing

loading of pre-defined programming sets under

I2C-bus control

■Dual D1 interface supports bi-directional, full

duplex, two channel, full D1 (CCIR-656) standards

■3 ×128 D word Video FIFO with overflow

detection and parity check

■Scaling functions include display of arbitrary-sized

windows and electronic zooming, and conversion

between sample schemes

■2-D phase-correct interpolation delivers excellent

signal quality, especially on compressed data (HPS)

■Bi-directional Binary Ratio Scaler (BRS) can con-

vert between full-size video (50 or 60 Hz) and

CIF/QCIF

■Processing of 4095 active samples per line and

active lines per frame

■Programmable RGB and YUV outputs include

packed and planar formats for local display and

compression

■Virtual memory management unit (4 MB per DMA

channel)

■Brightness, contrast and saturation control and

Chroma Key generation

■On-chip colour space matrix, dithering and gamma

correction

■Supports rectangle overlay and bit mask clipping

One of Philips’ most integrated and highly featured ICs, the

SAA7146 interfaces desktop video functions to the PCI bus and

includes a range of interfaces to provide flexible connection to a

large number of video and audio ICs. It also includes internal

Binary Ratio Scaling (BRS) and two-dimensional High

Performance Scaling (HPS) functions similar to those in the

SAA7140A/B, so is ideal for many applications requiring real-

time desktop video processing. For more information on the

BRS or HPS scaling functions, refer to the ‘Scalers’ section (page

4-8).

The SAA7146 includes a YUV 4:2:2 video input port which can

be configured in two ways. Firstly, it can accept 8-bit time-mul-

tiplexed bi-directional full duplex YUV data in accordance with

CCIR-656 standards (D1 video), with sync signals encoded in

the input data stream or brought in on separate sync. inputs.

These sync pins can be used as outputs when external synchro-

nization to the input source is required. Secondly, it can behave

as a 16-bit port, for backwards compatibility with the DMSD2

standard, in which Y luminance data are on one 8-bit port and

the U and V chrominance data are multiplexed on a second

8-bit port. This DSMD2 mode is compatible with other 16-bit

decoder devices in the DTV chipset such as the SAA7110A.

After scaling, the signal can be output in various programmable

RGB and YUV formats and can be dithered for low bit-rate for-

mats. A second YUV video channel bypasses the HPS and con-

nects the real-time video interface with the PCI interface

through FIFO and DMA control. This video bypass channel

offers the same BRS features as the SAA7146. VBI data and test

signals can be also be bypassed without processing. The FIFO

has overflow detection and ‘graceful’ recovery.

QUICK REFERENCE DATA

Power supply Core 5 V

I/O pad 3.3 V

Total supply current t.b.f.

PCI clock frequency 33 MHz

I2S clock frequency 12.5 MHz

Total power dissipation (max.) t.b.f.

Package TQFP208 (SOT316A1)

Datasheet Contact Philips

be quickly moved around the PC for real-time processing and

display. Philips PCI bridge IC includes scaling functions and a

range of ports for interfacing flexibility.

4-19

Multimedia PC

MSB799

PCI local bus

HIGH

PERFORMANCE

2-DIMENSIONAL

SCALER

DATA

EXPANSION

BUS

INTERFACE

I2C

MASTER

PCI interface, FIFOs

and DMA controls

BINARY

RATIO

SCALER

REAL TIME VIDEO INTERFACE

dual D1 or 16bit YUV

SERIAL I2S

AUDIO

INTERFACE I2S

I/O

I2C

SAA7146

The DEBI (Data Expansion Bus Interface) has parallel modes

for system set-up and programming of peripheral multimedia

devices further down the chain. It is also optimized to transport

compressed MPEG/JPEG data to and from peripheral ICs to

the PCI system. The DEBI is connected to the PCI by single

instruction direct access and via a data DMA channel for

streaming data.

Both PCI master and slave modes support 32-bit transfers at a

maximum clock rate of 33 MHz. To increase bus performance,

they can handle fast back-to-back transfers. Video signal flow to

and from the PCI bus is controlled by three video DMA chan-

nels, with the channel definition supporting the typical video

data structure (hierarchy) of pixels, lines, fields and frames. In

slave mode, access only to the programmable registers and con-

figuration space is provided. Audio signal flow is controlled by

four audio DMA channels. The digital audio serial interface is

I2S compatible and supports the connection of up to four

devices.

DESKTOP VIDEO PCI BRIDGES

4-20 Multimedia PC

DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS

All Philips ADCs offer:

■Sampling rates of at least 32 MHz

■Binary or two’s-complement 3-state TTL outputs

■TTL-compatible digital inputs and outputs

■High SNR ratio over large analog input frequency

range

■Internal reference voltage regulator

■No sample-and-hold circuit required

PHILIPS VIDEO ADCSTDA8707 TDA8708A/B TDA8709A TDA8758

ADC resolution 6-bit 8-bit 8-bit 8-bit

Variable pre-amplifier No No Yes No

AGC No Yes No Yes*

Clamp functions Yes Yes Yes Yes

Input selector circuit No Yes No Yes

* only on luminance channel

TDA8707

Triple RGB 6-bit ADC interface

■Triple ADC with 6-bit resolution

■Sampling rate up to 35 MHz

■Internal clamping functions

■Low power dissipation

The TDA8707 CMOS low power ADC converts RGB analog

inputs into 6-bit binary coded digital words. It incorporates

three A/D converters using the full-flash method; each has an

internal clamping circuit. Internal buffers are provided to drive

the A/D converter inputs.

MSC207

CLAMPING

CIRCUIT 6-BIT

ADC

BUFFER

CLAMPING

CIRCUIT 6-BIT

ADC

BUFFER

CLAMPING

CIRCUIT 6-BIT

ADC

BUFFER

TDA8707

INR

ING

INB

CREFH

CREFL

SLT

B0 to B5

G0 to G5

R0 to R5

CLREF CLP CLK

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 60 mA

Digital supply current 5 mA

Typical DC integral linear error 0.35 LSB

Typical power dissipation 335 mW

Package QFP44 (SOT307-2)

Datasheet (12NC) 9397 750 00605

Many ICs in the Philips DeskTop Video chipset include on-

board ADCs. Philips also has available a number of specialized

stand-alone ADCs which include a range of integrated signal

conditioning functions.

4-21

Multimedia PC

DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS

Video analog input interface

■Clamp and AGC functions for CVBS and Y signals

■Input selector circuit

■White peak control

The TDA8708A/B provides a simple interface for decoding

video signals and can be configured to operate in two modes.

Mode 1, which enables fast recovery of the sync pulses in the

decoder circuit, is used when video signals are weak and it only

adjusts the AGC amplifier gain roughly. If the sync period or

rear porch pulses become indistinct, the TDA8708 automatic-

ally switches to Mode 2, where the digital output of the ADC is

compared to the internal digital reference levels. Both chips pro-

vide white peak control in Mode 1 and the ‘A’ variant also has

this function in Mode 2.

TDA8708A/B

MSC191

TTL

OUTPUTS

output format/

chip enable

(3-state input)

D0 to D7

8 - bit

ADC

AMP.

VIDEO

AMPLIFIER

INPUT

SELECTOR

video input

selection bit 0 video input

selection bit 1

analog

voltage

output ADC

input clock

input decoupling

input TTL outputs

video input 0

video input 1

video input 2

clamp capacitor

connection

AGC capacitor

connection

AGC &

CLAMP

LOGIC

MODE

SELECTION

PEAK LEVEL

DIGITAL COMPARATOR

sync level

sync pulse black level

sync pulse

VCCO (+ 5 V)

TDA8708A/B

BLACK LEVEL

DIGITAL COMPARATOR

SYNC LEVEL

DIGITAL COMPARATOR

peak level current

resistor input

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 37 mA

Digital supply current 24 mA

Typical DC integral linear error ±1 LSB

SNR (effective bits at 4.43 MHz) 7.5

Total power dissipation 365 mW

Package TDA8708A/B DIP28 (SOT117-1)

TDA8708AT/BTSO28L (SOT136-1)

Datasheet (12NC) TDA8708A 9397 734 20011

Datasheet (12NC) TDA8708B 9397 734 80011

4-22 Multimedia PC

Video analog input interface

■Low level AC clock inputs and outputs

■Three selectable video inputs

■Variable gain pre-amplifier with clamp function

An analog input interface for video signal processing, the

TDA8709A includes an input selector to choose one out of

three video signals. A video pre-amplifier has external gain con-

trol and a clamp function which can be switched between digital

‘16’ for RGB signals and digital ‘128’ for chrominance or colour

difference signals.

TDA8709A

MSC190

TTL

OUTPUTS

fast output

chip enable

D0 to D7

output

format

selection

8 - bit

ADC

AMP.

VIDEO

AMPLIFIER

INPUT

SELECTOR

video input

selection bit 0 video input

selection bit 1

analog

voltage

output ADC

input clock

input decoupling

input TTL outputs V (+ 5 V)

video input 0

video input 1

video input 2

clamp capacitor

connection

gain control

input

CLAMP

LOGIC

CLAMP LEVEL "16"

DIGITAL COMPARATOR

CLAMP LEVEL "128"

DIGITAL COMPARATOR

clamp

level

selection

clamp

pulse

CCO

TDA8709A

DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 40 mA

Digital supply current 24 mA

Typical DC integral linear error ±1 LSB

SNR (effective bits at 4.43 MHz) 7.5

Total power dissipation 380 mW

Package TDA8709A DIP28 (SOT117-1)

TDA8709AT SO28L (SOT136-1)

Datasheet (12NC) 9397 734 60011

4-23

Multimedia PC

TDA8758

MSC208

TDA8758

CLAMP

LEVEL 128 ADC

INPUT

SELECTOR

COMPARATOR

TTL

TIMING

GENERATOR

COMPARATORS

ADC TTL

AGC &

CLAMP 64

C7 to C0

Y7 to Y0

OFC

ANOUTC

CLK

CHROM2

CHROM1

SEL2

CVBS3

Y2/CVBS2

Y1/CVBS1

SEL1 PWE ANOUTY

GATE A

GATE B

OFY

CCLPC

CCLPY CAGC

DESKTOP VIDEO VIDEO ANALOG-TO-DIGITAL CONVERTERS

Low power A/D interface

■Peak white enable input

■Input selector circuit for 1-of-5 video inputs

■Clamp and AGC functions for Y/CVBS channel

■Clamp function for C channel

The TDA8758 is a low power, dual ADC interface providing a

simple interface between CVBS or S-Video signals and a digital

colour decoder, processing either 1-of-2 Y/C or 1-of-3 CVBS

input signals. All analog signals are digitally clamped with a fast

pre-charge on clamp and AGC for start-up. An ADC interface is

provided on the Y/CVBS channel.

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 55 mA

Digital supply current 24 mA

Typical DC integral linear error ±0.75 LSB

Crosstalk between Y and C channels –56 dB

SNR (effective bits at 4.43 MHz) 7.0 (x2)

Total power dissipation 485 mW

Package LQFP48 (SOT313-2)

Datasheet (12NC) 9397 750 00606

4-24 Multimedia PC

Many ICs in the Philips DeskTop Video chipset include on-

board DACs - for example, all video encoders have 9- or 10-bit

DACs on board. In addition to a number of dedicated video

DACs, Philips also offers a highly integrated mixer/DA proces-

sor which mixes encoded and external RGB signals, and a video

enhancement processor/converter.

8-bit video DACs

■Sampling rate up to 30 MHz (TDA8702) or

50 MHz (TDA8712)

■Two complementary analog outputs

■Internal input resistor

■Internal 75 Ωoutput load

■Internal reference voltage regulator

■No deglitching circuit required

TDA8702/TDA8712

TDA8702

TDA8712

MSC209

REFERENCE

CURRENT

GENERATOR

CURRENT

SWITCHES

CURRENT

VOLTAGE

CONVERSION

CURRENT

GENERATORS

DATA

LATCHES

DATA

INPUT

INTERFACE

data (D7 - D0)

(TTL)

CLK

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 26 mA

Digital supply current 23 mA

DC integral non-linearity ±0.5 LSB

DC differential non-linearity ±0.5 LSB

Total power dissipation 250 mW

Package TDA8702/TDA8712 DIL16(SOT38)

TDA8702T/TDA8712T SO16 (SOT162)

Datasheet TDA8702 Handbooks IC22, IC02

TDA8712 9397 734 70011

DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS

PHILIPS VIDEO DACSTDA8702 TDA8712 TDA8771A TDA8772(A)H(3/8) TDA8775G

Sampling rate 30 MHz 50 MHz 35 MHz 35 MHz/85 MHz 50 MHz

TTL-compatible inputs Yes Yes Yes Yes Yes

Resolution 8-bit 8-bit 8-bit 8-bit 10-bit

4-25

Multimedia PC

DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS

TDA8771A

MSC155 - 1

RESISTOR

STRING

MSB

DECODER

LSB

DECODER

RESISTOR

STRING

MSB

DECODER

LSB

DECODER

RESISTOR

STRING

MSB

DECODER

LSB

DECODER

BANDGAP

REFERENCE

clock input

reference

current input

RED

analog output

GREEN

analog output

BLUE

analog output

reference voltage

decoupling input

BLUE

digital inputs

(bits B4 to B7)

BLUE

digital inputs

(bits B0 to B3)

GREEN

digital inputs

(bits G4 to G7)

GREEN

digital inputs

(bits G0 to G3)

RED

digital inputs

(bits R4 to R7)

RED

digital inputs

(bits R0 to R3)

TDA8771A

(I )

REF

(V )

REF

Triple 8-bit video DAC

■Triple DAC with sampling rate up to 35 MHz

■Large output voltage range

■1 kΩoutput load

■Internal reference voltage regulator

■No deglitching circuit required

The three DACs in the TDA8771A are based on resistor string

architecture with integrated output buffers, with the voltage out-

put range determined by an internal reference source.

QUICK REFERENCE DATA

Power supply 5 V

Total analog supply current 33 mA

Total digital supply current 7 mA

DC integral non-linearity ±0.5 LSB

DC differential non-linearity ±0.25 LSB

Total power dissipation 200 mW

Package QFP44 (SOT307-2)

Datasheet 9397 750 00591

4-26 Multimedia PC

Triple 8-bit video DAC

■Triple DAC with sample rates up to 35 MHz or

85 MHz

■Sync. & blank control inputs

■Independent clock input for each DAC

■1 V output range with 75 Ωload

■Internal reference voltage regulator

■No deglitching circuit required

These triple 8-bit DACs convert digital input signals to analog

output signals with conversion rates up to 35 MHz (for the

‘H/3’ variants) and 85 MHz (for the ‘H/8’ variants). The ‘A’

versions have a blank control input on the green channel only.

The three DACs in the TDA8772 are based on resistor string

architecture with integrated output buffers, with the voltage out-

put range determined by an internal reference source.

TDA8772(A)H(3/8)

MSC159 - 1

RESISTOR

STRING

MSB

DECODER

LSB

DECODER

RESISTOR

STRING

MSB

DECODER

LSB

DECODER

RESISTOR

STRING

MSB

DECODER

LSB

DECODER

BANDGAP

REFERENCE

CONTROL

reference

current input

RED

analog output

GREEN

analog output

BLUE

analog output

reference voltage

decoupling input

BLANK

control input

SYNC

control input

BLUE

digital inputs

(bits B4 to B7)

BLUE

digital inputs

(bits B0 to B3)

GREEN

digital inputs

(

bits G4 to G7)

GREEN

digital inputs

(bits G0 to G3)

RED

digital inputs

(bits R4 to R7)

RED

digital inputs

(bits R0 to R3)

TDA8772A RED

clock input

GREEN

clock input

BLUE

clock input

reference current

input for internal

reference

(V )

REF

(I )

REFA

(I )

REFB

QUICK REFERENCE DATA TDA8772(A)H/3 TDA8772(A)H/8

Power supply 5 V 5 V

Total analog supply current 65 mA 65 mA

Total digital supply current 7 mA 16 mA

DC integral non-linearity ±0.5 LSB ±0.75 LSB

DC differential non-linearity ±0.25 LSB ±0.5 LSB

Maximum clock frequency 35 MHz 85 MHz

Total power dissipation 260 mW 310 mW

Package QFP44 (SOT307B) QFP44 (SOT307B)

Datasheet (12NC) 9397 750 00029 9397 750 00029

DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS

4-27

Multimedia PC

Triple 10-bit video DAC

■10-bit resolution

■Sampling rate up to 50 MHz (normal mode, 37.5 Ω

load) or 35 MHz (low power mode, 150 Ωload)

■Triple DACs based on internal current source

architecture with selector for normal or low-

power mode

■0.66 V output range

■Sync. & blank control inputs

■Internal reference voltage regulator

■No deglitching circuit required

DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS

TDA8775G

MSC215

CURRENT

SOURCE

MSB

DECODER

LSB

DECODER

CURRENT

REFERENCE

CURRENT

SOURCE

MSB

DECODER

LSB

DECODER

CURRENT

SOURCE

MSB

DECODER

LSB

DECODER

CONTROL

OUTB

OUTG

OUTR

CLK

SLT reference current

decoupling input

(Iref)

red

digital inputs

(bits R0 to R3)

red

digital inputs

(bits R4 to R9)

green

digital inputs

(bits G0 to G3)

green

digital inputs

(bits G4 to G9)

blue

digital inputs

(bits B0 to B3)

blue

digital inputs

(bits B4 to B9)

BLANK

control input

SYNC

control input

TDA8775

QUICK REFERENCE DATA

Power supply 5 V

Total analog supply current 64 mA (RL= 37.5 Ω)

16 mA (RL= 150 Ω)

Total digital supply current 15 mA (RL= 37.5 Ω)

10 mA (RL= 150 Ω)

DC integral non-linearity ±1 LSB

DC differential non-linearity ±0.5 LSB

Maximum clock frequency 50 MHz (RL= 37.5 Ω)

35 MHz (RL= 150 Ω)

Total power dissipation 385 mW (RL= 37.5 Ω)

130 mW (RL= 150 Ω)

Package LQFP48 (SOT313-2)

Datasheet (12 NC) 9397 750 01021

4-28 Multimedia PC

Video Enhancement and D/A processor

(VEDA2)

■Digital Colour Transient Improvement (DCTI)

increases colour transition sharpness

■16-bit parallel input for 4:1:1 and 4:2:2 YUV data

■Separate DACs with 9-bit resolution on Y signals

and 8-bit resolution on U and V signals

■Line-locked data clock with maximum sampling

rate of 32 MHz

■8-bit luminance and multiplexed colour difference

formats with optional 7-bit format

■Microcontroller input supports various clock and

pixel rates

■Controllable peaking of luminance signal and

coring stage with controllable threshold eliminates

noise

■Interpolation filter increases data rate in

chrominance path

■1 V output range with 75 Ωload

■No external adjustments required

SAA7165

MSC202

INTERPOLATION

FILTER

FORMATTER

DCTI

SAA7165

DATA

SWITCH

DAC 3

CUR VDDA4

PEAKING

AND

CORING

DAC 2

DAC 1

FORMATTER

TIMING

CONTROL

I2C-BUS

CONTROL TEST

CONTROL

data clock

Y7 to Y0

UV7 to

UV0

LLC

HREF

RESET

SCL

SDA

YUV-bus

I2C-bus

(R − Y)

(B − Y)

CUV

REFLUV

REFLY

DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS

QUICK REFERENCE DATA

Power supply 5 V

Total supply current t.b.f.

DC integral non-linearity ±1 LSB

DC differential non-linearity ±0.5 LSB

Total power dissipation t.b.f.

Package PLCC44 (SOT187)

Datasheet Handbook IC22

The highly integrated SAA7165 upsamples and interpolates

YUV signals before D/A conversion and includes colour tran-

sient improvement and noise reduction. The input format is

first checked to ensure the right interpolation filter is used and is

then formatted into the internal processing format.

Peaking of the Y signal compensates for several bandwidth

reductions in external pre-processing, providing increased sharp-

ness. The coring stage suppresses small high frequency signal

components generated by the bandpass gain to reduce noise dis-

turbances, with the remaining high frequency peaking compo-

nent available for weighted addition after coring.

The chrominance interpolation filter consists of various filter

stages, multiplexers and de-multiplexers, increasing the data rate

by a factor of 2 or 4. After the DCTI stage, which improves the

transition behaviour of the UV colour difference signals, the sig-

nals are D/A converted using resistor chains with low impedance

output buffers.

4-29

Multimedia PC

DESKTOP VIDEO VIDEO DIGITAL-TO-ANALOG CONVERTERS

Mixer and D/A processor (MDAC)

■Three analog mixers blend DAC output with

external RGB signals

■High speed triple 8-bit DACs

■Two’s-complement or binary offset input format

■Keying control block supports pseudo-colour, high-

colour and true-colour input modes

■YUV-RGB colour space conversion according to

CCIR-601 standard

■Voltage output amplifiers for each of the RGB

channels

This mixed-mode IC converts digital YUV video data to analog

RGB video and mixes it with external analog RGB input from

another source, usually the VGA graphics board, allowing the

display of video in a window on the PC monitor. This is an

essential function in many desktop video applications such as

video conferencing or Video-CD playback.

Input YUV information is processed through the video data

path. First the reformatter demultiplexes the various YUV for-

mats (4:1:1, 4:2:2, 2:1:1) into the standard internal data format

of 4:4:4. After digital colour space conversion from YUV to

RGB, identical triple 8-bit DACs designed with voltage-drive

architecture (one for each of the RGB channels), provide high-

speed data conversion either at 50 MHz or 100 MHz (‘A’ ver-

sion). The chip will also accept RGB 5:6:5 input passed directly

to these DACs. Mixers, controlled by the keying control block,

blend the signals with external RGB. Internal level shifters and

amplifiers match the external analog inputs with the output level

of the DACs and each final RGB output is then buffered with a

built-in voltage output amplifier, so it can be used for direct

driving of an 150 Ω load.

SAA7167(A)

Bin Gin Rin

Rout

YUV7 to

YUV0

UV7 to

UV0

SAA7167

Crefh

MSB914

RE-

FORMATTER

YUV

RGB

MATRIX

MUX

VCLK PCLK EXTKEY P7 to P0

8-BIT

DAC

(3×)

MIXER OPAMP

CLOCK

GENERATOR KEYING CONTROL

Gout

MIXER OPAMP

Bout

MIXER OPAMP

HREF

I2C-BUS

CONTROL

SDA

SCL

RESN

QUICK REFERENCE DATA

Power supply 5 V

Total supply current (Vclk= 50 MHz) 100 mA

DC integral non-linearity 1 LSB

DC differential non-linearity 1 LSB

Total power dissipation t.b.f.

Package TQFP48

Datasheet (12NC) 9397 750 00416

4-30 Multimedia PC

Digital Colour Space Converter (DCSC)

■CCIR-601 compliant conversion matrix

■Input formatter with multiplexer, Y-delay line and

Cr/Cb interpolating filters

■Gamma correction with on-board VLUTs

■Matched pipeline delay line on horizontal

reference signal

The SAA7192A DCSC is a digital matrix for transforming

16-/24-bit digital input signals into an RGB 24-bit format in

accordance with CCIR-601 recommendations. Accepting the

various input formats from a digital multistandard decoder, it

provides a constant propagation delay and has a maximum data

rate of 16 MHz. The matched pipeline delay line permits the

HREF signal to be synchronized with the video data at the out-

put.

DESKTOP VIDEO MISCELLANEOUS ICs

SAA7192A

MSC214

VIDEO

LOOK-UP

TABLES

VIDEO

LOOK-UP

TABLES

VIDEO

LOOK-UP

TABLES

MATRIX

DELAY

Cr AND Cb

FILTER

MULTIPLEXER

PIPELINE DELAY LINE

I2C-BUS RECEIVER

I2C-bus

ADDRESS

HREF_OUT

DATAOUT3

DATAOUT2

DATAOUT1

HREF

DATAIN3

DATAIN2

DATAIN1

FORMATTER

SAA7192A

QUICK REFERENCE DATA

Power supply 5 V

I2C-bus interface Yes

Total supply current 150 mA

Total power dissipation (max.) 1.5 W

Package PLCC68 (SOT18-8AA,

AGA, CGS)

Datasheet Handbook IC22

4-31

Multimedia PC

DESKTOP VIDEO MISCELLANEOUS ICs

Video and Memory Controller (VMC)

■Accepts multi-standard 15/16-bit YUV and RGB

video signals in CCIR-601/656 input video formats

■Frame grabber for image capture

■Real-time scan rate signal conversions (both inter-

laced and non-interlaced)

■Control signals for colour and chroma keying

■Decimation and interpolation filters to reduce

conversion errors

■Range of on-chip video processing functions

■Luminance and chrominance filters to adapt band-

width and data rate

■Brightness Contrast Saturation control on YUV

output bus

■Variety of YUV output formats

■Display resolution up to 1024 × 1024 pixels

Combining several functions on one chip, the SAA7195A pro-

vides signal filtering, formatting, scaling and video buffering

functions, as well as controlling video memories and providing

an interface to the PC bus.

Supporting any number of VRAMs between two and twelve, the

memory controller can handle a range of simple to high-end

applications. By using real-time transfer it can store a complete

4:2:2 format PAL field in a single VRAM bank (4 VRAMs, each

256k ×4-bit). Video processing functions include horizontal fil-

tering, a simple arbitrary downscaling compatibility using

pixel/line dropping and a continuous squeeze, zoom panning

and scrolling function. YUV output can be merged with RGB

for windowing, or encoded to CVBS or Y/C signals.

SAA7195A

MBE203

VIDEO DATA PATH (VDP):

FILTER, SCALING, VLUTs,

MATRIX CHROMA KEY

ACQUISITION

CONTROL

AD(23:01) Ctrl

PC-INTERFACE

FIFO

MUX

DISPLAY

CONTROL COLOUR

KEYING

VRAM

CONTROL

address

RAM-Ctrl

(23:01) VRAM/

DRAM

chroma key

video select

video

data

display

clock graphics

syncs

pixel

clock graphic

data

SAA7195A

VDY (7:0)

VDC (7:0)

sync signals

video clock

QUICK REFERENCE DATA

Power supply 5 V

I2C-bus interface No

Total supply current 260 mA (@ fclk = 32 MHz)

Total power dissipation (max.) 2 W

Package QFP160 (SOT322B-1)

Datasheet Contact Philips

4-32 Multimedia PC

Sync separator IC for monitors

■Positive video input signals, capacitive-coupled

■Operates with non-standard video signals

■Video amplifier with black level clamping

■Generation of composite sync slicing level at 50%

of peak sync voltage

■Generation of vertical sync slicing level at 40% of

peak sync voltage

■Vertical sync separator with double slope

integrator

■Delay time of vertical output determined by

external resistor

■Output stages for vertical and horizontal sync

DESKTOP VIDEO MISCELLANEOUS ICs

TDA4820T

COMPOSITE

SYNC

OUTPUT

220 nF

TDA4820T

COMPOSITE

SYNC

SLICING

AMPLIFIER

BLACK LEVEL

VERTICAL

SYNC

OUTPUT

VERTICAL-

SLICING &

INTEGRATION

50% PEAK

SYNC

VOLTAGE

vertical synccomposite sync

220 nF

positive

CVBS

signal

MSC198

QUICK REFERENCE DATA

Power supply 12 V

Typical supply current 8 mA

Vsync (p-p) 50 - 500 mV

Vertical sync output 10 V

Composite sync output (max.) 10 V

Total power dissipation (typ.) 150 mW

Package SO8 (SOT96A)

Datasheet Handbook IC22

4-33

Multimedia PC

4 ×4 video switch matrix

■S-Video or CVBS processing

■3-state switches for all channels

■Selectable gain for video channels

■Sub-address facility

■Auxiliary audio outputs for audio switching

■System expansion up to 7 devices (28 sources)

■Static short-circuit proof outputs

■ESD protection

Primarily designed for switching between composite video sig-

nals, four input lines allow switching between two S-Video or

four CVBS signals. Each of the four outputs can be set to a high

impedance state, permitting parallel connection to several

devices. Controlled via the I2C-bus, 3-bits of the I2C address

can be selected via sub-address input pins, providing for parallel

operation of 7 devices. Control options include clamping input

signals to their negative peak (top sync); selecting a gain factor of

1× or 2×for the output; individually connecting output to

input; setting impedance state of outputs individually; and con-

trolling two binary output data lines for switching accompany-

ing sound signals.

DESKTOP VIDEO MISCELLANEOUS ICs

TDA8540(T)

PEAK-

CLAMP

PEAK-

CLAMP

PEAK-

CLAMP/

BIAS

SUPPLY

PEAK-

CLAMP/

BIAS

DECODER

1 OF 4 DECODER

1 OF 4

SWITCH MATRIX

DRIVER

IN3

IN2

IN1

IN0

VCC

DGND

AGND

S0 S1 S2 SCL SDA

OUT3

OUT2

OUT1

OUT0

VCC(D0,1) VCC(D2,3)

I2C RECEIVER

MSC216

TDA8540

EN0 to EN3

GAIN

G0 to G3

2222

4444

CL0 to CL1

power reset

QUICK REFERENCE DATA

Power supply 8 V

Typical supply current 20 mA

Crosstalk attenuation between channels 70 dB

Total power dissipation (max.) 750 mW

Package TDA8540 DIL20 (SOT146E)

TDA8540T SO20 (SOT163A)

Datasheet Handbook IC22

4-34 Multimedia PC

Sample analog ICs

Although digital systems are the driving force behind video pro-

cessing on the desktop PC, analog systems are still dominant in

broadcast and will be for the immediate future. Philips, with

vast experience in TV and video applications, has a diverse range

of analog chips that could be used in the front-end of desktop

video applications. The following ICs are just a small selection

from this range; for more details, refer to the

‘

TV designer’s

guide’ and the ‘Satellite and terrestrial TV front-end designer’s

guide’.

DESKTOP VIDEO SAMPLE ANALOG ICs

TDA4655

MSC203

TDA4655

ACC

STANDARD

SCANNING

HUE - CTRL

SERVICE

PAL / NTSC

OSCILLATOR

DIVIDER

PLL

PULSE

PROCESSING

SANDCASTLE

DETECTOR

BANDGAP

REFERENCE

PAL

SECAM

NTSC3.5

NTSC4.4

chroma

HUE

2 fsc

– (R–Y)

– (B–Y)

SSC

PAL / SECAM

NTSC

IDENT

PAL / NTSC

DEMODULATOR

SECAM

DEMODULATOR

DEEMPHASIS

BLANKING

COLOUR-

KILLER

BUFFER

SYSTEM

CONTROL

STANDARD

SELECTION

Generic multistandard analog decoder

■Automatic recognition of broadcast standard

■No adjustments required

■Reduced external components

■Low voltage and low power dissipation

■Not all time constraints integrated (ACC, SECAM

de-emphasis)

The TDA4655 is an integrated, full multistandard analog colour

decoder with negative colour difference output signals, designed

to operate with Philips’ integrated baseband delay line

(TDA4665). An on-board PLL generates a reference clock signal

at twice the colour carrier frequency and is available to drive

external devices such as a PAL comb filter. The IC can distin-

guish both NTSC 3.5 and NTSC 4.3 colour carrier frequencies

automatically.

QUICK REFERENCE DATA

Power supply 8 V

Typical supply current 31 mA

Total power dissipation 248 mW

Package TDA4655 SDIL24 (SOT234)

TDA4655T SO24 (SOT137A)

Datasheet Handbook IC02

4-35

Multimedia PC

Baseband delay line

■Multistandard baseband delay line circuit

■Two comb filters, using switched-capacitors for

one line delay time (64 µs)

■Adjustment-free application

■No crosstalk between SECAM colour carriers

■Clamping of AC-coupled input signals

■Addition of delayed and non-delayed output signals

■NTSC comb filtering to suppress cross-colour

distortion

The TDA4665 is an integrated baseband delay line circuit with

one delay line suitable for decoders with both positive and nega-

tive colour difference signal outputs. It includes output buffer

amplifiers on-chip.

TDA4665

SANDCASTLE

DETECTOR FREQUENCY

PHASE

DETECTOR

DIVIDER

BY 192

3 MHz shifting clock

LINE

MEMORY

SIGNAL

CLAMPING SAMPLE-

AND-HOLD

6 MHz

CCO DIVIDER

BY 2

addition

stages output

buffers colour-difference

output signals

colour-difference

input signals

±(B−Y)

±(R−Y)

±(B−Y)

sandcastle

pulse input

LINE

MEMORY

TDA4665

SIGNAL

CLAMPING

pre-amplifiers

SAMPLE-

AND-HOLD LP

MSC221

DESKTOP VIDEO SAMPLE ANALOG ICs

QUICK REFERENCE DATA

Power supply (analog and digital) 5 V

Total supply current 5.9 mA

Total power dissipation 30 mW

Package TDA4665 DIL16 (SOT38-4)

TDA4665T SO16 (SOT109A)

Datasheet (12NC) 9397 750 00381

4-36 Multimedia PC

PAL/NTSC analog encoder

■Alignment free modulators for PAL and NTSC

■Chrominance processing via a range of integrated

alignment-free filters

■Operates with either internal free running

oscillator or external sub-carrier signal

■RGB and YUV input signal paths with multiplexing

for insertion of teletext/OSD

■Fast switching between RGB and YUV inputs

■Sync separator circuit and pulse shaper for on-chip

generation of timing signals

■Y + sync, C and CVBS outputs

■Signal amplitudes are correct for 75 Ω driving via

an external emitter follower

This highly integrated analog PAL/NTSC encoder converts

RGB or YUV signals to PAL or NTSC broadcast standards.

RGB signals are connected to a matrix which outputs YUV, via

clamping and line blanking circuits and if selected, the U, V

matrix output signals can be routed to low pass filters, and the Y

signal to the adder where it is combined with the sync pulse.

Signals are routed through a PAL/NTSC selection switch, as the

filter/modulator stages operate in different modes depending on

the standard. External Y and -U, -V signals can also be fed

directly to the switch and multiplexed with the generated YUV

signals. The –3 dB nominal frequency response levels for the low

pass filters are 1.35 MHz for PAL and 1.1 MHz for NTSC.

Processing of chrominance signals includes low frequency filter-

ing; then, after signal modulation, a blanker blocks the signal

during the sync period to avoid signal distortion from the con-

trol loop.

TDA8501

MGA462

TDA8501

CSYNC

LPF

BUFFER

MODULATOR

switch

MATRIX

Y U V

CVBS out

PULSE

SHAPER ADDER

ADDER

BPF

BUFFER

OSC

PAL / NTSC

notch

Y out

chroma out

(f /2)

DESKTOP VIDEO SAMPLE ANALOG ICs

QUICK REFERENCE DATA

Power supply 5 V

Typical supply current 40 mA

Chrominance crosstalk –60 dB

Total power dissipation 200 mW

Package TDA8501 DIL24 (SOT234AH2)

TDA8501T SO24 (SOT137AH1)

Datasheet Handbook IC02

4-37

Multimedia PC

SECAM analog encoder

■Alignment free integrated filters

■Reference oscillators locked to the line frequency

■RGB and YUV input signal paths with multiplexing

for insertion of teletext/OSD

■Oscillators can be crystal controlled

■Colour kill and vertical identification modes

■Sync separator circuit and pulse shaper for on-chip

generation of timing signals

■Sandcastle output for transcoding applications

■Y + sync, C and CVBS outputs

The TDA8505 is a SECAM variant of the TDA8501 encoder

incorporating many of the same functions. It cannot use an

external sub-carrier signal and requires a single adjustment.

TDA8505

DESKTOP VIDEO SAMPLE ANALOG ICs

TDA8505

TIMING AND

REF. FREQ.

GENERATOR

Vident

GAIN

LIMITER

LPF

FRAME

IDENT

MODULATOR

PHASE

DET

PHASE

DET

FILTER +

BLANKING

switch

MATRIX Csync

Y U V

CVBS

MGA463

CSYNC

f /2

sandcastle

QUICK REFERENCE DATA

Power supply 5 V

Total analog supply current 39 mA

Total digital supply current 4 mA

Total power dissipation 215 mW

Package DIL32

Datasheet Handbook IC02

4-38 Multimedia PC

Picture signal improvement processor

■Luminance signal delay from 20 ns up to 1100 ns

(minimum step 45 ns)

■Colour transient improvement (CTI) reduces

colour difference transient times to those of high

frequency luminance signals

■Aperture correction

■Luminance peaking in 4 steps

■2.6 or 5 MHz peaking centre frequency with –3, 0,

+3 and +6 dB peaking

■Noise reduction by coring

■Handles negative and positive colour difference

signals

■5 or 12 V sandcastle input pulse synchronizes tim-

ing pulse generation

■Automatic luminance signal delay correction

■Luminance and colour difference input signal

clamping with capacitor coupling

The TDA4670 processes luminance and colour difference sig-

nals to improve picture quality. Colour transients are improved

on the chrominance signal; the luminance signal is delayed and

it can also be improved by peaking and noise reduction.

TDA4670

VARIABLE DELAY

20 TO 1155 ns

IN 45 ns STEPS APERTURE

CORRECTION

- (B-Y)

(B-Y)

sandcastle

pulse SANDCASTLE

PULSE

DETECTOR

MBA805 - 1

TRANSIENT

DETECTOR

TRANSIENT

DETECTOR

SWITCH

DRIVER

HIGH

PASS

FILTER STORAGE

CAPACITORS

- (B-Y)

(B-Y)

- (R-Y)

(R-Y)

- (R-Y)

(R-Y)

CORING

STAGE DEGREE

PEAKING

I C - BUS

RECEIVER

SDA

SCL

AUTOMATIC

DELAY TIME

CORRECTION

Y (td)Y

TDA4670

TDA4671

DESKTOP VIDEO SAMPLE ANALOG ICs

QUICK REFERENCE DATA

Power supply 5 V

Typical supply current 41 mA

Total power dissipation (max.) 0.97 W

Package DIL18 (SOT102)

Datasheet Handbook IC02

4-39

Multimedia PC

TDA4686(WP)

BRIGHTNISS

CONTROL,

BLANKING

WHITE

LEVEL

CONTROL CUT - OFF

CONTROL

CONTRAST

CONTROL

PAL/SECAM,

NTSC

RGB

MATRIX

FAST

SIGNAL

SWITCHES,

BLANKING

SAT.

CONTROL

BCUT - OFF

STORAGE

PEAK DRIVE

AND

AVERAGE

BEAM CURRENT

LIMITING

PDL PEAK

DRIVE

LIMITER OUTPUT

STAGES

PEAK

DRIVE

STORAGE

to video

output

stages

average

beam

current

FSW1

Y (VBS)

- (R-Y)

- (B-Y)

FSW2

sandcastle

pulse SANDCASTLE

PULSE

DETECTOR TIMING

GENERATOR

1 AND

2 SWITCH

ON DELAYS

nd CUT - OFF

COMPARATORS LEAKAGE

STORAGE

leakage and

cut-off current

feedback

I C - BUS

RECEIVER

HUE

CONTROL

SDA

SCL

hue control voltage

(to NTSC decoder) vertcal flyback

pulse

TDA4685, TDA4686

TDA4687, TDA4688

MBA800 - 2

DESKTOP VIDEO SAMPLE ANALOG ICs

Analog video processor

■Intended for double line frequency applications

(100/120 Hz)

■Luminance/negative colour difference signal

interface

■Black level clamping of colour difference, lumi-

nance and RGB input signals with capacitor-

coupling DC level storage

■Two analog RGB inputs with BCS control

■Same RGB output black levels for Y/C and RGB

input signals

■Full multistandard RGB matrix with fast switching

between standards

■BCS and peak white adjustments

■Timing pulse generation from a 2- or 3-level sand-

castle pulse

■Two switch-on delays prevent discoloration before

steady-state operation

■Clamped output or automatic cut-off with picture

tube leakage current compensation

■Peak drive and average beam current limiting

■Emitter follower RGB output stages

■I2C-bus controlled outputs for hue-adjust of NTSC

decoders

■No delay of clamping pulse

A luminance and colour difference interface for video processing

in TV receivers, the TDA4686’s primary function is to process

the luminance and chrominance signals from a colour decoder.

It accepts two RGB source signals, from a SCART connector or

an OSD generator and outputs RGB signals to drive video out-

put stages. All parameters are fully I2C-bus controlled. Add-

itional members in this device family offer different types and

degrees of white level control and the range includes an IC for

use with standard line frequency applications. There is also a

version with additional on-chip control.

QUICK REFERENCE DATA

Power supply 8 V

Total supply current 60 mA

Luminance input (peak-to-peak) 0.45 V

Power dissipation TDA4686 1.2 W

TDA4686WP 1.0 W

Package TDA4686 DIL28 (SOT117)

TDA4686WP PLCC28 (SOT261CG)

Datasheet Handbook IC22

5-1

Multimedia PC

TELEVISION

5-2 Multimedia PC

■VHF/UHF off-air TV and cable tuners

■50 to 850 MHz PLL-controlled tuning

■Tuning and control via I2C bus

■RTMA M and N system

■Baseband video and stereo sound output

■FCC radiation, signal handling, immunity

compliant

These tuners, available from Philips Components, integrate into

Philips Semiconductors desktop video chipset to provide a com-

plete solution for display of TV in the PC environment, either

full screen or within a window.

TELEVISION ANALOG TV TUNERS/SOUND DECODERS

Sound Decoders

The MTS (Multichannel Sound Modulation) stereo sound from

the tuner contains the Left and Right sound in the 50 to

15,000 Hz band. A pilot tone is transmitted at 15,734 Hz, and

the L-R signal is modulated on a 31,468 Hz carrier. The Second

Audio Program (SAP) sound channel allows broadcasts in two

PHILIPS SOUND DECODERS TDA9850 TDA9852 TDA9855 TEA5582*

Stereo decoder type BTSC/SAP BTSC/SAP BTSC/SAP BTSC

DBX noise reduction Yes Yes Yes No

Adjustable input level Yes Yes Yes No

Mute control via I2C-bus No Yes No No

60 dB output No No No Yes

at audio signal zero crossing Yes Yes Yes No

Interface for external noise reduction circuits No Yes No No

Independent channel volume control No Yes Yes No

Automatic volume level control No Yes Yes No

Loudness characteristic linked to volume control No Yes Yes No

Tone (bass and treble) control No No Yes No

Sub-woofer or surround output No No Yes No

Selector for external source (line in) No Yes Yes Yes

I2C-bus transceiver Yes Yes Yes No

*The older TEA5582 has no DBX decoder, so no licence is required to use this IC, as is the case with the TDA985x family. The licence can

be obtained from THAT Corporation.

TYPE NUMBER COUNTRY CONNECTOR

Fl1236 USA F or M

Fl1236J Japan F or M

Fl1246 UK/Ireland IEC

Fl1256 France IEC

Fl1216 Rest of Europe IEC

languages and is modulated on a 78,670 Hz subcarrier. The

stereo decoder locks its PLL to the pilot tone and extracts the

left, right and SAP sound signals. These ICs are a representative

selection from a larger family, described in more detail in the

TV designer’s guide.

ANALOG TV TUNERS

5-3

Multimedia PC

TELEVISION SOUND DECODERS

I2C-bus controlled BTSC stereo/SAP

decoder

■Selectable DBX decoded outputs include stereo,

mono, SAP

■Additional SAP output without DBX but including

de-emphasis

■Automatically tuned integrated filters

■Composite input noise detector with selectable

thresholds for stereo and SAP off

The TDA9850 is a bipolar integrated BTSC stereo/SAP decoder

and DBX expander for TV, VCR and multimedia applications.

Incorporating a stereo pilot PLL and ceramic resonator circuit, it

provides automatic I2C adjustment of stereo channel separation

with two selectable pilot thresholds and automatic pilot cancella-

tion, providing quasi-alignment free operation. All filter func-

tions necessary for stereo and SAP demodulation and part of the

DBX filter circuits are provided on-chip using transconductor

circuits, with the required accuracy obtained by an automatic

filter alignment circuit.

TDA9850

STEREO

ADJUST

SAP

DEMODULATOR

INPUT

LEVEL

ADJUST

composite

baseband

input NOISE

DETECTOR STEREO/SAP

SWITCH

DBX LOGIC, I2C

TRANSCEIVER

SDA

CLCR

SCL

MAD

DE-EMPHASIS SAP without DBX

DEMATRIX

MODE SELECT

OUTL

OUTR

stereo

mono

SAP

audio

processing

STEREO DECODER

L + R

L − BSAP

ceramic

resonator

MSB647

TDA9850

5-4 Multimedia PC

I2C-bus controlled BTSC stereo/SAP

decoder and audio processor

The TDA9852 and TDA9855 are enhanced versions of the

TDA9850. Incorporating the same stereo, SAP and DBX func-

tions, they also include a hi-fi audio processor providing an

extensive range of audio processing features, as well as a proces-

sor for producing linear stereo, pseudo stereo, spatial stereo and

forced mono effects. The TDA9852 has an additional interface

for external noise reduction circuits and offers I2C-bus mute

control; while the TDA9855 includes tone control (independent

bass and treble) and a sub-woofer or surround sound output

with its own volume control. Refer to the table for details.

TDA9852/55

TELEVISION SOUND DECODERS

STEREO

ADJUST

SAP

DEMODULATOR

INPUT

LEVEL

ADJUST

comp STEREO/

SAP

SWITCH

DEMATRIX

LINEOUT

SELECT

DBX

EIL

LOGIC, I2C

TRANSCEIVER

SDA SCL

STEREO DECODER

ceramic

resonator

MSB648

LOL LIL

EIR

LOR LIR

INPUT

SELECT

AUTOMATIC

VOLUME AND

LEVEL

CONTROL

MAD

EFFECTS

VOLUME

RIGHT

LOUDNESS

CONTROL

BASS

RIGHT

CONTROL

ZERO

CROSSING

VOLUME

LEFT

LOUDNESS

CONTROL

BASS

LEFT

CONTROL

VIL

VIR

TREBLE

LEFT

CONTROL

TREBLE

RIGHT

CONTROL

SUBWOOFER

MATRIX,

VOLUME

SURROUND

TDA9855

OUTR

OUTS

OUTL

QUICK REFERENCE DATA TDA9850 TDA9852/55

Power supply 9 V 8.5 V

Supply current 58 mA 75 mA

SNR line out (mono) 60 dB 60 dB

audio section – 94 dB

Channel separation Stereo > 25 dB > 25 dB

SAP/dual sound > 70 dB > 70 dB

Bandwidth Stereo 50 Hz to 10 kHz 50 Hz to 11 kHz

Mono, dual sound/SAP 50 Hz to 8 kHz 50 Hz to 8 kHz

Total harmonic distortion 0.2% 0.2%

Package TDA9850: SDIP32 (SOT232-1) TDA9852: SDIP42 (SOT270-1)

TDA9850T: SO32 (SOT287-1) TDA9855: SHDIL52 (SOT247AH)

TDA9855WP: PLCC68 (SOT188CG)

Datasheet (12NC) 9397 750 00176 TDA9852: 9397 750 00706

TDA9855: Handbook IC22

5-5

Multimedia PC

PLL BTSC stereo decoder

■Automatic mono/stereo switching via pilot

presence detector

■LED driver for stereo indicator

■Smooth mono/stereo control

■Matrix and two amplifiers for left and right output

signals

■Source selector for switching between internal

MUX signal and external signals

■External de-emphasis control

■6 dB attenuation of (L-R) with respect to (L+R)

prior to matrix

An integrated phase-locked loop (PLL) stereo decoder, the

TEA5582 is primarily designed for low cost stereo decoding in

low- to medium-range applications. It accepts either a low

impedance current input to the MUX, or can be switched to

accept an external input. The de-emphasis and the amplifier

gain can be set with external passive components. It has full

ESD protection.

TELEVISION SOUND DECODERS

TEA5582

AMP

left channel

right channel

right de-emphasisLED

driver

smooth

mono/stereo

control

pilot presence

detector

source

selector

Vo left

Vo right

mute

input 2

left

input 1

left

AMP

MUX

TEA5582

AMP

MSC222

input 1

right

input 2

right

AMP

MATRIX

(L−R)

de-emphasis

(L+R)

2fH

2fHfH fH fH

fH (L−R)

CONVERTER

VOLTAGE

CONTROLLED

OSCILLATOR

ON/OFF SWITCH

VOLTAGE

CONTROLLED

OSCILLATOR

phase detector VCO left de-emphasis

PHASE

DETECTOR FREQUENCY

DIVIDER

STABILIZER

SYNCHRONOUS

DEMODULATOR

VOLTAGE-TO-

CURRENT

CONVERTER

PILOT PRESENCE

DETECTOR

PILOT-CANCEL

+Vref

SMS

CONTROL

MONO/STEREO

SWITCH LED

DRIVER

QUICK REFERENCE DATA

Power supply 7 V to 16 V

Total current consumption (typ.) with no LED driver 19 mA

THD (at VO= 600 mV) 0.3 %

Channel separation 28 dB

SNR (bandwidth IEC 79) 82 dB

Total power dissipation (max.) 160 mW

Package DIL20 (SOT146)

Datasheet Handbook IC02

5-6 Multimedia PC

PC Text teletext software

■Intelligent page acquisition and caching

■Level 1.5 teletext

■Teletext functions accessible using any program-

ming language capable of calling functions from

Windows DLLs

■Teletext window class usable as main window or as

a control

■Supports a range of teletext devices

■Optional Fastext support

■C and Visual Basic demonstration application

The PC Text software consists of a number of Windows (3.1,

3.11 and ‘95) DLLs and a window class, allowing quick devel-

opment of Teletext applications on PCs using a compatible tele-

text decoder. It allows a single teletext device to be used by more

than one application simultaneously.

The acquisition software makes intelligent use of multichannel

teletext devices to acquire and cache pages the user is likely to

want next, ensuring minimum delay. With the SAA5246A or

SAA5281, it provides caching of up to 30 pages. PC Text pro-

vides full language coverage for Western Europe and can be

extended to cover all WST areas.

Philips has a range of teletext decoders applicable to the multi-

media PC market. The choice of decoder will depend on a num-

ber of issues including page access time, language support, cost,

package and whether to use a single chip or decoder/RAM solu-

tion. These ‘multimedia’ decoders are described below and on

the following pages is a selection of ICs from Philips full range

of teletext, closed caption and line 21 decoders.

Multimedia teletext decoders

All Philips multimedia decoders offer:

■I2C bus control by a bus master such as the

SAA7146

■Simple application, requiring very few external

components

■Similar register maps

■Support by the PC Text teletext software

TELEVISION CLOSED CAPTION/TELETEXTDECODERS

MSC234

COLOR

DECODER/

SCALER

PCI Bus

I2C

TELETEXT

DECODER

TUNER

CVBS

PCI BUS

MASTER

SAA5246A SAA5249 SAA5254 SAA5281

No. of pages 8 (external) 500 (external) 1 (internal) 8 (internal)

Acquisition channels 4 1 1 4

Language/region All WST By region By region All WST

Features External 8 ×8 K SRAM Single-chip teletext decoder Single-chip decoder with On-chip 8 ×8 k

for page storage with data slicer and on-chip 8 ×1.1 k RAM; RAM; supports

acquisition display driver supports Fastext/FLOF Fastext/FLOF and TOP

Package QFP64, DIL48 SO24, DIL24 QFP64, DIL40 QFP64, SDIL52

Datasheet Handbook IC02 Handbook IC02 Handbook IC02 Handbook IC02

5-7

Multimedia PC

Multimedia VBI and FF data acquisition IC

■High performance multistandard data slicer

■Intercast and DataCast PDC (packet 30 and 31)

compatible

■Supports 525 line teletext (USWST, NABTS and

MOJI) and 625 line teletext (EuroWST and

ChinaCCST)

■Supports European and American Closed

Captioning

■Supports Wide Screen Signalling (WSS) and Video

Programming Selection (VPS) data

■User programmable data format

■2 kbyte data cache

■Choice of clock frequencies (direct-in clock or

crystal oscillator)

■Parallel, Motorola, Intel, I2C and digital video bus

interfaces

■Data type selectable on individual video lines, with

VBI and FF modes

■Programmable interrupt, DMA or polling driven

■Optimized for EMC

The SAA5284 is a Vertical Blanking Interval (VBI) and Full

Field (FF) video acquisition IC tailored specifically for PC add-

in cards, motherboards and set-top boxes. It supports all com-

mon teletext and closed caption formats and will filter packets

30 and 31 WST/NABTS; it also has scope for accepting as yet

unspecified formats.

A very highly integrated IC, it incorporates all the necessary data

slicing, interfaces, data filtering and control logic, so requires

very few external components for design-in. Controlled via the

parallel interface or the I2C-bus, it can output data via the digi-

tal video bus when a parallel interface is not available.

TELEVISION CLOSED CAPTION/TELETEXTDECODERS

SAA5284

QUICK REFERENCE DATA

Power supply 5 V

Supply current t.b.f.

Typical sync amplitude 0.3 V

Crystal frequency 12, 13.5, 15, 16 MHz

Package QFP44

Datasheet Contact Philips

MSC233

C8[1...0]

SEL[1...0]

A[2...0]

D[7...0]

INT

RDY

SDA

SCL

DENB

(1)

WRLLCHREF DMARQ

DMACK

(1)

WRLLC2VPOin[7...6] (1)

MULTI STANDARD

HOST INTERFACE

(INTEL,

MOTOROLA,

DIGITAL VIDEO)

PACKET BUFFER

AND

FRONT END

CONTROL REGISTERS

PACKET BUFFER

RAM, 2KBYTE

(45 PACKETS)

OSCILLATOR

AND TIMING

OSCOUT OSCGND TEST0 TEST1

OSCIN

PACKET

FILTERING

(e.g. WST

PACKETS

30/31)

FIFO

I2C

INTERFACE

400 kHz

SLAVE

ANALOG

SWITCH

ANALOGUE

VIDEO TO

DATA BYTE

CONVERTOR

(DATA

DEMODULAT

OR)

CVBS0

VDDA VSSA VDDD VSSD RESET

CVBS1

Iref

black

5-8 Multimedia PC

TELEVISION CLOSED CAPTION/TELETEXTDECODERS

Line 21 decoder

■‘Stand-alone

’

or I2C-bus controlled line 21 decoder

■On-chip display RAM allowing full page Text mode

■Enhanced character display modes

■Full colour captions

■Automatic handling of Field 2 data

■Automatic selection of (1H, 1V), (2H, 1V) and

(2H, 2V) scan modes

■Onboard OSD facility using character generator

The SAA5252 is a single-chip line 21 decoder that will acquire,

decode and display line 21 Closed Captioning data from a

525-line CVBS signal. Normal and line progressive scan modes

are supported; it has an RGB interface for standard colour

decoder ICs and RGB inputs which support signals from

external OSD ICs. The displayed characters are defined on a 5 ×

12 matrix within a 7 ×13 window, allowing one blank pixel

either side and a pixel row above. It has video, text and caption

display modes.

SAA5252

MSC189

CHARACTER

GENERATOR

ADDRESSING

CONTROL

CODE

INTERPRETER

AND

ADDRESSING

CHARACTER

ROM

DISPLAY

TIMING

ROUNDING

ITALICS

AND

RGB

MULTIPLEXOR

PAGE

RAM

I C

INTERFACE

SERIAL/

PARALLEL

AND

PARITY

SYNC SEPARATOR

AND

ACQUISITION TIMING

ADC DATA

DETECTOR

OSCILLATOR

V H

RGBREF

BLAN

BLANIN

RIN

GIN

BIN

SDA

SCL

I C/DC

OSCIN

OSCGND

OSCOUT

BLACK

IREF

CVBS

SAA5252

QUICK REFERENCE DATA

Power supply 5 V

Supply current 30 mA

I2C-bus interface Yes

CVBS sync. amplitude 0.3 V

CVBS video amplitude 1 V

Package SAA5252P DIL24 (SOT101)

SAA5252T SO24L (SOT137-1)

Datasheet Handbook IC22

5-9

Multimedia PC

One-page economy teletext/TV

microcontroller

■Complete single-chip one-page teletext decoder

and TV microcontroller

■Supports Western European, Eastern European,

Turkish, Cyrillic, Arabic and Thai languages

■Double size, double width and double height

character capability for OSD

■Enhanced display features including meshing and

shadowing

■Separate display and acquisition timing for

increased flexibility

■525 and 625 line display synchronization

■Standby mode through power-down of teletext

and analog hardware

■Direct driving of LEDs

■80C51 compatible microcontroller

■16 kbytes masked ROM

■256 bytes on-chip RAM

■Six 6-bit PWMs and one 14-bit precision PWM

■4-bit DAC and comparator with 3-input multi-

plexer, providing 3 successive approximation soft-

ware ADCs

■Master and slave bit-level I2C-bus

This IC is a single-chip one-page economy teletext decoder and

TV microcontroller. It decodes 625-line based WST (World

System Teletext) transmissions and provides a range of TV con-

trol and OSD functions. The teletext decoder is derived from a

single page teletext decoder and static RAM is included on-chip

to hold one complete page of teletext for decoding/storage.

Interrupt logic 0 is triggered on rising and falling edges, allowing

pulse-width measurement for remote control decoding. The

microcontroller is an industry standard 80C51 device and the

SAA5290 is available as a mask-programmed ROM version or as

a Flash EEPROM version in a multichip package, for product

development.

TELEVISION CLOSED CAPTION/TELETEXTDECODERS

SAA5290

XTALOUT

MSC205

COR

SAA5290

BLACK IREF

CVBS0

CVBS1

XTALIN

OSCGND

RESET

DATA SLICER TELETEXT

ACQUISITION DISPLAY

TIMING

ACQUISITION

TIMING PAGE

RAM DISPLAY

OSC

16K8

ROM 256x8

RAM TEXT

I/FACE

ADC PWM TIMER/

CTRS/I C

PORT 3

80C51

CPU

data

addr

int

P3.0-P3.4/

ADC0-2 P2.0-P2.7/

PWM P1.0-P1.7/INT0,IN

T1, T0, T1, SDA, SCL P0.0-P0.7

VSYNC

HSYNC

FRAME

R, G, B

VDS

PORT 2 PORT 1 PORT 0

QUICK REFERENCE DATA

Power supply 5 V

Microcontroller supply current 25 mA

Analog supply current 35 mA

Teletext supply current 20 mA

Crystal frequency 12 MHz

Package SDIP52 (SOT247-1)

Datasheet Handbook IC02

5-10 Multimedia PC

Single-chip economy 10 page teletext/TV

microcontroller

■Complete multistandard teletext decoder and TV

controller chip

■RGB interface to standard colour decoder

■Supports video and scan related sync. modes

■Single crystal oscillator for teletext decoder,

microcontroller and display

■Ten page (10240 ×8) on-board teletext and OSD

memory

■Handles Western and Eastern European, and

Turkish, Cyrillic, Arabic and Thai languages

■260 characters in mask programmed ROM

■Acquisition and decoding of VPS data (EBU PDC

System A)

■Double size, width and height capability for OSD

■Enhanced display features and automatic detection

of Fastext

■Colour palette with 8 colours for both foreground

and background.

■80C51 compatible microcontroller with 32 kbytes

mask programmed ROM and 768 bytes RAM

■Eight 6-bit PWMs and one 14-bit PWM for tuning

control

■Four ADCs implemented as an 8-bit DAC and

comparator with 4 multiplexed outputs

As a combined, single-chip economy ten page TV teletext

decoder and controller IC, the SAA5296 is intended to provide

the central control mechanism in a TV receiver. It will decode

625 and 525 line based WST transmissions and provides tuner

control functions and OSD facilities. The teletext decoder is a

derivative of the IVT1.1X and the TV microcontroller is based

on an industry standard 80C51. A ten page static RAM module

is incorporated on-chip as memory for both teletext and OSD

functions. Information regarding teletext signal quality, whether

it is 625 or 525 line broadcast and which language variant is in

use can all be read via the I2C interface. Packet 26 data is han-

dled by dedicated hardware. There are two versions of this chip,

either with Flash EEPROM in a multichp package for software

development or mask programmed ROM.

TELEVISION CLOSED CAPTION/TELETEXTDECODERS

SAA5296

MSB591 - 1

DATA SLICER

ACQUISITION

TIMING

TELETEXT

ACQUISITION DISPLAY

TIMING

DISPLAY

10-PAGE

RAM

OSCILLATOR

8051 CPU

ANALOG-TO-

DIGITAL

CONVERTER

PULSE

WIDTH

MODULATOR

TIMER/

CTRS/ I C

data

address

32 K x 8

ROM

PORT 3

256 x 8

RAM

PORT 2

TEXT

INTERFACE

PORT 1

512 x 8

AUX RAM

PORT 0

P3.0 to P3.4 P2.0 to P2.7 P1.0 to P1.7 P0.0 to P0.7

RESET

OSCGND

XTALOUT

XTALIN

SAA5296

VSYNC

HSYNC

FRAME

R, G, B

VDS

COR

BLACK IREF

CVBS0

CVBS1

INT

QUICK REFERENCE DATA

Power supply 5 V

Supply current 115 mA

Supply current (standby text) 30 mA

Clock frequency 12 MHz

Datasheet Handbook IC22

EXTENDED TYPE NO. VERSION PACKAGE

SAA5296ZP/nnn ROM SDIL52 (SOT247)

SAA5296GP/nnn Int./ext. ROM QFP80 (SOT318)

SAA5499ZP/nnn EEPROM SDIL52 (SOT247)

5-11

Multimedia PC

Digital Broadcasting by cable and satellite is one of today’s most

significant technologies. Philips’ integrated chipset is not only

ideal for a highly-featured DVB set-top box or a DVB/DAVIC

cable modem, but is also ready for building into TVs, DVD

players and PCs. We are ideally placed to give our customers a

clear lead, as the only semiconductor and component manufac-

turer that can supply a completely integrated system solution,

for both cable and satellite systems. By drawing on our vast

audio and video experience in both analog and digital fields, we

provide a complete, single supplier solution, allowing you to

reach the market very quickly.

TELEVISION DIGITAL CABLE/SATELLITE ICs

MSB999

DESCRAMBLER

DEMULTIPLEXER

RISC PROCESSOR

Signal access

and control

Cable channel

AUDIO

VIDEO

GRAPHICS

MPEG

decoding

AUDIO

DAC

VIDEO

ENCODER

R/F

MODULATOR

CARD READER

INTERFACE

QAM

DEMODULATOR

FEC

Satellite

channel

QPSK

CONTROLLER

FEC

Input

TUNER

QPSK

DEMODULATOR

Receiver

OUTDOOR UNIT

MULTISWITCH

I/F demodulation

I/F AMPLIFIER/

CONVERTER

CABLE TUNER

Output

Satellite front-end

Cable front-end

Philips is actively involved in defining standards for these mar-

kets and we fully support the DVB and DAVIC standards. For

the cable modem market, Philips intends to support both

IEEE802.14 and the Cable Labs standards as they develop.

5-12 Multimedia PC

QPSK demodulator

■Quadrature accuracy optimized for digital

television

■Low crosstalk between I and Q channels

■High input sensitivity

■Internal voltage stabilizer for the VCO ensures

good shift performance

The demodulator amplifies the received RF signals in a high

gain amplifier and mixes them with two LO signals, 90° out of

phase, generated using an internal Voltage Controlled Oscillator

(VCO) and frequency divider. The resulting Inphase (I) and

Quadrature (Q) signals are buffered separately to drive external

low pass filters used for baseband filtering and then amplified.

TELEVISION DIGITAL CABLE/SATELLITE ICs

TDA8040

TDA8041

QPSK demodulator controller

■Operates with low SNR applications

■Handles up to 30 Msymbols/s

■On-board DACs and op-amps provide high

flexibility for loop time constraints

The QDMC TDA8041H is designed specifically to work with

the QDM and generates all the control signals needed to

demodulate QPSK (and BPSK) signals.

TDA8042

UHF QPSK demodulator

■Symbol rates up to 45 Msymbols/s

■AGC detector and amplifier with a 21 dB control

range

■Phase accuracy to less than two degrees; typically

one degree

The TDA8042 is an enhanced version of the TDA8040, han-

dling QPSK modulated RF signals from 350 MHz to 650 MHz

and with an on-chip 0° and 90° phase shifter.

TDA8043

One-chip satellite channel decoder

(ADC/QPSK/FEC)

■Handles QPSK and BPSK modulation schemes

■Accepts variable symbol rates at up to 32 Msymbols/s

■35%/50% roll-off Nyquist filter and A/D converters

built-in

■Programmable loop filters provide for internal

clock recovery and AGC loops

■No external loops

This is a one-chip, DVB compliant demodulator with

Viterbi/Reed-Solomon decoding for Forward Error Correction,

with de-interleaver and descrambler.

TDA8705(A)

Dual ADC

■2 times 6-bit resolution

■High SNR over a large analog input frequency

range

■TTL output

■Two separated inputs (AC-coupling)

■TTL-compatible digital inputs

■Low level AC clock input signal allowed

■Internal reference voltage regulator

■Low analog input capacitance with no buffer

amplifier needed

■No sample-and-hold circuit required

The TDA8705 and TDA8705A are 6-bit high-speed dual

ADCs. Converting two analog input signals into two 6-bit

binary-coded words they are designed for DBS (Direct

Broadcast Satellite) QPSK satellite video applications. Both ICs

interface directly to the TDA8040 and all-digital demodulators

for DVB or other DBS systems. The TDA8705 has a maximum

sampling rate of 40 MHz with an effective SNR of 5.8 bits at

10 MHz full-scale input; the TDA8705A has a maximum sam-

pling rate of 80 MHz with an effective SNR of 5.5 bits at

20 MHz full-scale input.

SATELLITE

5-13

Multimedia PC

CABLE SYSTEMS

TDA8761A

9-bit ADC

■Maximum sample rate of 30 MHz

■In-Range (IR) tri-state TTL output

■High Signal-to-Noise Ratio (SNR) and low power

dissipation

■TTL-compatible inputs and outputs

■No buffer amplifier is required

■No external sample-and-hold circuit needed

Optimized for digital video, the TDA8761A is a 9-bit converter

with high linearity, delivering the conversion accuracy needed in

256 QAM demodulation for all symbol frequencies. It is guaran-

teed for no missing codes.

8-bit 40 Msps 2.7 - 5.5 V universal ADC

■8-bit resolution with sample rates up to 40 MHz

■Operates between 2.7 V and 5.5 V

■DC sampling allowed

■CMOS/TTL-compatible digital inputs and outputs

■High Signal-to-Noise Ratio (SNR) and low power

dissipation

■No buffer amplifier is required

■No external sample-and-hold circuit needed

The TDA8790 is a low-power, low-cost universal CMOS ADC

for video and general purpose applications which includes a

sleep mode to reduce device power consumption when inactive

down to 4 mW. It is suitable for QPSK applications and when

used with the TDA8046 QAM demodulator, provides a cost

effective 64 QAM system solution. (For 256 QAM, use the

TDA8761A described above.)

TDA8790

TDA9819

TELEVISION DIGITAL CABLE/SATELLITE ICs

IF amplifier/converter and TV-VIF

■IF down conversion mixer with internal and

external AGC for DTV

■Complete analog VIF including AGC and AFC

■Multistandard VIF stage handles positively and

negatively modulated signals

■Sound IF stages process FM standards and

L-standard AM sound demodulation

■Processing of NICAM L sound carrier

Provides Vision IF (VIF) and sound IF signal processing with a

single reference Phase Locked Loop (PLL) demodulator, com-

bined with the signal stages for IF processing to the DVB stan-

dard.

Multi-mode QAM demodulator

■Supports 4, 16, 32, 64 and 256 modulation schemes

■Integral 15% or 20% roll-off Half-Nyquist filter

■Compensation for offset between I and Q branches

■Decision Feedback Equalizer produces

constellation diagram with no training sequence

required

■Four de-mapping schemes, including an 8-bit

parallel format suitable for FEC

■Variable symbol rates with external hardware

support

Broadly similar in function to the TDA8045, this enhanced dig-

ital demodulator covers both European and USA standards.

From the ADC, the TDA8046H accepts TTL-compatible sig-

nals and processes them to I and Q baseband signals. Digital

control values for coarse AGC are derived and converted on-

chip to analog control currents; these are feed back via a loop fil-

ter using an op-amp, which gives flexibility in selection of the

PLL loop time constraints. The same basic scheme is also used

for the clock and carrier recovery. The equalizer function, imple-

mented with a T-spaced 12- or 14-taps adaptive filter with feed-

back, produces a

‘clean’ constellation diagram, which is fed to the

output formatter.

TDA8046H

5-14 Multimedia PC

MPEG-2 decoder with graphics

■Decoding of video data in MPEG-2 PES, MPEG-1

packet or ES format using less than 2 Mbit of

DRAM

■On-board vertical and horizontal scaling functions

and a range of trick modes

■Layer-1 and layer-2 MPEG audio decoding support-

ing mono, stereo, surround sound and dual channel

modes

■On-chip audio de-emphasis, volume control and

programmable channel mixing

■From 16 Mbit, a minimum 1.2 Mbit is memory

available for graphics

■Multiple graphics boxes with background loading,

fast switching scrolling and fading

■Support for direct bitmaps or bitmaps coded to

DVB region-based graphics standards

With the adoption of the MPEG-2 compression standard in the

broadcasting world, Philips has developed a highly integrated

multistandard MPEG-2 decoder specifically for broadcast appli-

cations. It handles audio and video MPEG-2 streams and also

includes DVB graphics and OSD capability.

SAA7201

TELEVISION DIGITAL CABLE/SATELLITE ICs

SIGNAL ACCESS AND CONTROL

MPEG-2 transport and demultiplexer

■On-board teletext filter compatible with TXT

input the SAA7183 video encoder

■High speed filter allows output of entire transport

packets or packet payloads

■On-chip clock generation for interfacing to the

descrambler

■Works on its own on non-scrambled signals

After descrambling, this IC demultiplexes a broadcast signal. A

parser separates MPEG-2 compliant transport streams which,

after error handling, are routed to audio and video filters with

decoder specific interfaces, and the system microcontroller.

SAA7205

DVB compliant descrambler

■Descrambles MPEG-2 Transport Stream (TS) or

Packetized Elementary Stream (PES) signals

■Descrambler includes stream and block decipher

modules, with PID and CW banks

■Conditional access data is retrieved and passed to

the microcontroller

■On-chip µC interface with memory mapped I/O

The SAA7206 descrambles MPEG-2 signals in line with the

European DVB Super Descrambler Mechanism algorithm. A

parser separates MPEG-2 compliant transport streams and

routes them on to the main descrambler block.

SAA7206

Reed/Solomon decoder

■Handles DVB compliant R/S code

■Automatic synchronization of bytes, blocks and

frames

■De-interleaving according to a convolutional

scheme

■High throughput R/S decoder block with three fully

pipelined hardware computation units

■On-board error correction

■Energy dispersal de-scrambling algorithm

■Six quasi-bi-directional ports and an I2C-bus

interface

This IC provides Forward Error Correction for cable systems.

An input data stream, interpreted as non byte-aligned, is passed

to the synchronization block. This interprets a byte stream in

fixed length blocks of 204 bytes starting with a synchronization

byte, and both de-interleaving and Reed/Solomon decoding are

based on this block structure.

SAA7207H

6-1

Multimedia PC

RADIO

6-2 Multimedia PC

The OM560x family of FM tuner modules has been designed to

operate in the harsh electrical environment of a PC and deliver

high quality stereo radio reception. Shielded for use in the PC,

they meet the FCC requirements on radiation. These tuner

modules comprise a core self-tuned radio, an amplifier and a bus

converter which enables I2C-bus or STR control and provides

three additional I/O control lines. Three modules are available

to meet various international frequency and connector require-

ments. A number of complete reference boards are also available

using these modules, covering a basic tuner board, a multimedia

board including sound processing and an enhanced multimedia

board with R(B)DS functionality.

RADIO PC RADIO MODULES

QUICK REFERENCE DATA OM5604 OM5606 OM5608

Region USA Europe Japan

Frequency 87.5 to 108 MHz 87.5 to 108 MHz 76 to 90 MHz

Connector F-connector IEC F-connector

Datasheet 9397 750 00352 9397 750 00352 9397 750 00358

Software

The processing power available in the PC environment allows

designers to model the user interface on that of a high specifica-

tion music system. To simplify the design task, Philips has

designed reference software and can supply a number of sample

programs including application programs for DOS and

Windows, and a test program. Software is supplied as Pascal

source code.

User interface functions such as step, search and so on, and con-

trol of communications through the I2C-bus, are handled

through the software. The software displays and controls all

sound functions including volume, bass and treble, source selec-

tion and mute, balance (left/right and front/rear) and display of

the R(B)DS information. Up to 99 pre-set channels are avail-

able, which can also be set manually, giving the user a wide

choice of configurations. It is also possible to search for only

those stations that play a particular style of music, either by

manual tuning or automatically scanning for particular R(B)DS

codes.

IF AMP/DET MPX

SYNTH.

FM RECEIVER

TEA5757H

LINE

AMPLIFIER

TDA1308T

BUS CONVERTOR

PCF8574T (optional)

line

output

MPX

3 I/Os

OM5604

IIC-bus or STR-pins

75 Ω

aerial

MSB942

6-3

Multimedia PC

Self-tuned radio

■Combined tuning synthesizer and radio

■Unique analog fast-tuning algorithm typically iden-

tifies 40 stations within 20 s

■High signal-to-noise ratio

■Automatic fine tuning to counter signal drift

■Local/DX switching

■Stop detection circuit and microcontroller bus

interface on-chip

The TEA5757H is a highly integrated single-chip, self-tuned

radio covering AM (LW, MW and SW) and stereo FM broad-

casts and is available in versions covering European/USA (87.5

to 108 MHz) and Japanese (76 to 91 MHz) frequencies. The

chip uses Philips’ unique fast-tuning algorithm which increases

tuning speed the greater the distance to the desired frequency.

Once the tuner has defined the VCO frequency of a channel

within a set window, when that station is selected the chip fine

tunes the signal using the quality of the received signal as a refer-

ence, to lock the receiver to that frequency. The system then

goes into a power saving stand-by mode and if at any time the

quality of the signal weakens, then the chip wakes up and fine-

tunes itself once more, using the previously set VCO frequency.

Local/DX switching ensures reception is not overpowered when

tuned to strong local transmitters.

TEA5757H/5759H

RADIO PC RADIO MODULES

A/D

AFC

LEVEL

AM CHANNEL

FM CHANNEL

VCO

STEREO

DECODER SDS

MPXin

L R

audio

V/I

Sout

DET.

level

STABILIZER

DIGITAL CONTROL

TUNING FUNCTION

Cloop

ref. osc.

bus

RECEIVER INTERFACE TUNING

TEA5757H

MSB961

QUICK REFERENCE DATA

Power supply Static 2.1 to 12 V

Tuning 12 V

Supply current AM 15 mA

FM 16 mA

SNR 71 dB

RF sensitivity AM 55 µV

FM 1.2 µV

Total harmonic distortion AM 0.8%

FM 0.3%

MPX channel separation 30 dB

Total power dissipation (max.) 250 mW

Package QFP44 (SOT307)

Datasheet (12NC) 9397 750 00557

6-4 Multimedia PC

Class AB stereo headphone driver

The TDA1308T is a high performance integrated class AB

headphone driver providing a high SNR and slew rate, com-

bined with low distortion. Its low power consumption and small

size make it ideal for MPC audio applications. This IC is

described in detail in the ‘Digital audio’ section, on page 8-16.

TDA1308T

RADIO PC RADIO MODULES

Remote 8-bit I/O expander for I2C-bus

■I2C-bus to parallel port expander

■8-bit remote I/O port for the I2C-bus

■Up to three additional control lines

■Open-drain interrupt output

■Low standby current consumption of 10 µA

maximum

■Latched outputs with high current drive capability

for direct driving of LEDs

The optional PCF8574A provides general purpose I/O expan-

sion for most microcontrollers via the two-line bidirectional bus

(I2C), allowing I2C or STR control of the tuner module. It

includes an 8-bit quasi-bidirectional port and an I2C interface.

An interrupt signal can be sent on a dedicated line to the micro-

controller, allowing the remote I/O to inform the microcon-

troller if there is incoming data, without using the I2C-bus.

PCF8574A

MSC192

I C BUS

CONTROL

INPUT

FILTER

INTERRUPT

LOGIC

P0 to P7

8 BIT I/O

PORTS

SHIFT

LP FILTER

WRITE pulse

READ pulse

POWER-ON

RESET

VDD

SDA

SCL

INT

PCF8574

QUICK REFERENCE DATA

Power supply 2.5 to 6 V

Typical supply current 40 µA

Typical standby current 2.5 µA

Power-on reset value (max.) 2.4 V

Total power dissipation (max.) 400 mW

Package PCF8574P/AP DIP16 (SOT38-1)

PCF8574T/AT SO16 (SOT162-1)

PCF8574TS SSOP20 (SOT226-1)

Datasheet Handbook IC22

6-5

Multimedia PC

Philips has an extensive range of complementary ICs for build-

ing complete multimedia sound cards with in-built radio, reduc-

ing design time and simplifying complete system design. Very

few external components are needed for PC systems based on

the OM560x family of modules.

Philips offers two multifunction, multimedia radio reference

boards. Both include a sound processor, which can also accept

input from a CD-ROM drive, as well as a graphic equalizer and

power amplifier. The second also offers R(B)DS functionality.

These boards are intended as design examples; Philips has a great

range of other audio processing ICs, allowing customers to build

a variety of multimedia audio boards with various functionalities.

RADIO MULTIMEDIA/RADIO BOARDS WITH R(B)DS

CCR921

R(B)DS

DECODER

ISA-BUS

INTERFACE

SAA6579

RDS

DEMODULATOR

OM5604

FM MULTIMEDIA

MODULE

CD-ROM sound

TEA6320

SOUND

PROCESSOR

TEA6360

5 BAND

EQUALIZER

TDA1517P

POWER

AMPLIFIER

MULTIMEDIA

FM-RADIO CARD

I2C-bus

75 Ω

aerial

line

input

power

output

line

output

MSB943

CCR921

R(B)DS controller

■Supports all R(B)DS group types

■All decoded R(B)DS data plus status information

available via I2C-bus

■R(B)DS information available for processing by the

PC in real-time

■Data buffering (up to 700 ms), allows instant

access and ‘intelligent’ searching on specific

R(B)DS data

■Fast synchronization with block type A search

■Error processing with correction status for every

block

The CCR921 is an 80C51 µC with intelligent RDA data decod-

ing and pre-processing software incorporating automatic error

detection and correction. It accepts R(B)DS data and converts it

into tuning and display information. The microcontroller han-

dles decoding of all R(B)DS codes under I2C-bus control, after

which all R(B)DS data is present within the serial interface pro-

tocol. As an I2C slave, no multimaster bus is required.

I C-CLOCK

I C-DATA

CCR921

CTRQN

DAVN

I C-address

additional outputs

SYNCRESET TP TA M/S A0 A1

MSC120

I C

signals from

RDS/RBDS

demodulator

RDDA

RDCL

OSCI

QUICK REFERENCE DATA

Power supply 5 V

Typical supply current 24 mA

I2C-bus interface Yes

Oscillator frequency 8.664 MHz

Package QFP44

Datasheet Contact Philips

6-6 Multimedia PC

R(B)DS demodulator

■2nd order anti-aliasing filter

■8th order 57 kHz bandpass filter separates R(B)DS

data from the MPX signal

■Reconstruction filter (2nd order)

■57 kHz subcarrier regenerated by a Costas Loop

PLL

■RDCL signal (RDS clock) recovered by a second

PLL with lock on biphase data rate

■Biphase symbol decoder with integrate and dump

functions

■Pre-amplifier and comparator with automatic off-

set compensation

■Signal quality detector

■CMOS-level digital outputs

■Subcarrier output

After digitization, the radio signal is synchronously demodulated

to recover the biphase data symbols, which are further processed

in an integrate and dump circuit which generates the RDDA

(RDS Data) signal. The data signal RDDA and the regenerated

clock signal RDCL are provided as outputs for further process-

ing by a suitable decoder (or microcomputer) such as the

CCR921. The operation of the SAA6579 is in accordance with

the CENELEC EN 50067 standard.

The boards are completed with the following ICs:

■TDA1517P stereo radio power amplifier. A stereo, single-

ended audio amplifier delivering 2 × 6 W per channel for

driving passive speakers.

■TEA6320/1/2/3 sound processors. A family of sound

processors and audio control circuits, providing digital con-

trol via the I2C bus of various sound parameters.

■TEA6360 5-band graphic equalizer. The TEA6360 5-band

stereo graphic equalizer is an I2C-bus controlled tone proces-

sor for applications such as radios, TVs and music centres

with Dolby noise reduction.

SAA6579

SAA6579(T)

MSC204

ANTI-

ALIASING

FILTER

57 kHz

BANDPASS

(8th ORDER) RECONSTRUCTION

FILTER OSCILLATOR

AND

DIVIDER QUALITY BIT

GENERATOR

CLOCKED

COMPARATOR COSTAS LOOP

VARIABLE AND

FIXED DIVIDER

BIPHASE

SYMBOL

DECODER DIFFERENTIAL

DECODER

REFERENCE

VOLTAGE CLOCK

REGENERATION

AND SYNC TEST LOGIC AND

OUTPUT SELECTOR SWITCH

MUX

MPX

signal

SCOUT

CIN

VDDA

Vref

+5 V

VSSA TSTLD TEST VSSD

T57

RDCL

RDDA

QUAL

VDDD

OSCOOSCI

+5 V

VP1

RADIO MULTIMEDIA/RADIO BOARDS WITH R(B)DS

QUICK REFERENCE DATA

Power supply 5 V

Total supply current 6 mA

Minimum R(B)DS input amplitude (RMS) 1 V

Oscillator frequency 4.332/8.664 MHz

Package SAA6579 DIL16 (SOT38GG6)

SAA6579T SO16 (SOT162A)

Datasheet Handbook IC01

6-7

Multimedia PC

Astra Digital Radio

The ADR system uses the ISO/IEC 11172-3 MPEG-1 layer-II

international standard, more commonly known as Musicam, for

the digital encoding/decoding of audio signals for transmission

over their satellite network. Digital transmission allows provi-

sion of CD quality sound and ADR will provide two services to

their customers, at the moment primarily in Germany but likely

to be extended to other countries. These are a ‘free-to-air’ service

for public and private radio stations, and a subscription-based

RADIO DIGITAL RADIO SYSTEMS

The SAA2530 has been designed specifically to handle and

decrypt ADR/DMX transmissions and it performs all the

demodulation and decoding functions required for the process-

ing of the full frequency range of ADR SIF input signals.

It provides QPSK demodulation and de-interleaving of the

ancillary data. After pre-processing, this allows for display of

programme-related information, auxiliary data and R(B)DS

information. A full ADR system would also include a card read-

er and verifier IC to check for the relevant subscription informa-

tion for the pay-radio service. The SAA2530 includes an 8-bit

A/D converter and gain controlled amplifier, and performs the

synchronization of MPEG-1 layer-II data, which can then be

passed on to the SAA2502 interface. A number of additional

features are available with this chip such as Viterbi and differen-

tial decoding, depuncturing and descrambling, and FEC func-

tions. It has interfaces for both I2C and L3-bus control.

SAA2530

For details of the SAA2502 and others in the SAA250x family of

MPEG decoders, please refer to the Digital Audio section, page

8-12.

SAA2502

ADR DEMODULATION, DECODING &

AUDIO PROCESSING

SAA2530

MICROCONTROLLER

ancillary data

MPEG

MSC027

I2S-bus

SPDIF

SATELLITE

TUNER

REMOTE

CONTROL

TRANSCEIVER

PUSH

BUTTONS

AND

DISPLAYS

CARD

READER

AND

ELECTRONICS

LNB

POWER

SAA2502

DMX (Digital Music Express) service, offering 60 different

channels at the moment, to be extended to 120 thematic chan-

nels.

The first IC in Philips’ 2nd generation of MPEG decoders (the

SAA2502) and an ADR specific demodulator and decoder chip

(the SAA2530) are the only chips required for demodulation,

decoding and audio processing of both formats of ADR signals.

6-8 Multimedia PC

RADIO DIGITAL RADIO SYSTEMS

Digital Audio Broadcast channel decoder

The Musicam encoding system used in ADR will also be used

for the European Digital Audio Broadcasting standard, and

Philips has a first generation DAB chipset. The DAB channel

decoder contains all the key components for the Eureka-147

DAB system, supporting DAB modules I, II and III and all the

main features of the EBU ETSI draft prETS 300 401. It pro-

vides real-time processing of the FIC (Fast Information

Channel) and up to six service components, with error protec-

tion for both audio and data services.

FADIC

Differential demodulator and DSP interface

■Input symbol buffering

■Frequency transposition

■256-, 512- or 2048-point complex FFT

■Differential demodulation

■Metric generation

■8-bit parallel input and output interfaces

■16-bit parallel control interface

The FADIC is frame independent and operates on a symbol

basis. It processes each symbol in the baseband frame in an iden-

tical manner.

Program selector

■Decoding of FIC (Fast Information Channel) and

up to six service components

■4-bit soft decision Viterbi decoding

■320 kB decoding capacity

■432 unit deinterleaving capacity

■Error flag generated by re-encoding

■CRC syndrome calculation on each FIB

■4-bit parallel input and serial output (DAB3) inter-

faces

■256 K ×4 DRAM and L3 microcontroller interface

The SIVIC performs service selection, frequency and time-dein-

terleaving, and Viterbi decoding.

SIVIC

Audio source decoders

For details of the SAA250x family of audio MPEG decoders,

please refer to the Digital Audio section, page 8-12.

The channel decoder includes three main ICs: a differential

demodulator and DSP interface (FADIC), a program selector

(SIVIC) and the SAA2501 MPEG-1 or SAA2502 MPEG-2

audio source decoder. The whole chipset is suitable for small

DAB receivers.

SAA250X

TUNER IF

TUNER MODULE

FADIC SIVIC SAA2501

SAA2502 I2S

CONTROL

DSP

user interface

RAM

DIGITAL MODULE

MSB960

Multimedia PC 7-1

COMPACT DISC

7-2

Multimedia PC

COMPACT DISC CD SYSTEMS

As one of the pioneers of CD technology, Philips IC and system

solution offering for CD-audio, CD-ROM, CD-Recordable,

CD-i, Video-CD and other CD systems is so large, it is impossi-

ble to cover in detail in this document. Some key ICs and sys-

tems for CD-ROM/CD-recordable MPC applications are

described here; for a full round up, please refer to the separate

CD Designer’s Guide (12NC 9398 750 00952).

CD SYSTEMS

Philips makes a number of complete CD-ROM and CD-

Recordable system solutions, including all the ICs and compo-

nents needed to design a complete drive. Available from Philips

Key Modules, comprehensive starter-kits include a fully opera-

tional sample, and all the technical documentation and software.

They are guaranteed to meet specification, so are a valuable tool

for simplifying design-in for manufacturers, reducing both costs

and time-to-market. The systems themselves are in fact capable

of higher performance than those published in the starter kit

specifications so with careful optimization, drive manufacturers

can easily differentiate their products in a highly competitive

market.

A pre-programmed, masked microcontroller is available, han-

dling all the servo and decoding functions and offering a com-

prehensive control interface to reduce design effort further. The

system also includes a serial control interface (S2B) with serial

digital data output for further processing by a CD-ROM block

decoder.

The ROM 65200 subsystem for economy 8× systems is similar,

but uses a different loader/mechanism; the ROM 65100 is a 6×

subsystem. All three subsystems are also available as complete

system solutions, including either the SAA7388 (see page 7-6) or

SAA7385 (see page 7-7) block decoder/controller ICs, for IDE

and SCSI versions respectively.

MSC301

OQ8875

DIODE AMPLIFIER

LASER SUPPLY

CDM12.10

3-BEAM

MECHANISM WITH

BRUSHLESS MOTOR

L1270

CD LOADER

TDA7072A

SERVO

DRIVER

CDT6xx

MICRO

CONTROLLER

BA5934

DIGITAL

SERVO

DRIVERS

OQ8868

DIGITAL

SERVO

CONTROLLER

LO9585/88

COMPACT

DISC

DECODER

LO9585/88

COMPACT

DISC

DECODER

S2B bus

audio

L/R

ROM 65300 CD-ROM ENGINE

ROM 65XXX

6×and 8×CD-ROM system solutions

ROM 65XXX are families of subsystems and complete, pre-

developed system solutions for economy 6×and 8×, and high-

end 8×CD-ROM drives.

The high performance 8×solutions are based around the ROM

65300 subsystem, a pre-developed CD-ROM engine optimized

to deliver an average sustained data rate of 1200 kbytes/s,

115 ms seek time and 140 ms access time. It uses a fast, low

power CD decoder IC with sophisticated error correction specif-

ically for CD-ROM systems.

Its specially developed mechanism features a brushless disc

motor optimized for high speed operation, delivering long life-

time and high reliability. Available in a tray-type loader, which

also has special suspension units to provide the extra damping

and disc clamping required for sustained high performance 8×

operation, the complete engine is designed for installation in a

5.25" half-height disk bay.

For fast radial access, the sledge transmission has ultra-high ratio

gearing, controlled by an adjustment-free servo system. The

servo processor uses an FTC (Fast Track Count) algorithm opti-

mized for high speed performance and has other features such as

enhanced tracking capabilities and automatic initialization. The

engine also includes the diode amplifier and laser supply which,

by being incorporated onto the sledge of the CDM mechanism,

improves the SNR as the diode currents are converted to HF sig-

nals close to the source.

7-3

Multimedia PC

CD-ROM system solution

Philips latest CD-ROM solution is capable of 12× operation,

achieving an average sustained data transfer rate of 1800 kbytes/s,

110 ms seek time and 120-135 ms access time. This exceptional

performance is achieved using the SAA7348 All Compact disc

Engine (ACE), which combines CD decoding, servo-processing

and microcontroller functions all on one chip (see next page). It

also has a completely new tray loader and mechanism, dust tight

and vibration free, specially developed for operation at these very

high speeds. As with the ROM 65XXX systems, the engine is

available in both IDE and SCSI system solution versions.

Based on the CDU 2600 CD-R subsystem, the CDU Data

Engine forms the basis for a complete data CD-R drive, deliver-

ing 2× speed recording and playback at up to 6× speed, with a

fast access time of <300 ms at 6× operation.

The Recorder CDU 2600 subsystem provides all the basic func-

tions for a CD-Recordable application. It incorporates a CD-

encoder and decoder and a dedicated tray-type CD loader, fully

pre-wired with a simple interface and incorporating all the spe-

cial suspension and clamping features required for recordable

applications. A dedicated pre-programmed microcontroller

ensures reliable operation and provides a versatile interface; it

handles all servo, calibration and laser control functions during

read, write and access operations, as well as controlling CD-

decoding/encoding operations. The subsystem can also be used

in audio applications.

The Data Engine incorporates the high performance SAA7390

CD-R controller and host interface IC, providing both SCSI

and ATAPI solutions (see page 7-8). A complete CD-R drive

built around the CDU 2600 will fit into a standard 5.25" drive.

Also available is the Recorder E65400 and its derivative Data

Engine (D65420), which provides 2× speed write and 4× speed

read.

MSC297

OQ8875

DIODE AMPLIFIER

LASER SUPPLY

ROM1312

3-BEAM

MECHANISM WITH

BRUSHLESS MOTOR

SAA7348

ACE1

DECODER

DIGITAL SERVO

CONTROLLER

TDA1545

DA CONVERTOR

POWER

AMPLIFIER

MOTOR CONTROL

MOTOR DRIVER

ROM1312

CD LOADER

SAA7388GP

BLOCKDECODER

INTERFACE (ELM)

EXTERNAL 1 MB DRAM

I2S

audio L/R

S2B bus

I2C bus

MICRO

CONTROLLER

IDE-bus

with

ATAPI

commands

ROM1312 CD-ROM SUB-SYSTEM

MSC300

TDA1372HP

SIGNAL

PROCESSOR

CDM2600

3-BEAM

MECHANISM

CDL2600

CD LOADER

OQ8845T

DIGITAL

SERVO

CONTROLLER

LO9600

DECICATED

MICRO

CONTROLLER

57SZA1010T

DIGITAL

SERVO

DRIVERS

TDA1371HP

COMPACT

DISC

ENCODER

LO9585

COMPACT

DISC

ENCODER

serial user interface

subcode input

serial data input

serial data output

R . . . W subcode

digital output

COMPACT DISC CD SYSTEMS

ROA 1312

CD-RECORDABLE SYSTEMS

7-4

Multimedia PC

SAA7348

ACE (All Compact disc Engine)

■High speed (up to 12×) integrated CD-engine

■All standard decoder functions implemented

digitally on-chip

■Built-in access procedure

■Radial and focus servo loop with automatic closed

loop gain

■Sledge motor servo loop with pulsed sledge

support

■Lock-to-disc mode

■Low focus noise

■Audio data peak level detection

■Full error correction strategy (t = 2 and e = 4)

■2-4 times oversampling integrated digital filter

including fs mode

■FIFO overflow concealment for rotational shock

resistance

■Kill interface for DAC deactivation during digital

silence

■EBU interface handles audio and data

■S2B serial interface with host controller

The SAA7348 is a highly integrated IC incorporating the func-

tionality of a CD decoder and digital servo driver. In addition, a

large part of the glue logic from the ROM65000 CD-engine

family has also been integrated to minimize external component

count. Although developed primarily for high speed CD-ROM

applications, its very high level of integration makes the

SAA7348 ideal for a wide range of other CD applications.

The high speed servo includes four current input ADCs for

focus and two for the radial signals. A comparator input for the

Fast Track Count signal is available to achieve high performance

jumping. There are two subcode interfaces: the V4 and the EIAJ

set. Audio functions include de-emphasis as well as the KILL

function and there is a mono output selection. An audio output

clock for Bitstream-CC DACs is provided and the audio serial

data interface can be set to I2S or EIAJ mode.

The decoder can address 16 programmable registers. Control is

via an internal micro supporting external memory, or via an

external micro.

COMPACT DISC INTEGRATED CD DECODERS

MSC232

SERIAL

REGs

RAM

QCLV

TELE

SFR

CPU

CORE

SAA7348

RAM

ROM

PLA

SERVO

DECODER

LFinPLLHFin

QUICK REFERENCE DATA

Power supply Core 3.3 V

I/O pads 5 V

Analog supply current t.b.f.

Digital supply current t.b.f.

Package LQFP100 (SOT407-1)

Datasheet Contact Philips

7-5

Multimedia PC

COMPACT DISC INTEGRATED CD DECODERS

CD7: SAA7370(B)GP

10×single-chip digital servo processor and

compact disc decoder

■All standard decoder functions implemented

digitally

■Multi-speed decoder with up to 10×playback

speeds

■Full error correction strategy; t = 2 (C1 frames)

and e = 4 (C2 frames)

■Full EIAJ CP-2401 CD-graphics interface

■±8 frame FIFO overflow concealment for rotation-

al shock resistance

■Digital audio (EBU) interface provides 32-bit word,

IEC958-format biphasemark outputs

■2 to 4 times oversampling digital filter, including fs

mode

■Audio data peak level detection

■Kill interface for DAC deactivation during digital

silence

■Diode signal pre-processing

■Focus, radial and sledge-motor servo loop

■Three-line serial interface via microcontroller

■Fast radial jump or access procedure

■Low focus noise

■Automatic closed loop gain control available for

focus and radial loops

■Radial jumps at up to 80 kHz (or 160 kHz ‘B’

version)

■V4 interface provides subcode data in a similar

format to RS232

All ICs in the CD7 family combine the functions of a CD

decoder and digital servo processor. They have all the control

and start-up procedures found in previous Philips’ systems and

also including a number of high-level functions such as auto-

matic error handling, automatic sequencers, timer interrupts, and

high-level status and interfaces for the decoder and interrupts.

TIMING

TEST

SELPLL

CRIN

CROUT

CL16

CL11

CL4

SBSY

SFSY

SUB

RCK

STATUS

RESET

V1,V2 V3 to V5 KILL

MSB918

TEST1 to

TEST3

SRAM

EFM

DEMODULATOR

RAM

ADDRESSER

SUBCODE

PROCESSOR

DIGITAL

PLL

VREF

GENERATOR

VRH

ADC PREPROCESSING CONTROL

FUNCTION

FRONT

END

HFIN

HFREF

ISLICE

IREF

MICRO-

PROCESSOR

INTERFACE

SCL

SDA

RAB

SILD

R1,2

VRL IREFT

to D4

CONTROL

PART

DECODER

MICRO-

PROCESSOR

INTERFACE VERSATILE

PINS INTERFACE KILL

SCLK

DOBM

C2FAIL

CFLG

LDON

MOTO1,2

SAA7370BGP

FLAGS

WCLK

DATA

SERIAL

DATA

INTERFACE

EBU

INTERFACE

ERROR

CORRECTOR

AUDIO

PROCESSOR

MOTOR

CONTROL

OUTPUT

STAGES

PEAK

DETECT

Signals from the photo-detector in a two-stage three-beam com-

pact disc system are first A-to-D converted and then processed

into separate decoder and focus-servo loop signals, for input to

the IC’s servo control. The decoder signals are then conditioned

using logic circuits to obtain control signals. A normalized focus

error signal is produced, used to provide extra protection for

track-loss generation, drop out detection and the focus start-up

procedure. This provides optimum system performance and as

the chip automatically adjusts conditioning levels, the need for

external factory adjustments is removed.

The chip includes a lock-to-disc or CAV (Constant Angular

Velocity) mode for playback of discs whose input data-rates vary

from the inside to the outside of the disc. It supports pulsed

sledge signals and can perform radial jumps; during long jumps

the fast radial actuator is dampened electronically. The

‘

B’ vari-

ant includes an on-chip clock multiplier allowing crystals of

8.4672 MHz and 16.9344 MHz to be used. Both focus and

radial control loops can be controlled automatically for short

periods, such as at the start of a new disc.

QUICK REFERENCE DATA

Power supply 5 V

Total supply current 49 mA

Package QFP64 (SOT393-1)

Datasheet Contact Philips

7-6

Multimedia PC

COMPACT DISC CD-ROM & CD-R/E DATAPATH ICS

Philips SAA738x is a family of IDE/SCSI CD-ROM block

decoders/interfaces ICs for high speed drives, while the

SAA7390 is the first CD-recordable/erasable interface IC to sup-

port both ATAPI and SCSI systems. All offer real-time third

level error correction and detection and CRC checking of mode

1 (CD-ROM) and mode 2 form 1 (CD-i) sectors.

SAA7388 SAA7385 SAA7390

ATAPI/SCSI ATAPI SCSI-2 ATAPI/SCSI

Data rates up to 12×up to 12×8×read, 4×write

Transfer burst rate 11.1 Mbytes/s 10 Mbytes/s 16.9 Mbytes/s

Max. external memory 16 Mbits DRAM 256 kbytes or 4 Mbyte DRAM

128 kbytes SRAM 1 Mbyte DRAM

Supports Q-W subcode Yes No Yes

Dedicated S2B UART interface No Yes Yes

SAA7388

Error corrector and host interface

(up to 12×)

■Host transfer burst rate of 11.1 Mbytes/s

■Corrects two errors per symbol with erasure

correction

■36-kbit erco buffer RAM

■12 byte command and status FIFOs

■All ATAPI registers are present in the hardware

■Supports Q-W subcode buffering, de-interleaving

and correction

■Compatible with the Sanyo LC89510, Oak

OTI-012 and IDE/ATA/ATAPI hard disk interfaces

The SAA7388 is a block decoder and buffer manager for up to

12× CD-ROM applications, simultaneously performing input

data buffering, error correction and host data transfer. Input

data to the CD-DSP interface is programmable as I2S or EIAJ

format and is first synchronized, before being decoded and writ-

ten to the buffer memory, which can hold one full data sector.

The error corrector performs two pass correction in real time in

9-bit, 4096 byte words before an EDC (Electronic Data Check)

is performed. Sector header and sub-header are then written to

the header registers and the microcontroller reads the decoder

status, header information and sector start address.

Data transfer between the decoders and an external microcon-

troller, usually an 8051 derivative, is handled via a Motorola

SPI-based interface, which can be programmed for Sanyo, Oak

or ATA compatibility. Mapping of the external memory is

QUICK REFERENCE DATA

Power supply 5 V (3.3 V)

Total supply current 60 mA

Package QFP80 (SOT318-2)

Datasheet (12NC) 9397 750 00808

MSB911 - 1

CS1/HEN

HWR

HRD

HD0 to HD7

HD8 to HD15

DA0/CMD

IORDY/WAIT/HFBLB

SCRST/STEN

DMARQ/DTEN

DMACK

DA1

DA2/EJECT

CS2/SELRQ

IOCS16

SDA

SCL

INT

RESET

SYN

IRQ/EOP/HFBC

RA16/CAS

RA15/RAS

RWE

CRIN

CROUT

RD0 to RD7

RA6 to RA14

RA0 to RA5

HOST INTERFACE OSCILLATOR

TEST

ERROR

CORRECTOR

SRAM

CACHE

DECODER

SERIAL

INTERFACE

MEMORY

MANAGER

µP

INTERFACE

SAA7388

SFSY

RCK

SUB

BCK

DATA

C2PO

TEST1, 2

under software control and with the use of a RAM test executed

by the microcontroller, the SAA7380/88 can work with partially

defective dynamic memory units.

7-7

Multimedia PC

High performance CD-ROM controller

(up to 12×)

■NCR53CF94 equivalent SCSI-2 controller allows

operation at up to 10 Mbytes/s

■Single transfers of up to 16 Mbytes

■SCAM (SCSI Configuration AutoMatically)

function for plug and play

■48 mA on-chip SCSI drivers

■Front-end interface includes a block decoder, a

sector sequencer, a 212 ms watchdog timer and a

subcode interface

■80C32 microcontroller with 256 ×8 scratchpad

SRAM

■Three timer/event counters

■Red book audio pass through

■Input clock synthesizer

The SAA7385 CD-ROM controller incorporates a SCSI-2 con-

troller, microcontroller and all the necessary front-end interface

logic to provide a single-chip, high performance digital solution

for up to 12× speed systems.

The SCSI controller is software compatible with previous mem-

bers of the 53C90 family. It has a high speed 16-bit DMA inter-

face to the DRAM buffer manager, which has ten level arbitra-

tion logic and uses page mode access for high speed error correc-

tion and SCSI data transfer. Third level error corrections are

automatically written to the DRAM frame buffer.

The microcontroller has a programmable full duplex serial chan-

nel and eight general purpose I/O pins, and all control registers

can be mapped into the 80C32s special function memory space.

All error correction is handled by dedicated hardware, signifi-

cantly reducing microcontroller workload.

SAA7385

COMPACT DISC CD-ROM & CD-R/E DATAPATH ICS

QUICK REFERENCE DATA

Power supply 5 V

Total supply current t.b.f.

Package QFP128

Datasheet (12NC) 9397 750 00917

MSB908

DATA

CONVERTOR

SUBCODE

UART

LAYERED

ERROR

CORRECTOR BUFFER

MAPPER 53CF94

SCSI

data subcode

BUFFER MANAGER

MICROCONTROLLER INTERFACE

80C32 MICROCONTROLLER DEBUG UART

data

subcode

DECODER

DSIC

DSP

64k x 8 ROM

256k x 8

DRAM

SAA7385

7-8

Multimedia PC

COMPACT DISC CD-ROM & CD-R/E DATAPATH ICS

SAA7390

High speed CD-recordable block

decoder/encoder

■Generic interface with 16.9 Mbytes/s transfer for

external SCSI or ATAPI hosts

■Incorporates all digital electronics to connect a

CD-65 based decoder to a host.

■Designed for 8×read and 4×write speeds

■Third level error correction and third layer ECC

syndrome calculation

■Third layer encode/decode and buffer

management

■Block oriented host transfers

■Supports 256 KB, 1 MB or 4 MB of 70 ns low-cost

DRAM

■C-flag interface provides an absolute time stamp

■Ten level arbitration logic in buffer manager

■Authoring software available

The SAA7390 CD-recordable/erasable controller chip provides a

data path from the host to the CDCEP (CD encoder) for CD-

R/E operation in both SCSI and ATAPI systems. It combines

the interface logic, decoding/encoding and other sophisticated

functions required for complete CD-R/E applications.

In has on-board 80C32 microcontroller and 53CF90B or

53CF92A/B fast SCSI processor interfaces (which may also use

an ATAPI processor), needed to provide full block encode and

decode functions. The on-board block decoder function accepts

parallel data from the buffer manager, serializes it, calculates the

CRC and third-level ECC parity bytes when necessary and out-

puts them to the CDCEP using a special data clock.

An ASSS (Automatic Sector Size Select) function checks the

sub-header of Mode 2 data to determine the length of data

blocks stored within the memory buffer, with the rest of the

frame data loaded into the 3 kbyte buffer. This sector buffer

supports a number of data block sizes including Red Book

audio, fixed length sectors, and yellow and green book modes

and forms.

MSB889

DATA

CONVERTER

& SUB-CODE

UART

data subcode

data

subcode

c-flag

DECODER LAYERED

ERROR

CORRECTOR BUFFER

MAPPER GENERIC

EXTERNAL

INTERFACE

MICROCONTROLLER INTERFACE

BUFFER MANAGER

BASIC

ENGINE WRITE I/F

80C32 MICROCONTROLLER

S2B UART

SCSI or

ATAPI

interface

128K x 8 ROM

256K x 8 or 4M x 8 DRAM BUFFER

ENCODE

SAA7390

QUICK REFERENCE DATA

Power supply 5 V

Total supply current t.b.f.

Package QFP128

Datasheet (12NC) 9397 750 00942

7-9

Multimedia PC

Photodetector amplifiers and laser supply

■Six input buffer amplifiers with low pass filtering

and virtually no offset

■HF data amplifier with a high- or low-gain mode

■Fully automatic laser control including stabilisation

and on/off switch with separate supply for power

reduction

■Optimized interconnection between the pick-up

detector and digital servo processor

■Adjustable laser bandwidth and laser switch-on

current slope

■N- and p- sub laser monitor

■Built-in equalizers provide single/double speed

switching ‘on-the-fly’

■Constant laser output regardless of ageing

■Small outline package allows close mounting to

photo-diodes on the CD mechanism

This IC derives filtered currents for tracking, focus control and

the HF data signal for the CD decoder. They can be used with a

wide variety of 3-beam/sledge optics with p- and n-sub lasers

with single or double Foucault focus error detectors.

TDA1300T

COMPACT DISC DIODE AMPLIFICATION & LASER SUPPLY

1.5x

I/V

1.5x

I6in Id6out

I5in

I4in

I3in

I2in

I1in

I6 O6

Id5out O5

Id4out O4

Id3out O3

Id2out O2

Id1out

VDDL

LDON

RFE

VDD

GND

Vgap

OTA ILO

ON/OFFSUPPLY

TDA1300T

ADJ

−4

Icsin

(N-sub) or

IADJ (P-sub)

Vmon (N-sub) or

Imon (P-sub)

MSC187

QUICK REFERENCE DATA

Power supply 3.0 to 5.5 V

Diode current amplification (typ.) 1.55

Equalization delay time 320 ns

Laser supply output current (max.) 100 mA

Package SO24L

Datasheet (12NC) 9397 750 00441

7-10

Multimedia PC

COMPACT DISC DIODE AMPLIFICATION & LASER SUPPLY

Data amplifier and laser supply (H-DALAS)

■Six voltage-input buffer amplifiers with low pass

filtering and virtually no offset

■Universal photodiode IC interface using internal

conversion resistors

■Broadband RF data amplifier designed for

sustained 16×data rates (up to 18×max)

■Selectable RF gain for CD-Rewritable/CD-ROM

applications

■Programmable RF/FTC gain for optimal dynamic

range and playability

■Radial error signal for fast track counting

■Fully automatic laser control including stabilization

and an on/off switch, plus a separate supply for

power efficiency

■Automatic monitor diode polarity selection

(n-sub/p-sub)

■Adjustable laser bandwidth and laser switch-on

current slope using external capacitor

■Protection circuit to prevent laser damage due to

supply-voltage dip

■Optimized interconnection between data amplifier

and Philips’ digital servo/decoder circuits

This data amplifier and laser supply circuit is designed to pro-

vide system flexibility and an optimal interface to Philips’ cur-

rent input servo-decoders. The RF amplifier has a programma-

ble bandwidth, allowing the IC to be used in CD audio or CD-

ROM systems with up to 16× sustained data rates. A program-

mable RF gain and a gain switch to select CD or CD-R/E sys-

tems provides optimal playability.

TZA1015

QUICK REFERENCE DATA

Power supply 5 V

LF amplifier channel matching (max.) 1% FS

–3 dB bandwidth 80 kHz

RF amplifier –3 dB bandwidth 40 MHz

max flatness delay 0.9 ns

Laser supply max output current –100 mA

p-type monitor input 0.15 V

n-type monitor output VDD - 0.15 V

Package SO28 (SOT136)

Datasheet Contact Philips

MSC302

+−

LF AND RF SUPPLY

TZA1015

VDDLF VDDRF

Vref

VCOM

GSE

GARF

VDDL

LDON

GND

Vgop

I/V

7-11

Multimedia PC

COMPACT DISC DIGITAL SERVO CONTROLLER

OQ8868

Digital servo controller (DSIC-S)

■Focus, radial and sledge servo loop

■Built-in access procedure

■Sophisticated track loss detection mechanism

■Automatic focus start-up procedure and in-lock

indication (incl. fast focus restart)

■Automatic gain control for the complete focus and

radial loop

■Defect and shock detectors

■Flexible system oscillator

■Extended radial error signal

■Automatic initialization and jump procedure for

radial servo

■Automatic offset and gain control for radial error

■Single/double Foucault and astigmatic focusing

The highly integrated OQ8868 digital servo controller is opti-

mized for CD-ROM applications, providing all servo functions

for two-stage CD-systems except the spindle motor control. It

accepts diode currents and drives various power stages, and the

servo loops are very low noise. It can be tailored to the require-

ments of a broad range of CD-systems by adjusting the servo

characteristics via the fast three-wire serial interface.

MSC212

ANALOG-TO-DIGITAL

CONVERTER

ANALOG-TO-DIGITAL

CONVERTER

ANALOG-TO-DIGITAL

CONVERTER

ANALOG-TO-DIGITAL

CONVERTER

ANALOG-TO-DIGITAL

CONVERTER

ANALOG-TO-DIGITAL

CONVERTER

ANALOG-TO-DIGITAL

CONVERTER

MONITOR

ERROR

DETECTION

CONTROL

REFERENCE

OSCILATOR

TEST

COMM

VDDD

VSSD

CDID

RAB

FOK

LDO

RSTO

OTD

INTREQ

DEFO

CLKO

SIDA/SDA

SICL/SCL

SILD

ENIIC

RSTI

FTC

VDDA

XTLR

DEFI

VSSA

VrefH

VrefL

XTALO

XTALI

TEST1

TEST2

OQ8868

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 5 mA

Digital supply current 17 mA

Maximum quiescent current 10 µA

Package QFP44 (SOT307-2)

Datasheet (12NC) 9397 750 00785

7-12

Multimedia PC

Digital Servo Driver (DSD1)

■Optimized low-power, low-voltage IC for 3-beam,

2-stage CD optics

■Three gain-stabilized class-D amplifiers

■On-board laser-diode SMPS minimizes power

losses during DC-to-DC conversion

■Continuous gain control compensates for battery

voltage fluctuations

■Battery voltage indication

■Output resistance <4 Ω

■Suppression of idle switching

The TDA1303T provides three identical output driver func-

tions; the amplifiers receive PDM signals from the servo con-

troller (integrated into the CD7 CD-decoder ICs) and process

them for the radial tracking and focus actuators, and the sledge

motor. It is suitable for portable applications.

TDA1303T

COMPACT DISC SERVO POWER DRIVERS

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current (stabilized) 1 mA

Digital supply current (stabilized) 1 mA

Package SO24L (SOT137-1)

Datasheet Handbook IC01

MSC220

SLEDGE

DRIVER

notch filters

TDA1303T

OUTPUT

DRIVER

CONTROL

ADC

FOCUS

DRIVER

RADIAL

DRIVER

BATTERY

VOLTAGE

INDICATOR

SWITCHED-MODE

POWER

CONTROL

CLK

VDDA

Vctrl

Vref

VIs

SILO

SICL

LASER

DRIVER

VSS2

VDDD2

VDDD1

VSS1

enable Vol

SIDA

ORA(neg)

ORA(pos)

OFO(neg)

OFO(pos)

OSL(neg)

OSL(pos)

7-13

Multimedia PC

COMPACT DISC SERVO POWER DRIVERS

Triple digital servo driver (DSD2/DSD3)

■Three, 1-bit class-D actuator drivers for focus,

radial and sledge

■Separate power supply pins for all drivers

■Built-in high efficiency digital notch filters

■Enable input for focus/radial and sledge drivers

■Differential output for all drivers

Integrating class-D power drivers specifically designed for digital

servo applications allows these digital servo drivers to deliver

much higher efficiency than conventional analog drivers. It also

produces very highly integrated ICs, reducing the number of

external components required for a complete digital servo loop.

The SZA1010 is the successor to the OQ8844, offering addi-

tional features such as a radial tri-state selection pin for the radial

output drive and the ability to handle clock frequencies up to

10 MHz.

OQ8844/SZA1010

QUICK REFERENCE DATA OQ8844 SZA1010

Power supply (all driver pins) 5 V 5 V

Actuator driver (max. bridge resistance) Focus 4.1 Ω4 Ω

Radial 4.6 Ω4 Ω

Sledge 3.1 Ω2 Ω

Supply current (max.) Focus 250 mA 250 mA

Radial 250 mA 250 mA

Sledge 560 mA 560 mA

Input clock frequency (typ.) 4.2336 MHz 10 MHz

Package SO20 (SOT163-1) SO20 (SOT163-1)

Datasheet (12NC) 9397 750 00471 Contact Philips

MSC299

DIGITAL NOTCH

FILTER END STAGE

H-BRIDGE

END STAGE

H-BRIDGE

END STAGE

H-BRIDGE

DIGITAL NOTCH

FILTER

DIGITAL NOTCH

FILTER

CONTROL

SL+

FO+

RA+

VDDD

VSSD VSSR tristate VSSS/VSSF

VDDR VDDF VDDS

CLI

SLC

FOC

RAC

EN1

EN2

SZA1010

7-14

Multimedia PC

BTL motor drive circuits

■Single BTL and dual BTL versions

■BTL configuration allows bi-directional direct

currents to be fed to the loads

■Very high slew rate

■High output current (0.6 A)

■Suitable for handling PWM signals up to 176 kHz

■Short circuit and thermal protection, with ESD

protection on all pins

■Single 3 V to 18 V power supply

The TDA7072A(T) and TDA7073A(T) ICs are respectively

single and dual Bridge-Tied Load (BTL) CD servo power dri-

vers, receiving control signals from the servo controller (integrat-

ed into the CD7 CD-decoder ICs) and processing them for the

radial tracking and focus actuators, and the sledge and disc drive

motors. They have a very low output offset voltage and built-in

MCL protection, and are suitable for headphone applications.

COMPACT DISC SERVO POWER DRIVERS

TDA7072A(T)/73A(T)

QUICK REFERENCE DATA TDA7072A(T) TDA7073A(T)

Power supply 5 V 5 V

Total quiescent current 4 mA 8 mA

Input bias current 100 nA 100 nA

Slew rate 12 12

Cut-off frequency 1.5 MHz 1.5 MHz

Package TDA707xA DIP8 DIP16

TDA707xAT SO8 SO16L

Datasheet Handbook IC01 Handbook IC01

positive input 1

I + i

I – i

negative input 1

positive output 1

negative output 1

MSC196

positive input 2

TDA7073A

TDA7073AT

I + i

I – i

negative input 2

positive output 2

negative output 2

ΙΙ

SHORT - CIRCUIT AND

THERMAL PROTECTION

8-1

Multimedia PC

DIGITAL AUDIO

8-2 Multimedia PC

Low power, low voltage stereo CODEC

■Low voltage (2.7 V), low power CODEC

■Bitstream ADC and bitstream/CC DAC

■Separate power down modes for ADC and DAC

■Integrated high-pass filter to cancel DC offset

(ADC)

■Analog loop through function

■256 fssystem clock frequency for ADC and DAC

■192 fs, 256 fsand 384 fsDAC clock frequencies

■Digital de-emphasis (DAC)

■Multiple digital I/O formats

■Overload detector enabling automatic recording

level adjustment (ADC)

■DAC requires only one capacitor for analog post-

filtering

The TDA1309H combines a bitstream ADC sampling stereo

left and right channels simultaneously, with a bitstream/CC

DAC to provide a low power, low voltage stereo CODEC for

portable digital equipment with recording and playback func-

tions. The ADC uses a serial IIR filter to produce a fairly linear

phase response up to 15 kHz. The DAC section includes a digi-

TDA1309H

DIGITAL AUDIO CODECs

MSB206 - 1

DIGITAL

INTERFACE

ANLPTR

ADPON

ADSDA

ADBCK

ADWS

ADENB

DIGITAL

INTERFACE

DAPON

DASDADAWS

DABCK

VSS-10

DIGITAL

FILTER

DAC

DACR OUTR

analog

output

DAC

analog

output

DACL OUTL

DAREF

DADEM

DE-EMPH

TEST1

SYSCLK CLKEDOE

TEST0 MODE2

MODE1

MODE0

MODE SELECT

DIGITAL

FILTER

ADC

analog

input

OVLOAD

VRP VRN

BAORBAIRADREF

BAIL BAOL

analog

input

IREF

Idec

CURRENT

TDA1309H

tal up-sample filter, partly IIR and partly FIR, with a virtually

linear phase response up to 15 kHz.

Separate power down modes on both ADC and DAC allow

power reduction when either section is not in use and the loop

through function bypasses the ADC/DAC and filtering for ana-

log recording/playback, further reducing consumption. 16- and

18-bit I2S-bus and LSB fixed formats are supported.

QUICK REFERENCE DATA

Power supply 3 V

ADC Analog supply current 8 mA

Digital supply current 0.2 mA

Typical THD at 0 dB –85 dB

SNR 95 dB

DAC Analog supply current 3.5 mA

Digital supply current 0.2 mA

Typical THD at 0 dB –85 dB

SNR 99 dB (104 dB with

18-bit input)

Total power dissipation (max.) ADC 72 mW

DAC 84 mW

Package QFP44 (SOT307-1)

Datasheet (12NC) 9397 750 00879

8-3

Multimedia PC

16-bit stereo CODEC with FM synthesis

■16-bit Bitstream AD/DA converter

■Six channel MPC3 compatible digital mixer, with

full digital mixing on all audio channels

■Full duplex operation with different input and out-

put sample rates

■Six stereo input channels (three analog and three

digital)

■Allows recording and playback mixing to be

handled separately

■Integrated digital FM synthesis emulation and

Philips Incredible Sound 3D enhancement

■Full stereo I/O at sample rates from 3.6 kHz to

55 kHz in infinite steps

■Built-in interfaces for MIDI MPU-401, joystick,

wave table synthesis and OPLx

■Sample rate conversion on all digital inputs and

outputs

■Preamplifier with AGC for direct microphone

input

■24 mA ISA-bus drive capability

■16-bit ISA address decode

■Type ‘F’ DMA timing

■Power management

■Supports IMA ADPCM, A-Law and µ-Law com-

pression and decompression

TDA1396

MSC230

I/O

PROCESSING

FOR ANALOG

AND DIGITAL

SIGNALS

3 ANALOG IN

2 DIGITAL IN

1 DIGITAL OUT

6-CHANNEL

DIGITAL MIXER D/A OUTPUT

CONVERSION

SYNTHESIZER

3D ENHANCED

SOUND

VOLUME

AND TONE

MICRO

CONTROLLER

JOYSTICK

AND VOLUME

UP/DOWN

INTERFACE

MIDI

INTERFACE

1 INPUT

AND

1 OUTPUT

SAMPLE RATE

CONVERTER

ISA INTERFACE

WITH

PLUG & PLAY

COMPATIBILITY

REGISTERS

GAME

SOUND BLASTER 16

WINDOWS SOUND

SYSTEM

2 INPUT

SAMPLE RATE

CONVERTERS ISA

line out

MIDI I/O

DIGITAL

OUT

DIGITAL

CD-ROM

line in

microphone

DIGITAL

GAME

VOLUME

TDA1396

QUICK REFERENCE DATA

Power supply Core & analog 3.3 V

I/O 5 V

Supply current 3.3 V 180 mA

5 V 10 mA

THD + noise (0 dB) –85 dB

SNR 90 dBA

Package TQFP128 (SOT425-1)

Datasheet (12NC) 9397 750 00894

DIGITAL AUDIO CODECs

As a 16-bit true stereo audio CODEC, the TDA1396 is a highly

integrated and cost effective digital audio solution for PC sound-

card, notebook and motherboard applications. Using Philips’

patented Bitstream technology, it delivers a dynamic range and

level of audio performance that enables the recording and play-

back of high quality stereo music.

The TDA1396 is fully compatible with all current PC standards

including Soundblaster and Windows (both 3.1x and ‘95)

Sound System. It includes a ‘Plug and Play’ interface supporting

up to six logical devices and has a built in game port with quad

timer. It also supports host software acoustic echo cancellation.

8-4 Multimedia PC

Single-chip audio processor

■Incorporates DACs, digital de-emphasis filters, vol-

ume and tone control, and a headphone amplifier

■Accepts up to 20-bit serial input in I2S or

LSB-justified format

■Up to 128 times oversampling

■Cascaded 4-stage digital filter incorporates 2-stage

FIR filter and linear interpolator

■Noise-shaping filter delivers excellent THD and

noise figures

■Two separate dynamic ranges for the bass boost

filter

■Soft mute

■No zero crossing distortion

■Master and slave operation

Designed as a single-chip solution for all sound functions in

CD, MD and DCC personal stereo players, the TDA1548T

family of Bitstream/CC DACs also provides a complete sound

channel processing solution for multimedia PC applications and

dual-purpose CD-ROM drives. A selectable flat frequency

response allows the headphone outputs to be used as line out-

puts for driving speakers and its design means no bulky DC

blocking capacitors are needed in CD-ROM headphone driver

applications. With its low operating voltage and small package,

it is particularly suited to portable battery powered equipment,

including notebook PCs.

TDA1548T(Z)

DIGITAL AUDIO DSPs

QUICK REFERENCE DATA

Power supply 3 V

Supply current 16 mA

SNR 95 dB

Selectable system clock 64, 256 and 384 fs

THD + N at 0 dB –85 dB

Digital de-emphasis filter 44.1 kHz

Total power dissipation (max.) 50 mW

Package SSOP28

Datasheet (12NC) 9397 750 00773

MSB470 - 1

REFERENCE

SOURCE

16 (4-bit)

CALIBRATED

CURRENT

SINKS

LEFT

OUTPUT

SWITCHES

16 (4-bit)

CALIBRATED

CURRENT

SOURCES

OP1

RCONV1

2.2 kΩ

VREF

1 µF

GND OP3

VOL

IOL

1 nF

CEXT1

16 (4-bit)

CALIBRATED

CURRENT

SINKS

RIGHT

OUTPUT

SWITCHES

16 (4-bit)

CALIBRATED

CURRENT

SOURCES

OP1

RCONV2

2.2 kΩ

VOR

IOR

1 nF

CEXT2

VCOM

2nd ORDER

NOISE SHAPER

DATA

ENCODER

8 x OVERSAMPLING

(SAMPLE-AND-HOLD)

2nd ORDER

NOISE SHAPER

DATA

ENCODER

8 x OVERSAMPLING

(SAMPLE-AND-HOLD)

LINEAR INTERPOLATOR

FILTER STAGE 2

FILTER STAGE 1

SOUND CONTROL

SOFT MUTE CONTROL

VOLUME CONTROL

SERIAL DATA INPUT

1 FS

2 FS

4 FS

8 FS

OP ADREF

VDDO

GND

VDDA

GND

VOLUME

AND

SOUND

CONTROL

ADTR

ADBB

ADVC

AD3S

DEEM

MUTE

IF1 IF2 DATA WS BCK

MODE0

MODE1

TIMING

TDA1548T

SYSCLK

CLSEL

8-5

Multimedia PC

Single-chip audio processor

■On-chip filtering, DACs, postfiltering and buffering

■CD-ROM sound path features include separate

L & R soft mute, bilingual and monaural modes,

channel interchange or combinations

■DSP functions cover independent L & R volume

control, bass and treble boost, and de-emphasis

■I2S and LSB input formats

■Stereo line out with microprocessor-controlled

volume

■Stereo headphone output with potentiometer

volume control

■High linearity, wide dynamic range and low

distortion

The single-chip TDA1388 highly-integrated Bitstream/CC

filter-DAC offers many sound processing functions, providing a

complete sound reproduction solution in CD-ROM applica-

tions. It requires no analog postfilter and can be controlled by

static pins or by microcontroller interface.

TDA1388T/M

−

VDDA

APPL1

APPL2

ACPWS BCKDATAIF2IF1

APPL0

4fs

64fs

30 kΩ

VOL

Vref

FILTCL RCONV1 RCONV2

HPINL

HPOUTL

TDA1388

HPOUTR

VOR

FILTCR

MSC210

−

HPINR

−

16 (4-BIT)

CALIBRATED

CURRENT

SOURCES

16 (4-BIT)

CALIBRATED

CURRENT

SINKS

LEFT OUTPUT

SWITCHES

16 (4-BIT)

CALIBRATED

CURRENT

SOURCES

16 (4-BIT)

CALIBRATED

CURRENT

SINKS

RIGHT OUTPUT

SWITCHES

2nd-ORDER

NOISE

SHAPER

DATA

ENCODER

SAMPLE-AND-HOLD

16 × OVERSAMPLING

FILTER STAGE 1 + 2

SOFT MUTE

BASS BOOST AND TREBLE

VOLUME CONTROL

DE-EMPHASIS

CHANNEL INTERCHANGE

SERIAL DATA INPUT

2nd-ORDER

NOISE

SHAPER

DATA

ENCODER

REFERENCE

SOURCE

REFERENCE

SOURCE

FEATURE

CONTROL

UNIT

TIMING

SYSCLK

SYSSEL

QUICK REFERENCE DATA

Power supply 5 V

Supply current 22 mA

SNR 95 dBA

Dynamic range 95 dB

THD + N –85 dB line out

–65 dB headphone output

Total power dissipation 110 mW

Package TDA1388T SO28 (SOT136-1)

TDA1388TM SSOP28 (SOT341-1)

Datasheet (12NC) 9397 750 00516

DIGITAL AUDIO DSPs

8-6 Multimedia PC

General digital I/O input with DSP

(GDIN DSP)

■Up or down sample rate conversion over a wide

range of sample rates with no loss of quality

■Digital PLL with adaptive bandwidth for effective

jitter-free operation

■Fast and automatic detection and locking to the

input sampling rate, with continuous tracking

■Dedicated sub-code processing for CD

■ON-chip CS (consumer) and/or UC (professional)

demodulation and buffering

■IEC958 compatible decoder (for recording to CD)

with output sample rate tracking the input

■Converts I2S, Japanese or IEC958 input formats to

I2S or Japanese output formats

■Standard and 4-times over-sampled outputs

■8-bit gain/attenuation control

■‘Psycho-acoustic’ noise shaper effectively

eliminates quantization noise

■Audio outputs soft-muted during loop acquisition

DIGITAL AUDIO DSPs

TDA1373

QUICK REFERENCE DATA

Power supply 5 V

Total supply current 166 mA

Maximum output sample frequency 55 kHz

THD + N 20-bit data –113 dB

16-bit data –95 dB

Total power dissipation (max.) 830 mW

Package QFP64

Datasheet (12NC) 9397 750 00927

MSB468 - 1

IEC 958

DECODER

DATA

SLICER

4 x

UP-

SAMPLING

LOCK

DI1O

DI1D

CHANNEL

STATUS

EXTRACTION

USER

STATUS

EXTRACTION

PHASE

DETECTOR LOOP

FILTER HOLD VCO

GENERAL

CONTROL

CLOCK

SHOP

X-TAL

OSCILLATOR

768fo

384fo

256fo

128fo

CL04CL03CL02CL01CLIXTLOXTLIDALDCLCENCUSBS

MICRO-

CONTROLLER

INTERFACE

16 x

UP-

SAMPLING

VARIABLE

HOLD

FIFO

I S OUT

2I S IN

I S

OUT

I S

OUT

IN-BAND

NOISE

SHAPER

32 x

DOWN-

SAMPLING

4 x

DOWN-

SAMPLING

64fo

HOLD

ATTENUATOR BITSTREAM

DIGITAL

FILTER

DAC

OUTPUT

TDA1373H

DI2CDI2WDI2DFOWFOCFOD

AIL

AIR

RST

TST1

TST2

stereo

DI2

DI1S

FSL

DO2D

DO2W

DO2C

DO1D

DO1W

DO1C

AOL1

AOR1

CLD

DNI

DO1

DSO

DO2

MM0

DI2

DI1

MM1

The TDA1373H General Digital Input IC greatly simplifies the

interconnection of digital audio systems using different data for-

mats and sample rates. With the variety of professional and con-

sumer data formats in use, the high performance and exceptional

level of integrated functionality makes this chip ideal for profes-

sional quality sound mixing and recording equipment, universal

digital speaker systems, DCC and DAT recorders, digital ampli-

fiers and jitter killers. On-chip Bitstream inputs and filters for

use with external Bitstream ADCs/DACs allows the simple

building of high performance Bitstream CODECs.

8-7

Multimedia PC

Bitstream ADC

The SAA7360 is a very high performance ADC designed for

digital playback systems such as digital amplifiers, CD-record-

able and DCC. The decimation filters deliver high anti-aliasing

suppression and very low in-band ripple.

SAA7360

DIGITAL AUDIO ADCs

MSC217

SDM

TIMING

128f

OUTPUT

INTER-

FACE

TIMING

AND

CONTROL

BAOL BBOL NINL PINL DIOL DCKO XIN XOUT XSYS1 XSYS2

FSEL

WSEL

TSEL

ODF1

ODF2

SWSO

SCKO

SDO

SWSI

SCKI

CEN

RESET

TEST2

TEST1HPENDIORDSELBBORBAOR

1st

DECIMATION

FILTER

STAGE

VrefL

VrefR

SDM

Vref

MUX

2nd

DECIMATION

FILTER

STAGE

HIGH-

PASS

FILTER

MUX

128f

NINR PINR

BAIR

BAIL

VrefR

VrefL

VSSAT

VDDAT

VDACP

VDACN

Iref

SAA7360

VrefL

VrefR

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 39 mA

Digital supply current 43 mA

Total power dissipation 410 mW

Package QFP44 (SOT205A)

Datasheet (12NC) 9397 750 00081

Philips ADCs for MPC digital audio applications offer:

■Fully differential ADC using 3rd order Sigma-Delta

modulation

■Single-ended stereo inputs

■Uncommitted input buffer for filtering and

pre-scaling

■Four stage digital decimation filters

SAA7360 SAA7366

Anti-aliasing suppression > –93 dB > –60 dB

Typical THD + N at 0 dB –90 dB –80 dB

Crystal frequency 256 fs11.2896 MHz 12.288 MHz

512 fs22.5792 MHz –

Dynamic range 93 dB 90 dB

In-band ripple < 0.0002 dB < ±0.1 dB

Outputs 16- or 18-bit I2S 18-bit I2S

Two pseudo I2S formats One pseudo I2S format

■Up to 128 times oversampling

■Switchable high-pass filter to remove DC offsets

■Sampling rates between 18 and 53 kHz

■Master or slave operation

8-8 Multimedia PC

DIGITAL AUDIO ADCs

SAA7366

Bitstream ADC

■Integrated buffers for simple interfacing to analog

inputs

■4 flexible serial interface modes

■Overload detection of digital signal ≥–1 dB

amplitude

■Standby mode

Based on the SAA7360 and with the basic ADC features, the

SAA7366 has been designed for ease of application, minimal

board area and low cost. An economy ADC with a digital sec-

tion that can operate down to 3.4 V, it can be used for the

digital acquisition of analog audio signals from CD-recordable

drives and is particularly suitable for portable systems such as

DCC and DAT players.

MSC206

SAA7366

operational

amplifier REFERENCE

VOLTAGE

GENERATOR CLOCK

GENERATION

AND

CONTROL

SIGMA-

DELTA

MODULATOR

REFERENCE

CURRENT

GENERATOR TIMING

GENERATOR

DECIMATION FILTER

STAGE 1

COMB

FILTER

STAGE 2

3 HALF-BAND

FILTERS

HIGH-PASS

FILTER

SERIAL OUTPUT

INTERFACE

Ω3 k

1 pF

Ω10 k

Ω3 k

Ω10 k

SIGMA-

DELTA

MODULATOR

REFERENCE

VOLTAGE

GENERATOR

Ω3 k

1 pF

Ω10 k

Ω3 k

Ω10 k

operational

amplifier

operational

amplifier operational

amplifier

SFOR

STD

OVLD

CKIN

SDO

SWS

SCK

TEST1

HPEN

TEST2

SLAVE

VREFL

BIL

BOL

VDACP

VDACN

BOR

BIR

VREFR

IREF

QUICK REFERENCE DATA

Analog supply voltage 5 V

Digital supply voltage 3.4 to 5.5 V

Analog supply current 13 mA

Digital supply current 56 mA

Total power dissipation 345 mW

Standby power consumption 325 µW

Package SO24L (SOT137A)

Datasheet Handbook IC22

8-9

Multimedia PC

DIGITAL AUDIO STEREO FILTER DACs

Bitstream/CC filter DAC

■Cascaded 4-stage digital filter incorporating

2-stage FIR (Finite Impulse Response) filter, linear

interpolation and sample and hold circuit

■–12 dB fixed attenuation on volume control

■Soft mute and noise shaping

■No zero crossing distortion

■Digital de-emphasis filter for 32, 44.1 and 48 kHz

sampling rates

■I2S or ‘S’ 1fsserial input formats at 16-, 18- or

20-bits

■128 times oversampling at 256 ×fs; 96 times at

384 ×fs

The TDA1305T(AT) are BCC (Bitstream/Continuous-

Calibration) filter-DACs which use Philips’ Bitstream conver-

sion technique for optimum audio performance at low signal

levels, and the power-saving CC technique on larger signals.

TDA1305T(AT)

MSC197

REFERENCE

SOURCE

VOL

Vref

FILTER 16 (4 - BIT)

CURRENT

SOURCES

16 (4 - BIT)

CURRENT

SINKS

16 (4 - BIT)

CURRENT

SINKS

16 (4 - BIT)

CURRENT

SOURCES

FILTER

2nd - ORDER

NOISE SHAPING

ENCODING

AND

OUTPUT SWITCHING

L R 96 fs

L R 16 fs

6 x OVERSAMPLING

(SAMPLE & HOLD)

SERIAL

DATA

INPUT

FIR FILTER

(TDA1305)

IIR FILTER

(TDA1306)

DATA

BCK

TEST1

TDA1305T(AT)

TEST2

TIMING

XIN

XOUT

CDEC

CKSL1 CKSL2

CKSL1,2 DSMB

ATSB

DEEM1 MUSB

DEEM2

QUICK REFERENCE DATA

Power supply 3.4 to 5.5 V

Supply current 42 mA

Full scale output voltage 1.5 V

SNR 110 dB

Typical THD at 0 dB –90 dB

Total power dissipation (typ.) 210 mW

Package SO28 (SOT136-1)

Datasheet (12NC) 9397 750 00517

8-10 Multimedia PC

Noise shaping filter DAC

■Cascaded 4-stage digital filter incorporating IIR

filter stage

■–12 dB fixed attenuation on volume control

■Soft mute and noise shaping

■Variable volume control via microcontroller

interface

■No zero crossing distortion

■Digital de-emphasis filter at 44.1 kHz sampling

rate

■I2S or ‘S’ 1fsserial input formats at 16-, 18- or

20-bits

■4 times oversampling

■Selectable system clock 256 fsor 384 fs

(TDA1306T only)

■TDA1305T pin compatible (TDA1306T only)

The TDA1306T/86T dual Bitstream/CC-DACs are a low-cost

alternative to the TDA1305T. With their up-sampling filter and

noise shaping, they require only simple 1st-order analog post-fil-

tering. Two on-board operational amplifiers convert the digital-

to-analog current to an output voltage.

TDA1306T/TDA1386T

MSB204 - 2

REFERENCE

SOURCE

DIVIDER OP1

3 kΩ

RCONV2

FILTCR

VOR

RIGHT

OUTPUT

SWITCHES

NOISE

SHAPER

DIVIDER

OP1

3 kΩ

RCONV1

FILTCR

VOL

RIGHT

OUTPUT

SWITCHES

NOISE

SHAPER

VREF

VSSA

TEST1

TEST2

4 x f DIGITAL UP - SAMPLE

FILTER AND FEATURES

MODE

CONTROL

APP3

APP2

APP1

APP0

APPL

TIMING SYSCLK

CKSL1 CKSL2

SERIAL

DATA

INPUT

DATA

BCK

TDA1306T

TDA1386T

DIGITAL AUDIO STEREO FILTER DACs

QUICK REFERENCE DATA TDA1306T TDA1386T

Power supply 5 V 5 V

I2C-bus controlled No No

Typical THD at 0 dB –70 dB –70 dB

Typical SNR 110 dB 108 dB

RMS full scale output 1.1 V 1.1 V

Package SO24 (SOT137-1) SO24 (SOT137-1)

Datasheet Handbook IC22 9397 750 00518

8-11

Multimedia PC

■Low power consumption

■Space saving SO8 package

■Input format compatible with time multiplexed,

two’s complement and TTL

■18.4 MHz clock frequency

■Wide operating temperature range (–40 °C to

+85° C)

■Wide dynamic range (16-bit resolution)

■Single supply rail

■Output current and bias current proportional to

supply voltage

■Fast settling allows 2×, 4×and 8×oversampling

(serial input) or double speed operation at 4×

oversampling

■No crossing distortion

These DACs use the CC technique, where the largest bit-

currents are repeatedly generated by a single current reference

source. This duplication is based upon internal charge storage

principle, providing an accuracy insensitive to ageing, tempera-

ture matching and process variations. The accuracy of the

intrinsic high coarse current combined with a symmetrical offset

decoding principle eliminates zero-crossing distortion and

ensures high quality reproduction. Together with their low

power and small packages, they are ideal for MPC applications,

especially portables and notebooks. Versions are available with

either current output (TDA1387T) or voltage output

(TDA1311A(T)).

TDA1311A(T)/TDA1387T

DIGITAL AUDIO LOW POWER STEREO DACs

MBA858 - 1

TDA1311A(AT)

LEFT INPUT REGISTER RIGHT INPUT REGISTER

LEFT OUTPUT REGISTER RIGHT OUTPUT REGISTER

LEFT BIT SWITCHES RIGHT BIT SWITCHES

REFERENCE

SOURCE

11 - BIT

PASSIVE

DIVIDER

32 (3 - BIT)

CALIBRATED

CURRENT

SOURCES

1 CALIBRATED

SPARE

SOURCE

32 (3 - BIT)

CALIBRATED

CURRENT

SOURCES

1 CALIBRATED

SPARE

SOURCE

11 - BIT

PASSIVE

DIVIDER

IOR

CONTROL

AND

TIMING

VOL I

BCK

DATA

I/V I/V

VDD

MSC188

TDA1387T

LEFT INPUT REGISTER RIGHT INPUT REGISTER

LEFT OUTPUT REGISTER RIGHT OUTPUT REGISTER

LEFT BIT SWITCHES RIGHT BIT SWITCHES

REFERENCE

SOURCE

11 - BIT

PASSIVE

DIVIDER

32 (3 - BIT)

CALIBRATED

CURRENT

SOURCES

1 CALIBRATED

SPARE

SOURCE

32 (3 - BIT)

CALIBRATED

CURRENT

SOURCES

1 CALIBRATED

SPARE

SOURCE

11 - BIT

PASSIVE

DIVIDER

Rref

Iref

Vref

IDR OR

OP2

VDD

CONTROL

AND

TIMING

OP1

VOL

BCK

DATA

IBL IBR

VDD

QUICK REFERENCE DATA TDA1311A/AT TDA1387T

Power supply 5 V 5 V (min. 3 V)

Supply current 3.4 mA 5.5 mA

Input format ‘S’, up to 4 ×fsI2S up to 4 ×fs

Output 2 V 1.0 mA

Typical THD + N at 0 dB –68 dB –88 dB

Typical SNR 92 dB 98 dB

Typical power dissipation @5 V 17 mW 27.5 mW

@3 V – 10 mW

Package DIL8 (SOT97DE8) SO8 (SOT96-1)

SO8 (SOT96AE3)

Datasheet (12NC) 9397 750 00532 9397 750 00519

8-12 Multimedia PC

DIGITAL AUDIO AUDIO MPEG DECODERS

SAA2500 FAMILY

SAA2500

■Supports all MPEG-1 layer-I and layer-II audio

modes

■Supports all MPEG-1 bit rates and sample

frequencies with fully automatic switching

■L3 microcontroller interface

■Burst mode data input

■Programmable variable bit output precision

(16-, 18-, 20- or 22-bit)

■Integrated audio post processing for control of

signal level and inter-channel crosstalk

■De-multiplexing of ancillary data in input

bitstream

■Sample clock switching and on-chip clock

generation

■Automatic digital de-emphasis of decoded audio

signal

■Error concealment

■Low power consumption

SAA2501

All features of SAA2500, plus:

■Decodes error-protection schemes in Digital

Audio Broadcast (DAB) and Astra Digital Radio

(ADR) broadcasts

■Fully compatible with Eureka-147 specifications

■Demultiplexing of Program Associated Data

(PAD) in the input data stream

SAA2502

All features of SAA2500, plus:

■MPEG-2 compatible stereo output

■Supports low sample frequencies (16, 22.05 and

24 kHz) with CRC correction of scale factors

■Handles byte- and non-byte-aligned input data

■IEC958 digital output

■Programmable automatic internal dynamic range

compression algorithm

■Output formats include I2S, SPDIF and 256 (or

more) oversampled analog stereo

The SAA2500 family was developed for a range of broadcast

digital audio applications including digital radio. All three chips

have the same base features as the SAA2500 and can operate in

master and slave modes. The SAA2501 has additional error han-

dling for DAB and ADR applications; the SAA2502 is a second

generation, high feature general purpose MPEG-2 decoder sup-

porting both layer-I and layer-II of the MPEG-1 standard as

well as meeting all requirements for a stereo MPEG-2 decoder.

MSB515

DIVIDER PHASE

COMPARATOR CLOCK

GENERATOR DECODING

CONTROL

PC MCLKOUT

MCLKIN X22OUT X22IN

I/P

PROCESSOR

DEQUANTIZATION

SYNTHESIS

DAC

SPDIF

ENCODER

L3MODE

L3/I C CLOCK

L3DATA/I CDATA

analog right

analog left

SCK

TC1 TC0 TD1 TD0 TCK TMS TRST SPDIF RESET

SAA2502H

REF-CLK

FSCLKIN

FSCLKOUT

URDA/STOP

CDS/CDM

CDSCL/CDMCL

CDSEF/CDMEF

CDSWA/CDMWS

CDSSY

QUICK REFERENCE DATA SAA2500 SAA2501 SAA2502

Power supply 5 V 5 V 5 V

I2S interface Yes Yes Yes

I2C-bus controlled No No Yes

Package QFP44 (SOT307-2) QFP44 QFP44

Datasheet Handbook IC01 9397 746 40011 Contact Philips

8-13

Multimedia PC

Stereo radio power amplifier

■Fixed 20 dB closed loop voltage gain and high

output power

■Stereo channel balance within 1 dB

■Mute/standby switch

■Good ripple rejection

■No switch ON/OFF clicks

■Built-in protection against load dump, AC/DC

short circuit to ground or supply, reverse polarity,

adverse temperature conditions, ESD and SOAR

This stereo, single-ended audio amplifier delivers 2 ×6 W per

channel for driving passive speakers. The mute/standby switch

requires a very low current to switch between the two conditions

and uses less than 100 µA when in standby.

DIGITAL AUDIO OTHER AUDIO ICs

Philips extensive range of audio devices also includes general

audio processing ICs such as faders, graphic equalizers, ampli-

fiers etc. A few examples are included here; for details on the full

range, please refer to the data handbooks IC01 (‘Semiconductors

TDA1517P

MSB261 - 1

100 nF P

60 kΩ

TDA1517

stand-by switch

220 nF

input 1

1000 µF

input

reference

voltage

220 nF input 2

1000 µF

2200

µF

internal

1/2 VP

100

µF

60 kΩ

QUICK REFERENCE DATA

Power supply 14.4 V

Typical supply current 40 mA

Power output 2 ×6 W

Supply voltage ripple rejection 48 mA

Channel separation (min.) 40 dB

Package SIL9 (SOT110B)

Datasheet Handbook IC01

for radio and audio systems’). Information on audio ICs for spe-

cific application areas can be found in the appropriate Designer’s

guide (refer to Appendix 1 for a list of these guides).

8-14 Multimedia PC

Sound processors

■Source selector for four stereo and one mono

input

■Interface to an equalizer and noise reduction

circuits

■Control of bass and treble, volume level, balance

and fader

■Fast mute switching at zero signal crossing via IC

pin or I2C bus

■106 dB volume control range; maximum gain

20 dB

■Wide dynamic range with low noise and distortion

■Line out to drive active speakers

This family of sound processors and audio control circuits pro-

vide digital control via the I2C bus of various sound parameters.

The source selector selects input from the OM560x radio mod-

ule, line in and CD-ROM audio input. The hardware mute

function is particularly useful for applications using R(B)DS as

the zero crossing mute avoids modulation plops during changing

presets and/or sources (i.e. traffic announcement during cassette

playback). It also includes a loudness characteristic automatically

controlled with the volume (and the TDA6322T/23T also

include loudness control with the bass and treble). All functions

can be fully I2C-bus controlled.

DIGITAL AUDIO OTHER AUDIO ICs

TEA6320/1/2/3

MGA526

TEA6320T

VOLUME 2, LEFT

BASS FADER

G = 0...+55 dB

VOLUME 2, RIGHT

BASS FADER

TREBLE

LEFT

BASS

LEFT

+ / – 15 dB + / – 12 dB

G = 20...–31 dB

VOLUME 1

LOUDNESS

TREBLE

RIGHT

BASS

RIGHT

SOURCE

SELECTOR

I C-BUS

SDA SCL

audio

left

audio

right

MUTE

ZERO

CROSS

DETECTOR

POWER

SUPPLY

front rear

left output

front rear

right output

QUICK REFERENCE DATA (TEA6320(T))

Power supply 8.5 V

Typical supply current 26 mA

I2C-bus interface Yes

SNR 105 dB

THD 0.1%

Ripple rejection 76 dB

Channel separation 96 dB

(80 dB for TDA6322/23)

Package TDA6320 SDIL32

TDA6320T SO32

Datasheet (12NC) TEA6320 9397 750 00533

TEA6321 9397 750 00534

TEA6322 9397 750 00535

TEA6323 9397 750 00536

8-15

Multimedia PC

5-band graphic equalizer

■Fully I2C-bus controlled monolithic integrated

5-band stereo equalizer circuit

■Five filters for each channel

■Centre frequency, bandwidth and maximum

boost/cut defined by external components

■Variable, quasi-constant or constant Q-factor

selectable via I2C software

■Defeat mode for linear frequency response and

optimum noise performance

■All stages DC coupled

■Two different programmable module addresses

The TEA6360 5-band stereo graphic equalizer is an I2C-bus

controlled tone processor for applications such as radios, TVs

and music centres with Dolby noise reduction. It also offers the

possibility of sound control as well as equalization of sound pres-

sure behaviour for different rooms or loudspeakers. It has 5

stereo pairs of constant bandwidth boost/cut bandpass filters,

each centred on a different frequency. The control range

(±12 dB for example) of each stereo pair is divided into five steps

(2.4 dB in this case) with one extra step for the linear position.

Overall DC gain is 0 dB, so offset voltages are not amplified.

TEA6360

DIGITAL AUDIO OTHER AUDIO ICs

SDA SCL

C-BUSI2

CONTROL

MAD output

right

output

left

TEA6360

input

right

input

left

2.95 kHz 12 kHz 790 Hz 205 Hz 59 Hz

MSC218

QUICK REFERENCE DATA

Power supply 8.5 V

Typical supply current 24.5 mA

Frequency range 0 to 20 kHz

SNR 98 dB

THD (max.) 1.0%

Typical crosstalk attenuation 75 dB

Ripple rejection 70 dB

Package TEA6360 DIL32SHR (SOT232)

TEA6360T SO32 (SOT287)

Datasheet Handbook IC01

8-16 Multimedia PC

Class AB stereo headphone driver

■Large output voltage swing

■No switch ON/OFF clicks

■Excellent power supply ripple rejection

■Short circuit resistance

■Low power consumption

The TDA1308T is a high performance integrated class AB

headphone driver providing a high SNR and slew rate, com-

bined with low distortion. Its low power consumption and small

size make it ideal for MPC audio applications.

DIGITAL AUDIO OTHER AUDIO ICs

TDA1308T

QUICK REFERENCE DATA

Power supply Single 5 V (3 to 7 V)

Dual 2.5 V (± 1.5 to ± 3.5 V)

Supply current 3 mA

SNR 110 dB

Typical THD + N at 0 dB –70 dB

Power supply ripple rejection 90 dB

Channel separation 70 dB

Maximum output power 60 mW

Package Single DIP8 (SOT97-1)

Dual SO8 (SOT96-1)

Datasheet Handbook IC01

MSB207

TDA1308T

VSS VDD

OUTA

OUTB

INA

INB

9-1

Multimedia PC

CAMERA &

MISCELLANEOUS

ICs

CAMERA &

MISCELLANEOUS

ICs

9-2 Multimedia PC

TDA8706A

CAMERA AND MISCELLANEOUS ICs A/D INTERFACES

6-bit ADC with multiplexer and clamp

■6-bit resolution

■5.8 effective bits at 4.43 MHz input

■Maximum conversion frequency 40 MHz

■Binary tri-state CMOS outputs

■CMOS-compatible digital inputs

■R, G and B clamps on code 0

■Luminance and colour difference clamps

■Internal reference voltage

The TDA8706A is a 6-bit ADC with three analog multiplexed

inputs. An analog clamp on code 0 is provided for RGB process-

ing and the clamping level can also be adjusted externally up to

code 20. It can also be used as a single 6-bit ADC.

MULTIPLEXER 6-BIT

ADC CMOS

OUTPUTS

REGULATOR

SR SG SB

select

inputs

digital

voltage

outputs

MSC211

TDA8706A

CLP

RED

GREEN

BLUE

VDDA

VRB

CLK

VCLPB VCLPG

VCLPR

CLAMP

QUICK REFERENCE DATA

Power supply 2.7 to 5 V

Analog supply current 7 mA

Digital supply current 5 mA

Integral non-linearity ±0.25 LSB

Differential non-linearity ±0.20 LSB

Total power dissipation @ 3 V 36 mW

Package SSOP24 (SOT340-1)

Datasheet (12NC) 9397 750 00991

9-3

Multimedia PC

10-bit high speed 3 V ADC

■Sampling rate up to 20 MHz with 10-bit resolution

■DC sampling allowed

■High SNR over a large analog input frequency

range (9.3 effective bits at 1.0 MHz full scale input

at 20 MHz)

■In-range tri-state CMOS output

■CMOS/TTL-compatible inputs and outputs

■Power saving standby mode

■External voltage reference regulator

■Low analog input capacitance and no buffer

amplifier required

■No sample and hold circuit required

A high speed 3V ADC, the high resolution TDA8766 is ideal

for professional video and more general applications. A standby

mode allows the reduction of the devices power consumption

down to 4 mA.

CAMERA AND MISCELLANEOUS ICs A/D INTERFACES

TDA8766

MGC785

TDA8766

LATCHES TTL

OUTPUT

STAGES

HIGH - SPEED

10 - BIT A/D

CONVERTER

OVERFLOW/

UNDERFLOW

LATCH

CLOCK

DRIVER CMOS

OUTPUT

STAGE

D9 - D0

(tristate)

output

reference

overflow/

underflow

CLK

analog

input

voltage

reference

QUICK REFERENCE DATA

Power supply 3.3 V

Analog supply current 9 mA

Digital supply current 8 mA

Integral non-linearity ±2 LSB

Differential non-linearity ±0.9 LSB

SNR 60 dB

Typ. THD at 0 dB –63 dB

Total power dissipation (typ.) 66 mW

Package LQFP32 (SOT401-1)

Datasheet (12NC) 9397 750 00746

9-4 Multimedia PC

12-bit high speed ADC

■12-bit resolution with sampling rates up to 30 MHz

■Guaranteed for no missing codes

■Binary or two’s-complement CMOS outputs

■All digital inputs and outputs are CMOS

compatible

■In-range CMOS output

■3 V to 5 V CMOS-compatible digital outputs

■Differential clock input

■Differential or single analog input

■No external sample and hold circuit or buffer

amplifier required

The TDA8767 is a bipolar 12-bit high speed ADC for imaging

and a wide range of other applications. A sine wave clock input

signal is allowed and it has an external amplitude range control.

Three versions are available with different maximum clock fre-

quencies (10, 20 and 30 MHz).

CAMERA AND MISCELLANEOUS ICs A/D INTERFACES

TDA8767

MSC195

D11 MSB

data outputs

D10

Vref

VID2

D0 LSB

VCCO

CMOS

OUTPUTS

LATCHES

ANALOG-TO-DIGITAL

CONVERTER

CLOCK DRIVER

CLK

CMOS

OUTPUT

IN-RANGE

LATCH

OETC

AMP

sample-

and-hold

TDA8767

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 40 mA

Digital supply current 22 mA

Integral non-linearity ±3 LSB

Differential non-linearity ±0.75 LSB

Total power dissipation 335 mW

Package QFP44 (SOT307-2)

Datasheet (12NC) 9397 750 00889

9-5

Multimedia PC

CAMERA AND MISCELLANEOUS ICs A/D INTERFACES

TDA8786(A)

10-bit A/D interface for camera CCDs

■Minimum 18 MHz sampling frequency

■AGC gain from 3.5 dB to 33.5 dB in 0.1 dB steps

■Soft clipper for white compression (starting from

40% of input signal)

■Fully programmable via 3-wire serial interface

■Low power consumption of typically 400 mW, with

standby-modes available on individual blocks

■+6 dB fixed gain analog output for analog iris

control

■8-bit DAC; 10-bit DAC for analog settings

■TTL compatible inputs; TTL and CMOS

compatible outputs

■Small LQFP48 package

The TDA8786 is a 10-bit A/D converter and interface for CCD

digital video cameras. A highly-integrated IC, it includes CDS,

AGC, soft-clipper, preblanking and a reference regulator on-

chip. The ‘A’ version has the control pulse active LOW. Digital

outputs operate from 2.5 V to 5 V.

MSC213

SOFT

CLIPPER

OPTICAL

BLACK

CLAMP

PRE-

BLANKING

TRACK-

AND-HOLD TRACK-

AND-HOLD

TRACK-

AND-HOLD

TRACK-

AND-HOLD

CLAMP

8-BIT DAC

4-BIT DAC

10-BIT DAC

9-BIT DAC

+6 dB

AGC

CLOCK

GENERATOR

10-BIT ADC

REGULATOR SERIAL

INTERFACE

OUTPUTS

BUFFER

IN2 IN1 CDSP2 CDSP1 CLPCDS CLK OE

OFDOUT

STDBY SENSCLK

SDATA

DEC2

DEC1

VRT

VRB

DACOUT

Vref

CLPADC

ADCIN

PBOUT

VCCA1

PBIN

AGCOUT

PBK

CLPOPB

AMPOUT

TDA8786

TDA8786A

QUICK REFERENCE DATA

Power supply 5 V

Analog supply current 67 mA

Digital supply current 15 mA

Integral non-linearity ±2 LSB

Differential non-linearity ±0.9 LSB

CDS output amplifier gain 6 dB

AGC dynamic range 30 dB

Total power dissipation 400 mW

Package LQFP48 (SOT313-2)

Datasheet (12NC) 9397 750 00846

9-6 Multimedia PC

8-bit 40 Msps 2.7 to 5.5 V universal ADC

■8-bit resolution with sampling rate up to 40 MHz

■Operates between 2.7 V and 5.5 V

■DC sampling allowed

■CMOS/TTL-compatible digital inputs and outputs

■Low power dissipation and sleep mode

■High SNR (7.3 effective bits at 4.43 MHz full scale

input)

■Low analog input capacitance and no buffer

amplifier required

■No external sample-and-hold circuit needed

■External voltage reference regulator

The TDA8790 is a low-power, low-cost universal CMOS ADC

for video and general purpose applications which includes a

sleep mode to reduces device power consumption when inactive

down to 4 mW.

CAMERA AND MISCELLANEOUS ICs A/D INTERFACES

TDA8790

VRB

VRM

VRT

RLAD

ID4

CMOS

OUTPUTS

LATCHES

ANALOG -TO - DIGITAL

CONVERTER

CLOCK DRIVER

MSC156

CLK

SLEEP

TDA8790

VDDO

analog

voltage

input data

outputs

LSB

MSB

QUICK REFERENCE DATA

Power supply 3.3 V

Analog supply current 4 mA

Digital supply current 5 mA

Integral non-linearity ±0.75 LSB

Differential non-linearity ±0.5 LSB

SNR 47 dB

Typ. THD at 0 dB –50 dB

Total power dissipation 30 mW

Package SSOP20 (SOT266-1)

Datasheet (12NC) 9397 750 00677

9-7

Multimedia PC

Camera DSP

■Mosaic CCD to Y/C encoder

■9- or 10-bit input (10-bit internal processing)

■Horizontal resolution of up to 800 pixels/line

■White balance control

■Black offset pre-processing (including optical black

offset control)

■RGB separation

■RGB and YUV signal processing functions

■CIF, DTV2 and D1 digital output formats

■On-board PAL/NTSC encoder and 9-bit DACs for

analog output

■Measurement engine prepared for auto-exposure,

auto-focus and auto-white balance features

■VH reference and window timing

■I2C or SNERT serial interface

■Mode control including power management

CAMERA AND MISCELLANEOUS ICs CAMERA DSP

SAA8110

MSC316

Y-PROCESSING

RGB

YUV

UV-PROCESSING

DIGITAL

OUTPUT

FORMATTER

ANALOG

OUTPUT

PRE-

PROCESSING

(INCL. PAL/NTSC

ENCODER)

V-DACS.

RGB

PROCESSING

MEASUREMENT ENGINE

RGB

SEPARATION

OFFSET

PRE-

PROCESSING

8Y(UV)

8UV

VS, HREF

FIOUT

2LCC

CREF (PXQ)

3VDAC_OUT

VDAC_REF

XOSC_IN

SIS

XOSC_OUT

SERIAL

INTERFACE

VH-REFERENCE

WINDOW TIMING

AND CONTROL

ADDITIONAL FUNCTIONS

(e.g. SMPS PULSE GENERATOR,

CONTROL DACs)

CCD_IN

T(0,1, 2)

PMC

CLK2

CLK1

2 3

TEST

CONTROL

SAA8110

CDAC_OUT

CDAC_REF SMP P(1, 0) VD HD FI AO/SN_RES SDA

STROBE

SCLK

SDATA

SCL/SN_DA A1/SN_DA

QUICK REFERENCE DATA

Power supply 3 V or 5 V

Analog supply current 50 mA

Digital supply current 100 mA

Typical power dissipation 900 mW @ 5 V/14.3 MHz

Package LQFP80 (SOT315)

I2C-bus controlled Yes

Datasheet Contact Philips

The SAA8110 is a high precision DSP for video camera applica-

tions including desktop video (video conferencing, video cap-

ture), observation and videophone. It supports several types of

CCD including PAL, NTSC and CIF (progressive and inter-

laced). On-board RGB processing functions include a colour-

space conversion matrix to YUV, black offset, knee and gamma;

Y processing includes contour processing and noise reduction;

and UV processing include white clip, false colour correction

and noise reduction. It also includes an SMPS pulse generator

and control DAC.

9-8 Multimedia PC

CAMERA AND MISCELLANEOUS ICs MISCELLANEOUS ICs

UAA3201T

UHF/VHF remote control receiver

■Oscillator with external SAW resonator

■Wide frequency range and high sensitivity

■Low power consumption

■Superheterodyne architecture

■IF filter bandwidth determined by application

■Low cost solution

The UAA3201T is a fully integrated single-chip receiver,

primarily intended for use in VHF and UHF remote control

systems employing direct AM Return-to-Zero (RZ) Amplitude

Shift Keying (ASK) modulation. It can be used for RF remote

control applications such as keyless entry and wireless mouse.

The RF signal is fed directly into the mixer stage, where it is

reduced to a nominal 500 kHz IF signal by the SAWR-

controlled oscillator. The IF signal is then amplified and passed

through a 5th order elliptical low-pass filter. Filter output is

demodulated by a limiting amplifier that rectifies the incoming

IF signal and after further filtering, the output signal is limited

by a comparator.

MSC199

MIXER

AMP

OSCILLATOR

BAND GAP

REFERENCE

BUFFER

COMPARATOR

LIMITER

data

output

VCC

Vref

BUFFER

SAWRMON MOP CPB CPA

CPOCPCLFBLINMXINFA VEM

UAA3201T

QUICK REFERENCE DATA

Power supply 3.5 V to 6 V

Supply current 3.4 mA

Sensitivity –105 dBm

Receiver turn-on time 10 ms

Typical loaded Q (SAWR) 1600 (50 Ωload)

Package SO16 (SOT109-1)

Datasheet (12NC) 9397 750 00136

10-1

Multimedia PC

BUS ICs

10-2 Multimedia PC

USB transceiver

■Complies with Universal Serial Bus Specification

v1.0

■Fully compatible with the VHDL ‘Serial Interface

Engine’

■Digital inputs and outputs to transmit and receive

USB data

■Supports high (12 Mbits/s) and low (1.5 Mbits/s)

speed data transmission

■Samples available in SSOP and TSSOP packages

The PDIUSBP11 is a single-chip generic USB transceiver,

designed to work with the Serial Interface Engine and applica-

tion interface in a USB peripheral or hub design. It allows either

3.3 V or 5 V programmable and standard logic devices to inter-

face with the Physical layer of the USB, so is well suited for USB

peripherals using ASIC or programmable logic. The gated inputs

are decoded by the host, which also drives the outputs from the

serial interface engine. Applications include keyboards, mice,

monitors (control and hub), digital speakers, joysticks and

telecommunications.

BUS ICs UNIVERSAL SERIAL BUS ICs

PDIUSBP11

MSC235

D−

OE#

SPEED

VMO

VPO

RCV

D+

QUICK REFERENCE DATA

Power supply 3.3 V (5 V tolerant)

Supply current High speed 10 mA

Low speed 2 mA

Quiescent supply current 330 µA

Supply current in Suspend (max.) 65 µA

Total power dissipation t.b.f.

Package SO14 (SOT108-1)

Datasheet Contact Philips

10-3

Multimedia PC

USB stand-alone hub

■Complies with Universal Serial Bus Specification

v1.0

■Four downstream ports with per packet

connectivity; one upstream port

■Hub plus embedded function with two endpoints

■Integrated memory for hub and function

■Generates and checks CRC values

■Asynchronous transmit/receive FIFOs

■Versatile I2C-bus host and function interface

■Automatic USB protocol handling

■Full USB power management support including

suspend and wake-up modes

Philips’ USB stand-alone hub with embedded function provides

USB functionality and USB expandability to a PC peripheral.

The modular approach used to implement a hub and embedded

function allows the device to be used with either a dedicated low

cost microcontroller or an existing controller with a modified

version of the software. Control of the PDIUSBH11 is via a seri-

al I2C-bus slave interface, which also allows initialization, con-

figuration and USB data retrieval or set-up.

BUS ICs UNIVERSAL SERIAL BUS ICs

PDIUSBH11

QUICK REFERENCE DATA

Power supply 3.3 V

Supply current t.b.f.

Quiescent supply current 330 µA

Supply current in suspend (max.) 65 µA

DC input voltage (max.) 5.5 V

Total power dissipation (max.) t.b.f.

Package SDIP32

Datasheet Contact Philips

MSC246

HUB

REPEATER

DOWNSTREAM

PORT3

UPSTREAM

PORT

PHILIPS

SIE

FIFO

DOWNSTREAM

PORT2 DOWNSTREAM

PORT4 DOWNSTREAM

PORT5

HUB

CONTROLLER

EMBEDDED

PORT

(I2C)

Other USB ICs

In addition to these devices, Philips has other ICs with USB

functionality in development. These include the P83C190 mon-

itor microcontroller which includes a USB bus interface and hub

and the UDA1321T audio DAC, a CMOS bitstream DAC for

USB compliant devices.

10-4 Multimedia PC

BUS ICs IEEE 1394-1995 ICs

PDI1394L11

1394 AV link layer controller

■IEEE 1394-1995 compliant link layer controller

■Embedded audio/video layer interface

■A/V layer interface compatible with various

MPEG-2 and DVC codecs

■Application data packetization complies with

proposed IEC 1883 specification

■80C51 or MC68xx compatible byte-wide host

interface

■3.3 V supply with all inputs 5 V tolerant

The PDI1394L11 is Philips’ Audio/Video link layer controller

for the high speed IEEE-1394 Serial Bus, designed to pack and

unpack real-time application data packets for transmission using

isochronous data transfers. A microcontroller interface allows for

internal register configuration as well as performing asynchro-

nous data transfers.

The link layer provides an interface between the physical layer,

the host controller and connected devices. (Note: IEC 1883 is a

Specification of Digital Interface for Consumer Electronic

Audio/Video Equipment.)

QUICK REFERENCE DATA

Power supply 3.3 V

Supply current t.b.f.

Clock 49.978 MHz

Total power dissipation (max.) t.b.f.

Package QFP80 (SOT318-C5)

Datasheet Contact Philips

MSC243

AV LAYER

TRANSMITTER

AND

RECEIVER

5kB BUFFER

MEMORY

(ISOC & ASYNC

PACKETS) LINK CORE

8-BIT HOST

INTERFACE

ASYNCH

TRANSMITTER

AND

RECEIVER CONTROL

AND

STATUS

REGISTERS

CYCLOUT

AVCLK

AVDATA[7:0]

AVFSYNCOUT

AVFSYNCIN

AVSYNC

AVVALID

AVERR1

AVERR0

AVENDPCK

HIF A[8:0]

HIF D[7:0]

HIF WR_N

HIF RD_N

HIF CS_N

HIF INT_N

CYCLIN

D[0:7]

CTL0

CTL1

LREQ

ISO_N

SCLK

RESET_N

PDI1394L11

1394 AV physical layer controller

■IEEE 1394-1995 compliant physical layer controller

■Data transfers at up to 200 Mbits/s

■Industry standard Link/Physical interface (connects

to any link controller)

■3 ports

■3.3 V supply

The PDI1394P11 is an Audio/Video physical layer controller

for the IEEE-1394 Serial Bus. It is in development, with avail-

ability scheduled for available first quarter 1997.

PDI1394P11

11-1

Multimedia PC

REFERENCE/

EVALUATION

BOARDS AND

SOFTWARE

REFERENCE/

EVALUATION

BOARDS AND

SOFTWARE

11-2 Multimedia PC

REFERENCE/EVALUATION BOARDS & SOFTWARE DECODER/ENCODER MODULES

As well as individual ICs, Philips provides a number of evalua-

tion and demonstration boards, complete with software, devel-

oped in Philips Semiconductors - Systems Laboratories

(PS-SLs). These boards are invaluable tools which allow cus-

tomers to assess an IC’s functionality and performance, and pro-

vide a reference for real-world designs. Philips also still supports

DEMOBOARDS TYPE NUMBER MORE INFORMATION

Digital video decoder module DECMOD01 This page

Digital video encoder module ENCMOD02 This page

SAA7183 demoboard DTV7183 Page 11-3

SAA7146 demoboard DPC7146 Page 11-4

SAA7140 demoboard DPC7140 Page 11-8

MPEG-1 video playback evaluation kit DPC7131 Page 11-9

SAA7167 demoboard DPC7167 Page 11-10

Digital video decoder/encoder module system

To simplify the task of demonstrating and evaluating Philips’

extensive range of digital video encoder and decoder ICs, as well

as significantly reduce the costs involved, Philips

Semiconductors has developed a modular system which can be

configured for a number of devices and packages, removing the

need for individual PCBs.

This modular concept, which evolved from the DTV7183

demoboard (described on next page), was designed to allow sim-

ple, cost-effective assessment of different video decoders and

encoders, regardless of the package footprint. Encoder and

decoder modules can be connected together directly, to test

basic encoding/decoding quality and functionality. They can

also be operated stand-alone, or as front- or back-ends for cus-

tomized applications and other Philips demoboards.

Digital video decoder module

The digital decoder module accepts SAA7110(A) and

SAA7111(A) decoders (see pages 4-3, 4) in either PLCC68 or

LQFP64 packages. Input to the board is through two RCA jacks

for CVBS signals or a DIN connector for S-Video. Digital out-

put is fed to the YUV feature connector and resistors can be

used to suppress any high frequency ringing due to long wires.

The resistor/capacitor set-up has to be altered only for the low

voltage (3.3 V) SAA7111A decoder. A third order crystal is used

for the SAA7110(A) and SAA7111.

Digital video encoder module

The encoder module accepts PLCC84, QFP80 and LQFP64

packages, allowing for insertion of the SAA7182/83, SAA7182A/

83A or SAA7124/25 encoders (see page 4-12). A 26-pin YUV-

feature connector is used for the digital input, which can be in

CCIR-656 (D1) or 16-bit YUV (for the SAA7182(A)/

83(A)) formats. DAC output is passed through analog post-fil-

ters to the connectors. Filters are assigned to the connectors

depending on signal type and the DAC signals are routed via

jumpers, to adapt to the different output modes of the

SAA7124/25. Jumpers also allow the module to be configured

for the OSD signals and RGB inputs of the SAA7182A/83A

family, and for switching between the S-Video and RGB modes

of the SAA7124/25.

Boards are available individually, each with its own software

which interfaces with the I2C-bus via a printer port adapter.

Documentation includes a manual explaining the overall con-

cept and individual user manuals.

Microcontroller module

Each of the modules has a socket for an I2C-bus EEPROM,

used for storing initialization data and for a future microcon-

troller module. Although developed initially as an aid to evaluat-

ing and demonstrating ICs in applications where there is no pro-

cessing power (e.g. set-top box applications), the microcontroller

module will provide additional flexibility in testing in PC appli-

cations.

a number of boards for older ICs and has a number of new

boards in development. Boards are supported by two general

software tools, the Desktop Video Debugger and Universal

modules. There are also extensive application notes, user manu-

als, and hardware and software descriptions.

11-3

Multimedia PC

SAA7183 demoboard

This basic board is used by customers to evaluate two crucial

functions in the field of desktop video – encoding and decoding

– and it can be used either as a stand-alone board, or as an

extension for other demoboards.

The board accepts an analog input video signal, digitizes and

decodes it into YUV data and then passes it via the digital YUV

bus to the encoder, where the signal is reconstructed and con-

verted back to an analog output video signal. For evaluation, the

customer can plug in either the SAA7110(A) or SAA7111(A)

ICs (see pages 4-3 and 4-4), which offer complete multistandard

one-chip decoding. Both have on-chip A/D conversion, filter-

ing, clock generation and decoding of CVBS and S-Video sig-

nals, for PAL and NTSC standards (and SECAM if the appro-

priate derivative is chosen). The SAA7110 is a square-pixel

decoder; the SAA7111 is CCIR-601 compliant.

There are two sockets for Philips

’

encoder IC family (see Video

encoders section, pages 4-14 to 4-17). If the SAA7110(A)

decoder is used, then normally its square pixel equivalent

encoder is inserted, the SAA7187; if decoding is handled by the

SAA7111(A), then any of Philips

’

CCIR-601-compliant ICs

(SAA7182(A)/83(A), SAA7184/85B or SAA7185/88A) can be

used. They output CVBS, and/or S-Video and RGB, depending

on the encoder chosen. The board also includes a YUV feature

connector.

A number of operation modes are possible. First, direct decoder-

to-encoder for basic decoding/encoding evaluation. YUV-to-

encoder mode allows digital YUV data to be fed directly onto

the bus for encoding, by-passing the decoders. The board can

also be set up in Encoder Master mode and a Pattern Generator

mode is available when the board is operating stand-alone, to

demonstrate the high quality of the reconstructed video output

signal.

There is also space for an optional microcontroller, which allows

direct I2C-bus control of the encoders and decoders. It provides

eight different I2C-bus set-ups and requires no knowledge of

I2C-bus programming or control registers, for simple demon-

stration. If the microcontroller option is not used, a separate

I2C-bus control program is used to drive the DTV7183 board,

requiring an I2C-bus cable connection.

Real-Time Control

This board also shows very clearly the advantages of a unique

Philips’ development, RTC (Real-Time Control). This process

synchronizes encoding and decoding by locking the encoding

process to the decoding. This provides accurate and stable

colour rendition at the encoder end, even when the signal is

non-standard or subject to adverse affects such as noise; it also

provides solid decoding of NTSC signals.

MSB912

DIGITAL

COLOR

ENCODER

SAA7185

SAA7187

SAA7188A

DIGITAL

COLOR

DECODER

SAA7110

SAA7111

DIGITAL

COLOR

ENCODER

SAA7182

SAA7183

analog outputs

(CVBS, S-video)

analog inputs

(CVBS, S-video)

analog outputs

(CVBS, S-video, RGB)

YUV FEATURE

CONNECTOR

digital YUV bus

MICRO-

CONTROLLER

DTV7183

DEMOBOARD

REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS

DTV7183

11-4 Multimedia PC

REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS

SAA7146 demoboard

Philips is committed to three communications standards: IEEE

1394-1995 for external multimedia peripherals; the PCI bus as

the backbone in the PC; and the USB for general PC and low

data rate peripherals. In general, it is expected that all peripherals

will in the future be connected via one of these buses. This

board lies at the core of Philips PCI multimedia strategy and is a

complete silicon and software demonstration environment.

For multimedia over PCI, at the heart of Philips' solution is the

SAA7146 Multimedia PCI and Bridge Scaler IC. It has many

on-board interfaces, supporting video and audio inputs/outputs

via the PCI interface, and has a high performance scaler core

similar to that in the SAA7140.

As PCI bus master, it can send data from local video and audio

sources and the general data interface to its main memory, or it

can request data from memory. Data streams are handled locally

by powerful control engines which operate autonomously,

offloading the data control workload from the CPU and

enabling real-time control. Two Register Programming

Sequencer (RPS) engines, in combination the Local Event

Management, can control almost all data streams independently

of the CPU. Two Time Slot List (TSL) engines provide

enhanced audio features.

The DPC7146 is a 4-layer PCB, including several Philips audio

and video processing ICs, with a number of interfaces and con-

nectors. Its primary chip is the SAA7146 which, with its wide

range of interfaces, allows the board to be used as a base for

developing a number of applications, such as video-conferenc-

ing, as well as AC-3 playback and MPEG-2 codecs. It also fea-

tures the SAA7111A video decoder, TDA1309T audio codec,

PCF8598E EEPROM, and the SAA7185B video encoder and

TDA1308 headphone driver for video and audio output.

Hardware

The central element of the board is the SAA7146. It is con-

trolled via the PCI bus and data on the board can be uploaded

from the EEPROM, as required in the PCI specification. It has

two D1 video ports, giving it the capability for simultaneous

capture and playback of video. The TSL audio I/O engines can

be arbitrarily mapped onto five Serial Data (SD) lines and five

Word Select (WS) lines. The DEBI port can be configured for

either a 16-bit ISA bus format or Motorola-style bus, where the

data bandwidth is about double that of the standard PC ISA

bus. Additional functionality is provided through GPIO

(General Purpose I/O) and multi-master I2C bus interfaces.

AUDIO

VIDEO

SAA7146

uP DEVICES

I2C DEVICES

PCI

SCSI

L2 MEM

proc. -bus

ISA-bus

PCI-bus

MEM

CONTROL

+ BRIDGE

e.g.

PENTIUM

PCI

SCSI

HDHD ISA MOUSE

KEYBOARD

VGA

SCSI

MSC236

DPC7146

Philips multimedia - PCI architecture

11-5

Multimedia PC

Other major functional blocks are:

•Video front-end: this consists of the SAA7111A multistan-

dard video decoder (see page 4-4), I2C bus interface, and

CVBS and S-Video connectors. Alternatively, the SAA7111

or SAA7110 may be used (see pages 4-3 and 4-4). This block

provides colour decoded video streams from a CVBS or

S-Video source to one of the two video inputs to the

SAA7146 in 16-bit 4:2:2 format. Control of the decoder is

via the I2C interface and the standard set-up uses the PCI

Bridge as the I2C-bus master. Video data can be fed directly

to the SAA7146 and in addition to the video signals, the

S-Video connector features I2C bus connectivity. An external

tuner module could be added to the front-end.

•Video back-end: video playback uses the SAA7185B decoder

(see page 4-16) and a standard application uses Direct Mode

(DM), where video data are fed directly to the encoder. For

additional functionality, the SAA7146 supports line and field

memory access via VMI connectors, using additional Line

Memory Mode or Field Memory Mode modules. Encoded

video signals are available as CVBS or S-Video signals.

•Audio codec: the TDA1309T Bitstream audio codec (see page

8-2) provides independent analog audio I/O to the board.

Stereo signal capture is handled through the earphone con-

nector, using the ADC in the TDA1309T, with the sample

rate controlled using the appropriate clock signal. Audio out-

MSC303

VMI

CONNECTOR

VMI

PCI-BRIDGE

SAA7146

TDA1309

AUDIO

PROCESSING

chroma

ALE L

SAA7111A

VIDEO

DECODER

SAA7184

VIDEO

ENCODER

XAD(0 to 15)

D1D

D1D_SY

HA(0 to 3)

XAD(0 to 7)

D1C

XAD(8 to 16)

D1C_SY

D1BAUDIO

audio

R/L

audio

R/L

CVBS

chroma

I2C bus

D1B_SY

INSERT#

D1A

D1A_SY

D1A

D1A_SY

ISA(0 to 4)

GPIO(0 to3)

AUDIO

PCI-bus

put uses the DAC in the TDA1309T, after which the signal

is amplified using the TDA1308 headphone amplifier (see

page 8-16) and then passed to the earphone connector.

Additional connectors allow for the connection of Philips

audio evaluation boards using, for example, the TDA1548

audio processor (see page 8-4). The audio clock is generated

by an independent crystal.

•DEBI port: this behaves effectively as a high-speed ISA bus

interface and can be used to connect an ISA-based MPEG

decoder or, in principle, any other ISA device. It can also

operate as an interface to a Motorola-style bus. When com-

bined with the Local Event Management and the RPS func-

tionality, this makes the board very flexible.

•VMI connectors: these connectors allow additional boards to

be connected and provide access to most video, audio and

DEBI data signals.

•Power supply: the power supply for the board is split into two

different sections. The 12 V supply of the PCI edge connec-

tor is used to generate the decoupled 5 V supply for the video

decoder, encoder and analog audio supply. The PCI edge

connector 5 V supply is used as a general 5 V supply and for

the 3.3 V supply of the SAA7146. This splitting decouples all

sections from the main DC supply and supports local decou-

pling of functional blocks, resulting in very low noise content

in the video signals.

REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS

11-6 Multimedia PC

Software

Developed to assist customers’ software application and driver

development and reduce time-to-market, the software kit pro-

vides developers with a high level interface via a Hardware

Application Layer (HAL), consisting of two DLLs (for the

SAA7146 and the decoder). Virtual device drivers (VxD) are

included along with a debug utility, as well as a register editor

and universal I2C transceiver (described under

‘

General

Software’ at the end of this section). The kit also has demonstra-

tion drivers for audio and video capture, closed captioning, and

a sample application with source code. All HAL drivers can be

accessed directly, so PCI bus handling and other functions can

be performed through the Application Layer. The software cap-

ture drivers are designed for Microsoft’s Video for Windows

architecture, and are modular and expandable. The 16-bit ver-

sion will be available in Q3/96 for Windows ’95 and Windows

3.x, while the full 32-bit version for Windows ’95 and Windows

NT will be available by the end of 1996.

•Dynamic class library: contains all of the classes required to

control the DPC7146 demoboard covering video, audio,

closed captioning/teletext, I/O, memory and utilities.

•DMSD46.DLL: this DLL provides a generic class that

abstracts the specific details of Philips’ decoders used with the

,,,,,,,

,,,,,

,,,,,,,

,,,,,,

,,,,

,,,,,,

,,,,,,,,

,,,,

,,,

VIDEO / AUDIO CAPTURE

APPLICATION (VfW)

AVI CAPTURE

(AVICAP.DLL)

MICROSOFT VIDEO

(MSVIDEO.DLL)

,,,,,,,

PCI-bus

hardware interface

OEM appl.

Philips Semiconductors

Microsoft

MSC237

application interface

SAA7146 SAMPLE APPLICATION

(SMPL46.EXE)

SAA7146

APPLICATION BOARD

VIDEO CAPTURE DRIVER

(VCAP46.DLL)

SAA7146 DYNAMIC CLASS LIBRARY

(SAA7146.DLL)

DMSD46 (DLL) DENC46 (DLL)

VxD

SAA7146, including controls for the SAA7111 and

SAA7110. It allows the user to query and modify the input

format, video format standard and colour settings used by the

decoder.

•DENC46.DLL: this DLL provides a generic class that

abstracts the specific details of Philips

’

encoders used with the

SAA7146, including controls for the SAA7185B and

SAA7184 (with Macrovision option). It allows the user to

query and modify the output format, video format standard

and colour settings used by the encoder.

•Virtual device driver: the SAA714x VxD performs kernel

level operations and is responsible for providing services to

the DLLs, including allocating physically contiguous, locked

memory and providing an interface to Microsoftís Virtual

Memory Manager (VMM) and other virtual drivers for the

DLLs. The VxD operates in protected mode.

•Video capture device driver: this device driver provides low-

level video capture services for Windows multimedia applica-

tions. Featuring real-time video capture, video preview (dis-

played by host) and video overlay (video data directly bus

mastered over the PCI bus to the VGA frame buffer), it pro-

vides an interface for the user to select the image size and cap-

ture format. Utilizing PCI configuration information, and

DCI for Windows 3.1 or Direct Draw for Windows ’95, this

REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS

11-7

Multimedia PC

driver can determine information about the VGA board,

frame buffer, video format and occluded video regions. Any

number of occlusions are possible; the driver ensures continu-

ous video updates of non-occluded regions and commands

the SAA7146 not to write occluded pixels to the frame buffer

in the overlay mode. The clip mask is implemented using a

pixel map, which provides the flexibility to determine the

shape, position and number of occluded regions.

•Audio capture device driver: this driver supports a config-

urable capture buffer size and is capable of capturing 16-bit

stereo audio in an AVI file.

•Debug utility: with its simple graphical user interface, it

allows the user to identify quickly all PCI devices in the sys-

tem, view the configuration information, view and edit PCI

memory registers, select and execute macros, and access other

devices connected to the PCI bridge via DEBI and I2C inter-

faces.

Sample application

A C++ for Windows based sample application is provided which

exploits the “function of inheritance”, in that the functionality

of a process can be passed on to a child process. This allows a

REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS

customer to adapt the supplied sample very easily to a specific

application - code can be simply modified at high level (the sam-

ple APIs) and functionality will be retained. This allows very

easy product differentiation and quick times-to-market, the two

most critical factors for success.

The application demonstrates windowed display of live video

from a PC-top video camera or broadcast, which is freely scaled

as the size of the window is changed by the user. It demonstrates

video overlay using a clip mask, capture and storage of a video

image to system memory, and closed captioning processing. A

feature is in development which will display odd fields in real

time, with simultaneous capture of even fields, as required in

some video conference applications.

The RPS feature allows loading of different set-ups. This could

be used, for example, to alter the scaling factor after an event

such as a V-sync or H-sync signal, enabling the display of video

at two different locations simultaneously or the creation of spe-

cial effects. There is also a VBI mode for Intercast systems and

an audio capture and playback mode.

11-8 Multimedia PC

SAA7140 demoboard

The DPC7140 demoboard features Philips’ High Performance

Scaler IC, the SAA7140 (see page 4-11) and has two main appli-

cation areas. The first is for Multimedia PCs, where the video

display output is merged with the graphics display at the com-

puter monitor using the SAA7167 Mix-DAC (see page 4-29), to

provide video in a window. The second uses a digital video

encoder for digital television applications.

The board also can be used to evaluate the very high quality of

the High Performance Scaler core. It allows a direct contrast

between simple scaling by pixel and line dropping, used by the

SAA7195A (see page 4-31), which can produce artefacts, and

the high performance scaling of the SAA7140, which produces

high quality scaled images even down to icon size.

Hardware

The DPC7140 demoboard is a 16-bit ISA-bus based PC add-in

card. An SAA7111 or SAA7110A (see pages 4-4 and 4-3) digital

multistandard video decoder is used as the video front-end. This

converts analog video input from the CVBS or S-Video connec-

tors to a digital signal and delivers the control signal and the

line-locked clock. The SAA7140 then up- or down-scales the

video images before passing them to the SAA7195A, which per-

forms scan rate conversion from TV to graphics display. Output

is either a merged video and RGB signal using the SAA7167

Mix-DAC, or a reconstructed video signal from the SAA7183

encoder (see page 4-14), depending on the application.

As well as the video input connectors, there is an I2C-bus inter-

face and a YUV expansion connector which allows access to the

MSB909

EURO-DENC

SAA7182/

SAA7183

VIDEO

FRONT-END

SAA7110

SAA7111

HIGH PERF.

SCALER

SAA7140A

AND OPT.

LINE-MEMORY

CVBS

S-video

MIX-DAC

SAA7167

VIDEO

MEMORY

CONTROLLER

SAA7195A

EXPANSION

CONNECTOR VGA FEATURE

CONNECTOR

VRAM

BANK

RGB

input

key control

RGB

output

CVBS

S-video

RGB

output

PC ISA bus interface

DPC7140

HIGH PERFORMANCE

SCALER BOARD

digital YUV data bus. There is also a control connector for the

OSD function of the SAA7183 and a video output connection,

as well as analog RGB VGA input and output connections.

Software

The software is a demonstration application covering input

source selection, video attribute control and colour keying func-

tions, as well as the scaling and zooming functions, and it

includes all low level drivers. It operates under Windows 3.1 (or

higher) and provides a number of simple dialogue boxes for edit-

ing video parameters, described as follows:

• Configuration: used to set the I/O address of the DPC7140

board

• Video overlay: places the video in a window and stretches it

to fit, unless altered under the Video Location control.

• Video source: for selecting the video input connector and

video source, which sets the PLL lock-time for the decoder.

The HPS expansion port is used with applications which feed

direct video streams to the device, such as MPEG ICs.

• Video attributes: for control of input video BCS and lumi-

nance.

• Video location: used for manual selection of the size of the

video within a window and setting scale and zoom factors

independently, for both the horizontal and vertical axes.

• Miscellaneous: for adjusting display offset (which allows for

timing differences depending on the VGA card), scaling via

the SAA7140 or SAA7195A, freezing/unfreezing the video,

horizontal mirror and selecting the format for the video

memory.

REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS

DPC7140

11-9

Multimedia PC

MPEG-1 video playback evaluation kit

This board is an MPEG-1 technology demonstrator using the

SAA7131A FMPEG-1 decoder (not commercially available). It

particular, it shows its capability for synchronous processing of

audio and video data streams in a number of application modes.

In general, all of these application modes support slow motion,

scan, still picture operation and frame grabbing for further pro-

cessing.

The SAA7131A reads MPEG-1 data from hard disk or CD-

ROM through its ISA-bus interface. After decompression, the

signal is passed to the SAA7182/83 encoder (see page 4-14),

outputting CVBS, S-video or RGB for display on a TV or PC

monitor. Audio data is handled through the TDA1305 dual

audio DAC (see page 8-9) and the TDA1308 stereo headphone

driver (see page 8-16). Decompressed data can also be written

back onto the ISA bus for further processing or hard disk stor-

age.

For maximum flexibility, this board includes a digital multistan-

dard decoder, either the SAA7110A or the SAA7111 (see pages

4-3 and 4-4), the SAA7195A Video Memory Controller (see

page 4-31) with VRAM, and the SAA7167 Mix-DAC (see page

4-29). The decoder digitizes and decodes multistandard CVBS

or S-Video signals from broadcast sources, cameras or VCRs.

Signal filtering, formatting, scaling and video buffering func-

tions are handled by the SAA7195A, which also provides an

interface to the PC bus. Finally, the SAA7167 Mix-DAC takes

digital video data, converts it into the analog domain and

merges it with analog RGB signals from the VGA feature con-

nector, for display of video signals in a window. Several video

modes can then be demonstrated (in all cases audio is output

through the TDA1305 and TDA1308):

•MPEG direct TV output mode. MPEG data from the ISA-

bus is decoded in the SAA7131A; video is displayed directly

on a TV through the SAA7182/83 encoders.

MSB910

EURO-DENC

SAA7182/

SAA7183

VIDEO

FRONT-END

SAA7110

SAA7111

FMPEG

SAA7131

DRAM

CVBS

S-video

DAC

audio

MIX-DAC

SAA7167

VIDEO

MEMORY

CONTROLLER

SAA7195A

EXPANSION

CONNECTOR VGA FEATURE

CONNECTOR

VRAM

BANK MUX

RGB

input

key control

RGB

output

CVBS

S-video

RGB

output

PC ISA bus interface

MPEG DEMOBOARD

DPC7131

•Expansion connector mode. This is essentially the same, but

uses the expansion connector to take MPEG-decoded data off

the board for further processing on another board - scaling,

using Philips SAA7140 high performance scaler, for example

- or to a PCI bridge scaler (SAA7146).

•Cost-effective VGA slave mode MPEG overlay. MPEG data

from the ISA-bus is decoded in the SAA7131A; video is sent

through the SAA7167 where it is converted to analog RGB

and overlaid with the system VGA data as master, and dis-

played on the PC monitor.

•Normal MPEG overlay mode. In this advanced video play-

back mode, decompressed video data is fed through the

SAA7195A, which provides more flexibility for up and down-

scaling and positioning the window on the PC monitor.

•Genlocked mode. This capability is suitable for simultaneous

handling of video sources. The SAA7131A decodes the

MPEG data as described, while the SAA7110A/SAA7111

decodes an input video signal. The SAA7110A/SAA7111 is

the master and displays a full screen picture, overlaid with the

MPEG video (or you can toggle between full screen live video

and MPEG video).

•Genlocked MPEG/TV overlay mode. A high-end solution for

simultaneous handling of MPEG data and video. Similar to

the above example, it also uses the odd/even frame storage

capability of the SAA7195A so that a live video signal and the

MPEG video can both be displayed together in a window on

the PC.

This evaluation kit includes the board, driver software for

Windows MCI and DOS OMI along with debugging and

demonstration software with a sample Video-CD. For complete-

ness, it also has full hardware and software documentation,

ORCAD, layout, Gerber and Aperture files, and a device list -

and even a VGA feature connector and RGB cables.

REFERENCE/EVALUATION BOARDS & SOFTWARE EVALUATION KIT

DPC7131

11-10 Multimedia PC

SAA7167 Demoboard

This ISA-bus based PC add-on card provides a platform for

developing applications which capture live video for playback at

a later time. Although the board is primarily intended as a base

for an image capture, storage and graphics overlay board, audio

ICs can easily be integrated for real world multimedia applica-

tions.

The DPC7167 front-end has an SAA7110 or SAA7111 (see

page 4-2) digital multistandard decoder which digitizes and

decodes CVBS and S-Video signals. It also includes an

SAA7195A Video Memory Controller (see page 4-31) and

4 Mbit of VRAM, providing image storage, video buffering and

simple scaling functions. An ISA-bus interface and a feature con-

nector allow analog RGB signals to be fed through to the

SAA7167 Mix-DAC (see page 4-14), for mixing of processed

image data with separate analog RGB signals, for example for

video overlay in a window.

A suite of video capture software is provided, developed with the

Video for Windows 1.1 Software Development Kit. This

includes a video capture (VidCap) driver which allows the user

to freeze and capture single and multiple frames. It also allows

capture of live video streams and generation of AVI files, which

REFERENCE/EVALUATION BOARDS & SOFTWARE DEMOBOARDS

SAA7110 SAA7167

SAA7195A

2M-BIT

VRAM

2M-BIT

VRAM

GRAPHIC

SUBSYSTEM

ISA

INTERFACE FEATURE CONNECTOR

ISA-bus

I2C

MSC238

CVBS MUX

analog

RGB

can be saved for future playback, compression or editing.

Various software compression routines are provided.

The driver has components for device set-up, system configura-

tion and debugging. There is also extensive user control of video

parameters such as video format; image format, size, overlay and

display characteristics such as BCS; video source and so on.

Video images can be played back using either the Media Player

or through the VidEdit tool.

DPC7167

SAA7112

Evaluation board

An evaluation board for the SAA7112 (see page 4-2) is in devel-

opment. The SAA7112 is a single-chip decoder/scaler offering

essentially the combined functionality of the SAA7111A and

SAA7140 with an image port for direct interfacing to VGA con-

trollers. This functionality is described in a combined

Application Note AN96053.

11-11

Multimedia PC

This software is designed to accompany all DTV demoboards

and allows designers to set-up and evaluate individual ICs on a

board. It provides an interface to the ICs at register level, allow-

ing the register contents of each IC to be displayed and modified

in a separate window. Register settings can be saved and restored

from disk. The kit essentially provides standard low-level I2C

driver support and as such, can even be used outside the DTV

environment.

The kit consists of a number of tools running on a standard

IBM PC under Microsoft Windows (3.1, 3.11 and ’95). During

installation, the I2C-bus master must be configured, which can

either be the SAA7146 PCI bridge and Scaler (see page 4-9, 18),

the SAA7195A Video Memory Controller (see page 4-9, 31) or

a line printer port adapter, if installed.

Board builder

This powerful tool allows designers to build their own test

boards for testing, verification or evaluation (a board in this case

being a group of ICs accessed together in an application).

Standard set-up files are provided for all Philips MPC ICs,

which load the IC registers with start-up values. Initialization

can be manual for each IC, or can be performed automatically

for all ICs through the DTV shell, in which case you use the

board builder to create a board initialization file.

Standard IC set-up files can be used directly for board evalua-

tion or modified as required. They can also be overwritten with

user defined files. An example board file is provided with the

software, which can be modified to create board files without

using the board builder.

DTV shell

The DTV shell is a type of file manager, providing access to one

program (normally a register view) for each IC. It is used to load

a board set-up file (created manually or using the board builder),

which in fact simply provides links to the executables, making it

easier for users to modify them. All executables for a board set-

up are displayed as icons.

Other modules

The kit includes a Register View function, which allows viewing

and modifying of individual IC registers. If an I2C device has no

I2C Transceiver. There is also an I2C Status Viewer. Two spe-

cific Overlay Windows for the SAA7195A and for the

SAA7195A/SAA7140 provide easy access to these device regis-

ters - as the window is scaled and re-sized, the registers are

updated automatically. A VRAM I/O Access utility enables sim-

ple transfer of files to and from VRAM and VLUTs and a

Picture Converter tool allows translation of captured images

between various video formats. An MCI Media Player is also

included which, unlike the standard Windows player, can be

used to send individual MCI commands from a command line.

REFERENCE/EVALUATION BOARDS & SOFTWARE GENERAL SOFTWARE

The Universal Register Toolset (URT) was developed to reduce

the effort required to create the software needed to support new

devices, such as debuggers, sample applications, etc. This cuts

the time and cost for generating a working version of a complete

new software application and allows quicker and more cost-

effective updates.

The approach is based on allowing the user to work with logical

rather than absolute values and register addresses. The URT

allows the application engineer to define details of a chip in a

specially-developed language, in a description file. From this, the

URT compiler automatically generates a stand-alone Visual

BASIC application which allows IC data manipulation at the

logical level, allowing programming by simply changing logical

Toolset provides an interface between PC application software

and devices, handling the complex task of converting low level

data structures into readable formats.

The appearance of the program can be visually modified with

the Visual BASIC development system, which requires no

knowledge of BASIC itself. The URT also includes a ‘C’ inter-

face which a systems programmer can use in more complex

work-benches, to design a software module without knowing all

the register mappings and value assignments of the device.

Additional modules can be designed as a Visual BASIC add-in

(OCX), which can then be incorporated into the automatically

generated work-benches. The general approach is valid for all

bus systems and specific bus drivers are provided (I2C, PCI,

etc.). The URT supports single and multiple device sessions.

As a consequence, the hardware developer need not be familiar

with a specific Windows-related programming language or the

Windows system design when adapting tools for a new or modi-

fied IC. Similarly, a programmer creating a new user interface

for an existing device will not need to know all the details of the

IC at low level - the whole approach is aimed at ensuring simple

applicability to new targets for anyone familiar with the target

hardware functionality. It is a genuinely universal tool, support-

ing any device controlled using registers.

DESKTOP VIDEO DEBUGGER KIT

MACRO FILE

URT-COMPILER

URT.DLL

BUS DRIVER

DEVICE

DEFINITION FILE

APPLICATION URD

IDF URDHEADER

MSC240

UNIVERSAL REGISTER TOOLSET

11-12 Multimedia PC

The URT structure

Logical values are used in a hardware specification to describe a

device. However, for programming purposes a logical value may

cover several physical registers and a register might represent two

logical values, depending on the value being read/written. This

can lead to software errors which are very difficult to trace.

First a Device Definition File is created, describing the device in

terms of registers, RAM areas and logical groups. This can be

done manually using a text editor or using the provided Device

Definition development tool, which includes aids such as syntax

highlighting and a menu system to access URT components

such as the compiler. From this, the URT compiler creates an

Internal Definition File, read by the main URT DLL, which

acts as an interface between the application and the driver for

the bus in use. The bus driver DLLs can be accessed by the URT

DLL and the URD (Universal Register Debugger), and are

responsible for transferring read/write commands to the device.

REFERENCE/EVALUATION BOARDS & SOFTWARE GENERAL SOFTWARE

The URT DLL also creates ‘C’ header files from the Device

Definition Files. These contain definitions of registers and their

values, and entry points for the functions offered by the URT

DLL, which can be used by ‘C’ applications. Special support

such as automatic Form generation is provided for MS Visual

BASIC, offering a graphical user interface and a visual represen-

tation of some registers and macros, to make prototyping as fast

and simple as possible for developers not familiar with more

advanced programming.

A detailed definition of the low level interface is provided to

allow users to add their own low level drivers, written in C++,

without having to recompile the DLL. A number of OCX con-

trols will be added for special functions such as a Window

Overlay, Frame Grabber, etc. The URT DLL is provided in a

16-bit version for Windows 3.x and 32-bit for Windows ’95 and

NT.

APPLICATION

ENGINEER APPLICATION

ENGINEER

VISUAL

BASIC

INTERNAL

DEFINITION

FILE

URT-DLL

BUS DRIVER

DLLs

DEVICES

application creation

application path

device definition path

change notification

usage

URT-COMPILER

APPLICATION

ENGINEER

SYSTEM

PROGRAMMER

END USER

URD OCX

DEVICE

DEFINITION

FILE

MSC239

WORK

BENCH

12-1

Multimedia PC

MONITORS

12-2 Multimedia PC

Philips complete solutions

Philips has a vast array of specially designed or optimized ICs for

monitors, as well as a full range of discrete components. You can

source everything you need from Philips to build a monitor,

ranging from small, cost-effective PC monitors, through larger

and more highly featured displays for more demanding PC

applications, up to large workstation or CAD/CAM monitors.

Most ICs are I2C-bus controlled, which allows simple control of

the whole system, cutting design time and allowing quick auto-

matic factory adjustment of many functions.

Only a very brief summary of the main ICs and discrete semi-

conductors for core monitor functions are given here. For a

more detailed review, please refer to the quick selection guide

MICRO-

CONTROLLER

H/V

sync

DDC

int

H/V

eht

MSC219

brightness

uniformity

dynamic

convergence

control

USB

bus USB HUB

EEPROM

MULTIPLE

DACs

LCD

DISPLAY

OSD

VIDEO

PRE-AMP VIDEO OUTPUT

AMPLIFIERS

VECTOR

PROCESSOR

VERTICAL

DEFLECTION HORIZONTAL

DEFLECTION

POWER

SUPPLY

DEFLECTION

PROCESSOR

RGB

I2C-bus

factory

test &

calibration

MONITORS

‘Semiconductors for Monitors’ (12NC 9397 750 01004); full

details are in the separate ‘Monitors Designer’s guide’, which is

in preparation.

Philips Semiconductors devices for other functions in a monitor,

such as audio for multimedia monitors, are covered both in this

guide and in other Designer’s guides (see Appendix 1 on

Documentation); Philips can also provide other devices for a

complete solution, such as power supply controllers; and other

monitor components such as the picture tube, deflection units,

line transformers and so on are all available from Philips

Components.

Typical high-end monitor configuration with vector processing option for dynamic convergence

12-3

Multimedia PC

SYNC PROCESSORS TDA4855 TDA4858 TDA4854 TDA4853

Max. hor. frequency (kHz) (autosync) 30 to 100 30 to 100 15 to 130 15 to 130

Vert. freq. range (Hz) (autosync) 40 to 110 40 to 110 40 to 160 40 to 160

VGA mode yes no no no

E-W parabola generator yes yes yes yes

TV/VCR mode no no yes yes

Geometry controls external external on-chip on-chip

Adjustments DC DC I2C I2C

Supply voltage (V) 9.2 to 16 9.2 to 16 9.2 to 16 9.2 to 16

Package SDIP32 SDIP32 SDIP32 SDIP32

Deflection controllers

Philips has a large range of sync processors, with a wide range of

functionalities and integration levels, reflecting the evolution of

market technology and suitable for many types of monitor. The

products are grouped into families for 14", 15" and 17" models.

Currently, Philips highly integrated TDA4855/58 autosync

devices represent the state-of-the-art. The next generation

TDA4853/54 devices are already in design: they are based

Vertical boosters

As for the deflection controllers, Philips vertical booster product

family is divided into a low cost range, suitable for the highly

competitive market for monitors up to 15"; and a range for high

performance monitors of 17" and above. Two broad design

types are available: standard half-bridge circuits and highly inno-

vative full bridge solutions. The full bridge, a design unique to

Philips, has a very high level of integration, although it is does

have a higher power dissipation. The vertical boosters are DC-

coupled to the deflection controller, eliminating the need for

bulky blocking capacitors and keeping the circuit free from

bounce during mode changes.

MONITORS

around a complete I2C-bus control concept which addresses the

merging PC/TV market and also include features such as Moiré

cancellation and extensive integrated geometry control func-

tions. The TDA4855/54 include dynamic focus capability on

chip, while the TDA4858/53 are intended for markets segments

which do not require dynamic focus. Together with the

TDA488X video controller family and TDA486X booster fami-

ly, they form a complete and powerful solution for PC monitors.

Video controller

Philips has an excellent product offer for the low-end market

segment, with its TDA4882/84, 85 MHz ICs. These have a

higher integration level than most competitive products and also

include greyscale tracking, which ensures colour remains con-

stant as the user adjusts brightness and contrast.

The new TDA4885 has a range of innovative features such as

gain modulation, which delivers a uniform brightness across the

entire screen, compensating for light fall-off from the centre to

the edges of picture tubes (which is highly disturbing to

viewers). It is fully I2C bus controlled, which reduces the num-

ber of wires between the main board and video board, making

designs more tolerant of EMI disturbances.

VIDEO PRE-AMPLIFIERS TDA4882 TDA4884 TDA4885

Bandwidth (MHz) 85 85 150 (note 3)

Number of channels 3 3 3

Gain, brightness and contrast control DC (note 1) DC (note 2) I2C

Gain modulation no no yes

Greyscale tracking yes yes yes

Output stage can drive discretes can drive discretes universal

Supply voltage (V) 8 8 8

Package DIL20 DIL20 SDIP32

Notes

1Brightness control on-chip, two gain controls

2Brightness control via grid 1, three gain controls

3Pixel rate

12-4 Multimedia PC

Microcontrollers

Philips offers more 80C51 derivative microcontrollers than any

other supplier and this includes an exceptionally broad offer of

microcontrollers dedicated to monitor applications.

Versions are available with 4 K ROM, up to devices offering a

maximum of 64 K Flash EPROM, while RAM options extend

from 128 K up to 512 K. Devices are available with a range of

analog PWM outputs, on-board ADCs and full-duplex UARTs,

and some versions have up to 48 I/O lines. All have at least two

timer/counters and a watchdog timer that enables fail-safe

recovery.

More advanced controllers also include on-board DACs and a

number of dedicated functions such as composite sync separa-

tion, auto-sync detection and DDC1/DDC2 support. The very

latest also includes a USB-bus interface and HUB. For details of

the HUB, refer to Bus ICs in Section 10.

MONITORS

Vector processor

Philips has in test a vector processor offering a range of functions

including a correction waveform generator specifically for colour

monitors. It has two correction channels with current outputs

and the waveform generator tracks with picture width and

height, and is independent of scan frequency. It offers 3 ×3

point alignment with one channel and, by adding both chan-

nels, quasi 5 ×5 point alignment. Waveform alignment can be

I2C-bus controlled.

Multiple DACs

Philips multiple DACs are a simple and cost-effective single-chip

solution for various monitor applications, for example for RGB

gain and cut-off or for a range of geometry parameters.

MULTIPLE DACSTDA8444 TDA8447

Number of DACs 8 8

Resolution (bits) 6 8

Output voltage range (V) 0.1 to VP– 0.5 0.4 to VP– 0.8

I2C-bus yes yes

Supply voltage (V) 10.8 to 13.2 4.5 to 8.8

Package DIP16, SO16L, SO20 DIP16

Memories, OSD and LCD display drivers

As part of its complete monitors solution, Philips has an OSD

circuit which can display 128 characters (from ROM) in a

12 ×16 matrix, offering a variety of colour background modes.

LCD display drivers include segment and dot-matrix types.

Segment drivers can drive 24 to 96 or 40 to 160 segments;

matrix drivers offer either 18 ×16 or 32 ×60 dots (rows ×

columns). Non-volatile memories run from 128 ×8-bit serial

access, up to 2048 ×8.

Discrete semiconductors

Of course discrete semiconductors play a major role in monitor

design and function and Philips is one of the world’s major dis-

crete semiconductor manufacturers.

For deflection, rectification and EHT generation, Philips has

extensive ranges of fast soft recovery controlled avalanche recti-

fiers, ultra fast low-loss controlled avalanche rectifiers, high volt-

age soft recovery rectifiers and damper diodes, all available in a

number of voltage, current and power specification combina-

tions. Similarly, Philips has power transistors for horizontal

deflection output stages, ranging from devices for 14" SVGA

38 kHz monitors, up to 17", 64 kHz and 82 kHz monitors.

Other discrete semiconductors for monitors include video out-

put amplifier transistors and modules, transistors for the

modules’ input buffer stages and PowerMOSFETs for S-

correction capacitor/mode switching.

13-1

Multimedia PC

TRIMEDIA

13-2 Multimedia PC

PROGRAMMABLE

MULTIMEDIA PROCESSORS

In the multimedia market, some trends are clearly definable.

Individual media functions are evolving in graphics, audio, video

and communications and as they develop, they are being com-

bined to create true multimedia applications – ones which are

highly realistic and truly interactive. This demands an integrated

approach with high performance, concurrent processing of mul-

tiple data types and while programmable DSPs can provide the

power, they have been complex to program, using assembly lan-

guage. By combining cost-effective advanced microprocessor

technology, easy programmability and comprehensive software

tools, Philips TriMedia family of programmable multimedia

processors provides the answer.

At the core of the TriMedia chip is a DSP/CPU, which

integrates the power of a DSP with a high performance VLIW

architecture, with robust, CPU style development environment.

It is fully programmable in high-level C and C++ languages on

UNIX and PC platforms and by allowing the developer to work

in a familiar language, product development, testing, fine-tuning

and optimization of software libraries becomes quick and effi-

cient.

MSC244

PROGRAMMABLE DSP

Entertainment/Education

Audio

Graphics

Video

Communications

macrotrend:

combination of media functions

microtrend:

evolution of media functions

Settop TV

Video conferencing

mono stereo wavetable waveguide

still Indeo MPEG-1 MPEG-2

LAN WAN wireless

2D 3D VR

MSC193

PROGRAMMABLE DSP:

high performance, VLIW architecture

multifunctional hardware

integrated multimedia functions

ROBUST SOFTWARE ENVIRONMENT

compiler & tools

RTOS

video audio graphics communications

multimedia applications libraries

TRIMEDIA SOLUTION

combines DSP performance with CPU software

TRIMEDIA

With an instruction set optimized for multimedia operations

and its highly parallelized architecture, at 100 MHz TriMedia

yields a peak performance of 4 billion operations per second.

With this astonishing performance, its ease of programmability

and with the advanced algorithms for audio, video, graphics,

fax/modem, telephony and video conferencing available,

TriMedia reduces time to market for OEMs.

Unlike other multimedia processors, the TriMedia TM-1

DSP/CPU offers an open development environment. By not

forcing developers into a proprietary architecture and allowing

them to work in a familiar, open and easily programmable envi-

ronment, they can minimize the time-to-market for new, high

performance multimedia applications for the PC and consumer

markets. Philips fully expects TriMedia to become the industry

standard for multimedia applications.

13-3

Multimedia PC

PARTNERING FOR OPEN MULTIMEDIA

DEVELOPMENT

As part of its strategy of providing an open platform which will

drive the development of new, innovative multimedia applica-

tions, the TriMedia Group is developing relationships with a

growing list of Independent Software Vendors (ISVs). These

partnerships will result in continuous innovation in advanced

software libraries to meet evolving needs, driving the multimedia

applications market to the next level.

The first development partnership is with InVision Interactive,

Inc., a leader in digital audio technology. Their software will

enable the first processor in the TriMedia family, the TM-1, to

deliver virtually all the capabilities of a fully compliant General

MIDI synthesizer (see below for a broad look at the TM-1

chip). These new capabilities are in addition to TriMedia's sup-

port of Microsoft’s DirectX API, including the direct sound

interface, enabling TM-1 to play powerful sound effects and 3D

positional audio. Thus, TM-1 can transform a desktop

computer into a powerful musical instrument without the need

for a sound card. These libraries will be available to TriMedia

customers, so that they can develop state-of-the-art audio capa-

bilities for their multimedia applications.

TM-1: THE FIRST IN A FAMILY

The TM-1 family is a complete processing environment for

high-performance multimedia applications ranging from low-

cost, single-purpose systems such as video phones to re-program-

mable, multi-purpose plug-in cards for PCs. Controlled by a

small real-time OS kernel running on the VLIW core and using

a variety of open or proprietary multimedia algorithms, TM-1

easily implements popular multimedia standards such as

MPEG-1 and MPEG-2.

With its CPU, high-bandwidth internal bus and internal bus-

mastering DMA peripherals, TM-1 is tailored for use in PC-

based real-time multimedia applications. It provides the low cost

and chip count of a special-purpose, embedded solution, com-

bined with the re-programmability of a general-purpose proces-

sor. To give an indication of the power of this technology, using

a cycle-accurate simulator to evaluate a mixed multimedia appli-

cation of decoding MPEG-1 data at 30 fps with superimposed

texture mapped 3D graphics, at 100 MHz the TriMedia-1 con-

TRIMEDIA

sumes only 22% of the available processor cycles and 12% of the

memory bandwidth.

The main functional blocks in TM-1 are the microprocessor

core itself, a memory interface for SDRAM (Synchronous

DRAM) and peripheral I/O blocks for interfacing with multi-

media data streams. All interfaces are glueless and include

CCIR-601 compliant Video-in and Video-out units, and Audio-

in and Audio-out units which require only an ADC and DAC

respectively. Both audio and video units are programmable,

offering a high degree of user-customization. TriMedia includes

a PCI interface for communications with the host PC and a

V.34/ISDN interface providing remote communication support

or interfacing to a network. It also includes accelerators for video

scaling interpolation and variable length decoding for smooth

flow of video in an unlimited number of arbitrarily overlapped

windows.

Other TM-1 derivatives will have varying interface sets targeted

at different applications. All TM-1 solutions will be software

compatible at C/C++ source-code level, allowing Philips to

strike the optimum balance between cost and performance for

all the chips in the family. Engineering samples of the TM-1 are

currently shipping to Early Access Program (EAP) customers

with volume shipments expected by the first quarter of 1997, at

a pricing level compatible with consumer electronics applica-

tions.

DAC

JTAG

I2C

ADC

video

CCIR-601/656

YUV 4:2:2

video

CCIR-601/656

YUV 4:2:2

synchronous

serial i/f for

V.34 / ISDN

serial

digital

audio

SDRAM

PCI local bus

MSB932

HIGHWAY

IMAGE COPROCESSOR

SCALING

COLOUR CONVERSION

SYNC. SERIAL I/F

PCI MASTER / SLAVE BRIDGE

TIMERS

VIDEO DMA OUT

VLD COPROCESSORVIDEO DMA IN

AUDIO DMA IN

AUDIO DMA OUT

DSPCPU

CORE

I $

D $

13-4 Multimedia PC

TYPICAL TM-1 PC APPLICATIONS

PC-based MPEG video compression

In this case, a camera chip or other source supplying uncom-

pressed 8-bit 4:2:2 YUV video data is connected directly to the

TM-1’s video-in unit, which samples and demultiplexes the Y,

U and V data, storing it in separate SDRAM areas. When a

complete video frame has been read it interrupts the TM-1

CPU, which compresses the video data using a powerful set of

data-parallel software operations and writes it to another

SDRAM area. The compressed video data can now be sent to a

host system over the PCI bus, for archival on local mass storage,

or it could be transferred by the host over a network such as

ISDN. Alternatively, the data could be sent to a remote system

using the integrated V.34 interface, creating a video phone or

video conferencing system. The TM-1 CPU could also encrypt

the compressed data before transmission, for security.

Video decompression in a PC

One typical application for TM-1 is in a video-decompression

card in a PC. The PC operating system hands the TM-1 card a

pointer to compressed video data in the PC’s memory. The

TM-1 CPU fetches data from the compressed video stream via

the PCI bus, decompresses frames from the video stream (possi-

bly aided by the variable-length decoder unit) and places them

into local TM-1 SDRAM. When a frame is ready for display,

the TM-1 CPU issues a display command to the image

coprocessor, which fetches the decompressed frame and transfers

it over the PCI bus to the frame buffer, in the PC’s video display

card (or in system memory if the PC uses a Unified Memory

Architecture).

Video conferencing

TriMedia easily implements a PC-based video conferencing sys-

tem: with its dedicated communications, image and VLD co-

processing units, the TM-1 further relieves the computer of

compression/decompression and communication tasks.

SAA7111 SDRAM

SCSI

CONTR.

TM-1

PCI

80 × 86

PCI-bus

PCI

HDD

SAA7366T

MSC241

MSC231

SAA7111

VIDEO

DECODER

+ SCALER

SAA7366

PREAMP +

AUDIO A/D

SAA7185B

VIDEO

ENCODER

TDA1388T

AUDIO D/A

+ AMP

TM-1

TRIMEDIA

(DE) COM-

PRESSOR

TV or VCR

speakers

monitor

ISDN

RECEIVER

ISDN

TRANS-

MITTER

YUV YUV

CVBS

I2S I2S

PCI bus

microphone

ISDN

phone line ISDN

phone line

video in

GRAPHIC

CONTROLLER

TRIMEDIA

A-1

Multimedia PC

APPENDICES

A-2 Multimedia PC

APPENDICES

Separate data sheets

OQ8844 Triple digital servo driver 9397 750 00471

OQ8868 Digital servo controller 9397 750 00785

SAA2501 Audio MPEG-1 decoder for Astra Digital Radio (ADR) 9397 746 40011

SAA7110A One Chip Front-end (OCF) 9397 750 00368

SAA7111 Video Input Processor 9397 750 00847

SAA7112 Decoder with HPS scaler for image port 9397 750 00923

SAA7140A/B High Performance Scaler (HPS) 9397 750 00984

SAA7167(A) Mixer and D/A processor 9397 750 00416

SAA7182/83 EURO-DENC digital video encoder 9397 750 00324

SAA7184/85B DENC-M6 digital video encoder 9397 750 00928

SAA7187 DENC2 Square pixel digital video encoder 9397 750 00325

SAA7188A/85 DENC-M digital video encoder 9397 750 00944

SAA7360 Bitstream ADC 9397 750 00081

SAA7385 High performance CD-ROM controller 9397 750 00917

SAA7388 Error corrector and host interface 9397 750 00808

SAA7390 High speed CD-recordable block decoder/encoder 9397 750 00942

TDA1300T Photodetector amplifiers and laser supply 9397 750 00441

TDA1305T(AT) Bitstream/CC filter DAC 9397 750 00517

TDA1309H Low power, low voltage stereo CODEC 9397 750 00879

TDA1311A(T) Low power stereo DACs 9397 750 00532

TDA1373 General digital I/O input with DSP (GDIO DSP) 9397 750 00927

TDA1386T Noise shaping filter DAC 9397 750 00518

TDA1387T Low power stereo DACs 9397 750 00519

TDA1388T(Z) Single-chip audio processor 9397 750 00516

TDA1396 16-bit stereo CODEC with FM synthesis 9397 750 00894

TDA1548T(Z) Single-chip audio processor 9397 750 00773

TDA4665 Baseband delay line 9397 750 00381

TDA8706A Video Enhancement and D/A processor 9397 750 00991

TDA8707 Triple RGB 6-bit ADC interface 9397 750 00605

TDA8708A 6-bit ADC with multiplexer and clamp 9397 734 20011

TDA8708B Video analog input interface 9397 734 80011

TDA8709A Video analog input interface 9397 734 60011

TDA8712 8-bit video DAC 9397 734 70011

TDA8758 Low power A/D interface 9397 750 00606

TDA8766 10-bit, high speed 3 V ADC 9397 750 00746

TDA8767 12-bit high speed ADC 9397 750 00889

TDA8771 Triple 8-bit video DAC 9397 750 00591

TDA8772(A)H(3/8) Triple 8-bit video DAC 9397 750 00029

TDA8775G Triple 10-bit video DAC 9397 750 01021

TDA8786(A) 10-bit A/D interface for camera CCDs 9397 750 00846

TDA8790 8-bit 40 Msps 2.7 - 5.5 V universal ADC 9397 750 00677

TDA9850 I2C-bus controlled BTSC stereo/SAP decoder 9397 750 00176

TDA9852 I2C-bus controlled BTSC stereo/SAP decoder & audio processor 9397 750 00706

TEA5757H/5759H Self-tuned radio 9397 750 00557

TEA6320 Sound processor 9397 750 00533

TEA6321 Sound processor 9397 750 00534

TEA6322 Sound processor 9397 750 00535

TEA6323 Sound processor 9397 750 00536

UAA3201T UHF/VHF remote control receiver 9397 750 00136

DOCUMENTATION

APPENDIX 1

A-3

Multimedia PC

ICs covered in data handbooks

PCF8574A Remote 8-bit I/O expander for I2C-bus Handbook IC22

SAA2500 Audio MPEG-1 decoder Handbook IC01

SAA5246A Integrated VIP and teletext decoder Handbook IC02

SAA5249 Integrated VIP and teletext decoder with

background memory controller Handbook IC02

SAA5252 Line 21 decoder Handbook IC02

SAA5254 Integrated VIP and teletext decoder Handbook IC02

SAA5281 Integrated VIP and teletext decoder Handbook IC02

SAA5290 One-page economy teletext/TV microcontroller Handbook IC02

SAA5296 Single-chip economy 10 page teletext/TV microcontroller Handbook IC02

SAA6579 R(B)DS demodulator Handbook IC01

SAA7146 Scaler and PCI bridge (SPCI) IC Handbook IC22

SAA7165 Video Enhancement and D/A processor Handbook IC22

SAA7186 Digital video scaler Handbook IC22

SAA7192A Digital colour space converter (DCSC) Handbook IC22

SAA7196 Digital video decoder and scaler (DESC-Pro) Handbook IC22

SAA7199B CCIR and square pixel digital encoder with genlock Handbook IC22

SAA7366 Bitstream ADC Handbook IC22

TDA1303T Digital Servo Driver (DSD1) Handbook IC01

TDA1306T Noise shaping filter DAC Handbook IC22

TDA1308T Class AB stereo headphone driver Handbook IC01

TDA1517P Stereo radio power amplifier Handbook IC01

TDA4655 Generic multistandard analog decoder Handbook IC02

TDA4670 Picture signal improvement processor Handbook IC22

TDA4686(WP) Analog video processor Handbook IC22

TDA4820T Sync. Separator IC for monitors Handbook IC22

TDA7072A(T) BTL motor drive circuits Handbook IC01

TDA7073A(T) BTL motor drive circuits Handbook IC01

TDA8501 PAL/NTSC analog encoder Handbook IC02

TDA8505 SECAM analog encoder Handbook IC02

TDA8540(T) 4 × 4 video switch matrix Handbook IC22

TDA8702 8-bit video DAC Handbook IC22

TDA9855 I2C-bus controlled BTSC stereo/SAP decoder and

audio processor Handbook IC22

TEA5582 PLL BTSC stereo decoder Handbook IC02

TEA6360 5-band graphic equalizer Handbook IC01

APPENDIX 1

APPENDICES

A-4 Multimedia PC

APPENDICES APPENDIX 1

Other information on ICs

There is preliminary technical information available on the following ICs: contact your local Philips sales office for more information

or refer to the Philips WWW home page.

CCR921 R(B)DS controller

CDU 2600 CD-Recorder subsystem and CD-R data engine

D65420 CD-Recordable data engine

E65400 CD-Recordable subsystem

P83C190 Monitor microcontroller with USB plus hub

PDI1394L11 IEEE P1394 serial bus AV link layer controller

PDI1394P11 IEEE P1394 serial bus AV physical layer controller (in development)

PDIUSBH11 USB stand alone hub

PDIUSBP11 USB transceiver

ROA1312/X CD-ROM subsystem and system solution (12×)

ROM 65XXX CD-ROM subsystems and system solutions (6× and 8×)

SAA2502 Audio MPEG-1 decoder with MPEG-2 stereo capability

SAA5284 Multimedia VBI and FF data acquisition IC

SAA7111A Enhanced Video Input Processor

SAA7124/5 ECO-DENC digital video encoder

SAA7182A/83A EURO-DENC2 digital video encoder

SAA7195A Video and Memory Controller (VMC)

SAA7348 ACE (All Compact disc Engine)

SAA7370(B)GP 10×single-chip digital servo processor and compact disc decoder

SAA8110 Camera DSP

SZA1010 Triple digital servo driver

TZA1015 Data amplifier and laser supply

Application notes

AN9312 TDA1305T

AN95014, AN94036 SAA2500/1

AN95056 User’s Manual DPC7167 Demo Board

AN96053 High Performance Scaler SAA7140A(/B)

AN96054 SAA7146 Software Development Kit

AN96055 Digital Video Decoder/Encoder Module System

AN96063 DPC7146 Demonstration Board User Manual

User manuals

UM95009 DTV7183 Demonstration Board V0.3

UM9601 DPC7140 Demonstration Software

UM9603 DPC7146 Evaluation Board V1.0

UM960XX DPC7140 Demo Board V0.1

A-5

Multimedia PC

APPENDICES APPENDIX 1

Data handbooks

IC01 Semiconductors for radio and audio systems 9398 652 93011 (new)

IC02 Semiconductors for television and video systems 9398 750 00074

IC22 Desktop video 9397 750 00141

IC12 I2C peripherals 9397 750 00306

Linecards

Digital video decoders linecard 9397 750 00621 (new)

Digital video encoders linecard 9397 750 00622 (new)

Video <-> PCI bridges 9397 750 00624

Other relevant designer’s guides

Audio data converters and miscellaneous digital audio ICs designer’s guide 9397 750 00151

Compact Disc designer’s guide 9398 750 00952 (new)

Digital Media Broadcast designer’s guide 9397 750 00727

Multimedia ICs selection guide 9397 750 00286 (new)

Portable and home hi-fi/radio designer’s guide 9397 750 00907

Terrestrial and satellite TV front-ends designer’s guide 9397 750 00147

TV designer’s guide 9397 750 00148

CD-ROMs

Desktop Video 9397 750 00644

A-6 Multimedia PC

µC Microcontroller

ACC Automatic Clamp Control

ACCU Accumulator

ADC Analog-to-Digital Converter

ADPCM Adaptive Differential Pulse Code Modulation

ADR Astra Digital Radio

AGC Automatic Gain Control

AM Amplitude Modulation

API Application Program Interface

ASIC Application Specific Integrated Circuit

ASK Amplitude Shift Keying

ASSS Automatic Sector Size Select

ATAPI AT - Additional Packet Interface

AVI Audio-Video Interleave

BCC Bitstream/Continuous-Calibration

BCS Brightness, Contrast and Saturation

BER Bit Error Ratio

BIOS Basic Input/Output System

BITBLT BIT-BLock Transfer

BRS Binary Ratio Scaler

CAS Column Address Select

CAV Constant Angular Velocity

CC Continuous-Calibration

CC Closed Caption

CCD Charge-Coupled Device

CCIR Comité Consultatif International des

Radiocommunication

CD Compact Disc

CD-i Compact Disc - Interactive

CDM Compact Disc Mechanism

CD-R Compact Disc Recordable

CD-R/E Compact Disc - Recordable/Erasable

CIF Common Interchange Format

CLUT Colour Look-Up Table

CMOS Complementary Metal Oxide Semiconductor

CODEC COder-DECoder

CPU Central Processing Unit

CRC Cyclic Redundancy Check

CRT Cathode Ray Tube

CTI Colour Transient Improvement

CVBS Composite Video Baseband Signal

DAB Digital Audio Broadcast

DAC Digital-to-Analog Converter

DAT Digital Audio Tape

DAVIC Digital Audio VIdeo Council

DCC Digital Compact Cassette

DCT Discrete Cosine Transformation

DCTI Digital Colour Transient Improvement

DEBI Dynamic Expansion Bus Interface

DENC Digital ENCoder

DIN Deutches Institut für Normung

DLL Dynamic Link Library

APPENDICES APPENDIX 2

DM Direct Mode

DMA Direct Memory Access

DMSD Digital Multi-Standard Decoder

DMX Digital Music Express

DRAM Dynamic Random Access Memory

DSP Digital Signal Processing

DTV DeskTop Video

DVB Digital Video Broadcast

DVS Digital Video Scaler

EAP Early Access Program

EBU European Broadcasting Union

EDC Electronic Data Check

EEPROM Electrically Erasable Programmable Read Only

Memory

EHT Extra High Tension

EIAJ Electronic Indentity Association Japan

EMC ElectroMagnetic Compatibility

EMI ElectroMagnetic Interference

EPLD Electronically Programmable Logic Device

EPROM Erasable Programmable Read Only Memory

ESD Electro-Static Discharge

FCC Federal Communications Commission

FF Full Field

FIC Fast Information Channel

FIFO First In, First Out

FIR Finite Impulse Response

FM Frequency Modulation

FMM Field Memory Mode

FMV Full Motion Video

FPGA Fast Programmable Logic Array

FTC Fast Track Control

GUI Graphical User Interface

HAL Hardware Application Layer

HPS High Performance Scaler

I2C Inter-IC

I2S Inter-IC Sound

IDE Integrated Drive Electronics

IEC International Electrotechnical Commission

IEEE Institute of Electronic and Electrical Engineers

IIR Infinite Impulse Response

ISA Industrial Standard Architecture

ISDN Integrated Services Digital Network

ISO International Standardization Organization

ISV Independent Software Vendor

JPEG Joint Photography Experts Group

LCD Liquid Crystal Display

LED Light Emitting Diode

LMM Line Memory Mode

LUT Look-Up Table

MCI Media Control Interface

MD Music Disc

MIDI Music Instrument Digital Interface

GLOSSARY OF ABBREVIATIONS

A-7

Multimedia PC

MPC Multimedia Personal Computer

MPEG Motion Picture Expert Group

MTS Multichannel Sound Modulation

MUSICAM Masking pattern adapted Universal Subband

Integrated Coding And Multiplexing

MUX Multiplexer

NABTS North American Broadcasting Teletext

Specifications

NTSC National Television Standards Committee

OCF One-Chip Front-end

OCX OLE Custom Control

OMI Open Messaging Interface

OSD On-Screen Display

PAD Program Associated Data

PAL Phase Alternate Line

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCMCIA Personal Computer Memory Card

International Association

PDM Pulse Density Modulation

PES Packetized Elementary Stream

PLL Phase-Locked Loop

PS-SL Philips Semiconductors - Systems Laboratory

PWM Pulse Width Modulation

QCIF Quarter Common Interchange Format

QPSK Quadrature Phase Shift Keying

R(B)DS Radio (Broadcast) Data Signals

RAMDAC Ramdom Access Memory Digital-to-Analog

Converter

RAS Row Address Select

RCA Radio Corporation of America

RDCL R(B)DS CLock

RDDA R(B)DS DAta

RF Radio Frequency

RPS Register Programming Sequencer

RTC Real-Time Control

RZ Return-to-Zero

SAP Second Audio Program

SCAM SCSI Configuration AutoMatically

SCSI Small Computer Systems Interface

SDRAM Synchronous DRAM

SECAM SEquential Colour And Memory

SIF Source Input Format

SMPS Switched Mode Power Supply

SNR Signal-to-Noise Ratio

SOAR Safe Operating Arena

SPDIF Sony-Philips Digital Interface Arena

SPI Serial Peripheral Interface

SRAM Static Random Access Memory

STN Super Twisted Nematic

STR Sychronous Transmitter/Receiver

SVGA Super Video Graphics Array

TFT Thin Film Transistor

THD Total Harmonic Distortion

TOP Technical/Office Protocol

TTL Transistor Transistor Logic

UHF Ultra High Frequency

URD Universal Register Debugger

URT Universal Register Toolset

USB Universal Serial Bus

USWST United States World Service Teletext

VBI Vertical Blanking Interval

VBR Variable Bit Rate

VCO Voltage Controlled Oscillator

VGA Video Graphics Array

VHDL VHSIC Hardware Description Language

VHSIC Very high speed IC

VHF Very High Frequency

VLD Variable Length Decoder

VLIW Very Long Instruction Word

VLUT Video Look-Up Table

VMC Video and Memory Controller

VMM Virtual Memory Manager

VoD Video on Demand

VPS Video Programming Selection

VPU Video Processing Unit

VRAM Video Random Access Memory

WSS Wide Screen Signalling

WST World System Teletext

APPENDICES APPENDIX 2

A-8 Multimedia PC
A
APPENDICES
TYPE NUMBER DESCRIPTION PAGE
CCR921 R(B)DS controller 6-5
CDU 2600 CD-Recordable subsystem and CD-R data engine 7-3
DMB chipset Range of ICs from Philips Digital Media Broadcast chipset 5-11
D65420 CD-Recordable data engine 7-3
E65400 CD-Recordable subsystem 7-3
OQ8844 Triple digital servo driver 7-13
OQ8868 Digital servo controller 7-11
PC Text Software for a range of Teletext decoder ICs  5-6
PCF8574A  Remote 8-bit I/O expander for I2C-bus 6-4
PDI1394L11 IEEE P1394 serial bus AV link layer controller 10-4
PDI1394P11 IEEE P1394 serial bus AV physical layer controller 10-4
PDIUSBP11  USB transceiver 10-2
PDIUSBH11 USB stand alone hub 10-3
P83C190 Monitor microcontroller with USB plus hub 10-3
ROA 1312 CD-ROM subsystem and system solutions (12×) 7-3
ROM 65XXX CD-ROM subsystem and system solutions (6× and 8×) 7-2
SAA2500  Audio MPEG-1 decoder 8-12
SAA2501 Audio MPEG-1 decoder for Astra Digital Radio (ADR) 8-12
SAA2502 Audio MPEG-1 decoder with MPEG-2 stereo capability 8-12
SAA5246A Integrated VIP and teletext decoder 5-6
SAA5249 Integrated VIP and teletext decoder with background memory controller 5-6
SAA5252  Line 21 decoder 5-8
SAA5254 Integrated VIP and teletext decoder 5-6, 7
SAA5281 Integrated VIP and teletext decoder 5-6
SAA5284 Multimedia VBI and FF data acquisition IC 5-6, 7
SAA5290 One-page economy teletext/TV microcontroller 5-9
SAA5296  Single-chip economy 10 page teletext/TV microcontroller 5-10
SAA6579  R(B)DS demodulator 6-6
SAA7110A  One Chip Front-end (OCF) 4-2, 3
SAA7111(A)  Video Input Processor 4-2, 4
SAA7112  Decoder with HPS scaler for image port 4-2, 5, 9
SAA7124/5  DENC-N digital video encoder 4-12, 15
SAA7140A/B  High Performance Scaler (HPS) 4-9, 11
SAA7146 Scaler and PCI bridge (SPCI) IC 4-9, 18
SAA7165  Video Enhancement and D/A processor 4-28
SAA7167(A)  Mixer and D/A processor 4-29
SAA7182/83  EURO-DENC digital video encoder 4-12,14
SAA7182A/83A  EURO-DENC2 digital video encoder 4-12, 13
SAA7184/85B DENC-M6 digital video encoder 4-12, 16
SAA7186  Digital video scaler 4-9, 10
SAA7187 DENC2 Square pixel digital video encoder 4-12, 16
SAA7188A/85 DENC-M digital video encoder 4-12, 16
SAA7192A  Digital colour space converter (DCSC) 4-30
SAA7195A Video and Memory Controller (VMC) 4-9, 31
SAA7196  Digital video decoder and scaler (DESC-Pro) 4-2, 7, 9
APPENDIX 3
INDEX OF TYPE NUMBERS

A-9
Multimedia PC
A
APPENDICES
TYPE NUMBER DESCRIPTION PAGE
SAA7199B  CCIR and square pixel digital encoder with genlock 4-12, 17
SAA7348 ACE (All Compact disc Engine) 7-4
SAA7360  Bitstream ADC 8-7
SAA7366  Bitstream ADC 8-7, 8
SAA7370(B)GP  10×single-chip digital servo processor and compact disc decoder 7-5
SAA7385 High performance CD-ROM controller 7-6, 7
SAA7388  Error corrector and host interface 7-6
SAA7390  High speed CD-recordable block decoder/encoder 7-6, 8
SAA8110 Camera DSP 9-7
SZA1010 Triple digital servo driver 7-13
TDA1300T Photodetector amplifiers and laser supply 7-9
TDA1303T  Digital Servo Driver (DSD1) 7-12
TDA1305T(AT)  Bitstream/CC filter DAC 8-9
TDA1306T Noise shaping filter DAC 8-10
TDA1308T Class AB stereo headphone driver 6-4, 8-16
TDA1309H  Low power, low voltage stereo CODEC 8-2
TDA1311A(T) Low power stereo DACs 8-11
TDA1373  General digital I/O input with DSP (GDIO DSP) 8-6
TDA1386T  Noise shaping filter DAC 8-10
TDA1387T  Low power stereo DACs 8-11
TDA1388T(Z)  Single-chip audio processor 8-5
TDA1396  16-bit stereo CODEC with FM synthesis 8-3
TDA1517P  Stereo radio power amplifier 8-13
TDA1548T(Z)  Single-chip audio processor 8-4
TDA4655  Generic multistandard analog decoder 4-34
TDA4665  Baseband delay line 4-35
TDA4670 Picture signal improvement processor 4-38
TDA4686(WP) Analog video processor 4-39
TDA4820T  Sync. Separator IC for monitors 4-32
TDA7072A(T) BTL motor drive circuits 7-14
TDA7073A(T)  BTL motor drive circuits 7-14
TDA8501  PAL/NTSC analog encoder 4-36
TDA8505 SECAM analog encoder 4-37
TDA8540(T) 4 ×4 video switch matrix 4-33
TDA8702  8-bit video DAC 4-24
TDA8706A 6-bit ADC with multiplexer and clamp 9-2
TDA8707  Triple RGB 6-bit ADC interface 4-20
TDA8708A/B  Video analog input interface 4-20, 21
TDA8709A  Video analog input interface 4-20, 22
TDA8712  8-bit video DAC 4-24
TDA8758  Low power A/D interface 4-20, 23
TDA8766  10-bit, high speed 3 V ADC 9-3
TDA8767  12-bit high speed ADC 9-4
TDA8771A  Triple 8-bit video DAC 4-24, 25
TDA8772(A)H(3/8)  Triple 8-bit video DAC 4-24, 26
TDA8775G Triple 10-bit video DAC 4-24, 27
TDA8786(A)  10-bit A/D interface for camera CCDs 9-5
APPENDIX 3

A-10 Multimedia PC

TYPE NUMBER DESCRIPTION PAGE

TDA8790 8-bit 40 Msps 2.7 - 5.5 V universal ADC 9-6

TDA9850 I2C-bus controlled BTSC stereo/SAP decoder 5-2, 3

TDA9852 I2C-bus controlled BTSC stereo/SAP decoder and audio processor 5-2, 4

TDA9855 I2C-bus controlled BTSC stereo/SAP decoder and audio processor 5-2, 4

TEA5582 PLL BTSC stereo decoder 5-2, 5

TEA5757H/5759H Self-tuned radio 6-3

TEA6320/1/2/3 Sound processors 8-14

TEA6360 5-band graphic equalizer 8-15

TZA1015 Data amplifier and laser supply 7-10

UAA3201T UHF/VHF remote control receiver 9-8

APPENDICES APPENDIX 3