MX29F400CBMC-12 - Macronix International Co., Ltd.

P/N:PM1200 REV. 0.02 , APR. 15, 2005

MX29F400CT/CB

4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE

5V ONLY BOOT SECTOR FLASH MEMORY

- Data# Polling & Toggle bit for detection of program

and erase cycle completion.

• Ready/Busy pin (RY/BY#)

- Provides a hardware method of detecting program or

erase cycle completion.

- Sector protect/unprotect for 5V only system or 5V/

12V system.

• Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

• 20 years data retention

FEATURES

• 524,288 x 8/262,144 x 16 switchable

• Single power supply operation

- 5.0V only operation for read, erase and program

operation

• Fast access time: 70/90/120ns

• Compatible with MX29F400T/B device

• Low power consumption

- 40mA maximum active current(5MHz)

- 1uA typical standby current

• Command register architecture

- Byte/word Programming (9us/11us typical)

- Sector Erase (Sector structure 16K-Bytex1, 8K-

Bytex2, 32K-Bytex1, and 64K-Byte x7)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with

Erase Suspend capability.

- Automatically program and verify data at specified

address

• Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, another sector that is not being

erased, then resumes the erase.

• Status Reply

GENERAL DESCRIPTION

The MX29F400CT/CB is a 4-mega bit Flash memory

organized as 512K bytes of 8 bits or 256K words of 16

bits. MXIC's Flash memories off er the most cost-eff ec-

tive and reliab le read/write non-v olatile random access

memory. The MX29F400CT/CB is packaged in 44-pin

SOP, 48-pin TSOP. It is designed to be reprogrammed

and erased in system or in standard EPROM pro gr am-

mers.

The standard MX29F400CT/CB offers access time as

fast as 70ns, allowing operatio n of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion, the MX29F400CT/CB has separate chip enable

(CE#) and o utput enable (OE#) co ntrols.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and pro gramming. The

MX29F400CT/CB uses a co mmand register to manage

this functio nality . The command register allows fo r 100%

TTL level control inputs and fixed power supply levels

during erase and pro gramming, while maintaining maxi-

mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and pro gram cycles. The MXIC

cell is designed to optimize the erase and programming

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and program operations produces reliable cy-

cling. The MX29F400CT/CB uses a 5.0V±10% VCC sup-

ply to perform the High Reliability Erase and auto Pro-

gram/Erase algorithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

ADVANCED INFORMATION

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

PIN CONFIGURATIONS

44 SOP(500 mil)

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A17 Address Input

Q0~Q14 Data Input/Output

Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)

CE# Chip Enable Input

WE# Write Enable Input

BYTE# Wo rd/Byte Selection input

RESET# Hardware Reset Pin/Secto r Protect

Unlock

OE# Output Enable Input

R Y/BY# Ready/Busy Output

VCC P ower Supply Pin (+5V)

GND Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

RY/BY#

A17

CE#

GND

OE#

Q10

Q11

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

GND

Q15/A-1

Q14

Q13

Q12

VCC

MX29F400CT/CB

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

BYTE#

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

OE#

GND

CE#

MX29F400CT/CB

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

Sector Size Address Range (in hexadecimal)

(Kbytes/ (x8) (x16)

Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA0 0 0 0 X X X 64/32 00000h-0FFFFh 00000h-07FFFh

SA1 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh

SA2 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh

SA3 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh

SA4 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh

SA5 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh

SA6 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh

SA7 1 1 1 0 X X 32/16 70000h-77FFFh 38000h-3BFFFh

SA81111008/4 78000h-79FFFh 3C000h-3CFFFh

SA91111018/4 7A000h-7BFFFh 3D000h-3DFFFh

SA10 1 1111X16/8 7C000h-7FFFFh 3E000h-3FFFFh

Sector Size Address Range (in hexadecimal)

(Kbytes/ (x8) (x16)

Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range

SA000000X16/8 00000h-03FFFh 00000h-01FFFh

SA10000108/4 04000h-05FFFh 02000h-02FFFh

SA20000118/4 06000h-07FFFh 03000h-03FFFh

SA3 0 0 0 1 X X 32/16 08000h-0FFFFh 04000h-07FFFh

SA4 0 0 1 X X X 64/32 10000h-1FFFFh 08000h-0FFFFh

SA5 0 1 0 X X X 64/32 20000h-2FFFFh 10000h-17FFFh

SA6 0 1 1 X X X 64/32 30000h-3FFFFh 18000h-1FFFFh

SA7 1 0 0 X X X 64/32 40000h-4FFFFh 20000h-27FFFh

SA8 1 0 1 X X X 64/32 50000h-5FFFFh 28000h-2FFFFh

SA9 1 1 0 X X X 64/32 60000h-6FFFFh 30000h-37FFFh

SA10 1 1 1 X X X 64/32 70000h-7FFFFh 38000h-3FFFFh

Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode.

SECTOR STRUCTURE

MX29F400CT TOP BOOT SECTOR ADDRESS TABLE

MX29F400CB BOTTOM BOOT SECTOR ADDRESS TABLE

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER

Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q15/A-1

A0-A17

CE#

OE#

WE#

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

AUTOMATIC PROGRAMMING

The MX29F400CT/CB is byte programmable using the

A utomatic Pro gramming algo rithm. The Auto matic Pro-

gr amming algorithm makes the e xternal system do no t

need to have time out sequence nor to verify the data

programmed. The typical chip programming time at ro om

temperature of the MX29F400CT/CB is less than 4.5

seconds.

A UTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at ro o m temperature is acco mplished in

less than 4 seco nd. The Auto matic Erase algo rithm au-

tomatically programs the entire array prior to electr ical

erase. The timing and verification o f electrical erase are

co ntro lled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F400CT/CB is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase mo des allow

secto rs of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically programs

the specified secto r(s) prior to electrical erase. The tim-

ing and v erification of electrical erase are co ntrolled in-

ternally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's A utomatic Programming algorithm requires the

user to o nly write pro gram set-up commands (including 2

unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the pro-

gram v erificatio n, and co unts the number o f sequences.

A status bit similar to Data# P o lling and a status bit to g-

gling between co nsecutive read cycles, pro vide feedback

to the user as to the status of the programming opera-

tion.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algo rithm requires the user to

write commands to the command register using stan-

dard micro processor write timings. The device will auto-

matically pre-progr am and verify the entire arra y. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides f eedback to the user as to the

status o f the pro gramming operation.

machine which co ntrols the erase and pro gramming cir-

cuitry. During write cycles, the co mmand register inter-

nally latches address and data needed for the program-

ming and erase o perations. During a system write cycle,

addresses are latched o n the falling edge, and data are

latched on the rising edge of WE# or CE#, whichever

happens first .

MXIC's Flash technology combines years of EPROM

e xperience to pro duce the highest le vels o f quality, reli-

ability, and cost effectiveness. The MX29F400CT/CB

electrically erases all bits simultaneo usly using F owler-

No rdheim tunneling. The bytes are pro grammed by us-

ing the EPROM pro gramming mechanism of hot electron

injection.

During a program cycle, the state-machine will control

the progr am sequences and command register will no t

respond to any command set. Dur ing a Sector Erase

cycle, the command register will o nly respo nd to Erase

Suspend co mmand. After Erase Suspend is completed,

the de vice stays in read mode. After the state machine

has co mpleted its task, it will allo w the co mmand regis-

ter to respond to its full command set.

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXXH F0H

Read 1 RA RD

Read Silicon Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

ID Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI

Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H

Verify x02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H

x04H 01H

Program Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD

Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H

Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H

Sector Erase Suspend 1 XXXH B0H

Sector Erase Resume 1 XXXH 3 0H

Unlock for sector 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H

protect/unprotect

TABLE 1. SOFTWARE COMMAND DEFINITIONS

Note:

1. ADI = Address of Device identifier ; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code, A2~A17=do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH (x8) and 2223H/22ABH (x16) for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memor y location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A17 in either state.

4. For Sector Protect Verify o peration:If read out data is 01H, it means the sector has been pro tected. If read o ut data is 00H, it

means the sector is still not being protected.

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

Pins CE# OE # WE# A0 A1 A6 A9 Q 0 ~ Q1 5

Mode

Read Silicon ID L L H L L X VID(2) C2H (Byte mode)

Manufacture Code(1) 00C2H (Word mode)

Read Silicon ID L L H H L X VID(2) 23H/ABH (Byte mode)

Device Code(1) 2223H/22ABH (Word mode)

Read L L H A0 A1 A6 A9 DOUT

Standby H XXXXXX HIGH Z

Output Disable L H H XXXX HIGH Z

Write L H L A0 A1 A6 A9 DIN(3)

Sector Protect with 12V L VID(2) L X X L VID(2) X

system(6)

Chip Unprotect with 12V L VID(2) L X X H VID(2) X

system(6)

Verify Sector Protect L L H X H X VID(2) Code(5)

with 12V system

Sector Protect without 12V L H L X X L H X

system (6)

Chip Unprotect without 12V L H L X X H H X

system (6)

Verify Sector Protect/Unprotect L L H X H X H Code(5)

without 12V system (7)

Reset X XXXXXX HIGH Z

TABLE 2. MX29F400CT/CB BUS OPERATION

NOTES:

1. Manufacturer and device codes may also be accessed via a command register wr ite sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a wr ite operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

A17~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system"

command.

Note that the Erase Suspend (B0H) and Erase Resume

(30H) commands are valid only while the Sector Erase

operation is in progress. Either of the two reset com-

mand sequences will reset the device(when applicable).

COMMAND DEFINITIONS

Device operations are selected by writing specific address

and data sequences into the command register. Writing

incorrect address and data values or writing them in the

improper sequence will reset the device to the read mode.

Table 1 defines the valid register command sequences.

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READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. Howe ver , multiple xing high vo ltage o nto

address lines is not generally desired system design

practice.

The MX29F400CT/CB co ntains a Silicon-ID-Read opera-

tion to supplement traditional PROM programming meth-

odology. The operation is initiated by writing the read

silicon ID command sequence into the command regis-

ter. Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H/

00C2H. A read cycle with A1=VIL, A0=VIH returns the

device code of 23H/2223H fo r MX29F400CT , ABH/22ABH

fo r MX29F400CB.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacture code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H

Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H

Device code Word VIH VIL 22H 0 0 1 0 0 0 1 1 2223H

for MX29F400CT Byte VIH VIL X 0 0 1 0 0 0 1 1 23H

Device code Word VIH VIL 22H 1 0 1 0 1 0 1 1 22ABH

for MX29F400CB Byte VIH VIL X 1 0 1 0 1 0 1 1 ABH

Sector Protection X VIH X 0 0 0 0 0 0 0 1 01H (Protected)

Verification X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)

TABLE 3. EXPANDED SILICON ID CODE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlo c k" write cycles. These are f o llo wed by writing the

"set-up" command 80H. Two more "unlock" write cy-

cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory fo r an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array(no

erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating the erase operation

exceed internal timing limit.

The automatic erase begins on the rising edge of the

last WE# or CE#, whichever happens later , pulse in the

command sequence and terminates when the data on

Q7 is "1" and the data on Q6 stops toggling for two con-

secutive read cycles, at which time the device returns

to the Read mode.

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REV. 0.02, APR. 15, 2005

Status Q7 Q6 Q5 Q3 Q2 RY/BY#

Note1 Note2

Byte Program in Auto Program Algorithm Q7 # Toggle 0 N/A No 0

Toggle

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1

(Erase Suspended Sector) Toggle

In Progress Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)

Erase Suspend Program Q7# Toggle 0 N/A N/A 0

Byte Program in Auto Program Algorithm Q7 # Toggle 1 N/A No 0

Toggle

Exceeded

Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7# Toggle 1 N/A N/A 0

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two "un-

lo ck" write cycles. These are fo llowed by writing the set-

up command 80H. Two more "unlock" write cycles are

then followed by the sector erase command 30H. The

sector address is latched on the falling edge of WE# or

CE#, whichever happens later, while the command(data)

is latched on the rising edge o f WE# or CE#, whiche v er

happens first. Sector addresses selected are loaded

into internal register o n the sixth f alling edge of WE# o r

CE#, whichever happens later. Each successive secto r

load cycle started by the falling edge of WE# or CE#,

whichever happens later, must begin within 30us from

the rising edge of the preceding WE# or CE#, whichever

happens First, otherwise, the loading per iod ends and

internal auto sector erase cycle star ts. (Monitor Q3 to

determine if the secto r erase timer windo w is still o pen,

see section Q3, Sector Erase Timer.) Any command other

than Sector Erase(30H) or Erase Suspend(B0H) during

the time-out period resets the device to read mode.

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-

vice to be entirely pre-programmed prior to executing

the Automatic Set-up Sector Erase command and Auto-

matic Sector Erase command. Upon executing the Au-

tomatic Sector Erase command, the device will auto-

matically program and verify the sector(s) memory for

an all-zero data pattern. The system is not required to

provide any control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

Table 4. Write Operation Status

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for fur ther details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more infor mation.

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ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Secto r Erase o peratio n. When the Erase Suspend com-

mand is written during a sector erase operation, the de-

vice requires a maximum of 20us to suspend the erase

operations. However, When the Erase Suspend co mmand

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mo de. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

the Read Memor y Array, Erase Resume and program

commands.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

ERASE RESUME

This command will cause the co mmand register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Pro gram mode, A three-cycle co m-

mand sequence is required. There are two "unlock" write

cycles. These are fo llowed by writing the Auto matic Pro-

gram command A0H.

Once the Automatic Program command is initiated, the

next WE# or CE#, pulse causes a transition to an active

programming operation. Addresses are latched on the

falling edge, and data are internally latched on the

rising edge of the WE# o r CE#, whichever happens first,

pulse. The rising edge o f WE# or CE#, whichev er hap-

pens first, also begins the pro gramming o peration. The

system is no t required to pro vide further contro ls o r tim-

ings. The device will auto matically pro vide an adequate

internally generated pro gram pulse and verify margin.

If the pro gr am o peration was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating the pro gram o peratio n

exceed internal timing limit. The automatic pro gramming

operation is completed when the data read on Q6 stops

toggling for two consecutive read cycles and the data

on Q7 and Q6 are equivalent to data written to these two

bits, at which time the device returns to the Read mode(no

pro gram verify co mmand is required).

DATA# POLLING-Q7

The MX29F400CT/CB also f eatures Data# P o lling as a

method to indicate to the host system that the Auto-

matic Program or Erase algorithms are either in progress

or completed.

While the Automatic Programming algorithm is in opera-

tion, an attempt to read the device will produce the

complement data of the data last written to Q7. Upon

completion of the Automatic Program Algorithm an at-

tempt to read the device will produce the true data last

written to Q7. The Data# P o lling feature is valid after the

rising edge of the four th WE# or CE#, whichever hap-

pens first, pulse of the four write pulse sequences for

auto matic program.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1". The Data# Polling feature is valid after the

rising edge of the sixth WE# o r CE#, whichever happens

first pulse of six write pulse sequences for automatic

chip/secto r erase.

The Data# Polling feature is active during Automatic Pro-

gram/Erase algorithm or sector erase time-out. (see sec-

tio n Q3 Secto r Erase Timer)

RY/BY#:Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program algorithm

is in progress or complete. The RY/BY# status is valid

after the rising edge o f the final WE# o r CE#, whichever

happens first, pulse in the command sequence. Since

RY/BY# is an open-drain output, several RY/BY# pins

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REV. 0.02, APR. 15, 2005

can be tied together in parallel with a pull-up resistor to

Vcc.

If the o utput is low (Busy), the device is activ ely erasing

or programming. (This includes programming in the Erase

Suspend mo de.) If the o utput is high (Ready), the device

is ready to read array data (including during the Erase

Suspend mo de), o r is in the standby mode.

Table 4 shows the o utputs f o r R Y/BY#.

Q6:Toggle BIT I

To ggle Bit I o n Q6 indicates whether an A utomatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge o f the final WE# o r CE#, whichever

happens first, pulse in the co mmand sequence (prio r to

the program or erase operation), and during the sector

time-out.

During an Auto matic Program o r Erase algo rithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

co ntrol the read cycles. When the o peratio n is complete,

Q6 sto ps to ggling.

After an erase co mmand sequence is written, if all sec-

tors selected f or erasing are protected, Q6 to ggles and

returns to reading arra y data. If not all selected sectors

are pro tected, the Auto matic Erase algo rithm erases the

unpro tected secto rs, and igno res the selected secto rs

that are pro tected.

The system can use Q6 and Q2 to gether to determine

whether a sector is actively erasing or is erase sus-

pended. When the device is actively erasing (that is, the

A utomatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However, the system must also use Q2

to determine which sectors are erasing or erase-sus-

pended. Alternatively, the system can use Q7.

If a program address f alls within a protected sector , Q6

toggles for approximately 2 us after the program com-

mand sequence is written, then returns to reading array

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algorithm

is complete.

Table 4 shows the o utputs f o r To ggle Bit I o n Q6.

Q2:Toggle Bit II

The "To ggle Bit II" o n Q2, when used with Q6, indicates

whether a par ticular sector is actively erasing (that is,

the Auto matic Erase algorithm is in pro cess), or whether

that secto r is erase-suspended. Toggle Bit I is valid after

the rising edge o f the final WE# o r CE#, whiche ver hap-

pens first, pulse in the co mmand sequence .

Q2 to ggles when the system reads at addresses within

tho se sectors that have been selected fo r erasure. (The

system may use either OE# or CE# to control the read

cycles.) But Q2 cannot distinguish whether the sector

is activ ely erasing o r is erase-suspended. Q6, b y co m-

parison, indicates whether the device is actively eras-

ing, o r is in Erase Suspend, but canno t distinguish which

sectors are selected for erasure. Thus , bo th status bits

are required f o r secto rs and mo de info rmatio n. Refer to

Table 4 to co mpare o utputs f o r Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whene v er the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a to ggle bit is toggling. Typically , the

system would no te and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the to ggle bit is no t toggling, the device has co m-

pleted the pro gram o r erase o peratio n. The system can

read arra y data o n Q7-Q0 on the fo llowing read cycle.

How ever, if after the initial two read cycles , the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is , the system sho uld then

determine again whether the toggle bit is toggling, since

the to ggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully co mpleted the program o r erase o pera-

tio n. If it is still to ggling, the device did not co mplete the

operation successfully, and the system must wr ite the

reset co mmand to return to reading array data.

The remaining scenario is that system initially determines

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

that the to ggle bit is toggling and Q5 has no t go ne high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previo us paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it retur ns to determine the status of the

operation.

Exceeded Timing Limits

Q5 will indicate if the program o r erase time has exceeded

the specified limits (internal pulse co unt). Under these

co nditions Q5 will produce a "1". This time-out co nditio n

indicates that the program or erase cycle was not suc-

cessfully completed. Data# Polling and Toggle Bit are

the o nly operating functio ns of the device under this con-

dition.

If this time-out condition o ccurs during sector erase op-

eratio n, it specifies that a particular secto r is bad and it

may no t be reused. However , other sectors are still func-

tio nal and ma y be used f o r the pro g ram o r erase o per a-

tion. The device must be reset to use other sectors.

Write the Reset co mmand sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

If this time-out condition occurs during the chip erase

o peration, it specifies that the entire chip is bad o r co m-

binatio n o f sectors are bad.

If this time-o ut condition occurs during the byte pro gram-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

The time-o ut co ndition may also appear if a user tries to

program a non blank location without erasing. In this

case the de vice locks out and ne ver co mpletes the Au-

tomatic Algorithm operation . Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

f ailure co ndition since the de vice was incorrectly used.

DATA PROTECTION

The MX29F400CT/CB is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transitio n. During power up the device automatically re-

sets the state machine in the Read mode. In addition ,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorpo rates several features to prevent inadvertent write

cycles resulting from VCC power-up and power-down tran-

sition or system noise.

TEMPORARY SECTOR UNPROTECT

This feature allows tempo rary unpro tection of previously

pro tected secto r to change data in-system. The Tempo-

rary Sector Unprotect mode is activated by setting the

RESET# pin to VID(11.5V -12.5V). During this mode, for-

merly protected secto rs can be prog rammed or erased

as un-protected sector. Once VID is remove from the

RESET# pin, all the previously protected sectors are pro-

tected again.

Sector Erase Timer

After the co mpletio n of the initial sector erase co mmand

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-o ut is co mplete. Data# P o lling

and T o ggle Bit are valid after the initial secto r erase co m-

mand sequence.

If Data# P olling o r the To ggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is co mpleted as indicated b y Data# Polling or

To ggle Bit. If Q3 is low ("0"), the device will accept addi-

tio nal secto r er ase co mmands. To insure the co mmand

has been accepted, the system software should check

the status o f Q3 prio r to and f o llowing each subsequent

sector erase command. If Q3 were high o n the second

status check, the command may no t have been accepted.

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REV. 0.02, APR. 15, 2005

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND .

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

TEMPORARY SECTOR UNPROTECT OPERATION

Start

RESET# = VID (Note 1)

Perform Erase or Program Operation

RESET# = VIH

Temporary Sector Unprotect Completed(Note 2)

Operation Completed

2. All previously protected sectors are protected again.

Notes : 1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description Test Setup All Speed Options Unit

tVIDR VID Rise and F all Time (See No te) Min 5 00 ns

tRSP RESET# Setup Time for T emporary Sector Unprotect Min 4 us

Note:

Not 100% tested

TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM

RESET#

CE#

WE#

RY/BY#

tVIDR tVIDR

Program or Erase Command Sequence

12V

0 or 5V 0 or 5V

tRSP

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

RESET# TIMING WAVEFORM

AC CHARACTERISTICS

Parameter Std Description T est Setup All Speed Options Unit

tREAD Y1 RESET# PIN Low (During Auto matic Algorithms) MAX 2 0 us

to Read o r Write (See No te)

tREAD Y2 RESET# PIN Low (NOT During Auto matic MAX 500 ns

Algo rithms) to Read o r Write (See No te)

tRP1 RESET# Pulse Width (During Auto matic Algo rithms) MIN 1 0 us

tRP2 RESET# Pulse Width (NO T During Automatic Algo rithms) MIN 5 00 ns

tRH RESET# High Time Befo re Read(See Note) MIN 0 ns

tRB1 RY/BY# Reco very Time(to CE#, OE# go low) MIN 0 ns

tRB2 RY/BY# Reco very Time(to WE# go low) MIN 5 0 ns

Note:Not 100% tested

tRH

tRB1

tRB2

tReady1

tRP2

tRP1

tReady2

RY/BY#

CE#, OE#

RESET#

Reset Timing NOT during Automatic Algorithms

Reset Timing during Automatic Algorithms

RY/BY#

CE#, OE#

RESET#

WE#

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F400CT/CB features hardware secto r pro tec-

tion. This feature will disable both program and erase

operations for these sectors protected. To activate this

mode, the programming equipment must force VID on

address pin A9 and control pin OE#, (suggest VID = 12V)

A6 = VIL and CE# = VIL.(see Table 2) Programming o f

the protectio n circuitry begins o n the f alling edge of the

WE# pulse and is terminated on the rising edge. Please

refer to secto r pro tect algo rithm and wavefo rm.

To verify programming o f the pro tection circuitry , the pro-

gramming equipment must force VID on address pin A9

( with CE# and OE# at VIL and WE# at VIH). When

A1=1, it will produce a logical "1" code at device output

Q0 for a protected sector . Otherwise the device will pro-

duce 00H for the unprotected sector . In this mode, the

addresses, e xcept fo r A1, are do n't care. Address lo ca-

tions with A1 = VIL are reserved to read manufacturer

and device co des.(Read Silico n ID)

It is also possible to determine if the sector is protected

in the system by writing a Read Silicon ID command.

P erfo rming a read o peratio n with A1=VIH, it will produce

a logical "1" at Q0 for the pro tected sector .

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F400CT/CB also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in the

code. It is recommended to protect all sectors before

activating chip unprotect mode.

To activate this mode, the programming equipment must

force VID on control pin OE# and address pin A9. The

CE# pins must be set at VIL. Pins A6 must be set to

VIH.(see Table 2) Refer to chip unprotect algorithm and

waveform for the chip unprotect algorithm. The

unprotection mechanism begins on the falling edge of the

WE# pulse and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs(Q0-Q7) for an unprotected sector. It

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

POWER-UP SEQUENCE

The MX29F400CT/CB powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature -40oC to 85oC (*)

Ambient T emperature with P ower -55oC to 125oC

Applied

Storage T emperature -65oC to 125oC

Applied Input Vo ltage -0.5V to 7.0V

Applied Output Vo ltage -0.5V to 7.0V

VCC to Gro und Po tential -0.5V to 7.0V

A9 & OE# -0.5V to 13.5V

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXI-

MUM RATINGS may cause permanent damage to the de-

vice. This is a stress rating only and functional operational

sections of this specification is not implied. Exposure to ab-

solute maximum rating conditions for extended period may

affect reliability.

NOTICE:

Specifications contained within the following tables are sub-

ject to change.

* The automotive grade is under development.

SECTOR PROTECTION WITHOUT 12V SYS-

TEM

The MX29F400CT/CB also feature a hardware sector

protection method in a system without 12V power supply.

The programming equipment do not need to supply 12

volts to protect sectors. The details are shown in sector

protect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F400CT/CB also feature a hardware chip

unprotection method in a system without 12V power

supply. The programming equipment do not need to

supply 12 volts to unprotect all sectors. The details are

shown in chip unprotect algorithm and waveform.

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MX29F400CT/CB

REV. 0.02, APR. 15, 2005

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V

CIN2 Control Pin Capacitance 12 pF VIN = 0V

COUT Output Capacitance 12 pF VOUT = 0V

DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ±±

±±

±10%

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

IL I Input Leakage Current 1 uA VIN = GND to VCC

ILO Output Leakage Current 10 uA VOUT = GND to VCC

ISB1 Standby VCC current 1 mA CE# = VIH

ISB2 1(Note3) 5(Note3) uA CE# = VCC ± 0.3V

ICC1 Operating VCC current 40 mA IOUT = 0mA, f=5MHz

ICC2 50 mA IOUT= 0mA, f=10MHz

VIL Input Low Voltage -0.3(NOTE 1) 0.8 V

VIH Input High Voltage(NOTE 2) 0.7xVCC VCC + 0.3 V

VOL Output Low Voltage 0.45 V IOL = 2.1mA, VCC= VCC MIN

VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA, VCC= VCC MIN

VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA,VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. ISB2 20uA max. for Automotive grade. Which is under development.

READ OPERATION

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ± ±

± ±

± 10%

Notes:

1 . tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

2. Auto motive grade is under dev elopment.

TEST CONDITIONS:

•Input pulse levels: 0.45V/0.7xVCC

•Input rise and fall times is equal to or less than 10ns

•Output load: 1 TTL gate + 100pF (Including scope and

jig)

•Reference levels for measuring timing: 0.8V, 2.0V

29F400C-70 29F400C-90 29F400C-12

SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT Conditions

tACC Address to Output Delay 7 0 9 0 1 2 0 ns CE#=OE#=VIL

tCE CE# to Output Delay 7 0 90 12 0 ns OE#=VIL

tOE OE# to Output Delay 3 0 3 5 5 0 ns CE#=VIL

tD F OE# High to Output Flo at 0 2 0 0 2 0 0 3 0 ns CE#=VIL

(Note 1)

tO H Address to Output ho ld 0 0 0 ns CE#=OE#=VIL

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

READ TIMING WAVEFORMS

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

Notes:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum v alue , pro gr amming o peration canno t be guaranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

5. The Automo tive grade is under development.

DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ±±

±±

± 10%

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ICC1 (Read) Operating VCC Current 40 mA IOUT=0mA, f=5MHz

ICC2 50 mA IOUT=0mA, f=10MHz

ICC3 (Program) 50 mA In Programming

ICC4 (Erase) 50 mA In Erase

ICCES VCC Erase Suspend Current 2 mA CE#=VIH, Erase Suspended

Addresses

CE#

OE#

tACC

WE#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z HIGH Z

D ATA V alid

tOE tDF

tCE

Outputs

tOH

ADD V alid

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

AC CHARACTERISTICS TA = -40 oC to 85oC, VCC = 5V ±±

±±

± 10%

29F400C-70 29F400C-90 29F400C-12

Symbol PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. Unit

tOES OE# setup time 0 0 0 ns

tCWC Command programming cycle 70 90 120 ns

tCEP WE# programming pulse width 35 45 45 ns

tCEPH1 WE# programming pulse width High 20 20 20 ns

tCEPH2 WE# programming pulse width High 20 20 20 ns

tAS Address setup time 0 0 0 ns

tAH Address hold time 4 5 4 5 5 0 ns

tDS Data setup time 3 0 4 5 5 0 ns

tDH Data hold time 0 0 0 ns

tCESC CE# setup time before command write 0 0 0 ns

tDF Output disable time (Note 1) 2 0 2 0 3 0 ns

tAETC Erase time in auto chip erase 4(typ.) 32 4(typ.) 32 4(typ.) 32 s

tAETB Erase time in auto sector erase 0.7(typ.) 15 0.7(typ.) 15 0.7(typ.) 15 s

tAVT Programming time in auto verify 9/11 300/360 9/11 300/360 9/11 300/360 us

(byte/ word program time) (typ.) (typ.) (typ.)

tBAL Sector address load time 5 0 5 0 5 0 us

tCH CE# Hold Time 0 0 0 ns

tCS CE# setup to WE# going low 0 0 0 ns

tVLHT Voltage Transition Time 4 4 4 us

tOESP OE# Setup Time to WE# Active 4 4 4 us

tWPP1 Write pulse width for sector protect 10 1 0 1 0 us

tWPP2 Write pulse width for sector unprotect 1 2 1 2 1 2 ms

Notes:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. The Auto mo tive grade is under de velo pment.

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS

COMMAND WRITE TIMING WAVEFORM

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 1.2K ohm

1.6K ohm +5V

CL=100pF Including jig capacitance,

2.0V 2.0V

0.8V

TEST POINTS

0.7xVCC

0.45V

AC TESTING: Inputs are driven at 0.7xVCC for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall time are < 20ns.

OUTPUT

INPUT

Addresses

CE#

OE#

WE#

DIN

tDS

tAH

Data

tDH

tCS tCH

tCWC

tCEPH1

tCEP

tOES

tAS

VCC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD V alid

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)

AUTOMATIC PROGRAMMING TIMING WAVEFORM

tCWC

tAS

tCEP

tDS tDH tDF

Vcc 5V

CE#

OE#

Q0,Q1,Q2

Q4(Note 1)

WE#

A11~A17

tCEPH1

tAH

ADD V alid

tCESC

Command In

ADD V alid

A0~A10

Command InCommand In Data In DATA

Command In Command InCommand In Data In DATADATA#

tAVT

tOE

Data# Polling

2AAH

555H 555H

(Q0~Q7)

Command #55H Command #A0H

Note :

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

Command #AAH

One byte data is programmed. Verify in fast algorithm

and additional programming b y external control are not

required because these operations are executed auto-

matically by internal control circuit. Programming co mple-

tio n can be verified by Data# Polling and toggle bit check-

ing after automatic verification star ts. Device outputs

DA TA# during programming and DAT A# after programming

o n Q7.(Q6 is f o r to ggle bit; see toggle bit, Data# P o lling,

timing waveform)

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Verify Word Ok

YES

Q5 = 1

Reset

Auto Program Completed

Auto Program Exceed

Timing Limit

Invalid

Command

YES

NO .

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

All data in chip are erased. External erase verificatio n is

not required because data is erased automatically by

internal control circuit. Erasure completion can be veri-

fied by Data# P o lling and to ggle bit checking after auto-

AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

matic erase starts. Device outputs 0 during erasure

and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle

bit, Data# P olling, timing wavefo rm)

tCWC

tAS

tCEP

tDS tDH

Vcc 5V

CE#

OE#

Q0,Q1,

Q4(Note 1)

WE#

A11~A17

tCEPH1

tAH

Command In

A0~A10

Command InCommand In

Command In Command InCommand In

tAETC

Data# Polling

2AAH

555H 555H

Command #AAH Command #55H Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H 2AAH 555H

Command In

Command #AAH

Command In

Command #55H

Command In

Command #10H

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REV. 0.02, APR. 15, 2005

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Reset

Auto Chip Erase Exceed

Timing Limit

DATA# Polling

Q7 = 1 YES

Q5 = 1

Auto Chip Erase Completed

YES

Invalid

Command

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)

Secto r data indicated by A12 to A17 are erased. Exter-

nal erase verify is not required because data are erased

automatically by internal control circuit. Erasure comple-

tion can be verified by Data# Po lling and toggle bit check-

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

ing after automatic erase starts. De vice outputs 0 dur-

ing erasure and 1 after erasure on Q7.(Q6 is for toggle

bit; see to ggle bit, Data# P o lling, timing wa vef o rm)

tAH

Sector

Address0

555H 2AAH 2AAH

555H 555H

Sector

Address1 Sector

Addressn

VCC 5V

CE#

OE#

Q0,Q1,

Q4(Note 1)

WE#

A12~A17

A0~A10

Command

In Command

Command

In Command

Command

In Command

Command

In Command

Command

In Command

Command

Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH

(Q0~Q7)

Command

tDH

tDS

tCEP

tCWC

tAETB

tBAL

Data# Polling

tCEPH1

tAS

Note:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Toggle Bit Checking

Q6 not Toggled

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Reset

Auto Block Erase Exceed

Timing Limit

Data# Polling

Q7 = 1

Q5 = 1

Auto Block Erase Completed

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

YES

Last Block

to Erase

Time-out Bit

Checking Q3=1 ?

Toggle Bit Checking

Q6 Toggled ? Invalid Command

YES

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

YES

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO

YES

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

tOE

Data

OE#

WE#

12V

CE#

tOESP

tWPP 1

tVLHT

Verify

01H F0H

A17-A12 Sector Address

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

tOE

Data

OE#

WE#

12V

CE#

tOESP

tWPP 2

tVLHT

Verify

00H

F0H

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A17,A16,A15,A14,A13,A12)

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

OE#=VID,A9=VID,CE#=VIL

A6=VIL

Activate WE# Pulse

Time Out 10us

Set WE#=VIH, CE#=OE#=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=32?

Yes

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE#=A9=VID

CE#=VIL,A6=1

Activate WE# Pulse

Time Out 12ms

Set OE#=CE#=VIL

A9=VID,A1=1

Set Up First Sector Addr

All sectors have

been verified?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=1000?

Increment

PLSCNT

Read Data from Device

Yes

Increment

Sector Addr

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

OE#

WE#

CE#

* See the following Note!

Verify

01H

A18-A16 Sector Address

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection

for a system without 12V provided.

Note2: Except F0H

Toggle bit polling

Don't care

(Note 2)

tCEP

F0H

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

tOE

Data

WE#

CE#

Verify

00H

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection

for a system without 12V provided.

OE#

tCEP

Toggle bit polling

Don't care

(Note 2)

* See the following Note!

F0H

Note2: Except F0H

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Set Up Sector Addr

(A17,A16,A15,A14,A13,A12)

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

OE#=VIH,A9=VIH

CE#=VIL,A6=VIL

Activate WE# Pulse to start

Data don't care

Set CE#=OE#=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

Protect Another

Sector?

Write Reset Command

Device Failed

PLSCNT=32?

Yes

Increment PLSCNT

Write "unlock for sector protect/unprotect"

Command(Table1)

Toggle bit checking

Q6 not Toggled No

Yes

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE#=A9=VIH

CE#=VIL,A6=1

Activate WE# Pulse to start

Data don't care

Set OE#=CE#=VIL

A9=VIH,A1=1

Set Up First Sector Addr

All sectors have

been verified?

Write Reset Command

Device Failed

PLSCNT=1000?

Increment

PLSCNT

Read Data from Device

Yes

Increment

Sector Addr

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

Write "unlock for sector protect/unprotect"

Command (Table 1)

Toggle bit checking

Q6 not Toggled

Yes

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

ID CODE READ TIMING WAVEFORM

tACC

tCE

tACC

tOE

tOH tOH

tDF

DATA OUT

C2H/00C2H 23H/ABH (Byte)

2223H/22ABH (Word)

VID

VIH

VIL

ADD

A1-A8

A10-A17

CE#

OE#

WE#

ADD

DATA OUT

DATA

Q0-Q15

VCC 5V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V

Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V

Current -100mA +100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE(1)

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C,5V.

3.Maximum values measured at 25°C,4.5V.

PARAMETER MIN. UNIT

Data Retention Time 2 0 Years

DATA RETENTION

LIMITS

PARAMETER MIN. TYP.(2) MAX.(3) UNITS

Sector Erase Time 0.7 1 5 sec

Chip Erase Time 4 32 sec

Byte Programming Time 9 3 00 us

Word Programming Time 11 360 us

Chip Programming Time Byte Mode 4.5 13.5 sec

Word Mode 3 9 sec

Erase/Program Cycles 100,000 Cycles

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

ORDERING INFORMATION

P ART NO. Access Time Operating Current Standby Current T emperature PACKAGE Remark

(ns) MAX.(mA) MAX.(uA) Range

MX29F400CTMC-70 70 40 5 0oC~70oC 44 Pin SOP

MX29F400CTMC-90 90 40 5 0oC~70oC 44 Pin SOP

MX29F400CTMC-12 120 40 5 0oC~70oC 44 Pin SOP

MX29F400CTTC-70 70 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400CTTC-90 90 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400CTTC-12 120 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400CBMC-70 70 40 5 0oC~70oC 44 Pin SOP

MX29F400CBMC-90 90 40 5 0oC~70oC 44 Pin SOP

MX29F400CBMC-12 120 40 5 0oC~70oC 44 Pin SOP

MX29F400CBTC-70 70 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400CBTC-90 90 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400CBTC-12 120 40 5 0oC~70oC 48 Pin TSOP

(Normal T ype)

MX29F400CTMI-70 70 40 5 -40oC~85oC 44 Pin SOP

MX29F400CTMI-90 90 40 5 -40oC~85oC 44 Pin SOP

MX29F400CTMI-12 120 40 5 -40oC~85oC 44 Pin SOP

MX29F400CTTI-70 70 40 5 -40oC~85oC 48 Pin TSOP

(Normal T ype)

MX29F400CTTI-90 90 40 5 -40oC~85oC 48 Pin TSOP

(Normal T ype)

MX29F400CTTI-12 120 40 5 -40oC~85oC 48 Pin TSOP

(Normal T ype)

MX29F400CBMI-70 70 40 5 -40oC~85oC 44 Pin SOP

MX29F400CBMI-90 90 40 5 -40oC~85oC 44 Pin SOP

MX29F400CBMI-12 120 40 5 -40oC~85oC 44 Pin SOP

MX29F400CBTI-70 70 40 5 -40oC~85oC 48 Pin TSOP

(Normal T ype)

MX29F400CBTI-90 90 40 5 -40oC~85oC 48 Pin TSOP

(Normal T ype)

MX29F400CBTI-12 120 40 5 -40oC~85oC 48 Pin TSOP

(Normal T ype)

Note: The A utomo tive grade is under develo pment.

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

P ART NO. Access Time Operating Current Standby Current T emperature PACKAGE Remark

(ns) MAX.(mA) MAX.(uA) Range

MX29F400CTMC-70G 70 40 5 0oC~70oC 44 Pin SOP PB-free

MX29F400CTMC-90G 90 40 5 0oC~70oC 44 Pin SOP PB-free

MX29F400CTMC-12G 120 40 5 0oC~70oC 44 Pin SOP PB-free

MX29F400CTTC-70G 70 40 5 0oC~70oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CTTC-90G 90 40 5 0oC~70oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CTTC-12G 120 40 5 0oC~70oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CBMC-70G 70 40 5 0oC~70oC 44 Pin SOP PB-free

MX29F400CBMC-90G 90 40 5 0oC~70oC 44 Pin SOP PB-free

MX29F400CBMC-12G 120 40 5 0oC~70oC 44 Pin SOP PB-free

MX29F400CBTC-70G 70 40 5 0oC~70oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CBTC-90G 90 40 5 0oC~70oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CBTC-12G 120 40 5 0oC~70oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CTMI-70G 70 40 5 -40oC~85oC 44 Pin SOP PB-free

MX29F400CTMI-90G 90 40 5 -40oC~85oC 44 Pin SOP PB-free

MX29F400CTMI-12G 120 40 5 -40oC~85oC 44 Pin SOP PB-free

MX29F400CTTI-70G 70 40 5 -40oC~85oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CTTI-90G 90 40 5 -40oC~85oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CTTI-12G 120 40 5 -40oC~85oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CBMI-70G 70 40 5 -40oC~85oC 44 Pin SOP PB-free

MX29F400CBMI-90G 90 40 5 -40oC~85oC 44 Pin SOP PB-free

MX29F400CBMI-12G 120 40 5 -40oC~85oC 44 Pin SOP PB-free

MX29F400CBTI-70G 70 40 5 -40oC~85oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CBTI-90G 90 40 5 -40oC~85oC 48 Pin TSOP PB-free

(Normal T ype)

MX29F400CBTI-12G 120 40 5 -40oC~85oC 48 Pin TSOP PB-free

(Normal T ype)

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

PART NAME DESCRIPTION

MX 29 F 70C T T C G

OPTION:

G: Lead-free package

SPEED:

70:70ns

90: 90ns

12: 120ns

TEMPERATURE RANGE:

C: Commercial (0˚C to 70˚C)

I: Industrial (-40˚C to 85˚C)

PACKAGE:

M:SOP

T: TSOP

BOOT BLOCK TYPE:

T: Top Boot

B: Bottom Boot

REVISION:

DENSITY & MODE:

400: 4M, x8/x16 Boot Sector

TYPE:

F: 5V

DEVICE:

29: Flash

400

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

PACKAGE INFORMATION

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

P/N:PM1200

MX29F400CT/CB

REV. 0.02, APR. 15, 2005

REVISION HISTORY

Revision No. Description Page Date

0.01 1. Modified Ambient Operating Temperature P17 MAR/18/2005

0.02 1. Added P art Name Description P42 APR/15/2005

MX29F400CT/CB

MACRONIX INTERNATIONAL CO., LTD .

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.