ees AT 2811256 Features Fast Read Access Time - 70 ns Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum 1 to 64-Byte Page Write Operation Low Power Dissipation 80 mA Active Current 3 mA Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 10 or 10 Cycles Data Retention: 10 Years Single 5V + 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Full Military, Commercial, and Industrial Temperature Ranges Description The AT28HC256 is a high-performance Electrically Erasable and Programmable R ead Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA. : . : continued, Pin Configurations ( ) Pin Name Function TSOP AO-A14 Addresses Top View cE Chip Enable we p an OF >! 28 7 AY og OE Output Enable aa FT 8 6 35 b 7 Vo6 , WE Al3 6 5 24 23 YOs vos WE Write Enable ave Dy 22 F403 Np OO - VO7 Data Inputs/Outputs a7 4 40 19 vo NC No Connect AS 12 WE YOO no AS 13 16 Al pc Don't Connect aa 14 ce CERDIP, PDIP, PGA FLATPACK LCC, PLCC Top View Top View Top View AT A14VCC A13 4/3 4 | a7 | 26 aac as | a7 | a4! WE | ats ai2t/2 A\2 DG WE 5 | 2 | 28 24 | 25 a7 | 3 AS | A12| VCC: Ag | AB AB | 4 7 | 6 22 | 23 le AB | A4 | OE ant a3 17 9 | 8 20 21 A2'| 8 AL | AQ TE | A10 At | 9 pee ELAN 14: 10) 14] 16 | 19 Ao | O0 | AO | GND) VO4 | 107 | oo 12143] 15 | 17 | 18 toe 14151617181920 vO1 | YO2| VO3] 1/05 | VOE GND VO's 12 DC345 GND Note: PLCC package pins 1 and 17 are DON'T CONNECT. AIMmEt 256 (32K x 8) High Speed CMOS EPROM 0007F 2-279AIMEL Description (Continued) The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external compo- nents. The device contains a 64-byte page register to al- low writing of up to 64-bytes simultaneously. During a write cycle, the address and 1 to 64-bytes of data are in- ternally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of /O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Block Diagram Atmel's 28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inad- vertent writes. The device also includes an extra 64-bytes of E2PROM for device identification or tracking. Veco > DATA INPUTS/OUTPUTS GND > YOO - VO7- AAepaats OE --> > OF Tl OE, CE AND WE DATA LATCH LOGIC _| INPUT/OUTPUT cE -- > _ BUFFERS *} Y DECODER > Y-GATING ADDRESS | + ~ INPUTS | CELL MATRIX | X DECODER Long IDENTIFICATION Absolute Maximum Ratings Temperature Under Bias..........0.0... -55C to +125C Storage Temperature... -65C to +150C Ail input Voltages (including NC Pins) with Respect to Ground ..............0. -0.6V to +6.25V All Output Voltages with Respect to Ground............. -0.6V to Voc + 0.6V Voltage on OE and AQ with Respect to Ground ........... ee -0.6V to +13.5V 2-280 NOTICE: Stresses beyond those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT28HC256 ques A | St C256 Device Operation READ: The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The_outputs are put in the high impedance state when either CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cy- cle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of twc, a read operation will effectively be a poll- ing operation. PAGE WRITE: The page write operation of the AT28HC256 allows 1 to 64-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be writ- ten within 150 Ls (tac) of the previous byte. If the tatc limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition during the page write operation, A6 - A14 must be the same. The AO to AS inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur, DATA POLLING: The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on 1/07. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, succes- sive attempts to read data from the device will result in VO6 toggling between one and zero. Once the write has completed, 1/06 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. ANMEL DATA PROTECTION: If precautions are not taken, inad- vertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel has incorporated both hardware and software fea- tures that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28HC256 in the follow- ing ways: (a) Vcc sense - if Vcc is below 3.8V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8V the device will automatically time out 5 ms typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typi- cal) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28HC256. When enabled, the software data protection (SOP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after twc the entire AT28HC256 will be pro- tected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28HC256. This is done by pre- ceding the data to be written by the same 3-byte command sequence. Once set, SDP will remain active unless the disable com- mand sequence is issued. Power transitions do not dis- able SDP and SDP will protect the AT28HC256 during power-up and power-down conditions. All command se- quences must conform to the page write timing specifica- tions. It should also be noted that the data in the enable and disable command sequences is not written to the de- vice and the memory addresses used in the sequence may be written with data in either a byte or page write op- eration. After setting SDP, any attempt to write to the device with- out the three byte command sequence will start the inter- nal write timers. No data will be written to the device; how- ever, for the duration of twc, read operations will effec- tively be polling operations. (continued) 2-281AIMEL Device Operation (Continued) DEVICE IDENTIFICATION: An extra 64-bytes of E2PROM memory are available to the user for device identification. By raising A9 to 12V + 0.5V and using ad- dress locations 7FCOH to 7FFFH the additional bytes may be written to or read from in the same manner as the regu- lar memory array. DC and AC Operating Range OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Soft- ware Chip Erase application note for details. AT28HC256-70 AT28HC256-90 AT28HC256-12 : Com. ac - 70C oc - 70C 0c - 70C Soreareture (Case) 104: -40C - 85C -40C - 85C -40C - 85C Mil. -55C - 125C -55C - 125C Vcc Power Supply 5V + 10% 5V+10% 5V+10% Operating Modes Mode CE OE WE vO Read Vin Vit Vin Dout Write (2) Vib Vin VIL Din StandbyMWrite Inhibit Vie x x High Z Write Inhibit x x VIH Write inhibit x Vit X Output Disable xX Vin Xx High Z Chip Erase Vit Vy Vie High Z Notes: 1. X can be Vit or Vin. 3. Vu = 12.0V + 0.5V. 2. Refer to AC Programming Waveforms. DC Characteristics Symbol Parameter Condition Min Max Units qui Input Load Current Vin = OV to Vcc + 1V 10 pA lLo Output Leakage Current Vio = OV to Voc 10 pA Isat Vcc Standby Current TTL CE =2.0V to Voc + 1V ATEBHC256-90, 12 3__mA AT28HC256-70 60 mA Isp2 Vcc Standby Current CMOS CE =-3.0V to Vcc + 1V AT28HC256-90, -12 300 LA loc Vcc Active Current f = 5 MHz; louT =O mA 80 mA VIL Input Low Voltage 0.8 Vv Vin Input High Voltage 2.0 Vv VoL Output Low Voltage lo. = 6.0 mA 45 Vv VoH Output High Voltage loH = -4 mA 2.4 Vv 2-282 AT28HC256 equmms AT OSH C256 AC Read Characteristics AT28HC256-70 AT28C256-90 AT28HC256-12 Symbol Parameter Min Max Min Max Min Max Units tacc Address to Output Delay 70 90 120 ns tee) | CE to Output Delay 70 90 120 ns toe @) | OE to Output Delay 0 35 0 40 0 50 ns tor 84) | CE or OE to Output Float 0 35 0 40 0 50 ns Output Hold from OE, CE or toH fags whichever occurred 0 0 0 ns AC Read Waveforms 2: *: ADDRESS <[__ ADDRESS VALID CE tCE tOE -> OE tOH > i tacc > HIGH Z OUTPUT G OUTPUT VALID Notes: 1. CE may be delayed up to tacc - tce after the address 3. tpg is specified from OE or CE whichever occurs first transition without impact on tacc. (CL = 5 pF). 2. OE may be delayed up to tce - toe after the falling 4. This parameter is characterized and is not 100% tested. edge of CE without impact on tce or by tacc - toe after an address change without impact on tacc. Input Test Waveforms and Output Test Load Measurement Level 5.0V 3.0V AC AC 1.8K DRIVING MEASUREMENT PN LEVELS LEVEL 0.0V 100 pF tr, tk< 5ns 13K L , Pin Capacitance (f = 1 MHz, T = 25C) Typ Max Units Conditions Cin 4 6 pF Vin = OV CoutT 8 12 pF VouT = 0V Note: 1. This parameter is characterized and is not 100% tested. ANMEL 228AC Write Characteristics Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 ns taH Address Hold Time 50 ns tcs Chip Select Set-up Time 0 ns tcH Chip Select Hold Time 0 ns twe Write Pulse Width (WE or CE) 100 ns tos Data Set-up Time 50 ns tor, toEH Data, OE Hold Time 0 ns tov Time to Data Valid NR") Note: 1. NR =No Restriction AC Write Waveforms WE Controlled OE _ oe ; tOES tOEH woos > DTP tAS | .tAH LL ce O~~ KK. tCH ~ oo oN _ Mtes7 : WE ee K x<Y \ j~----tWPH L.--__tWP_ +] DATA IN CE Controlled OE : Le ene) tOES tOEH ADDRESS <C| eK - tas CH - _____. WE NX ' \ cs CE a Ky l- tWPH-~ Le nn et WP--- LL 1OV = +b tS -! |- -1DH DATA IN eee ; 2-284 AT28HC256ees AT 28h C256 Page Mode Write Characteristics Symbol! Parameter Min Typ Max Units two Write Cycle Time AT28HC256 8 10 ms AT28HC256F 2 3.0 ms tas Address Set-up Time 0 ns tAH Address Hold Time 50 ns tps Data Set-up Time 50 ns tbH Data Hold Time 0 ns twp Write Pulse Width 100 ns tBLc Byte Load Cycle Time 150 pS twPeH Write Pulse Width High 50 ns Page Mode Write Waveforms " wal an a a x p tDS DATA SXVALID DATA ; XK KX eK BYTE 0 BYTE 1 i BYTE 2 BYTE 3 BYTE 62 BYTE 63 |. twe _ Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2, OE must be high only when WE and CE are both low. Chip Erase Waveforms VIH~. ON VIL VH foo ~\ OE / \ VIH ~ ts tH \ VIH \ === WE rN ts = th = 5 usec (min.) VIL PON | tw = 10 msec (min.) <tW oe Vu = 12.0V + 0.5V | ANMEL zaneANE? Software Data ; Protection Enable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA AO TO ADDRESS 5555 WRITES ENABLED LOAD DATA XX TO ANY ADDRESS ) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE Notes: 1. Data Format: 1/07 - 1/00 (Hex); Address Format: A14 - AO (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64-bytes of data are loaded. Software Data Protection Disable Algorithm TO ADDRESS 5555 ~~ LOAD DATA AA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX To ANY ADDRESS LOAD LAST BYTE TO LAST ADDRESS Software Protected Write Cycle Waveforms ":) OE A EXIT DATA PROTECT STATE ) A NI NS NIN ION _ LWP wey 1 Ye we y ~ vy WE tAS Cy a oy | tAH [~~~] tDH _ a AO - A5 ; ean _ Xevte ADDRESS SS, ay D 2AAA 5555 be A6 - A14 X PAGE ADDRESS , iy. 10S a a wa) pm ae | pee ay 4 sy Af DATA X AA 55 AA Xx x x eee BYTE 0 BYTE 62 = BYTE 63 _ wo! Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software codehasbeenentered. = 2. OE must be high only when WE and CE are both low. 2-286 AT28HC256 suesDes AT OSC 256 Data Polling Characteristics Symbol Parameter Min Typ Max Units toH Data Hold Time 0 ns toeH OE Hold Time 0 ns toe OE to Output Delay ) ns twr Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms eS NS NS NS tOEH OE Nf ON 1DH + oP. (OE HIGHZ a7 tWR VO7 ~ AO-A14 An xX An X An An xX An) 7 Toggle Bit Characteristics Symbol Parameter Min Typ Max Units toH Data Hold Time 10 ns toEH OE Hold Time 10 ns toe OE to Output Delay 2) ns toEHP OE High Pulse 150 ns twR Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Toggle Bit Waveforms WE - wf fo cE Vf \ ay foo -- OE VS \ a vos - \ TO fre ~ tWR - Notes: 1. Toggling either GE or CE or both OF and CE will 3. Any address location may be used but the operate toggle bit. address should not vary. 2. Beginning and ending state of 1/06 will vary ANMEL 2207 )NORMALIZED SUPPLY CURRENT vs. Qen--mpZIxz0 2 o0o- NORMALIZED SUPPLY CURRENT vs. 08 OO- eaener--MBZ20Z 0.6 2-288 AINEL TEMPERATURE T t M 1 -65 -26 5 35 65 95 125 Temperature (C) 0.9 J 074 ADDRESS FREQUENCY Voc = 5V - Leen os feneme ig oe | ! | a 2 4 6 8 10 Frequency (MHz) NORMALIZED SUPPLY CURRENT vs. be SUPPLY VOLTAGE N : pose - 1 1 | d ' c C 064 : r : 4.50 4.75 .00 .25 .50 Supply Voltage (V) AT28HC256 neuenees A T2811 C256 Ordering Information") tacc Icc (mA) . ; Ordering Code Package Operation Range (ns) Active | Standby 70 80 60 AT28HC256(E,F)-70JC 32J Commercial AT28HC256(E,F)-70PC 28P6 (0C to 70C) 80 0.3 AT28HC256(E,F)-70JI 32J Industrial AT28HC256(E,F)-70Pt 28P6 (-40C to 85C) 90 80 0.3 AT28HC256(E,F)-90JC 32J Commercial AT28HC256(E,F)-90PC 28P6 (0C to 70C) 80 0.3 AT28HC256(E,F)-90ul 32J Industrial AT28HC256(E,F)-90P! 28P6 (-40C to 85C) 80 0.3 AT28HC256(E,F)-90DM/883 28D6 Military/883C AT28HC256(E,F)-90FM/883 28F Class B, Fully Compliant AT28HC256(E,F)-90LM/883 32L (-55C to 125C) AT28HC256(E,F)-90UM/883 28U 120 80 0.3 AT28HC256(E,F)-12JC 32J Commercial AT28HC256(E,F)-12PC 28P6 (0C to 70C) AT28HC256(E,F)-12SC 28S AT28HC256(E,F)-12TC 28T 80 0.3 AT28HC256(E,F)-121 32J Industrial AT28HC256(E,F)-12PI 28P6 (-40C to 85C} AT28HC256(E,F)-12S! 28S AT28HC256(E,F)-12T| 28T 80 0.3 AT28HC256(E,F)-12DM/883 28D6 Military/883C AT28HC256(E,F)-12FM/883 28F Class B, Fully Compliant AT28HC256(E,F)-12LM/883 32L (-55C to 125C) AT28HC256(E,F)-12UM/883 28U 90 80 0.3 5962-88634 03 UX 28U Military/883C 5962-88634 03 XX 28D6 Class B, Fully Compliant 5962-88634 03 YX 32L (-55C to 125C) 5962-88634 03 ZX 28F 80 0.3 5962-88634 04 UX 28U Military/883C 5962-88634 04 XX 28D6 Class B, Fully Compliant 5962-88634 04 YX 32L (-55C to 125C) 5962-88634 04 ZX 28F 120 80 0.3 5962-88634 01 UX 28U Military/883C 5962-88634 01 XX 28D6 Class B, Fully Compliant 5962-88634 01 YX 32L (-55C to 125C) 5962-88634 01 ZX 28F 80 0.3 5962-88634 02 UX 28U Military/883C 5962-88634 02 XX 28D6 Class B, Fully Compliant 5962-88634 02 YX 32L (-55C to 125C) 5962-88634 02 ZX 28F Note: 1. See Valid Part Number table below. 2-289 |AIMEL Ordering Information Note Previous data sheets included the low power suffixes L, LE and LF on the AT28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28HC256 70 JC, Jl, PC, Pl AT28HC256 90 JC, Jl, PC, Pl, TC, Ti, DM/883, FM/883, UM/883 AT28HC256E 90 JC, Jt, PC, Pl, TC, Tl, OM/883, FM/883, UM/883 AT28HC256F 90 Jc, Jl, PC, Pl, TC, T), OM/883, FM/883, UM/883 AT28HC256 12 JC, Jl, PC, Pl, TC, Tl, DM/883, FM/883, UM/883 AT28HC256E 12 JC, Jl, PC, Pi, TC, Tl, DM/883, FM/883, UM/883 AT28HC256F 12 JC, Jl, PC, Pi, TC, Tl, OM/883, FM/883, UM/883 Package Type 28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip} 28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28 Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Plastic Thin Smalt Outline Package (TSOP) 28U 28 Pin, Ceramic Pin Grid Array (PGA) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 2-290 AT28HC256 sues