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© 2000
MOS INTEGRATED CIRCUIT
MC-45D32CD641
Document No. M14899EJ1V0DS00 (1st edition)
Date Published June 2000 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
32 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-45D32CD641 is a 33,554,432 words by 64 bits DDR synchronous dynamic RAM module on which 16
pieces of 128M DDR SDRAM:
µ
PD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 64 bits organization
• Clock frequency
Part number /CAS l at ency Clock f requency Module type
(MAX.)
MC-45D32CD641KFA-C75 CL = 2.5 133 MHz DDR SDRAM
CL = 2 100 MHz Unbuffered DIMM
MC-45D32CD641KFA-C80 CL = 2.5 125 MHz Design spec i ficat i on
CL = 2 100 MHz Rev.0.9 compli ant
• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• 2.5 V ± 0.2 V Power supply for VDD
• 2.5 V ± 0.2 V Power supply for VDDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
Preliminary Data Sheet M14899EJ1V0DS00
2
MC-45D32CD641
Ordering Information
Part number Clock frequency
(MAX.) Package Mounted devices
MC-45D32CD641KFA-C75 133 MHz 184-pin Dual In-li ne Memory Module 16 pieces of
µ
PD45D128842G5 (Rev. K)
(Socket Type) (10.16 m m (400) TSOP (II))
MC-45D32CD641KFA-C80 125 MHz Edge connector: Gold pl at ed
31.75 m m height
Preliminary Data Sheet M14899EJ1V0DS00 3
MC-45D32CD641
Pin Configuration
184-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
V
SS
DQ36
DQ37
V
DD
DM4/DQS13
DQ38
DQ39
V
SS
DQ44
/RAS
DQ45
V
DD
Q
/S0
/S1
DM5/DQS14
V
SS
DQ46
DQ47
NC
V
DD
Q
DQ52
DQ53
NC
V
DD
DM6/DQS15
DQ54
DQ55
V
DD
Q
NC
DQ60
DQ61
V
SS
DM7/DQS16
DQ62
DQ63
V
DD
Q
SA0
SA1
SA2
V
DD
SPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQ32
V
DD
Q
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
Q
/WE
DQ41
/CAS
V
SS
DQS5
DQ42
DQ43
V
DD
NC
DQ48
DQ49
V
SS
CK2
/CK2
V
DD
Q
DQS6
DQ50
DQ51
V
SS
V
DD
ID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
/RESET
V
SS
DQ8
DQ9
DQS1
V
DD
Q
CK1
/CK1
V
SS
DQ10
DQ11
CKE0
V
DD
Q
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
NC
NC
V
DD
NC
A0
NC
V
SS
NC
BA1
V
SS
DQ4
DQ5
V
DD
Q
DM0/DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DD
Q
DQ12
DQ13
DM1/DQS10
V
DD
DQ14
DQ15
NC
V
DD
Q
NC
DQ20
NC
V
SS
DQ21
A11
DM2/DQS11
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DD
Q
DM3/DQS12
A3
DQ30
V
SS
DQ31
NC
NC
V
DD
Q
CK0
/CK0
V
SS
NC
A10
NC
V
DD
Q
NC
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A9]
BA0, BA1 : SDRAM Bank Select
D Q 0 - DQ 6 3 : Data Inputs/Outputs
CK0 - CK2 : Clock Input
(positive line of differential pair)
/CK0 - /CK2 : Clock Input
(negative line of differential pair)
CKE0 : Clock Enable Input
/S0, /S1 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQS0 - DQS7 : Low Data Strobe
D M( 0 - 7) / D QS ( 9 - 1 6 ) : Low Data Masks /
High Data Strobe
SA0 - SA2 : Address Input for EEPROM
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
VDD : Power Supply
VSS : Ground
VDDID : VDD Identification Flag
VDDQ : Power Supply for DQ and DQS
VREF : Input Reference
VDDSPD : Power supply for EEPROM
NC : No Connection
/RESET : Reset Input
/xxx indicates active lo w signal.
Preliminary Data Sheet M14899EJ1V0DS00
4
MC-45D32CD641
Block Diagram
DM0/DQS9
DM /S
DQ 0
DQ 1
DQ 2
DQ 3
DQ 7
DQ 6
DQ 1
DQ 0
V
DD
D0 - D15
D0 - D15
D0
BA0, BA1 BA0, BA1 : SDRAMs D0 - D15 SERIAL PD
SDA
A0 A1 A2
SA0 SA1 SA2
SCL
A0 - A11 A0 - A11 : SDRAMs D0 - D15
/RAS /RAS : SDRAMs D0 - D15
/CAS /CAS : SDRAMs D0 - D15
CKE0 CKE0 : SDRAMs D0 - D15
/WE /WE : SDRAMs D0 - D15
CK0, /CK0 CK, /CK : SDRAMs D3, D4, D11, D12
CK1, /CK1 CK, /CK : SDRAMs D0, D1, D2, D8, D9, D10
CK2, /CK2 CK, /CK : SDRAMs D5, D6, D7, D13, D14, D15
V
SS
/S0
/S1
DQ 4
DQ 5
DQ 6
DQ 7
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQS0
DM1/DQS10
DM /S
DQ 8
DQ 9
DQ 10
DQ 11
D1
DQ 12
DQ 13
DQ 14
DQ 15
DQS
DQS1
DM2/DQS11
DM /S
DQ 16
DQ 17
DQ 18
DQ 19
D2
DQ 20
DQ 21
DQ 22
DQ 23
DQS
DQS2
DM3/DQS12
DM /S
DQ 24
DQ 25
DQ 26
DQ 27
D3
DQ 28
DQ 29
DQ 30
DQ 31
DQS
DQS3
DM4/DQS13
DM /S
DQ 32
DQ 33
DQ 34
DQ 35
DQ 7
DQ 6
DQ 1
DQ 0
D4
DQ 36
DQ 37
DQ 38
DQ 39
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQS4
DM5/DQS14
DM /S
DQ 40
DQ 41
DQ 42
DQ 43
D5
DQ 44
DQ 45
DQ 46
DQ 47
DQS
DQS5
DM6/DQS15
DM /S
DQ 48
DQ 49
DQ 50
DQ 51
D6
DQ 52
DQ 53
DQ 54
DQ 55
DQS
DQS6
DM7/DQS16
DM /S
DQ 56
DQ 57
DQ 58
DQ 59
D7
DQ 60
DQ 61
DQ 62
DQ 63
DQS
DM /S
DQ 0
DQ 1
DQ 6
DQ 7
D8
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DM /S
D9
DQS
DM /S
D10
DQS
DM /S
D11
DQS
DM /S
DQ 0
DQ 1
DQ 6
DQ 7
D12
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DM /S
D13
DQS
DM /S
D14
DQS
DM /S
D15
DQS
DQS7
V
DD
QD0 - D15
V
REF
D0 - D15
V
DD
ID
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 0
DQ 1
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQ 0
DQ 1
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQ 0
DQ 1
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 7
DQ 6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQ 0
DQ 1
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQ 0
DQ 1
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQ 0
DQ 1
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
Remarks 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22 Ω.
2. D0 – D15:
µ
PD45D128842 (4M words × 8 bits × 4 banks)
Preliminary Data Sheet M14899EJ1V0DS00 5
MC-45D32CD641
Electrical Specifications
•All voltages are referenced to VSS (GND).
•After power up, wait more than 1 ms and then, execute Power on sequence and CBR (auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin rel ative to VSS VDD, VDDQ –0.5 to +3.6 V
Voltage on input pin relat i ve t o V SS VT–0. 5 to +3.6 V
Short ci rcuit out put current IO50 mA
Power dissipat i on PD12 W
Storage temperature Tstg –55 t o +125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply volt age VDD 2.3 2.5 2.7 V
Supply volt age for DQ, DQS VDDQ 2.3 2.5 2.7 V
Input reference voltage VREF 0.49 × VDDQ 0.51 × VDDQV
Termination voltage VTT VREF − 0. 04 VREF VREF + 0.04 V
High level dc i nput voltage VIH (DC) VREF + 0.15 VDD + 0.3 V
Low level dc input voltage VIL (DC) −0.3 VREF − 0.15 V
Input dif ferential vol tage (CLK and /CLK ) VID (DC) 0.36 VDDQ + 0.6 V
Input crossing poi nt vol tage (CLK and /CLK ) VIX 0.5 × VDDQ–0.2 0.5 × VDDQ+0.2 V
Operating ambient t emperature TA070
°C
Capacitance (TA = 25 °
°°
°C, f = 100 MHz)
Parameter Symbol Test condi tion MIN. TYP. MAX. Unit
Input capacitance CI1 A0 - A11 , BA0 , BA1 , /R AS,
/CAS, /WE TBD TBD pF
CI2 CK0 - CK2, /CK0 - /CK2 TBD TBD
CI3 CKE0 TBD TBD
CI4 /S0, /S1 TBD TBD
Data input/ output capacitanc e CI/O1 DM(0-7)/DQS(9-16),
DQS0 - DQS7
TBD TBD pF
CI/O2 DQ0 - DQ63 TBD TBD
Preliminary Data Sheet M14899EJ1V0DS00
6
MC-45D32CD641
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test conditi on /CAS
latency Grade MIN. MAX. Unit Notes
-C75 TBD mAOperating current
(ACT-PRE) IDD0 tRC = tRC(MIN.), tCK = t CK ( M IN.), One bank,
Acti ve-precharge, DQ, DM and DQS
inputs changing twice per c l ock cycle,
Address and control i nput s changing
once per clock cycle -C80 TBD
CL = 2 -C75 TBD mA 1
-C80 TBD
CL = 2.5 -C75 TBD
Operating current
(ACT-READ-PRE)
IDD1 tRC = tRC(MIN.), tCK = tCK ( M IN.), One
bank, Active-read-prec harge,
IO = 0 mA, Burst length = 2,
Address and control i nput s
changing once per clock cycle -C80 TBD
Precharge power down
standby c urrent IDD2P CKE ≤ VIL(MAX.), tCK = tCK(MIN.),
All bank s i dl e, Power down mode TBD mA
Idle s t andby current IDD2N CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.),
All bank s i dl e, Address and other control input s
changing once per clock cycle
TBD mA
Acti ve power down
standby c urrent IDD3P CKE ≤ VIL(MAX.), tCK = tCK(MIN.), One bank act i ve,
Power down mode TBD mA
Act i ve standby c urrent IDD3N /CS ≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC =
tRAS(MAX.), One bank, Ac tive-precharge, DQ, DM
and DQS inputs changing twice per c l ock
cycle, Address and other control i nputs
changing once per clock cycle
TBD mA
CL = 2 -C75 TBD mA 2
-C80 TBD
CL = 2.5 -C75 TBD
Operating current
(Burst read)
IDD4R tCK = tCK(MIN.), Cont i nuous burst
read, Burst length = 2, IO =
0mA, One bank ac t i ve,
Address and control i nput s
changing once per clock cycle -C80 TBD
CL = 2 -C75 TBD mA 2
-C80 TBD
CL = 2.5 -C75 TBD
Operating current
(Burst write)
IDD4W tCK = tCK(MIN.), Cont i nuous burst
write, Burst length = 2, One
bank act i ve, Address and
control i nput s changing once
per clock cycle -C80 TBD
CBR (auto) ref resh current IDD5 tRFC = tRFC(MIN.) -C75 TBD mA
-C80 TBD
Self ref resh current IDD6 CKE ≤ 0.2 V TBD mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output
open.
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test c ondi t i on MIN. MAX. Unit Notes
Input leak age current II(L) VI = 0 to 3.6 V, al l other pins not under test = 0 V TBD TBD
µ
A
Output leak age current IO(L) DOUT is disabl ed, VO = 0 to VDDQ + 0.3 V TBD TBD
µ
A
Output high c urrent IOH VOUT = VDDQ − 0.43 V TBD m A
Output low current IOL VOUT = 0.35 V TBD m A
Preliminary Data Sheet M14899EJ1V0DS00 7
MC-45D32CD641
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter Symbol Value Unit Notes
Input Reference voltage (I nput timing measurement ref erence level) VREF VDDQ x 0.5 V
Termination voltage (Output ti ming measurement reference level) VTT VREF V1
High level ac i nput voltage V IH(ac) VREF + 0. 31 V
Low level ac input voltage VIL(ac) VREF − 0.31 V
Input different i al vol tage (CK0 - CK2 and /CK0 - / CK 2) VID(ac) 0.7 V
Input si gnal slew rate SLEW 1 V/ns 2
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level.
2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)-
VIL(ac))/ ∆t
Output
RT = 50 Ω
CLOAD = 30 pF
VTT
Preliminary Data Sheet M14899EJ1V0DS00
8
MC-45D32CD641
Synchronous Characteristics
Param eter Sym bol -C75 (PC266B) -C80 (PC200) Uni t Note
MIN. MAX. MIN. MAX.
Clock cycle time CL = 2.5 tCK 7.515815ns
CL = 2 10151015
CLK high-level width tCH 0.45 0.55 0.45 0.55 tCK
CLK low-level width tCL 0.45 0.55 0.45 0.55 tCK
DQ output access time from CLK, /CLK tAC –0.75 0.75 –0.8 0.8 ns
DQS output access time from CLK, /CLK tDQSCK –0.75 0.75 –0.8 0.8 ns
DQS-DQ skew (for DQS and as sociated DQ
signals) tDQSQ –0.5 0.5 –0.6 0.6 ns
DQS-DQ skew (for DQS and al l DQ s i gnal s) tDQSQA –0.5 0.5 –0.6 0.6 ns
Data out low-im pedance time from CLK, /CLK tLZ –0.75 0.75 –0.8 0.8 ns
Data out high-i mpedance tim e from CLK, /CLK tHZ –0.75 0.75 –0.8 0.8 ns
Half clock period tHP tCH, tCL tCH, tCL ns
DQS read preambl e tRPRE 0.9 1.1 0.9 1.1 tCK
DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK
DQ-DQS hold, DQS to firs t DQ to go non-valid,
per access tQH tHP – 0.75 tHP – 1 ns
DQ and DM input setup tim e tDS 0.5 0.6 ns
DQ and DM input hold time tDH 0.5 0.6 ns
DQ and DM input pulse width (f or each input) tDIPW 1.75 2 ns
DQS write preambl e setup ti me tWPRES 00ns
DQS write preambl e tWPRE 0.25 0.25 tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
Write command t o f i rst DQS l atching t ransition tDQSS 0.75 1.25 0.75 1.25 tCK
DQS input high pul se width tDQSH 0.35 0.35 tCK
DQS input low pulse width t DQSL 0.35 0.35 tCK
DQS falli ng edge to CLK setup time tDSS 0.2 0.2 tCK
DQS falli ng edge hol d time from CLK tDSH 0.2 0.2 tCK
Address and control i nput setup ti me tIS 0.9 1.1 ns
Address and control i nput hol d time tIH 0.9 1.1 ns
Address and control i nput pul se width tIPW 2.2 2.5 ns
Internal write t o read command delay tWTR 11t
CK
Remark These specifications are applied to the monolithic device.
Preliminary Data Sheet M14899EJ1V0DS00 9
MC-45D32CD641
Asynchronous Characteristics
Parameter Symbol -C75(PC266B) -C80(PC200) Unit
MIN. MAX. MIN. MAX.
ACT to REF/ACT com mand period (operat ion) tRC 65 70 ns
REF to REF/ A CT c ommand period (refresh) tRFC 75 80 ns
ACT to PRE c ommand period t RAS 45 120,000 50 120,000 ns
PRE to ACT c ommand period tRP 20 20 ns
ACT to READ/WRITE delay tRCD 20 20 ns
ACT(one) to ACT(anot her) command period tRRD 15 15 ns
Writ e recovery time tWR 15 15 ns
Auto precharge write recovery time + precharge time tDAL 35 35 ns
Mode register set comm and cycle ti me tMRD 15 15 ns
Exit self refresh to command tXSNR 75 80 ns
Refresh ti me (4,096 refresh cycles) tREF 64 64 ms
Preliminary Data Sheet M14899EJ1V0DS00
10
MC-45D32CD641
Serial PD (1/2)
Byte No . Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines t he number of bytes written i nto
serial PD memory 80H 1 0 0 0 0 0 0 0 128 bytes
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental mem ory type 07H 0 0 0 0 0 1 1 1 DDR SDRAM
3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns 0AH 0 0 0 0 1 0 1 0 10 columns
5 Number of banks 02H 0 0 0 0 0 0 1 0 2 banks
6 Data width 40H 0 1 0 0 0 0 0 0 64 bits
7 Data width (conti nued) 00H 0 0 0 0 0 0 0 0 0
8 Voltage interface 04H 0 0 0 0 0 1 0 0 S S T L2
9 CL = 2.5 Cycle t i me -C75 75H 0 1 1 1 0 1 0 1 7.5 ns
-C80 80H 1 0 0 0 0 0 0 0 8 ns
10 CL = 2.5 Access t i me -C75 75H 0 1 1 1 0 1 0 1 0.75 ns
-C80 80H 1 0 0 0 0 0 0 0 0.8 ns
11 DIMM configurati on type 00H 0 0 0 0 0 0 0 0 None
12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal
13SDRAM width 08H00001000x8
14 Error chec king SDRA M width 00H 0 0 0 0 0 0 0 0 None
15 Minimum cl ock delay 01H 0 0 0 0 0 0 0 1 1 clock
16 Burst l ength supported 0EH 0 0 0 0 1 1 1 0 2, 4, 8
17 Number of bank s on each SDRAM 04H 0 0 0 0 0 1 0 0 4 bank s
18 /CAS latency supported 0CH 0 0 0 0 1 1 0 0 2, 2.5
19 /CS lat ency supported 01H 0 0 0 0 0 0 0 1 0
20 /WE l at ency support ed 02H 0 0 0 0 0 0 1 0 1
21 SDRAM m odul e at tributes 20H 0 0 1 0 0 0 0 0 Differential Clock
22 SDRAM device at tributes : General 00H 0 0 0 0 0 0 0 0 VDD ± 0.2 V
23 CL = 2 Cycle ti me -C75 A0H 1 0 1 0 0 0 0 0 10 ns
-C80 A0H 1 0 1 0 0 0 0 0 10 ns
24 CL = 2 Access t i me -C75 75H 0 1 1 1 0 1 0 1 0.75 ns
-C80 80H 1 0 0 0 0 0 0 0 0.8 ns
25-26
27 tRP(MIN.) -C75 50H 0 1 0 1 0 0 0 0 20 ns
-C80 50H 0 1 0 1 0 0 0 0 20 ns
28 tRRD(MIN.) -C75 3CH 0 0 1 1 1 1 0 0 15 ns
-C80 3CH 0 0 1 1 1 1 0 0 15 ns
29 tRCD(MIN.) -C75 50H 0 1 0 1 0 0 0 0 20 ns
-C80 50H 0 1 0 1 0 0 0 0 20 ns
30 tRAS(MIN.) -C75 2DH 0 0 1 0 1 1 0 1 45 ns
-C80 32H 0 0 1 1 0 0 1 0 50 ns
31 Module bank densit y 20H 0 0 1 0 0 0 0 0 128M bytes
Preliminary Data Sheet M14899EJ1V0DS00 11
MC-45D32CD641
(2/2)
Byte No . Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
32 Command and address signal input
setup ti me C0H110000001.2 ns
33 Command and address signal input
hold time C0H110000001.2 ns
34 Data signal i nput setup ti me 60H 0 1 1 0 0 0 0 0 0.6 ns
35 Data signal i nput hol d time 60H 0 1 1 0 0 0 0 0 0.6 ns
36-61
62SPD revision 00H00000000
63 Checksum for bytes 0 - 62 -C75 1DH 0 0 0 1 1 1 0 1
-C8043H01000011
64-71 Manufacture’ s JE DE C ID code
72 Manufacturing l ocation
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-99 Assembly s eri al number
100-127 Mf g specif i c 00H 0 0 0 0 0 0 0 0
Timing Chart
Refer to the
µ
PD45D128442, 45D128842, 45D128164 Data sheet (M13852E).
Preliminary Data Sheet M14899EJ1V0DS00
12
MC-45D32CD641
Package Drawing
184-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
ITEM MILLIMETERS
A
A1
B
C1
C2
D
E
G
H
133.35
64.77
1.80
3.80
49.53
133.35±0.13
1.27 (T.P.)
J
6.35
J1
C
I
6.35
10.00
J2
K
M
N
P
Q
R
S
31.75±0.13
4.0 MAX.
17.80
4.0 MIN.
2.50
4.0
U
19.80
23.38
T
1.27±0.1
0.2±0.15
1.0±0.05
2.50±0.15
3.0 MIN.
φ
J1 (AREA B) U
M
J2 (AREA A)
E
C
P
Q
detail of A part
C2
C1 T
R
A
(OPTIONAL HOLES)
N
K
A (AREA B)
A1 (AREA A)
J
I
B
GD
S
H
M
Preliminary Data Sheet M14899EJ1V0DS00 13
MC-45D32CD641
[MEMO]
Preliminary Data Sheet M14899EJ1V0DS00
14
MC-45D32CD641
[MEMO]
Preliminary Data Sheet M14899EJ1V0DS00 15
MC-45D32CD641
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
MC-45D32CD641
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
M8E 00. 4
The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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