5
AT45DB642
1638D–11/01
send 32 don't care clock cycles before the first bit (or byte if using the parallel interface mode)
of the memory array can be read.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Burst Array Read
with Synchronous Delay is defined by the fBARSD specification. The Burst Array Read with Syn-
chronous Delay bypasses both data buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory page read allows the user to read data directly
from any one of the 8192 pages in the main memory, bypassing both of the data buffers and
leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H
must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence) and a series of don’t care bytes (four don’t care bytes if
using the serial interface or 60 don’t care bytes if the using parallel interface). The first 13 bits
(PA12 - PA0) of the 24-bit (three-byte) address sequence specify the page in main memory to
be read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence specify the starting
byte address within that page. The four or 60 don’t care bytes that follow the three address
bytes are sent to initialize the read operation. Following the don’t care bytes, additional pulses
on SCK/CLK result in data being output on either the SO (serial output) pin or the parallel out-
put pins (I/O7 - I/O0). The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a page in main
memory is reached, the device will continue reading back at the beginning of the same page.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7 - I/O0).
BUFFER READ: Data can be read from either one of the two buffers, using different opcodes
to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer
1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a buffer read,
the opcode must be clocked into the device followed by three address bytes comprised of 13
don’t care bits and 11 buffer address bits (BFA10 - BFA0). Following the three address bytes,
an additional don’t care byte must be clocked in to initialize the read operation. Since the
buffer size is 1056 bytes, 11 buffer address bits are required to specify the first byte of data to
be read from the buffer. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a buffer is
reached, the device will continue reading back at the beginning of the buffer. A low-to-high
transition on the CS pin will terminate the read operation and tri-state the output pins (SO or
I/O7 - I/O0).
STATUS REGISTER READ: The status register can be used to determine the device’s
ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of 57H or D7H must be loaded into the
device. After the opcode is clocked in, the 1-byte status register will be clocked out on the out-
put pins (SO or I/O7 - I/O0), starting with the next clock cycle. When using the serial interface,
the data in the status register, starting with the MSB (bit 7), will be clocked out on the SO pin
during the next eight clock cycles.
The five most-significant bits of the status register will contain device information, while the
remaining three least-significant bits are reserved for future use and will have undefined val-
ues. After the one byte of the status register has been clocked out, the sequence will repeat
itself (as long as CS remains low and SCK/CLK is being toggled). The data in the status regis-
ter is constantly updated, so each repeating sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device
is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. The user can continuously poll bit 7 of the status register by stopping SCK/CLK at a low
level once bit 7 has been output on the SO or I/O7 pin. The status of bit 7 will continue to be
output on the SO or I/O7 pin, and once the device is no longer busy, the state of the SO or