K7P321874C-HC25000 - SAMSUNG

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 1 -

36Mb Late Write SRAM Specification

119BGA with Pb & Pb-Free

(RoHS compliant)

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.

ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-

lar applications where Product failure could result in loss of life or personal or physical harm, or any military

or defense application, or any governmental procurement to which special terms or provisions may apply.

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 2 -

1Mx36 & 2Mx18 Synchronous Pipelined SRAM

Revision History

Rev. No.

Rev. 0.0

Rev. 0.1

Rev. 0.2

Rev. 0.3

Rev. 1.0

Rev. 1.1

Rev. 1.2

Remark

Advance

Preliminary

Final

History

1. Initial Document

1. Change VDD range : from 1.8~2.5V to 1.8 or 2.5V

1. Put the data in the table of DC Characteristics, Pin Capacitance and Thermal

Resistance.

1. Change Samsung JEDEC Code in ID REGISTER DEFINITION

1. Correct typo

1. Change Max. VREF and VCM-CLK from 0.9V to 0.95V in recommended DC

operating conditions.

1. Change VOH in JTAG DC OPERATING CONDITION

Draft Date

Dec. 2005

Jan. 2006

Apr. 2006

Jun. 2006

Aug. 2006

Dec. 2006

Feb. 2007

Document Title

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 3 -

1Mx36 & 2Mx18 Synchronous Pipelined SRAM

FEATURES

Org. Maximum

Frequency

Access

Time VDD Part Number

1Mx36 300MHz 1.6 2.5V K7P323674C-H(G)1C30

250MHz 2.0 1.8 / 2.5V K7P323674C-H(G)1C25

2Mx18 300MHz 1.6 2.5V K7P321874C-H(G)1C30

250MHz 2.0 1.8 / 2.5V K7P321874C-H(G)1C25

• 1Mx36 or 2Mx18 Organizations.

• 1.8 or 2.5V VDD/1.5V ~1.8VDDQ.

• HSTL Input and Output Levels.

• Differential, HSTL Clock Inputs K, K.

• Synchronous Read and Write Operation

• Registered Input and Registered Output

• Internal Pipeline Latches to Support Late Write.

Note 1 : H(G) [Package type] : G-Pb Free, H-Pb

2 : 300MHz is supported only at 2.5V VDD. 250MHz is the maximum speed at 1.8V VDD

GENERAL DESCRIPTION

The K7P323674C and K7P321874C are 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of 36

bits(or 2,097,152 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.

Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the

rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are

updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one

cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

• Byte Write Capability(four byte write selects, one for each 9bits)

• Synchronous or Asynchronous Output Enable.

• Power Down Mode via ZZ Signal.

• Programmable Impedance Output Drivers.

• JTAG 1149.1 Compatible Test Access port.

• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).

ORDERING INFORMATION

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 4 -

PIN DESCRIPTION

Pin Name Pin Description Pin Name Pin Description

K, K Differential Clocks VREF HSTL Input Reference Voltage

SAn Synchronous Address Input M1, M2 Read Protocol Mode Pins ( M1=VSS, M2=VDDQ )

DQn Bi-directional Data Bus G Asynchronous Output Enable

SW Synchronous Global Write Enable SS Synchronous Select

SWa Synchronous Byte a Write Enable TCK JTAG Test Clock

SWb Synchronous Byte b Write Enable TMS JTAG Test Mode Select

SWc Synchronous Byte c Write Enable TDI JTAG Test Data Input

SWd Synchronous Byte d Write Enable TDO JTAG Test Data Output

ZZ Asynchronous Power Down ZQ Output Driver Impedance Control

VDD Core Power Supply VSS GND

VDDQ Output Power Supply NC No Connection

FUNCTIONAL BLOCK DIAGRAM

SA[0:19] or SA[0:20]

SWx

1Mx36

Data In

DQx[1:9]

(x=a, b, c, d)

or (x=a, b)

(x=a, b, c, d)

or (x=a, b)

KCK

2Mx18

Array

Row Decoder

Column Decoder

Write/Read Circuit

0 1

Data Out

Read

Address

Latch

SWx

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 5 -

PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7P323674C(1Mx36)

1234567

AVDDQ SA SA NC SA SA VDDQ

BNC SA SA SA SA SA NC

CNC SA SA VDD SA SA NC

DDQc DQc VSS ZQ VSS DQb DQb

EDQc DQc VSS SS VSS DQb DQb

FVDDQ DQc VSS G VSS DQb VDDQ

GDQc DQc SWcNCSWbDQbDQb

HDQc DQc VSS NC VSS DQb DQb

JVDDQ VDD VREF VDD VREF VDD VDDQ

KDQd DQd VSS KVSS DQa DQa

LDQd DQd SWdKSWaDQaDQa

MVDDQ DQd VSS SW VSS DQa VDDQ

NDQd DQd VSS SA VSS DQa DQa

PDQd DQd VSS SA VSS DQa DQa

RNC SA M1VDD M2SA2NC

TNC NC SA SA SA NC ZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

K7P321874C(2Mx18)

1234567

AVDDQ SA SA NC SA SA VDDQ

BNC SA SA SA SA SA NC

CNC SA SA VDD SA SA NC

DDQb NC VSS ZQ VSS DQa NC

ENC DQb VSS SS VSS NC DQa

FVDDQ NC VSS G VSS DQa VDDQ

GNC DQb SWbNC NC NCDQa

HDQb NC VSS NC VSS DQa NC

JVDDQ VDD VREF VDD VREF VDD VDDQ

KNC DQb VSS KVSS NC DQa

LDQb NC NC K SWaDQa NC

MVDDQ DQb VSS SW VSS NC VDDQ

NDQb NC VSS SA VSS DQa NC

PNC DQb VSS SA VSS NC DQa

RNC SA M1VDD M2SA NC

TNC SA SA NC SA SA ZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 6 -

During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second

edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this

cycle, signaling that the SRAM should drive out the data.

During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Write(Store) Operation

All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,

one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the

Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.

Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write

cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of

read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the

same as the SW signal.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be

done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is

the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored

write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the

SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have

new byte data from the write data buffer and the other bytes from the SRAM array.

Mode Control

There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined

operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDDQ. These

mode pins must be set at power-up and must not change during device operation.

Programmable Impedance Output Buffer Operation

This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance

can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM

and VSS. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250Ω

resistor will give an output buffer impedance of 50Ω. The allowable range of RQ is from 175Ω to 350Ω. Internal circuits evaluate and

periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-

ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the

optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.

Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance

match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum

number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-

tion by connecting ZQ to VSS or VDDQ.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied

simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ

does not exceed VDD by more than 0.5V during power-down.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored

and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep

mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all

pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.

Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

Read Operation

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 7 -

TRUTH TABLE

NOTE : K & K are complementary

KZZ GSS SW SWaSWbSWcSWdDQa DQb DQc DQd Operation

XHXXXXXXXHi-ZHi-ZHi-ZHi-ZPower Down Mode. No Operation

XLHXXXXXXHi-ZHi-ZHi-ZHi-ZOutput Disabled.

↑LLHXXXXXHi-ZHi-ZHi-ZHi-ZOutput Disabled. No Operation

↑LLLHXXXXD

OUT DOUT DOUT DOUT Read Cycle

↑L X L L H H H H Hi-Z Hi-Z Hi-Z Hi-Z No Bytes Written

↑LXLLLHHHD

IN Hi-Z Hi-Z Hi-Z Write first byte

↑LXLLHLHHHi-ZD

IN Hi-Z Hi-Z Write second byte

↑L X L L H H L H Hi-Z Hi-Z DIN Hi-Z Write third byte

↑L X L L H H H L Hi-Z Hi-Z Hi-Z DIN Write fourth byte

↑LXLLLLLLD

IN DIN DIN DIN Write all bytes

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Value Unit

Core Supply Voltage Relative to VSS VDD -0.5 to 3.13 V

Output Supply Voltage Relative to VSS VDDQ -0.5 to 2.4 V

Voltage on any I/O pin Relative to VSS VIN -0.5 to VDDQ+0.5 (2.4V MAX)V

Output Short-Circuit Current IOUT 25 mA

Operating Temperature TOPR 0 to 70 °C

Storage Temperature TSTG -55 to 125 °C

RECOMMENDED DC OPERATING CONDITIONS

NOTE : 1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parame-

ters.

2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).

3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).

4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK.

5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK.

6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock

7. This device support both 250MHz and 300MHz frequency at VDD1. and support only 250MHz frequency at VDD2.

Parameter Symbol Min Typ Max Unit Note

Core Power Supply Voltage VDD1 2.37 2.5 2.63 V 7

VDD2 1.7 1.8 1.9 V 7

Output Power Supply Voltage VDDQ 1.4 1.5 1.9 V

Input High Level VIH VREF+0.1 - VDDQ+0.3 V 1, 2

Input Low Level VIL -0.3 - VREF-0.1 V1, 3

Input Reference Voltage VREF 0.6 VDDQ/2 0.95 V

Clock Input Signal Voltage VIN-CLK -0.3 - VDDQ+0.3 V 1, 4

Clock Input Differential Voltage VDIF-CLK 0.1 - VDDQ+0.6 V 1, 5

Clock Input Common Mode Voltage VCM-CLK 0.6 0.75 0.95 V 1, 6

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 8 -

DC CHARACTERISTICS

NOTE :1. Minimum cycle. IOUT=0mA.

2. 50% read cycles.

3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.

4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.

5. Programmable Impedance Output Buffer Mode. The ZQ pin is connected to VSS through RQ.

6. Minimum Impedance Output Buffer Mode. The ZQ pin is connected to VSS or VDD.

Parameter Symbol Min Max Unit Note

Average Power Supply Operating Current-x36

(VIN=VIH or VIL, ZZ & SS=VIL)

IDD30

IDD25 -620

550 mA 1, 2

Average Power Supply Operating Current-x18

(VIN=VIH or VIL, ZZ & SS=VIL)

IDD30

IDD25 -570

500 mA 1, 2

Power Supply Standby Current

(VIN=VIH or VIL, ZZ=VIH)ISBZZ -70mA1

Active Standby Power Supply Current

(VIN=VIH or VIL, SS=VIH, ZZ=VIL)ISBSS - 200 mA 1

Input Leakage Current

(VIN=VSS or VDDQ)ILI -1 1 µA

Output Leakage Current

(VOUT=VSS or VDDQ, DQ in High-Z) ILO -1 1 µA

Output High Voltage(Programmable Impedance Mode) VOH1 VDDQ/2 VDDQ V3,5

Output Low Voltage(Programmable Impedance Mode) VOL1 VSS VDDQ/2 V 4,5

Output High Voltage(IOH=-0.1mA) VOH2 VDDQ-0.2 VDDQ V6

Output Low Voltage(IOL=0.1MA) VOL2 VSS 0.2 V 6

Output High Voltage(IOH=-6mA) VOH3 VDDQ-0.4 VDDQ V6

Output Low Voltage(IOL=6mA) VOL3 VSS 0.4 V 6

PIN CAPACITANCE

NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz)

Parameter Symbol Test Condition Min Max Unit

Input Capacitance CIN VIN=0V - 4 pF

Data Output Capacitance COUT VOUT=0V - 5 pF

Clock Capacitance CCLK VCLK=0V - 5 pF

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 9 -

AC TEST CONDITIONS (TA=0 ~ 70°C, VDD=1.7 ~ 1.9V and 2.37 ~ 2.63V, VDDQ=1.4~1.9V)

NOTE : Parameters are tested with RQ=250Ω and VDDQ=1.5V.

Parameter Symbol Value Unit

Core Power Supply Voltage VDD 1.7~1.9 and 2.37~2.63 V

Output Power Supply Voltage VDDQ 1.4~1.9 V

Input High/Low Level VIH/VIL VDDQ/2 ± 0.5 V

Input Reference Level VREF VDDQ/2 V

Input Rise/Fall Time TR/TF0.5/0.5 ns

Input and Out Timing Reference Level VDDQ/2 V

Clock Input Timing Reference Level Cross Point V

50Ω

AC TEST OUTPUT LOAD

25Ω5pF

VDDQ/2

5pF

VDDQ/2

50Ω

VDDQ/2

AC CHARACTERISTICS

Parameter Symbol

-30 -25

Unit Note

2.5V VDD Only 1.8V / 2.5V VDD

Min Max Min Max

Clock Cycle Time tKHKH 3.3 - 4.0 - ns

Clock High Pulse Width tKHKL 1.3 - 1.6 - ns

Clock Low Pulse Width tKLKH 1.3 - 1.6 - ns

Clock High to Output Valid tKHQV -1.6-2.0ns

Clock High to Output Hold tKHQX 0.5 - 0.5 - ns

Address Setup Time tAVKH 0.3 - 0.3 - ns

Address Hold Time tKHAX 0.5 - 0.5 - ns

Write Data Setup Time tDVKH 0.3 - 0.3 - ns

Write Data Hold Time tKHDX 0.5 - 0.5 - ns

SW, SW[a:d] Setup Time tWVKH 0.3 - 0.3 - ns

SW, SW[a:d] Hold Time tKHWX 0.5 - 0.5 - ns

SS Setup Time tSVKH 0.3 - 0.3 - ns

SS Hold Time tKHSX 0.5 - 0.5 - ns

Clock High to Output Hi-Z tKHQZ -1.6-2.0ns

Clock High to Output Low-Z tKHQX1 0.5 - 0.5 - ns

G High to Output High-Z tGHQZ -1.6-2.0ns

G Low to Output Low-Z tGLQX 0.5 - 0.5 - ns

G Low to Output Valid tGLQV -1.6-2.0ns

ZZ High to Power Down(Sleep Time) tZZE - 15 - 15 ns

ZZ Low to Recovery(Wake-up Time) tZZR - 20 - 20 ns

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 10

TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)

12345678

SAn

SWx

DQn

NOTE

1. D3 is the input data written in memory location A3.

2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the

last write cycle address.

A1A2A3A4A5A4A6A7

Q1D3D4Q5Q4

TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)

12345678

SAn

SWx

DQn

NOTE

1. D3 is the input data written in memory location A3.

2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last

write cycle address.

A1A2A3A4A5A4A6A7

Q1D3D4Q5Q4Q2

tKHKH

tKHAX

tAVKH

tKHKL tKLKH

tKHSX

tSVKH

tWVKH tKHWX tWVKH tKHWX

tKHQX1 tKHQX

tWVKH tKHWX

tKHQV tKHDX

tKHQZ tDVKH tKHDX

tKHKH

tGHQZ

tGLQX

tGLQV

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 11

TIMING WAVEFORMS OF STANDBY CYCLES

12345678

SAn

SWx

DQn

A2A1A2A3

Q1Q2Q1

tKHKH

tZZE tZZR

tKHQV

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 12

JTAG Instruction Coding

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of

other SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the serial

shift of the external TDI data.

3. Bypass register is initiated to VSS when BYPASS instruction is

invoked. The Bypass Register also holds serially loaded TDI when

exiting the Shift DR states.

4. SAMPLE instruction dose not places DQs in Hi-Z.

5. PRIVATE is reserved for the exclusive use of SAMSUNG. This

instruction should not be used.

IR2 IR1 IR0 Instruction TDO Output Notes

0 0 0 SAMPLE-Z Boundary Scan Register 1

0 0 1 IDCODE Identification Register 2

0 1 0 SAMPLE-Z Boundary Scan Register 1

0 1 1 BYPASS Bypass Register 3

1 0 0 SAMPLE Boundary Scan Register 4

101 PRIVATE 5

1 1 0 BYPASS Bypass Register 3

1 1 1 BYPASS Bypass Register 3

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not

driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-

ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,

therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without

interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an

undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be

tied to VDD through a resistor. TDO should be left unconnected.

TAP Controller State Diagram

JTAG Block Diagram

SRAM

CORE

BYPASS Reg.

Identification Reg.

Instruction Reg.

Control Signals

TAP Controller

TDO

M2M1

TDI

TMS

TCK

Test Logic Reset

Run Test Idle

011

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 13

ID REGISTER DEFINITION

Part Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1) Start Bit(0)

1Mx36 0000 01000 00100 XXXXXX 00011001110 1

2Mx18 0000 01001 00011 XXXXXX 00011001110 1

BOUNDARY SCAN EXIT ORDER(x36)

36 3B SA SA 5B 35

37 2B SA SA 6B 34

38 3A SA SA 5A 33

39 3C SA SA 5C 32

40 2C SA SA 6C 31

41 2A SA SA 6A 30

42 2D DQc9DQb96D 29

43 1D DQc8DQb87D 28

44 2E DQc7DQb76E 27

45 1E DQc6DQb67E 26

46 2F DQc5DQb56F 25

47 2G DQc4DQb46G 24

48 1G DQc3DQb37G 23

49 2H DQc2DQb26H 22

50 1H DQc1DQb17H 21

51 3G SWcSWb5G 20

52 4D ZQ G4F 19

53 4E SS K4K18

54 4B SA K4L 17

55 4H NC* SWa5L 16

56 4M SW DQa17K 15

57 3L SWdDQa26K 14

58 1K DQd1DQa37L 13

59 2K DQd2DQa46L 12

60 1L DQd3DQa56M 11

61 2L DQd4DQa67N 10

62 2M DQd5DQa76N 9

63 1N DQd6DQa87P 8

64 2N DQd7DQa96P 7

65 1P DQd8ZZ 7T 6

66 2P DQd9SA 5T 5

67 3T SA SA 6R 4

68 2R SA SA 4T 3

69 4N SA SA 4P 2

70 3R M1M25R 1

BOUNDARY SCAN EXIT ORDER(x18)

26 3B SA SA 5B 25

27 2B SA SA 6B 24

28 3A SA SA 5A 23

29 3C SA SA 5C 22

30 2C SA SA 6C 21

31 2A SA SA 6A 20

DQa96D 19

32 1D DQb1

33 2E DQb2

DQa87E 18

DQa76F 17

34 2G DQb3

DQa67G 16

DQa56H 15

35 1H DQb4

36 3G SWb

37 4D ZQ G4F 14

38 4E SS K4K13

39 4B SA K4L 12

40 4H NC* SWa5L 11

41 4M SW DQa47K 10

42 2K DQb5DQa36L 9

43 1L DQb6

44 2M DQb7DQa26N 8

45 1N DQb8DQa17P 7

ZZ 7T 6

46 2P DQb9SA 5T 5

47 3T SA SA 6R 4

48 2R SA

49 4N SA SA 4P 3

50 2T SA SA 6T 2

51 3R M1M25R 1

SCAN REGISTER DEFINITION

Part Instruction Register Bypass Register ID Register Boundary Scan

1Mx36 3 bits 1 bits 32 bits 70 bits

2Mx18 3 bits 1 bits 32 bits 51 bits

NOTE :1. Pin 4H is no connection pin to internal chip and the scanned data is "0".

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 14

JTAG DC OPERATING CONDITIONS

NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.

Parameter Symbol Min Typ Max Unit Note

Power Supply Voltage VDD 1.7 2.5 2.63 V

Input High Level VIH 0.7*VDD -VDD+0.3 V

Input Low Level VIL -0.3 - 0.3*VDD V

Output High Voltage(IOH=-2mA) VOH 0.75*VDD -VDD V

Output Low Voltage(IOL=2mA) VOL VSS -0.2V

JTAG TIMING DIAGRAM

JTAG AC Characteristics

Parameter Symbol Min Max Unit Note

TCK Cycle Time tCHCH 50 - ns

TCK High Pulse Width tCHCL 20 - ns

TCK Low Pulse Width tCLCH 20 - ns

TMS Input Setup Time tMVCH 5-ns

TMS Input Hold Time tCHMX 5-ns

TDI Input Setup Time tDVCH 5-ns

TDI Input Hold Time tCHDX 5-ns

SRAM Input Setup Time tSVCH 5-ns

SRAM Input Hold Time tCHSX 5-ns

Clock Low to Output Valid tCLQV 010ns

JTAG AC TEST CONDITIONS

NOTE : 1. See SRAM AC test output load on page 7.

Parameter Symbol Min Unit Note

Input High/Low Level VIH/VIL VDD/0.0 V

Input Rise/Fall Time TR/TF 1.0/1.0 ns

Input and Output Timing Reference Level VDD/2 V 1

TCK

TMS

TDI

tCHCH

tMVCH tCHMX

tCHCL tCLCH

tDVCH tCHDX

tCLQV

TDO

(SRAM)

tSVCH tCHSX

K7P321874C 1Mx36 & 2Mx18 SRAM

K7P323674C

Rev. 1.2 February 2007

- 15

119 BGA PACKAGE DIMENSIONS

119 BGA PACKAGE THERMAL CHARACTERISTICS

NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.

Parameter Symbol Thermal Resistance Unit Note

Junction to Ambient (at still air) Theta_JA 20.0 °C/W 1.5W Heating

Junction to Case Theta_JC 4.3 °C/W

Junction to Board Theta_JB 5.4 °C/W 1.5W Heating

119x 0.750±0.15

1.27 x 6 = 7.62

12.50 ± 0.10

0.60±0.10

4x C1.00 4x C0.70

14.00 ± 0.10

22.00 ± 0.10

20.50 ± 0.10

NOTE :

1.All Dimensions are in Millimeters.

2. Cavity Surface : Mat finish (Rz 10~15um)

Pin Surface : polish (Rz 2um Max)

3. Solder Ball to PCB Offset : 0.10 MAX.

4. PCB to Cavity Offset : 0.10 MAX.

5. PKG Warpage : 0.05 MAX

# A1 INDEX MARK

2.00

2.00 1.00 Dp 0.10 ± 0.05

2.00

2.00 Dp 0.10 ± 0.05

0.15 MAX

0.30 MAX

1.27 x 16 = 20.32

1.27

25° ± 5°

0.56 ± 0.04

0.90 ± 0.05

1.50 ± 0.10

2.21 MAX

1234567