IDT70V06S25JG8 - Integrated Device Technology

6.07

MARCH 2000

DSC-2942/7

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/WL

CEL

OEL

BUSYL

A13L

A0L

2942 drw 01

I/O0L-I/O

CEL

OEL

R/WL

SEML

INTLM/S

BUSYR

I/O0R-I/O7R

A13R

A0R

SEMR

INTR

CER

OER

(2)

(1,2) (1,2)

(2)

R/WR

CER

OER

R/WR

IDT70V06S/L

HIGH-SPEED 3.3V

16K x 8 DUAL-PORT

STATIC RAM

Features

◆◆

◆True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆◆

◆High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

◆◆

◆Low-power operation

– IDT70V06S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V06L

Active: 380mW (typ.)

Standby: 660mW (typ.)

◆◆

◆IDT70V06 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

◆◆

◆M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

◆◆

◆Interrupt Flag

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆◆

◆Battery backup operation—2V data retention

◆◆

◆TTL-compatible, single 3.3V (±0.3V) power supply

◆◆

◆Available in 68-pin PGA and PLCC, and a 64-pin TQFP

◆◆

◆Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

2942 drw 02

INDEX

98765432168676665

27 28 29 30 31 32 33 34 35 36 37 38 39

VCC

I/O1R

I/O2R

I/O3R

I/O4R

INTL

GND

A4L

A3L

A2L

A1L

A0L

A3R

A0R

A1R

A2R

I/O2L A5L

M/S

26 40 41 42 43

64 63 62 61

I/O3L

GND

I/O0R

VCC

A4R

BUSYL

GND

BUSYR

INTR

12R

I/O

N/C

GND

OER

SEMR

CER

OEL

SEML

CEL

N/C

I/O

IDT70V06J

J68-1(4)

68-Pin PLCC

Top View(5)

I/O4L

I/O5L

I/O6L

I/O7L

I/O5R

I/O6R

N/C

12L

N/C

11R

10R

11L

10L

13R

13L

Description

The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The

IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port

Static RAM or as a combination MASTER/SLAVE Dual-Port Static

RAM for 16-bit-or-more word systems. Using the IDT MASTER/

SLAVE Dual-Port Static RAM approach in 16-bit or wider memory

system applications results in full-speed, error-free operation without

the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by CE permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 400mW of power.

The IDT70V06 is packaged in a ceramic 68-pin PGA and PLCC

and a 64-pin thin quad flatpack (TQFP).

Pin Configurations(1,2,3)

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. J68-1 package body is approximately .95 in x .95 in x .17 in

PN-64 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

INDEX

70V06PF

PN-64(4)

64-Pin TQFP

Top View(5)

I/O2L

VCC

GND

A4R

BUSYL

BUSYR

INTR

INTL

GND

M/S

A5L

I/O1L

SEM

VCC

SEM

A12R

GND

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

I/O0R

I/O1R

I/O2R

VCC

I/O3R

I/O4R

I/O5R

I/O6R

I/O7R

A11R

A10R

A9R

A8R

A7R

A6R

A5R

A3R

A2R

A1R

A0R

A0L

A1L

A2L

A3L

A4L

A6L

A7L

A8L

A9L

A10L

A11L

A12L

I/O0L

2942 drw 03

A13RA13L

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.18 in x 1.18 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

Pin Configurations(1,2,3) (con't.)

2942drw04

51 50 48 46 44 42 40 38 36

1357911 13 15

IDT70V06G

G68-1(4)

68-Pin PGA

Top View(5)

ABCDEFGHJKL

47 45 43 41 34

2 4 6 8 10 12 14 16

18 19

49 39 37

A5L

INTL

N/C

SEMLCEL

VCC

OELR/WL

I/O0L N/C

GND GND

I/O0R

VCC N/C

OERR/WR

SEMRCER

GND BUSYR

BUSYLM/SINT

N/C

GND

A1R

INDEX

A4L A2L A0L A3R

A2R A4R A5R

A7R A6R

A9R A8R

A11R A10R

A12R

A0R

A7L A6L A3L A1L

A9L A8L

A11L A10L

A12L

VCC I/O2R I/O3R I/O5R I/O6R

I/O1R I/O4R I/O7R

I/O1L I/O2L I/O4L I/O7L

I/O3L I/O5L I/O6L

A13R

A13L

Left Port Right Port Names

CELCERChip Enable

R/WLR/WRRead/ Write Enable

OELOEROutp ut Enable

A0L - A13L A0R - A13R Address

I/O0L - I/ O7L I/O0R - I/ O7R Data Inp ut/ Outp ut

SEMLSEMRSemaphore Enable

INTLINTRInte rrup t F la g

BUSYLBUSYRBusy Flag

M/SMaster or Slave Select

VCC Power

GND Ground

2 9 42 tb l 01

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Truth Table II: Semaphore Read/Write Control(1)

NOTE:

1. A0L — A13L ≠ A0R — A13R

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.

Inputs(1) Outputs

Mode

CE R/WOE SEM I/O0-7

H X X H Hi gh-Z De s e le c te d : P ower-Down

LLXHDATA

IN Write to Me mory

LHLHDATA

OUT Read Memory

X X H X High-Z Outputs Disabled

2942 tbl 02

Inputs Outputs

Mode

CE R/WOE SEM I/O0-7

HHLLDATA

OUT Read Data in Semaphore Flag

H↑XLDATA

IN Write I/ O0 into Semaphore Flag

LXXL ____ Not All owed

2942 tbl 03

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

Recommended DC Operating

Conditions

Maximum Operating Temperature

and Supply Voltage(1)

Absolute Maximum Ratings(1)

Capacitance (TA = +25°C, f = 1.0MHz)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 0.3V.

NOTE:

1. This is the parameter TA.

NOTES:

1. VIL> -1.5V for pulse width less than 10ns.

2. VTERM must not exceed VCC +0.3V.

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

Symbol Rating Commercial

& Industrial Unit

VTERM(2) Terminal Voltage

with Re s p ec t

to G ND

-0.5 to +4. 6 V

TBIAS Temperature

Und e r B ias -55 to + 125 oC

TSTG Storage

Temperature -55 to +125 oC

IOUT DC Outp u t

Current 50 mA

2942 tbl 04

Grade Amb ient Tem peratur e GND Vcc

Commercial 0OC to + 70OC0V3.3V

+ 0. 3V

Industrial -40OC to + 85OC0V3.3V

+ 0. 3V

2942 tbl 05

Symbol Parameter(1) Conditions Max. Unit

CIN Input Capacitance VIN = 3dV 9 pF

COUT Outp ut Cap acitance VOUT = 3dV 10 pF

2942 tbl 07

Symbol Parameter Min. Typ. Max. Unit

VCC Sup p ly Vo ltag e 3.0 3. 3 3.6 V

GND Ground 0 0 0 V

VIH Inp ut Hi gh Vol tag e 2. 0 ____ VCC+0.3(2) V

VIL Inp ut Lo w Vo ltag e -0. 5(1) ____ 0.8 V

2942 tbl 06

Symbol Parameter Test Conditi ons

70V06S 70V06L

UnitMin. Max. Min. Max.

|ILI| Input Le akag e Current(1) VCC = 3. 6V, VIN = 0V to VCC ___ 10 ___ 5µA

|ILO| Outp ut Le ak age Curre nt VOUT = 0V to VCC ___ 10 ___ 5µA

VOL Outp ut Lo w Voltag e IOL = +4mA ___ 0.4 ___ 0.4 V

VOH Outp ut Hig h Vol tag e IOH = -4mA 2.4 ___ 2.4 ___ V

2942 tbl 08

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VCC = 3.3, TA = +25°C.

3. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of

GND to 3V.

4. f = 0 means no address or control lines change.

70V06X15

Com'l Only 70V06X20

Com'l

& Ind

70V06X25

Com'l

& Ind

Sym bol Param eter Test Conditi on Versio n Typ. (2) Max. Typ.(2) Max. Typ.(2) Max. Unit

ICC Dy nam ic O p e rating

Current

(Both Ports Active)

CE = VIL, Outputs Op en

SEM = VIH

f = fMAX(3)

COM'L S

L150

140 215

185 140

130 200

175 130

125 190

165 mA

IND S

L____

____

____ 140

130 225

195 130

125 210

180 mA

ISB1 Stand by Curre nt

(Bo th Po rts - TTL

Le ve l Inp uts)

CER = CEL = VIH

SEMR = SEML = VIH

f = fMAX(3)

COM'L S

L25

20 35

30 20

15 30

25 16

13 30

25 mA

IND S

L____

____

____ 20

15 45

40 16

13 45

40 mA

ISB2 Stand by Curre nt

(One Po rt - TTL

Le ve l Inp uts)

CEL or CE

R = VIH

Activ e Po rt Outputs Op en,

f=fMAX(3)

COM'L S

L85

80 120

110 80

75 110

100 75

72 110

95 mA

IND S

L____

____

____ 80

75 130

115 75

72 125

110 mA

ISB3 Full Standby Current

(Bo th Po rts -

CM OS L e v e l Inputs )

Bo th P orts CEL and

CER > VCC - 0. 2V,

VIN > VCC - 0. 2V o r

VIN < 0.2V , f = 0(4)

SEMR = SEML > VCC - 0. 2V

COM'L S

L1.0

0.2 5

2.5 1.0

0.2 5

2.5 1.0

0.2 5

2.5 mA

IND S

L____

____

____ 1.0

0.2 15

51.0

0.2 15

5mA

ISB4 Full Standby Current

(One Po rt -

CM OS L e v e l Inputs )

One Port CEL or

CER > VCC - 0. 2V

SEMR = SEML > VCC - 0. 2V

VIN > VCC - 0.2V o r VIN < 0.2V

Activ e Po rt Outputs Op en,

f = fMAX(3)

COM'L S

L85

80 125

105 80

75 115

100 75

70 105

90 mA

IND S

L____

____

____ 80

75 130

115 75

70 120

105 mA

2942 tbl 09a

70V06X35

Com'l

& Ind

70V06X55

Com'l

& Ind

Sym bol Param eter Test Cond ition Versi on Typ. (2) Max. Typ.(2) Max. Unit

ICC Dy namic Operating

Current

(Bo th P orts A c ti ve )

CE = VIL, Outputs Open

SEM = VIH

f = fMAX(3)

COM'L S

L120

115 180

155 120

115 180

155 mA

IND S

L120

115 200

170 120

115 200

170 mA

ISB1 Standb y Current

(Bo th Ports - TTL

Le ve l Inp uts)

CER = CEL = VIH

SEMR = SEML = VIH

f = fMAX(3)

COM'L S

L13

11 25

20 13

11 25

20 mA

IND S

L13

11 40

35 13

11 40

35 mA

ISB2 Standb y Current

(One P ort - TTL

Le ve l Inp uts)

CEL or CER = VIH

Activ e Po rt Outputs Ope n,

f=fMAX(3)

COM'L S

L70

65 100

90 70

65 100

90 mA

IND S

L70

65 120

105 70

65 120

105 mA

ISB3 Full Standb y Current

(Bo th Ports -

CM OS Le v e l Inp u ts )

Bo th P orts CEL and

CER > VCC - 0.2V,

VIN > VCC - 0. 2V o r

VIN < 0.2V , f = 0(4)

SEMR = SEML > VCC - 0. 2V

COM'L S

L1.0

0.2 5

2.5 1.0

0.2 5

2.5 mA

IND S

L1.0

0.2 15

51.0

0.2 15

5mA

ISB4 Full Standb y Current

(One P ort -

CM OS Le v e l Inp u ts )

One Port CEL or

CER > VCC - 0.2V

SEMR = SEML > VCC - 0. 2V

VIN > VCC - 0. 2 V or VIN < 0. 2V

Activ e Po rt Outputs Ope n,

f = fMAX(3)

COM'L S

L65

60 100

85 65

60 100

85 mA

IND S

L65

60 115

100 65

60 115

100 mA

2942 t b l 09b

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions

Timing of Power-Up Power-Down

Figure 2. Output Test Load

(For tLZ, tHZ, tWZ, tOW)

*Including scope and jig.

Figure 1. AC Output Test Load

In p ut P ul s e Le v e l s

In p u t R i s e/ F a l l Ti m es

Inp ut Tim ing Re fe rence Le v e l s

Ou tp ut Refe r e nc e L e ve l s

Outp ut Load

GND to 3. 0V

3ns Max .

1.5V

Fi g ure s 1 and 2

2942 tbl 10 2942 drw 05

590Ω

30pF

435Ω

3.3V

DATAOUT

BUSY

INT

590Ω

5pF*

435Ω

3.3V

DATAOUT

2942 drw 06

tPU

ICC

ISB

tPD

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed but not tested.

3. To access SRAM, CE = VIL, SEM = VIH.

4. 'X' in part number indicates power rating (S or L).

70V06X15

Com'l Only 70V06X20

Com'l

& I nd

70V06X25

Com'l

& I nd

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

tRC Re ad Cy cle Ti me 15 ____ 20 ____ 25 ____ ns

tAA Address Access Time ____ 15 ____ 20 ____ 25 ns

tACE Chip Enab le Acce ss Time(3) ____ 15 ____ 20 ____ 25 ns

tAOE Output Enable Access Time(3) ____ 10 ____ 12 ____ 13 ns

tOH Output Hold from Address Change 3 ____ 3____ 3____ ns

tLZ O u t pu t Low - Z Tim e(1,2) 3____ 3____ 3____ ns

tHZ Outp ut Hig h-Z Time (1,2) ____ 10 ____ 12 ____ 15 ns

tPU Chip E nab l e to P o we r Up Ti me(1,2) 0____ 0____ 0____ ns

tPD Chi p Dis able to Po wer Down Time (1,2) ____ 15 ____ 20 ____ 25 ns

tSOP Semaphore Flag Update Pulse (OE or SEM)10

____ 10 ____ 10 ____ ns

tSAA Semaphore Ad dress Access(3) ____ 15 ____ 20 ____ 25 ns

29 42 tb l 11 a

70V06X35

Com'l

& I nd

70V06X55

Com'l

& I nd

UnitSymbol Parameter Min. Max. Min. Max.

READ CYCLE

tRC Re ad Cy cle Ti me 35 ____ 55 ____ ns

tAA Address Access Time ____ 35 ____ 55 ns

tACE Chip Enab le Acce ss Time(3) ____ 35 ____ 55 ns

tAOE Output Enable Access Time(3) ____ 20 ____ 30 ns

tOH Output Hold from Address Change 3 ____ 3____ ns

tLZ O u t pu t Low - Z Tim e(1,2) 3____ 3____ ns

tHZ Outp ut Hig h-Z Time (1,2) ____ 15 ____ 25 ns

tPU Chip E nab l e to P o we r Up Ti me(1,2) 0____ 0____ ns

tPD Chi p Dis able to Po wer Down Time (1,2) ____ 35 ____ 50 ns

tSOP Semaphore Flag Update Pulse (OE or SEM)15

____ 15 ____ ns

tSAA Semaphore Ad dress Access(3) ____ 35 ____ 55 ns

2 942 tb l 11b

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted las OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

tRC

R/W

ADDR

tAA

2942 drw 07

(4)

tACE(4)

tAOE(4)

(1)

tLZ tOH

(2)

tHZ

(3,4)

tBDD

DATAOUT

BUSYOUT

VALID DATA(4)

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed but not tested.

3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and

temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

Symbol Parameter

70V06X15

Com'l Only 70V06X20

Com'l

& Ind

70V06X25

Com'l

& Ind

UnitMin. Max. Min. Max. Min. Max.

WRI TE CYCLE

tWC Write Cycle Time 15 ____ 20 ____ 25 ____ ns

tEW Chip Enable to End-of-Write(3) 12 ____ 15 ____ 20 ____ ns

tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns

tAS Address Set-up Time (3) 0____ 0____ 0____ ns

tWP Write Pulse Width 12 ____ 15 ____ 20 ____ ns

tWR Write Recovery Time 0 ____ 0____ 0____ ns

tDW Data Val id to E nd -o f-Wri te 10 ____ 15 ____ 15 ____ ns

tHZ Outp ut Hig h-Z Time (1,2) ____ 10 ____ 12 ____ 15 ns

tDH Data Hold Time (4) 0____ 0____ 0____ ns

tWZ Write Enab l e to Outp ut i n Hig h-Z(1,2) ____ 10 ____ 12 ____ 15 ns

tOW Outp ut Ac ti ve from End -o f-W ri te (1,2,4) 0____ 0____ 0____ ns

tSWRD SEM Flag Write to Re ad Tim e 5____ 5____ 5____ ns

tSPS SEM Flag Contention Window 5____ 5____ 5____ ns

2 942 tb l 12 a

Symbol Parameter

70V06X35

Com'l

& Ind

70V06X55

Com'l

& Ind

UnitMin. Max. Min. Max.

WRI TE CYCLE

tWC Write Cycle Time 35 ____ 55 ____ ns

tEW Chip Enable to End-of-Write(3) 30 ____ 45 ____ ns

tAW Address Valid to End-of-Write 30 ____ 45 ____ ns

tAS Address Set-up Time (3) 0____ 0____ ns

tWP Write Pulse Width 25 ____ 40 ____ ns

tWR Write Recovery Time 0 ____ 0____ ns

tDW Data Val id to E nd -o f-Wri te 15 ____ 30 ____ ns

tHZ Outp ut Hig h-Z Time (1,2) ____ 15 ____ 25 ns

tDH Data Hold Time (4) 0____ 0____ ns

tWZ Write Enab l e to Outp ut i n Hig h-Z(1,2) ____ 15 ____ 25 ns

tOW Outp ut Ac ti ve from End -o f-W ri te (1,2,4) 0____ 0____ ns

tSWRD SEM Flag Write to Re ad Tim e 5____ 5____ ns

tSPS SEM Flag Contention Window 5____ 5____ ns

2942 tbl 12b

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, or R/W.

7. Timing depends on which enable signal is de-asserted first, CE, or R/W.

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the

bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

9. To access SRAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

R/W

tWC

tHZ

tAW

tWR

tAS tWP

DATAOUT

(2)

tWZ

tDW tDH

tOW

ADDRESS

DATAIN

CE or SEM

(6)

(4) (4)

(3)

2942 drw 08

(7)

(9)

2942 drw 09

tWC

tAS tWR

tDW tDH

ADDRESS

DATAIN

CE or SEM

R/W

tAW

tEW (3)

(2)

(6)

(9)

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. “DATAOUT VALID” represents all I/O's (I/O0 - I/O7) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention(1,3,4)

SEM"A"

2942 drw 11

tSPS

MATCH

R/W"A"

MATCH

A0"A"-A2"A"

SIDE "A"

(2)

SEM"B"

R/W"B"

A0"B"-A2"B"

SIDE "B"

(2)

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. “A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.

4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

SEM

2942 drw 10

tAW tEW

tSOP

DATA0

VALID ADDRESS

tSAA

R/W

tWR

tOH

tACE

VALID ADDRESS

DATAIN VALID DATA OUT

tDW

tWP tDH

tAS

tSWRD tAOE

tSOP

Read Cycle

Write Cycle

A0-A2

VALID(2)

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6)

NOTES:

1 . Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH) or "Timing Waveform of Write With

Port-To-Port Delay (M/S=VIL)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited during contention.

5. To ensure that a write cycle is completed after contention.

6. "X" is part numbers indicates power rating (S or L).

70V06X15

Com 'l Ony 70V06X20

Com'l

& Ind

70V06X25

Com'l

& Ind

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

BUSY TIMI NG (M/S = VIH)

tBAA BUSY Acce ss Time from Address Match ____ 15 ____ 20 ____ 20 ns

tBDA BUSY Disable Time fro m Address Not Matched ____ 15 ____ 20 ____ 20 ns

tBAC BUSY Acce ss Time fro m Chip Enable LOW ____ 15 ____ 20 ____ 20 ns

tBDC BUSY Disab l e Time fro m Chi p E nab l e HIGH ____ 15 ____ 17 ____ 17 ns

tAPS Arbitration Priority Set-up Time (2) 5____ 5____ 5____ ns

tBDD BUSY Disable to Valid Data(3) ____ 18 ____ 30 ____ 30 ns

tWH Write Hold Afte r BUSY(5) 12 ____ 15 ____ 17 ____ ns

BUSY TIMI NG (M/S = VIL)

tWB BUSY Inp ut to Wri te (4) 0____ 0____ 0____ ns

tWH Write Hold Afte r BUSY(5) 12 ____ 15 ____ 17 ____ ns

PORT -TO-P ORT DEL AY T I MI NG

tWDD Write P ulse to Data Delay(1) ____ 30 ____ 45 ____ 50 ns

tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 35 ____ 35 ns

2 942 tb l 13 a

70V06X35

Com'l

& Ind

70V06X55

Com'l

& Ind

Symbol Parameter Min. Max. Min. Max. Unit

BUSY TIMI NG (M/S = VIH)

tBAA BUSY Acce ss Time from Address Match ____ 20 ____ 45 ns

tBDA BUSY Disable Time fro m Address Not Matched ____ 20 ____ 40 ns

tBAC BUSY Acce ss Time fro m Chip Enable LOW ____ 20 ____ 40 ns

tBDC BUSY Disab l e Time fro m Chi p E nab l e HIGH ____ 20 ____ 35 ns

tAPS Arbitration Priority Set-up Time (2) 5____ 5____ ns

tBDD BUSY Disable to Valid Data(3) ____ 35 ____ 40 ns

tWH Write Hold Afte r BUSY(5) 25 ____ 25 ____ ns

BUSY TIMI NG (M/S = VIL)

tWB BUSY Inp ut to Wri te (4) 0____ 0____ ns

tWH Write Hold Afte r BUSY(5) 25 ____ 25 ____ ns

PORT -TO-P ORT DEL AY T I MI NG

tWDD Write P ulse to Data Delay(1) ____ 60 ____ 80 ns

tDDD Write Data Valid to Read Data Delay (1) ____ 45 ____ 65 ns

2942 tbl 13b

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

2942 drw 12

tDW

tAPS

ADDR"A"

tWC

DATAOUT "B"

MATCH

tWP

R/W"A"

DATAIN "A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD (3)

tWDD

tBAA

Timing Waveform of Write with Port-To-Port Read and BUSY(2,4,5)

(M/S = VIH)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. If M/S = VIL(slave) then BUSY is input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.

5. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the port opposite from Port "A".

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(1) (M/S = VIH)

Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)

NOTES:

1. tWH must be met for both BUSY input (slave) output master.

2. BUSY is asserted on Port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.

3. tWB is only for the slave version.

2942 drw 13

R/W"A"

BUSY"B"

tWP

tWB(3)

R/W"B"

tWH(1)

(2)

2942 drw 14

ADDR"A"

and "B" ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS

tBAC tBDC

(2)

2942 drw 15

ADDR"A" ADDRESS "N"

ADDR"B"

BUSY"B"

tAPS

tBAA tBDA

(2)

MATCHING ADDRESS "N"

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTE:

1. 'X' in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

70V06X15

Com'l Only 70V06X20

Com'l

& I nd

70V06X25

Com'l

& I nd

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

tAS Address Set-up Time 0 ____ 0____ 0____ ns

tWR Write Re co ve ry Tim e 0 ____ 0____ 0____ ns

tINS Inte rrupt Se t Time ____ 15 ____ 20 ____ 20 ns

tINR Inte rrupt Re se t Time ____ 15 ____ 20 ____ 20 ns

2 942 tb l 14a

2942 drw 16

ADDR"A" INTERRUPT SET ADDRESS

CE"A"

R/W"A"

tAS

tWC

tWR

(3) (4)

tINS(3)

INT"B"

(2)

70V06X35

Com'l

& I nd

70V06X55

Com'l

& I nd

Symbol Parameter Min. Max. Min. Max. Unit

INTERRUPT TIMING

tAS Address Set-up Time 0 ____ 0____ ns

tWR Write Re co ve ry Tim e 0 ____ 0____ ns

tINS Inte rrupt Se t Time ____ 25 ____ 40 ns

tINR Inte rrupt Re se t Time ____ 25 ____ 40 ns

2942 tbl 14b

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table III  Interrupt Flag(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

Waveform of Interrupt Timing(1) (con't.)

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

2942 drw 17

ADDR"B" INTERRUPT CLEAR ADDRESS

CE"B"

OE"B"

tAS

tRC

(3)

tINR(3)

INT"B"

(2)

Left Port Right P ort

FunctionR/WLCE

LOELA13L-A0L INTLR/WRCE

ROERA13R-A0R INTR

L LX 3FFFXXXX X L

(2) S e t Ri g ht INTR Flag

XXX X XX L L 3FFF H

(3) Res e t Ri g ht INTR Flag

XXX X L

(3) LLX3FFEXSet Left INTL Flag

XLL3FFE H

(2) X X X X X Res et Le ft INTL Flag

2942 tbl 15

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table IV  Address BUSY

Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V06 are push

pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.

2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable

inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when

BUSYR outputs are driving LOW regardless of actual logic level on the pin.

Truth Table V  Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V06.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0 - I/O7). These eight semaphores are addressed by A0 -A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Functional Description

The IDT70V06 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70V06 has an automatic power down

feature controlled by CE. The CE controls on-chip power down circuitry

that permits the respective port to go into a standby mode when not

selected (CE = VIH). When a port is enabled, access to the entire

memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is set when the right port writes to memory location 3FFE

(HEX). The left port clears the interrupt by reading address location 3FFE.

Likewise, the right port interrupt flag (INTR) is set when the left port writes

to memory location 3FFF (HEX) and to clear the interrupt flag (INTR), the

right port must read the memory location 3FFF. The message (8 bits) at

3FFE or 3FFF is user-defined. If the interrupt function is not used, address

locations 3FFE and 3FFF are not used as mail boxes, but as part of the

random access memory. Refer to Truth Table III for the interrupt

operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

SRAM have accessed the same location at the same time. It also

Inputs Outputs

Function

CELCERA13L-A0L

A13R-A0R BUSYL(1) BUSYR(1)

XXNO MATCH H H Normal

HX MATCH H H Normal

XH MATCH H H Normal

L L MATCH (2) (2) Write Inhi b it(3)

2 9 42 tb l 16

Functions D0 - D7 Left D0 - D7 Righ t Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

2942 tbl 17

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V06 SRAMs.

enough for a BUSY flag to be output from the master before the actual write

pulse can be initiated with the R/W signal. Failure to observe this timing

can result in a glitched internal write inhibit signal and corrupted data in the

slave.

Semaphores

The IDT70V06 is an extremely fast Dual-Port 16K x 8 CMOS Static

RAM with an additional 8 address locations dedicated to binary

semaphore flags. These flags allow either processor on the left or right

side of the Dual-Port SRAM to claim a privilege over the other processor

for functions defined by the system designer’s software. As an ex-

ample, the semaphore can be used by one processor to inhibit the

other from accessing a portion of the Dual-Port SRAM or any other shared

resource.

The Dual-Port SRAM features a fast access time, and both ports

are completely independent of each other. This means that the activity

on the left port in no way slows the access time of the right port. Both

ports are identical in function to standard CMOS Static RAM and can

be read from, or written to, at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port SRAM. These devices have an automatic power-

down feature controlled by CE, the Dual-Port SRAM enable, and SEM,

the semaphore enable. The CE and SEM pins control on-chip power

down circuitry that permits the respective port to go into standby mode

when not selected. This is the condition which is shown in Truth Table

I where CE and SEM are both HIGH.

Systems which can best use the IDT70V06 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT70V06's

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V06 does not use its semaphore flags

allows one of the two accesses to proceed and signals the other side that

the SRAM is “busy”. The BUSY pin can then be used to stall the access

until the operation on the other side is completed. If a write operation has

been attempted from the side that receives a BUSY indication, the write

signal is gated internally to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of an

illegal or illogical operation. If the write inhibit function of BUSY logic is not

desirable, the BUSY logic can be disabled by placing the part in slave mode

with the M/S pin. Once in slave mode the BUSY pin operates solely as

a pin. Normal operation can be programmed by tying the BUSY pins HIGH.

If desired, unintended write operations can be prevented to a port by tying

the BUSY pin for that port LOW.

The BUSY outputs on the IDT 70V06 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the busy indication

for the resulting array requires the use of an external AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70V06 SRAM array in width while using

BUSY logic, one master part is used to decide which side of the SRAM array

will receive a BUSY indication, and to output that indication. Any number

of slaves to be addressed in the same address range as the master use

the BUSY signal as a write inhibit signal. Thus on the IDT70V06 RAM the

BUSY pin is an output if the part is used as a master (M/S pin = VIH), and

the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown

in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for part of

the other word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid long

2942 drw 18

MASTER

Dual Port

SRAM

BUSY (L) BUSY (R)

MASTER

Dual Port

SRAM

BUSY (L) BUSY (R)

SLAVE

Dual Port

SRAM

BUSY (L) BUSY (R)

SLAVE

Dual Port

SRAM

BUSY (L) BUSY (R)

DECODER

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

to control any resources through hardware, thus allowing the system

designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port SRAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that a

shared resource is in use. If the left processor wants to use this

resource, it requests the token by setting the latch. This processor then

verifies its success in setting the latch by reading it. If it was successful,

it assumes control over the shared resource. If it was not successful

in setting the latch, it determines that the right side processor has set

the latch first, has the token and is using the shared resource. The left

processor can then either repeatedly request that semaphore’s status

or remove its request for that semaphore to perform another task and

occasionally attempt again to gain control of the token via the set and

test sequence. Once the right side has relinquished the token, the left

side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

The eight semaphore flags reside within the IDT70V06 in a

separate memory space from the Dual-Port SRAM. This address

space is accessed by placing a LOW input on the SEM pin (which

acts as a chip select for the semaphore flags) and using the other

control pins (Address, OE, and R/W) as they would be used in

accessing a standard Static RAM. Each of the flags has a unique

address which can be accessed by either side through address pins

A0 – A2. When accessing the semaphores, none of the other address

pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level

is written into an unused semaphore location, that flag will be set to a

zero on that side and a one on the other side (see Truth Table V). That

semaphore can now only be modified by the side showing the zero.

When a one is written into the same location from the same side, the

flag will be set to a one for both sides (unless a semaphore request

from the other side is pending) and then can be written to by both sides.

The fact that the side which is able to write a zero into a semaphore

subsequently locks out writes from the other side is what makes

semaphore flags useful in interprocessor communications. (A thor-

ough discussion on the use of this feature follows shortly.) A zero

written into the same location from the other side will be stored in the

semaphore request latch for that side until the semaphore is freed by

the first side.

When a semaphore flag is read, its value is spread into all data bits

so that a flag that is a one reads as a one in all data bits and a flag

containing a zero reads as all zeros. The read value is latched into one

side’s output register when that side's semaphore select (SEM) and

output enable (OE) signals go active. This serves to disallow

the semaphore from changing state in the middle of a read cycle

due to a write cycle from the other side. Because of this latch, a repeated

read of a semaphore in a test loop must cause either signal (SEM or OE)

to go inactive or the output will never change.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Table V). As an example, assume a processor

writes a zero to the left port at a free semaphore location. On a

subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side during

subsequent read. Had a sequence of READ/WRITE been used

instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag LOW and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first side’s request latch. The

second side’s flag will now stay LOW until its semaphore request latch

is written to a one. From this it is easy to understand that, if a

semaphore is requested and the processor which requested it no

longer needs the resource, the entire system can hang up until a one

is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making

the request, the first side to make the request will receive the token. If

both requests arrive at the same time, the assignment will be arbitrarily

made to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is

secure. As with any powerful programming technique, if semaphores

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any sema-

phore request flag which contains a zero must be reset to a one, all

semaphores on both sides should have a one written into them at

initialization from both sides to assure that they will be free when

needed.

6.42

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Using SemaphoresSome Examples

Perhaps the simplest application of semaphores is their application as

resource markers for the IDT70V06’s Dual-Port SRAM. Say the 16K x

8 SRAM was to be divided into two 8K x 8 blocks which were to be

dedicated at any one time to servicing either the left or right port. Semaphore

0 could be used to indicate the side which would control the lower section

of memory, and Semaphore 1 could be defined as the indicator for the

upper section of memory.

To take a resource, in this example the lower 8K of Dual-Port

SRAM, the processor on the left port could write and then read a zero in

to Semaphore 0. If this task were successfully completed (a zero was read

back rather than a one), the left processor would assume control of the

lower 8K. Meanwhile the right processor was attempting to gain control of

the resource after the left processor, it would read back a one in response

to the zero it had attempted to write into Semaphore 0. At this point, the

software could choose to try and gain control of the second 8K section by

writing, then reading a zero into Semaphore 1. If it succeeded in gaining

control, it would lock out the left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could

undo its semaphore request and perform other tasks until it was able

to write, then read a zero into Semaphore 1. If the right processor

performs a similar task with Semaphore 0, this protocol would allow the

two processors to swap 8K blocks of Dual-Port SRAM with each other.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the

2942 drw 19

WRITE D0

QWRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT RPORT

SEMAPHORE

READ SEMAPHORE

READ

Figure 4. IDT70V06 Semaphore Logic

Dual-Port SRAM or other shared resources into eight parts. Semaphores

can even be assigned different meanings on different sides rather than

being given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory

during a transfer and the I/O device cannot tolerate any wait states.

With the use of semaphores, once the two devices has determined

which memory area was “off-limits” to the CPU, both the CPU and the

I/O devices could access their assigned portions of memory continu-

ously without any wait states.

Semaphores are also useful in applications where no memory

“WAIT” state is available on one or both sides. Once a semaphore

handshake has been performed, both processors can access their

assigned SRAM segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one

processor may be responsible for building and updating a data

structure. The other processor then reads and interprets that data

structure. If the interpreting processor reads an incomplete data

structure, a major error condition may exist. Therefore, some sort of

arbitration must be used between the two different processors. The

building processor arbitrates for the block, locks it and then is able to

go in and update the data structure. When the update is completed, the

data structure block is released. This allows the interpreting processor

to come back and read the complete data structure, thereby guaran-

teeing a consistent data structure.

IDT70V06S/L

High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

2942 drw 20

Power

999

Speed

Package

Process/

Temperature

Range

Blank

I(1) Commercial (0°Cto+70

°C)

Industrial (-40°Cto+85

°C)

64-pin TQFP (PN64-1)

68-pin PGA (G68-1)

68-pin PLCC (J68-1)

LStandard Power

Low Power

XXXXX

Device

Type

128K (16K x 8) 3.3V Dual-Port RAM70V06

IDT

Speed in Nanoseconds

Commercial Only

Commercial & Industrial

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6166 831-754-4613

Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

3/10/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 and 3 Added additional notes to pin configurations

6/9/99: Changed drawing format

11/10/99: Replaced IDT logo

3/10/00: Added 15 & 20ns speed grades

Upgraded DC parameters

Added Industrial Temperature information

Changed ±200mV to 0mV