CYP15G0401DXB
CYV15G0401DXB
Quad HOTLink II™ Transceiver
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-02002 Rev. *N Revised August 18, 201 1
Features
■Second-generation HOTLink® technology
❐Compliant to multiple standards
—ESCON, DVB-ASI, fibre channel and gigabit ethernet
(IEEE802.3z)
—CPRI™ compliant
—CYV15G0401DXB compliant to SMPTE 259M and
SMPTE 292M
—8 B/10 B encoded or 10-bit unencoded data
■Quad channel transceiver operates from 195 to 1500 MBaud
serial data rate
❐Aggregate throughput of 12 GB per second
■Selectable parity check/generate
■Selectable multi-channel bonding options
❐Four 8-bit channels
❐Two 16-bit channels
❐One 32-bit channel
❐N × 32-bit channel support (inter-chip)
■Skew alignment support for multiple bytes of offset
■Selectable input/output clocking options
■MultiFrame™ receive framer
❐Bit and byte alignment
❐Comma or full K28.5 detect
❐Single- or multi-byte framer for byte alignmen t
❐Low-latency option
■Synchronous LVTTL parallel interface
■Optional elasticity buffer in receive path
■Optional phase align buffer in transmit path
■Internal phase-locked loops (PLLs) with no external PLL
components
■Dual differential PECL-compatible serial inputs per channel
❐Internal DC-restoration
■Dual differential PECL-compatible serial outputs per channel
❐Source matched for 50 Ω transmission lines
❐No external bias resistors required
❐Signaling-rate controlled edge-rates
■Compatible with
❐Fiber-optic modules
❐Copper cables
❐Circuit board traces
■JTAG boundary scan
■Built-in self-test (BIST) for at-speed link testing
■Per-channel link quality indicator
❐Analog signal detect
❐Digital signal detect
■Low power 2.5 W at 3.3 V typical
■Single 3.3 V supply
■256-ball thermally enhanced BGA
■Pb-free package option available
■0.25 μ BiCMOS technology
Functional Description
The CYP(V)15G0401DXB[1] Quad HOTLink II™ Transceiver
is a point-to-point or point-to-multipoint communications
building block allowing the transfer of data over high-speed
serial links (optical fiber, balanced, and unbalanced copper
transmission lines) at signaling speeds ranging from
195-to-1500 MBaud per serial link.
Figure 1. HOTLink II System Connections
Note
1. CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M complian t devices. CYP15G0401DXB refers to d evices not compliant to SMPTE 259M and SMPTE
292M pathological test requirements.
System Host
Serial Links
10
10
10
10
10
10
10
10
System Host
10
10
10
10
10
10
10
10
Serial Links
Serial Links
Serial Links
Backplane or
Cabled
Connections
CYP(V)15G0401DXB
CYP(V)15G0401DXB
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 2 of 55
Contents
CYP(V)15G0401DXB Transceiver
Logic Block Diagram .............. .. .............. ... ... .............. ... ...4
Transmit Path Block Diagram .........................................5
Receive Path Block Diagram ...... ... ................. .................6
Pin Configuration (Top View) ...........................................7
Pin Configuration (Bottom View) ......................................8
Pin Descriptions ...............................................................9
CYP(V)15G0401DXB HOTLink II Operation ..................1 6
CYP(V)15G0401DXB Transmit Data Path ................16
Transmit Modes .............. ... .. .............. ... .............. ... ... .18
Transmit BIST .. .............. ... .............. .. ... .............. ... ....20
Serial Output Drivers .................................................22
Transmit PLL Clock Multiplier ....................................2 2
CYP(V)15G0401DXB Receive Data Path .......................22
Serial Line Receivers ................................................22
Signal Detect/Link Fault ......... ... ... .............. ... .. ..........23
Clock/Data Recovery .................................................24
Deserializer/Framer ................................................... 24
Receive BIST Operation ............................................25
Receive Elasticity Buffer ............................................26
Receive Modes ..........................................................2 6
Power Control .............. ... ... .............. .. .............. ... ... ....28
Output Bus ................................................................28
Parity Generation ......................................................29
Receive Synchronization State Machine
when Channel Bonding is enabled 30
JTAG Support ............................................................33
Maximum Ratings ...........................................................35
Power-up Requirements ............................................35
CYP(V)15G0401DXB DC Electrical Characteristics
Over the Operating Range ...............................................35
Test Loads and Waveforms ..........................................36
CYP(V)15G0401DXB AC Characteristics
Over the Operating Range ...............................................37
Ordering Information ......................................................51
Ordering Code Definitions .........................................51
Package Diagram ...........................................................52
Acronyms ........................................................................ 52
Document Conventions ............ .............. ... .. .............. ...52
Document History Page ..................... .............. ... ...........53
Sales, Solutions, and Legal Information ......................55
Worldwide Sales and Design Support .......................55
Products .................................................................... 55
PSoC Solutions .......................... ... ... .............. ... ... .....55
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 3 of 55
The CYV15G0401DXB satisfies the SMPTE 259M and SMPTE
292M compliance as per the EG34 -1999 Pathological Test
Requirements.
The multiple channels in each device may be combined to allow
transport of wide buses across significant distances with minimal
concern for offsets in clock phase or link delay. Each transmit
channel accepts parallel characters in an Input Register,
encodes each character for transport, and converts it to serial
data. Each receive channel accepts serial data and converts it to
parallel data, decodes the data into characters, and presents
these characters to an Output Register. Figure 1 illustrates
typical connections between independent host systems and
corresponding CYP15G0401DXB parts.
As a second-generation HOTLink device, the
CYP(V)15G0401DXB extends the HOTLink famil y with
enhanced levels of integration and faster data rates, while
maintaining serial-link compatibility (data, command, and BIST)
with other HOTLink devices. The transmit (TX) section of the
CYP(V)15G0401DXB Quad HOTLink II consists of four
byte-wide channels that can be operated independently or
bonded to form wider buses. Each channel can accept either
eight-bit data characters or pre-encoded 10-bit transmission
characters. Data characters are passed from the T ransmit Input
Register to an embedded 8B/10B Encoder to improve their serial
transmission characteristics. These encoded characters are
then serialized and output from dual Positive ECL
(PECL)-compatible differential transmission-line drivers at a
bit-rate of either 10- or 20-times the input referen c e clock.
The receive (RX) section of the CYP(V)15G0401DXB Quad
HOTLink II consists of four byte-wide channels that can be
operated independently or synchronously bonded for greater
bandwidth. Each channel accepts a serial bit-stream from one of
two PECL-compatible differential line receivers and, using a
completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. Each
recovered serial stream is deserialized and framed into
characters, 8B/10B decoded, and checked for transmission
errors. Recovered decoded characters are then written to an
internal Elasticity Buffer, and presented to the destination host
system. The integrated 8B/10B Encoder/Decoder may be
bypassed for systems that present externally encoded or
scrambled data at the parallel interface.
For those systems using buses wider than a single byte, the four
independent receive paths can be bonde d together to allow
synchronous delivery of data across a two-byte-wide (16-bit)
path, or across all four bytes (32-bit). Multiple
CYP(V)15G0401DXB devices may be bonded together to
provide synchronous transport of buses wider than 32 bits.
The parallel I/O interface may be configured for numerous forms
of clocking to provide the highest flexibility in system archi-
tecture. In addition to clocking the transmit path, the receive
interface may be configured to present data relative to a
recovered clock or to a local reference clock.
Each transmit and receive channel contains an independent
BIST pattern generator and checker . This BIST hardware allows
at-speed testing of the high-speed serial data paths in each
transmit and receive section, and across the interconnecting
links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include
interconnecting backplanes on switches, routers, servers and
video transmission systems.
The CYV15G0401DXB is verified by testing to be compliant to
all the pathological test patterns documented in SMPTE
EG34-1999, for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
1. Repetitions of 20 ones and 20 zero s.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros followed
by 1 one.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 4 of 55
CYP(V)15G0401DXB Transceiver Logic Block Diagram
Serializer
Phase
Encoder
8B/10B Decoder
8B/10B
Framer
Deserializer
TX RX
Serializer
Encoder
8B/10B Decoder
8B/10B
Framer
Deserializer
TX RX
Serializer
Encoder
8B/10B Decoder
8B/10B
Framer
Deserializer
TX RX
Serializer
Encoder
8B/10B Decoder
8B/10B
Framer
Deserializer
TX RX
TXDA[7:0]
RXDA[7:0]
TXDB[7:0]
RXDB[7:0]
TXDC[7:0]
RXDC[7:0]
TXDD[7:0]
RXDD[7:0]
OUTA1
±
OUTA2
±
INA1
±
INA2
±
OUTB1
±
OUTB2
±
INB1
±
INB2
±
OUTC1
±
OUTC2
±
INC1
±
INC2
±
OUTD1
±
OUTD2
±
IND1
±
IND2
±
Align
Buffer
Phase
Align
Buffer
Phase
Align
Buffer
Phase
Align
Buffer
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
Elasticity
Buffer
TXCTA[1:0]
RXSTA[2:0]
TXCTB[1:0]
RXSTB[2:0]
TXCTC[1:0]
RXSTC[2:0]
TXCTD[1:0]
RXSTD[2:0]
x11x11x11
x10 x11 x10 x10 x10
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 5 of 55
TXRATE
Character-Rate Clock
Bit-rate Clock
HML
TXCLKA
HML
HML
TXCLKB
TXCLKC
8
TXCTA[1:0]
TXDA[7:0]
TXOPA
Input
Register
8
TXCTB[1:0]
TXDB[7:0]
TXOPB
Input
Register
8
TXCTC[1:0]
TXDC[7:0]
TXOPC
Input
Register
TXPERA
TXPERB
2
2
2
TXPERC
HML
TXCLKD
8
TXCTD[1:0]
TXDD[7:0]
TXOPD
Input
Register
11
TXPERD
Phase-align
Buffer Phase-align
Buffer Phase-align
Buffer Phase-align
Buffer
SCSEL
11
11
12
Parity
Check
BIST LFSR
8B/10B
12
11
Parity
Check
BIST LFSR
8B/10B
12
12
Parity
Check
BIST LFSR
8B/10B
12
11
Parity
Check
BIST LFSR
8B/10B
12
11
Shifter
10
10
Shifter
Shifter
10
10
Shifter
OUTA1+
OUTA1–
OUTA2+
OUTA2–
TXLBA
OUTB1+
OUTB1–
OUTB2+
OUTB2–
TXLBB
OUTC1+
OUTC1–
OUTC2+
OUTC2–
TXLBC
OUTD1+
OUTD1–
OUTD2–
TXLBD
Character-Rate Clock
SPDSEL
TXRST
TXMODE[1:0]
PARCTL Parity Control
REFCLK+
REFCLK–
Transmit PLL
Clock Multiplier
Transmit
Mode
TXCLKO+
TXCLKO–
TXCKSEL
2
Transmit Path Block Diagram
BISTLE
OELE
= Internal Signal
BIST Enable
Latch
Output
Enable
4
8
Latch
BOE[7:0]
RBIST[D:A]
OUTD2+
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 6 of 55
INA1+
INA1–
INA2+
INA2–
INSELA
TXLBA
INB1+
INB1–
INB2+
INB2–
INSELB
TXLBB
INC1+
INC1–
INC2+
INC2–
INSELC
TXLBC
IND1+
IND1–
IND2+
IND2–
INSELD
TXLBD
Character-Rate Clock
Clock &
Data
Recovery
PLL
Shifter
Clock &
Data
Recovery
PLL
Shifter
Clock &
Data
Recovery
PLL
Shifter
Clock &
Data
Recovery
PLL
Shifter
LPEN
LFID
LFIC
LFIB
LFIA
8
RXSTC[2:0]
RXDC[7:0]
RXOPC
3
8
RXSTB[2:0]
RXDB[7:0]
RXOPB
3
8
RXSTD[2:0]
RXDD[7:0]
RXOPD
3
8
RXSTA[2:0]
RXDA[7:0]
RXOPA
3
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
Output
Register
Output
Register
Output
Register
Output
Register
Elasticity
Buffer
Framer
RXCLKD+
RXCLKD–
10B/8B
BIST
Elasticity
Buffer
10B/8B
BIST
Framer
Elasticity
Buffer
10B/8B
BIST
Framer
Elasticity
Buffer
10B/8B
BIST
Framer
Parity Control
÷2
RXCLKC+
RXCLKC–
÷2
RXCLKB+
RXCLKB–
÷2
RXCLKA+
RXCLKA–
÷2
RXRATE
FRAMCHAR
RFMODE
RFEN
RXMODE[1:0]
SDASEL
JTAG
Boundary
Scan
Controller TDO
TMS
TCLK
TDI
Clock
Select
Clock
Select
Clock
Select
Clock
Select
Bonding
Control BOND_ALL
BONDST
BOND_INH
RXCKSEL
TRSTZ
2
2
DECMODE MASTER
Receive Path Block Diagram = Internal Signal
RBIST[D:A]
RX PLL Enable
Latch
RXLE
BOE[7:0]
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 7 of 55
Pin Configuration (Top View)[2]
12345678910 11 12 13 14 15 16 17 18 19 20
AINC1- OUT
C1- INC2- OUT
C2- VCC IND1- OUT
D1- GND IND2- OUT
D2- INA1- OUT
A1- GND INA2- OUT
A2- VCC INB1- OUT
B1- INB2- OUT
B2-
BINC1+ OUT
C1+ INC2+ OUT
C2+ VCC IND1+ OUT
D1+ GND IND2+ OUT
D2+ INA1+ OUT
A1+ GND INA2+ OUT
A2+ VCC INB1+ OUT
B1+ INB2+ OUT
B2+
CTDI TMS INSELC INSELB VCC PAR
CTL SDA
SEL GND BOE[7] BOE[5] BOE[3] BOE[1] GND TX
MODE
[0]
RX
MODE
[0]
VCC TX
RATE RX
RATE LPEN TDO
DTCLK TRSTZ INSELD INSELA VCC RF
MODE SPD
SEL GND BOE[6] BOE[4] BOE[2] BOE[0] GND TX
MODE
[1]
RX
MODE
[1]
VCC BOND
INH RXLE RFEN MAS
TER
EVCC VCC VCC VCC VCC VCC VCC VCC
FTXPER
CTXOP
CTXDC
[0] RXCK
SEL BISTLE RXSTB
[1] RXOPB RXSTB
[0]
GTXDC
[7] TXCK
SEL TXDC
[4] TXDC
[1] DEC
MODE OELE FRAM
CHAR RXDB
[1]
HGNDGNDGNDGND GND GND GND GND
JTXCTC
[1] TXDC
[5] TXDC
[2] TXDC
[3] RXSTB
[2] RXDB
[0] RXDB
[5] RXDB
[2]
KRXDC
[2] RXCLK
C– TXCTC
[0] LFIC RXDB
[3] RXDB
[4] RXDB
[7] RXCLK
B+
LRXDC
[3] RXCLK
C+ TXCLK
CTXDC
[6] RXDB
[6] LFIB RXCLK
B– TXDB
[6]
MRXDC
[4] RXDC
[5] RXDC
[7] RXDC
[6] TXCTB
[1] TXCTB
[0] TXDB
[7] TXCLK
B
NGNDGNDGNDGND GND GND GND GND
PRXDC
[1] RXDC
[0] RXSTC
[0] RXSTC
[1] TXDB
[5] TXDB
[4] TXDB
[3] TXDB
[2]
RRXSTC
[2] RXOP
CTXPER
DTXOP
DTXDB
[1] TXDB
[0] TXOP
BTXPER
B
TVCC VCC VCC VCC VCC VCC VCC VCC
UTXDD
[0] TXDD
[1] TXDD
[2] TXCTD
[1] VCC RXDD
[2] RXDD
[1] GND RX
OPD BOND
_ALL REF
CLK- TXDA
[1] GND TXDA
[4] TXCTA
[0] VCC RXDA
[2] RXOPA RXSTA
[2] RXSTA
[1]
VTXDD
[3] TXDD
[4] TXCTD
[0] RXDD
[6] VCC RXDD
[3] RXSTD
[0] GND RXSTD
[2] BOND
ST[0] REF
CLK+ BOND
ST[1] GND TXDA
[3] TXDA
[7] VCC RXDA
[7] RXDA
[3] RXDA
[0] RXSTA
[0]
WTXDD
[5] TXDD
[7] LFID RXCLK
D– VCC RXDD
[4] RXSTD
[1] GND TXCLK
O- TXRST TXOPA SCSEL GND TXDA
[2] TXDA
[6] VCC LFIA RXCLK
A- RXDA
[4] RXDA
[1]
YTXDD
[6] TXCLK
DRXDD
[7] RXCLK
D+ VCC RXDD
[5] RXDD
[0] GND TXCLK
O+ N/C TXCLK
ATXPER
AGND TXDA
[0] TXDA
[5] VCC TXCTA
[1] RXCLK
A+ RXDA
[6] RXDA[
5]
Note
2. N/C = Do Not Connect
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 8 of 55
Pin Configuration (Bottom View)[3]
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
OUT
B2- INB2- OUT
B1- INB1- VCC OUT
A2- INA2- GND OUT
A1- INA1- OUT
D2- IND2- GND OUT
D1- IND1- VCC OUT
C2- INC2- OUT
C1- INC1- A
OUT
B2+ INB2+ OUT
B1+ INB1+ VCC OUT
A2+ INA2+ GND OUT
A1+ INA1+ OUT
D2+ IND2+ GND OUT
D1+ IND1+ VCC OUT
C2+ INC2+ OUT
C1+ INC1+ B
TDO LPEN RX
RATE TX
RATE VCC RX
MODE
[0]
TX
MODE
[0]
GND BOE[1] BOE[3] BOE[5] BOE[7] GND SDA
SEL PAR
CTL VCC INSELB INSELC TMS TDI C
MAS
TER RFEN RXLE BOND
INH VCC RX
MODE
[1]
TX
MODE
[1]
GND BOE[0] BOE[2] BOE[4] BOE[6] GND SPD
SEL RF
MODE VCC INSELA INSELD TRSTZ TCLK D
VCC VCC VCC VCC VCC VCC VCC VCC E
RXSTB
[0] RXOP
BRXSTB
[1] BISTLE RXCK
SEL TXDC
[0] TXOP
CTXPER
CF
RXDB
[1] FRAM
CHAR OELE DEC
MODE TXDC
[1] TXDC
[4] TXCK
SEL TXDC
[7] G
GND GND GND GND GND GND GND GND H
RXDB
[2] RXDB
[5] RXDB
[0] RXSTB
[2] TXDC
[3] TXDC
[2] TXDC
[5] TXCTC
[1] J
RXCLK
B+ RXDB
[7] RXDB
[4] RXDB
[3] LFIC TXCTC
[0] RXCLK
C- RXDC
[2] K
TXDB
[6] RXCLK
B- LFIB RXDB
[6] TXDC
[6] TXCLK
CRXCLK
C+ RXDC
[3] L
TXCLK
BTXDB
[7] TXCTB
[0] TXCTB
[1] RXDC
[6] RXDC
[7] RXDC
[5] RXDC
[4] M
GND GND GND GND GND GND GND GND N
TXDB
[2] TXDB
[3] TXDB
[4] TXDB
[5] RXSTC
[1] RXSTC
[0] RXDC
[0] RXDC
[1] P
TXPER
BTXOP
BTXDB
[0] TXDB
[1] TXOP
DTXPER
DRXOP
CRXSTC
[2] R
VCC VCC VCC VCC VCC VCC VCC VCC T
RXSTA
[1] RXSTA
[2] RXOPA RXDA
[2] VCC TXCTA
[0] TXDA
[4] GND TXDA
[1] REF
CLK- BOND
_ALL RXOP
DGND RXDD
[1] RXDD
[2] VCC TXCTD
[1] TXDD
[2] TXDD
[1] TXDD
[0] U
RXSTA
[0] RXDA
[0] RXDA
[3] RXDA
[7] VCC TXDA
[7] TXDA
[3] GND BOND
ST[1] REF
CLK+ BOND
ST[0] RXSTD
[2] GND RXSTD
[0] RXDD
[3] VCC RXDD
[6] TXCTD
[0] TXDD
[4] TXDD
[3] V
RXDA
[1] RXDA
[4] RXCLK
A- LFIA VCC TXDA
[6] TXDA
[2] GND SCSEL TXOP
ATXRST TXCLK
O- GND RXSTD
[1] RXDD
[4] VCC RXCLK
D– LFID TXDD
[7] TXDD
[5] W
RXDA
[5] RXDA
[6] RXCLK
A+ TXCTA
[1] VCC TXDA
[5] TXDA
[0] GND TXPER
ATXCLK
AN/C TXCLK
O+ GND RXDD
[0] RXDD
[5] VCC RXCLK
D+ RXDD
[7] TXCLK
DTXDD
[6] Y
Note
3. N/C = Do Not Connect
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 9 of 55
Pin Descriptions
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
Transmit Path Data Signals
TXPERA
TXPERB
TXPERC
TXPERD
LVTTL Output, changes
relative to REFCLK↑ [4] Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is
enabled and a parity error is detected at the Encoder. This output is HIGH for one
transmit character clock period to indicate detection of a parity error in the character
presented to the Encoder.
If a parity error is detected, t he character in error is replaced with a C0.7 character to
force a corresponding bad-character dete ction at the remote end of the link. This
replacement takes place regardless of the encoded/non-encoded state of the
interface.
When BIST is enabled for the specific transmit channel, BIST progress is presented
on these outputs. Once every 511 character times (plus a 16-character Word Sync
Sequence when the receive channels are clocked by a common clock, i.e., RXCKSEL
= LOW or HIGH), the associated TXPERx signal will pulse HIGH for one
transmit-character clock period (if RXCKSEL= MID) or seventeen transmit- character
clock periods (if RXCKSEL = LOW or HIGH and Encoder is enabled) to indicate a
complete pass through the BIST sequence. Therefore, in this case TXPERx signal
will pulse HIGH for one transmit-character clock period.
These outputs also provide indication of a transmit Phase-align Buffer underflow or
overflow. When the transmit Phase-align Buffers are enabled (TXCKSEL ≠ LOW, or
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is
detected, TXPERx for the channel in error is asserted and remains asserted until
either an atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to
re-center the transmit Phase-align Buffers.
TXCTA[1:0]
TXCTB[1:0]
TXCTC[1:0]
TXCTD[1:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx↑ or
REFCLK↑ [4]
Transmit Control. These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL, and are passed to the Encoder or Transmit
Shifter . They identify how the associated TXDx[7:0] characters are interpreted. When
the Encoder is bypassed, these inputs are interpreted as data bits of 10-bit input
character. When the Encoder is enabled, these inputs determine if the TXDx[7:0]
character is encoded as Data, a Special Character code, a K28.5 fill character or a
Word Sync Sequence. See Table 1 for details.
TXDA[7:0]
TXDB[7:0]
TXDC[7:0]
TXDD[7:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx↑ or
REFCLK↑ [4]
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL and passed to the Encoder or Transmit
Shifter.
When the Encoder is enabled (TXMODE[1:0] ≠ LOW), TXDx[7:0] specify the specific
data or command character to be sent. When the Encoder is bypassed, these inputs
are interpreted as data bits of the 10-bit input character. See Table 1 for details.
TXOPA
TXOPB
TXOPC
TXOPD
LVTTL Input,
synchronous,
internal pull-up,
sampled by the
respective TXCLKx↑ or
REFCLK↑ [4]
Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the
parity captured at these inputs is XORed with the data on the associated TXDx bus
(and sometimes TXCT[1:0]) to verify the integrity of the captured character. See
Table 2 for de tails.
SCSEL LVTTL Input,
synchronous,
internal pull-down,
sampled by
TXCLKA↑
or REFCLK↑ [4]
Special Character Select. Used in some transmit mode s along with TXCTx[1:0] to
encode special characters or to initiate a Word Sync Sequence. When the transmit
paths are configured for independent input clocks (TXCKSEL = MID), SCSEL is
captured relative to TXCLKA↑.
Note
4. When REFCLK is configured fo r half-rat e operat ion (TXRATE = HIGH), these input s are sampled (or the out put s chang e) relati ve to both the rising and falling
edges of REFCLK.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 10 of 55
TXRST LVTTL Input,
asynchronous,
internal pull-up,
sampled by
REFCLK↑ [4]
Transmit Clock Phase Reset. Active LOW. When sampl e d LO W, the transmi t
Phase-align Buffers are allowed to adjust their data-transfer timing (relative to the
selected input clock) to allow clean transfer of data from the Input Register to the
Encoder or Transmit Shifter. When TXRST is sampled HIGH, the internal phase
relationship between the associated TXCLKx and the internal character-rate clock is
fixed and the device operates normally.
When configured for half-rate REFCLK sampling of the transmit character stream
(TXCKSEL = LOW an d TXR ATE = HIGH), assertion of TXRST is only used to clear
Phase-align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs
with excessive cycle-to-cycle jitter. During this alignment period, one or more
characters may be added to or lost from all the associated transmit paths as the
transmit Phase-align Buffers are adjusted. TXRST must be sampled LOW by a
minimum of two consecutive rising edges REFCLK to ensure the reset operation is
initiated correctly on all channels. This input is ignored when both TXCKSEL and
TXRATE are LOW, since the phase align buffer is bypassed. In all other configurations,
TXRST should be asserted during device initialization to ensure proper operation of
the Phase-align buffer. TXRST should be asserted after the presence of a valid
TXCLKx and after allowing enough time for the TXPLL to lock to the reference clock
(as specified by parameter tTXLOCK).
Transmit Path Clock and Clo ck Control
TXCKSEL Three-level Select [5],
static control input T ransm it Clock Sele ct. Selects the clock source, used to write data into the transmit
Input Register of the tran smit channel(s). When LOW, REFCLK↑ [4] is used as the
Input Register clock for TXDx[7:0] and TXCTx[1:0] of all channels. When MID,
TXCLKx↑ is used as the Input Register clock for TXDx[7:0] and TXCTx[1:0]. When
HIGH, TXCLKA↑ is used as the Input Register clock for TXDx[7:0] and TXCTx[1:0] of
all channels.
TXCLKO±LVTTL Output Transmit Clock Output. This true and compleme nt output clock is synthesized by
the transmit PLL and is synchronous to the internal transmit character clock. It has
the same frequency as REFCLK (when TXRATE = LOW), or twice the frequency of
REFCLK (when TXRA TE = HIGH). This output clock has no direct phase relationship
to REFCLK.
TXRATE LVTTL Input,
static control input,
internal pull-down
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multi-
plies REFCLK by 20 to generate the serial bit-rate clock. When TXRA TE = LOW, the
transmit PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See
Table 11 for a list of operating serial rates.
When REFCLK is selected to clock the receive parallel interfaces (RXCKSEL = LOW),
the TXRATE input also determines if the clocks on the RXCLKA± and RXCLKC±
outputs are full or half-rate. When TXRATE = HIGH (REFCLK is half-rate), the
RXCLKA± and RXCLKC± output clocks are also half-rate clocks and follow the
frequency and duty cycle of the REFCLK input. When TXRATE = LOW (REFCLK is
full-rate), the RXCLKA± and RXCLKC± output clocks are full-rate clocks and follow
the frequency and duty cycle of the REFCLK input.
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input
register), configuring TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of
operation.
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input,
internal
pull-down
Transmit Path Input Clocks. These clocks must be frequency-coherent to
TXCLKO±, but may be offset in phase. The internal operating phase of each input
clock (relative to REFLCK or TXCLKO±) is adjusted when TXRST = LOW and locked
when TXRST = HIGH.
Note
5. Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and
HIGH. The LOW level is usual ly impl emented by d irect conne ction to VSS (groun d). The HIGH level is usually impl emented by dire ct conn ection to V CC. When
not connected or allowed to float, a Three-level select input will self-bias to the MID level.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 11 of 55
Transmit Path Mode Control
TXMODE[1:0] Three-level Select [5]
static control inputs Transmit Operating Mode. These inputs are interpreted to select one of nine
operating modes of the transmit path. See Table 3 for a list of operating modes.
Receive Path Data Signals
RXDA[7:0]
RXDB[7:0]
RXDC[7:0]
RXDD[7:0]
LVTTL Output,
synchronous to the
selected RXCLKx↑ output
(or REFCLK↑ input[4]
when RXCKSEL = LOW)
Parallel Data Output. These outputs change following the rising edge of the selected
receive interface clock.
When the Decoder is enabled (DECMODE = HIGH or MID), these outputs represent
either received data or special characters. The status of the received data is repre-
sented by the valu e s of R XSTx[ 2:0].
When the Decoder is bypassed (DECMODE = LOW), RXDx[7:0] become the higher
order bits of the 10-bit received character. See Table 18 for details.
RXSTA[2:0]
RXSTB[2:0]
RXSTC[2:0]
RXSTD[2:0]
LVTTL Output,
synchronous to the
selected RXCLKx↑ output
(or REFCLK↑ input[4]
when RXCKSEL = LOW)
Parallel Status Output. These outputs change following the rising edge of the
selected receive interface clock.
When the Decoder is bypassed (DECMODE = LOW), RXSTx[1:0] become the two
low-order bits of the 10-bit received character, while RXSTx[2] = HIGH indicates the
presence of a Comma character in the Output Register. See Table 18 for details.
When the Decoder is enabled (DECMODE = HIGH or MID), RXSTx[2:0] provide
status of the received signal. See Table 20, 21 and 22 for a list of Receive Character
status.
RXOPA
RXOPB
RXOPC
RXOPD
three-state, LVTTL
Output, synchronous to
the selected
RXCLKx↑ output
(or REFCLK↑ input[4]
when RXCKSEL = LOW)
Receive Path Odd Parity . When p arity generation is enabled (PARCTL ≠ LOW), the
parity output at these pins is valid for the data on the associated RXDx bus bits. When
parity generation is disabled (PARC TL = LOW) these output drivers are disabled
(High-Z).
Receive Path Clock and Clock Control
RXRATE LVTTL Input, static control
input, internal pull-dow n Receive Clock Rate Select. When LOW , the RXCLKx± recovered clock outputs are
complementary clocks operating at the recovered character rate. Data for the
associated receive channels should be latched on the rising edge of RXCLKx+ or
falling edge of RXCLKx–.
When HIGH, the RXCLKx± recovered clock outputs are complementary clocks
operating at half the character rate. Data for the associated receive channels should
be latched alternately on th e rising edge of RXCLKx+ and RXCLKx–.
When REFCLK± is selected to clock the output registers (RXCKSELx = LOW),
RXRATEx is not interpreted. The RXCLKA± and RXCLKC± output clocks will follow
the frequency and duty cycle of REFCLK±.
FRAMCHAR Three-level Select [5],
static control input Framing Character Se lect. Used to select the character or portion of a character
used for character framing of the received data streams. When MID, the Framer looks
for both positive and negative disparity versions of the eight-bit Comma character.
When HIGH, the Framer looks for both positive and negative disparity versions of the
K28.5 character. Configuring FRAMCHAR to LOW is reserved for component test.
RFEN LVTTL Input,
asynchronous,
internal pull-down
Reframe Enable for All Channels. Active HIGH. When HIGH, the f ramers in all four
channels are enabled to frame per the presently enabled framing mode as selected
by RFMODE and selected framing character as selected by FRAMCHAR.
RXMODE[1:0] Three-level Select [5],
static control inputs Receive Operating Mode. These inputs are interpreted to select one of nine
operating modes of the receive path. See Table 14 for details.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 12 of 55
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
Three-state, LVTTL
Output clock or static
control input
Receive Character Clock Output or Clock Select Input. When configured such that
all output data paths are clocked by the recovered clock (RXCKSEL = MID), these
true and complement clocks are the receive interface clocks which are used to control
timing of output data (RXDx[7:0], RXSTx[2:0] and RXOPx). These clocks are output
continuously at either the dual-character rate (1/20th the serial bit-rate) or character
rate (1/10th the serial bit-rate) of the data being received, as selected by RXRATE.
When configured such that all output data paths are clocked by REFCLK instead of a
recovered clock (RXCKSEL = LOW), the RXCLKA± and RXCLKC± output drivers
present a buffered and delayed form of REFCLK. RXCLKA± and RXCLKC± are
buffered forms of REFCLK that are slightly different in phase. This phase difference
allows the user to select the optimal setup/hold timing for their speci fic in terface.
When RXCKSEL = LOW and quad channel bonding is enabled, RXCLKB+ and
RXCLKD+ are static control inputs used to select the master channel for bonding and
status control.
When RXCKSEL = HIGH and quad-channel bonding is enabled, one of the recovered
clocks from channels A, B, C or D can be selected to clock the bonded output data.
The selection of the recovered clock is made by RXCLKB+ and RXCLKD+ which act
as static control inputs in this mode. Both RXCLKA± and RXCLKC± output buffered
forms of the recovered clock selected from receive channel A, B, C, or D. See Table 15
for details.
When RXCKSEL = HIGH and dual-channel bonding is enabled, one of the recovered
clocks from channels A or B is selected to present bonded data from channels A and
B, and one of the recovered clocks from channels C or D is selected to present bonded
data from channels C and D. RXCLKA± output the recovered clock from either receive
channel A or receive channel B as selected by RXCLKB+ to clock the bonded output
data from channels A and B, and RXCLKC± output the recovered clock from either
receive channel C or receive channel D as selected by RXCLKD+ to the clock the
bonded output data from channels C and D. See Table 16 fo r details.
RXCKSEL Three-level Select [5],
static control input Receive Clock Mode. Selects the receive clock source used to transfer data to the
Output Registers.
When LOW, all four Output Registers are clocked by REFCLK. RXCLKB± and
RXCLKD± outputs are disabled (High-Z), and RXCLKA± and RXCLKC± present
buffered and delayed forms of REFCLK. This clocking mode is required for channel
bonding across multiple devices.
When MID, each RXCLKx± output follows the recovered clock for the respective
channel, as selected by RXRATE. When the 10B/8B Decoder and Elasticity Buffer are
bypassed (DECMODE = LOW), RXCKSEL must be MID.
When HIGH and channel bonding is enabled in dual-channel mode (RX modes 3 and
5), RXCLKA± outputs the recovered clock from either receive channel A or B as
selected by RXCLKB+, and RXCLKC± outputs the recovered clock from either receive
channel C or D as selected by RXCLKD+. These output clocks may operate at the
character-rate or half the character-rate as selected by RXRATE.
When HIGH and channel bonding is enabled in quad channel mode (RX modes 6 and
8), or if the receive channels are operated in independent mode (RX modes 0 and 2),
RXCLKA± and RXCLKC± output the recovered clock from receive channel A, B, C,
or D, as selected by RXCLKB+ and RXCLKD+. This output clock may operate at the
character-rate or half the character-rate as selected by RXRATE.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 13 of 55
DECMODE Three-level Select [5],
static control input Decoder Mode Select. This input selects the behavior of the Decoder block. When
LOW, the Decoder is bypassed and raw 10-bit characters are passed to the Output
Register. When the Decoder is bypassed, RXCKSEL must be MID.
When MID, the Decoder is enabled and the Cypress decoder table for Special Code
characters is used.
When HIGH, the Decoder is enabled and the alternate decoder table for Special Code
characters is used. See Table 27 for a list of the Special Codes supported in both
encoded modes.
RFMODE Three-level Select [5],
static control input Reframe Mode Select. Used to select the type of character framing used to adjust
the character boundaries (based on detection of one or more framing characters in
the received serial bit stream). This signal operates in conjunction with the presently
enabled channel bonding mode, and the type of framing character selected.
When LOW , the Low-Latency Framer is selected. This will frame on each occurrence
of the selected framing character(s) in the received data stream. This mode of framing
stretches the recovered character-rate clock for one or multiple cycles to align that
clock with the recovered data.
When MID, the Cypress-mode Multi-Byte parallel Framer is selected. This requires a
pair of the selected framing character(s), on identical 10-bit boundaries, within a span
of 50 bits, before the character boundaries are adjusted. The recovered character
clock remains in the same phase regardless of character offset.
When HIGH, the alternate mode Multi-Byte parallel Framer is selected. This requires
detection of the selected framing character(s) of the allowed disparities in the received
serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters.
The recovered character clock remains in the same phase regardless of character
offset.
Device Control Signals
PARCTL Th ree-level Select [5],
static control input Parity Check/Generate Control. Used to control the different parity check and
generate functions. When LOW , parity checking is disabled, and the RXOPx outputs
are all disabled (High-Z). When MID, and the 8B/10B Encode r and Decoder are
enabled (TXMODE[1] ≠LOW, DECMODE ≠LOW) , TXDx[7:0] inputs are checked
(along with TXOPx) for valid ODD parity, and ODD parity is generated for the
RXDx[7:0] outputs and presented on RXOPx. When the Encoder and Decoder are
disabled (TXMODE[1] = LOW, DECMODE =LOW), theTXDx[7:0] and TXCTx[1:0]
inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is
generated for the RXDx[7:0] and RXSTx[1:0] outputs and presented on RXOPx. When
HIGH, parity checking and generation are enabled. Th e TXDx[7:0] and TXCTx[1:0]
inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is
generated for the RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx. See
Table 2 and 19 for details.
SPDSEL Three-level Select [5]
static control input Serial Rate Select. This input specifies the operating bit-rate range of both transmit
and receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud,
HIGH = 800–1500 MBaud. When SPDSEL is LOW, setting TXRATE = HIGH (Half-rate
Reference Clock) is invalid.
TRSTZ LVTTL Input,
internal pull-up Device Reset. Active LOW . Initializes all state machines and counters in the device.
When sampled LOW by the rising edge of REFCLK↑, this input resets the internal
state machines and sets the Elasticity Buffer pointers to a nominal offset. When the
reset is removed (TRSTZ sampled HIGH by REFCLK↑), the status and data outputs
will become deterministic in less than 16 REF CLK cycles. The BISTLE, OELE, and
RXLE latches are reset by TRSTZ. If the Elasticity Buffer or the Phase-align Buffer
are used, TRSTZ should be applied after power up to initialize the internal pointers
into these memory arrays.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 14 of 55
REFCLK±Differential LVPECL or
single-ended
LVTTL Input Clock
Reference Clock. This clock input is used as the timing reference for the transmit
PLL. It is also used as the centering frequency of the Rang e Controller block of the
Receive CDR PLLs.This input clock may also be selected to clock the transmit and
receive parallel interfaces. When driven by a single-ended LVCMOS or LVTTL clock
source, connect the clock source to either the true or complement REFCLK input, and
leave the alternate REFCLK input open (floating). When driven by an L VPECL clock
source, the clock must be a differential clock, using both inputs. When TXCKSEL =
LOW , REFCLK is also used as the clock for the parallel transmit data (input) interface.
When RXCKSEL = LOW , the Elasticity Buffer is enabled and REFCLK is used as the
clock for the parallel receive data (output) interface.
If the Elasticity Buffer is used, framing characters will be inserted or deleted to/from
the data stream to compensate for frequency differences between the reference clock
and recovered clock. When an addition happens, a K28.5 will be appended immedi-
ately after a framing is detected in the Elasticity Buffer. When deletion happens, a
framing character will be removed from the data stream when detected in the Elasticity
Buffer.
Analog I/O an d Control
OUTA1±
OUTB1±
OUTC1±
OUTD1±
CML Differential
Output Primary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3 V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
OUTA2±
OUTB2±
OUTC2±
OUTD2±
CML Differential
Output Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3 V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
INA1±
INB1±
INC1±
IND1±
LVPECL Differential Input Primary Differential Serial Dat a Input s. These inputs accept the serial data stream
for deserialization and decoding. The INx1± serial str eams are passed to the receiver
Clock and Data Recovery (CDR) circuits to extract the data content when INSELx =
HIGH.
INA2±
INB2±
INC2±
IND2±
LVPECL Differential Input Secondar y Differential Serial Data Inputs. These inputs accept the serial data
stream for deserialization and decoding. The INx2± serial streams are passed to the
receiver Clock and Data Recovery (CDR) circuits to extract the data content when
INSELx = LOW.
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous Receive Input Selector . Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the INx1± input is select ed .
When LOW, the INx2± input is select ed .
SDASEL Three-level Select [5]
static configuration input Signal Detect Amplitude Level Select. Allows selection of one of three predefined
amplitude trip points for a valid signal indication, as listed in Table 12.
LPEN LVTTL Input,
asynchronous,
internal pull-down
All-Port Loop-Back Enable. Active HIGH. When asserted (HIGH), the transmit serial
data from each channel is internally routed to the associated receiver Clock and Data
Recovery (CAR) circuit. All enabled serial drivers are forced to differential logic “1.”
All serial data inputs are ignored.
OELE LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enab le. Active HIGH. When OELE = HIGH, the
signals on the BOE[7:0] inputs directly control the OUTxy± differential drivers. When
the BOE[x] input is HIGH, the associated OUTxy± differential driver is enabled. When
the BOE[x] input is LOW , the associated OUTxy± differential driver is powered down.
The specific mapping of BOE[7:0] signals to transmit output enables is listed in
Table 10. When OELE returns LOW, the last values present on BOE[7:0] are captured
in the internal Output Enable Latch. If the device is reset (TRSTZ is sampled LOW),
the latch is reset to disable all outputs.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 15 of 55
BISTLE LVTTL Input,
asynchronous,
internal pull-up
T ransmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[7:0] inputs directly control the transmit and receive BIST enables.
When the BOE[x] input is LOW, the associated transmit or receive channel is
configured to generate or compare the BIST sequence respectively. When the BOE[x]
input is HIGH, the associated transmit or receive channel is configured for normal data
transmission or reception. The specific mapping of BOE[7:0] signals to transmit and
receive BIST enables is listed in Table 10. When BISTLE returns LOW , the last values
present o n BOE[7:0 ] are ca ptured in the internal BIST Enable Latch. When the latch
is closed, if the device is reset (TRSTZ is sampled LOW), the latch is reset to disable
BIST on all transmit and receive channels.
RXLE LVTTL Input,
asynchronous,
internal pull-up
Receive Channel Power-control Latch Enable. Active HIGH. When RXLE = HIGH,
the signals on the BOE[7:0] inputs directly control the power enables for the receive
PLLs and analog circuitry. When the BOE[7:0] input is HIGH, the associated receive
channel A through D PLL and analog circuitry are active. When the BOE[7:0] input is
LOW, the associated receive channel A through D PLL and analog circuitry are
powered down. The specific mapping of BOE[7:0] signals to the associated receive
channel enables is listed in Table 10. When RXLE returns LOW, the last values
present on BOE[7:0] are captured in the internal RX PLL Enable Latch. When the
device is reset (TRSTZ = LOW), the latch is reset to disable all receive channels.
BOE[7:0] LVTTL Input,
asynchronous,
internal pull-up
BIST, Serial Outpu t, and Receive Chann el Enables. These inputs are passed to
and through the Output Enable Latch when OELE is HIGH, and captured in this latch
when OELE returns LOW. These inputs are passed to and through the BIST Enable
Latch when BISTLE is HIGH, and captured in this latch when BISTLE returns LOW.
These inputs are passed to and through the Receive Channel Enable Latch when
RXLE is HIGH, and captured in this latch when RXLE returns LOW.
LFIA
LFIB
LFIC
LFID
LVTTL Output,
Asynchronous Link Fault Indica t io n Ou tput. Active LOW. LFIx is the logical OR of four internal
conditions:
1. Received serial data frequency outside expected range
2. Analog amplitude below expe cted levels
3. Transition density lower than expected
4. Receive Channel disabled.
Bonding Control
BONDST[1:0] Bidirectional Open Drain,
internal pull-up Bonding S tatus. These signals are only used when multiple devices are bonded
together. They communicate the status of Elasticity Buffer management events from
master device of the bonding domain to the slave devices of the same bonding
domain. These outputs change at the same character rate as the receive output data
buses, but are connected only to all the slave CYP(V)15G0401DXB devices. When
MASTER = LOW, these are output signals and present the Elasticity Buffer status
from the selected master receive channel of the device configured as the master.
Receive master channel selection is performed using the RXCLKB+ and RXCLKD+
inputs. The BONDST[1:0] Outputs of the master device must be connected to
BONDST[1:0] Inputs of all the slave devices in the bonding domain. These status
outputs indicate one of four possible conditions, on a synchronous basis, to the slave
devices. These conditions are:
00—Reserved
01—Add one K28.5 immediately following the next framing character received
10—Delete next framing character received
11—Normal data.
These outputs are driven only when the device is configured as a master, all four
channels are bonded together, and the receive parallel interface is clocked by
REFCLK↑.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 16 of 55
CYP(V)15G0401DXB HOTLink II Operation
The CYP(V)15G0401DXB is a highly configurable device
designed to support reliable transfer of large quantities of data,
using high-speed serial links, from one or multiple sources to one
or multiple destinations. This device supports four single-byte or
single-character channels that may be combined to suppo rt
transfer of wider buses.
CYP(V)15G0401DXB Transmit Data Path
Operating Modes
The transmit path of the CYP(V)15G0401DXB supports four
character-wide data paths. These data paths are used in multiple
operating modes as controlled by the TXMODE[1:0] inputs.
Input Register
The bits in the Input Register for each channel support different
assignments, based on if the character is unencoded, encoded
with two control bits, or encoded with three control bits. These
assignments are shown in Table 1. Each Input Register captures
a minimum of eigh t da ta bits and two control bits o n ea ch in pu t
clock cycle. When the Encoder is bypassed, the TXCTx[1:0]
control bits, are part of the preencoded 10-bit character.
When the Encoder is enabled (TXMODE[1] ≠ LOW), the
TXCTx[1:0] bits are interpreted along with the associated
TXDx[7:0] character to generate the specific 10-bit transmission
character. When TXMODE[0] ≠ HIGH, an additional special
character select (SCSEL) input is also captured and interpreted.
This SCSEL input is used to modify the encoding of the
associated characters. When the transmit Input Registers are
clocked by a common clock (TXCLKA↑ or REFCLK↑), this
SCSEL input can be changed on a clock-by-clock basis and
affects all four channels.
When operated with a separate input clock on each transmit
channel, this SCSEL input is sampled synchronous to
TXCLKA↑. While the value on SCSEL still affects all channels, it
is interpreted when the character containing it is read from the
transmit Phase-align Buffer (where all four paths are internally
clocked synchronously).
MASTER LVTTL Input,
static configuration input,
internal pull-down
Master Device Select. When LOW, the present device is configured as the master,
and BONDST[1:0] outputs are driven. When HIGH, the present device is configured
as a slave, and BONDST[1:0] are inputs. MASTER is only interpreted when
configured for quad channel bonding, and the receive parallel interface is clocked by
REFCLK↑.
BOND_ALL Bidirectional Open Drain,
Internal pull-up All Channels Bonded Indicator. Active HIGH, wired AND. BOND_ALL pins from all
CYP(V)15G0401DXB devices in the same bonding domain must be wired together. After
bonding resolution is completed and when HIGH, all receive channels have detected valid
framing. This output is LOW during the bonding resolution process. This output is driven
only when configured for four channel bonding, and the receive parallel interface is
clocked by REFCLK↑.
BOND_INH LVTTL Input,
static configuration input,
Internal pull-up
Parallel Bond Inhibit. Active LOW. When asserte d (LOW), this signal inhibits the
adjustment of character offsets in all receive channels if the Bonding Sequence ha s
not been detected in all bonded chan nels. When HIGH, all channels that have
detected the Bonding Sequence are allowed to align their Receive Elasticity Buffer
pipelines. For any channels to bond, the selected master channel must be a member
of the group. When multiple devices are used together, the BON D_INH input on all
parts must be configured the same.
JTAG Interface
TMS LVTTL Input,
internal pull-up T est Mode Select. Used to control access to the JT AG T est Modes. If maintained high
for ≥5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset
automatically upon application of power to the device.
TCLK LVTTL Input,
internal pull-down JTAG Test Clock
TDO Three-state
LVTTL Output Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
TDI LVTTL Input, internal pull-up Test Data In. JTAG data input port.
Power
VCC +3.3 V Power
GND Signal and power ground for all internal circuits.
Pin Descriptions (continued)
CYP(V)15G0401DXB Quad HOTLink II Transceiver
Pin Name I/O Characteristics Signal Description
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 17 of 55
Phase-align Buffer
Data from the Input Registers are passed either to the Encoder
or to the associated Phase-align Buffer . When the transmit paths
are operated synchronous to REFCLK↑ (TXCKSEL = LOW and
TXRATE = LOW), the Phase-align Buffers are bypassed and
data is passed directly to the Parity Check and Encoder blocks
to reduce latency.
When an Input-Register clock with an uncontrolle d phase
relationship to REFCLK is selected (TXCKSEL ≠ LOW) or if dat a
is captured on both edges of REFCLK (TXRATE = HIGH), the
Phase-align Buffers are enabled. These buffers are used to
absorb clock phase differences between the presently selected
input clock and the internal character clock.
Initialization of the Phase-align Buffers takes place when the
TXRST input is sampled LOW by two consecutive rising edges
of REFCLK. When TXRS T is retu rned HIGH, the present input
clock phase relative to REFCLK is set. TXRST is an
asynchronous input, but is sampled internally to synchronize it to
the internal transmit path state machines.
Once set, the input clocks are allowed to skew in time up to half
a character period in either direction relative to REFCLK; i.e.,
±180°. This time shift allows the delay paths of the character
clocks (relative to REFCLK) to change due to operating voltage
and temperature, while not affecting the design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK↑, exceeds the skew handling capabilities of
the Phase-align Buffer, an error is reported on the associated
TXPERx output. This output indicates a continuous error until the
Phase-align Buffer is reset. While the error remains active, the
transmitter for the associated channel will output a continuous
C0.7 character to indicate to the remote receiver that an error
condition is present in the link.
In specific transmit modes, it is also possible to reset the
Phase-align Buffers individually and with minimal disruption of
the serial data stream. When the transmit interface is configured
for generation of atomic Word Sync Sequences (TXMODE[1] =
MID) and a Phase-align Buffer error is present, the transmission
of a Word Sync Sequence will re-center the Phase-align Buffer
and clear the error condition.[7]
Parity Support
In addition to the ten data and control bits that are captured at
each transmit Input Register , a TXOPx input is also available on
each channel. This allows the CYP(V)15G0401DXB to support
ODD parity checking for each channel. Parity checking is
available for all operating modes (including Encod er Bypass).
The specific mode of parity checking is con trolled by the
PARCTL input, and operates per Table 2.
When PARCTL is MID (open) and the Encoders are enabled
(TXMODE[1] ≠ LOW), only the TXDx[7:0] data bits are checked
for ODD parity along with the associated TXOPx bit. When
PARCTL = HIGH with the Encoder enabled (or MID with the
Encoder bypassed), the TXDx[7:0] and TXCTx[1:0] inputs are
checked for ODD parity along with the associated TXOPx bit.
When PARCTL = LOW, parity checking is disabled.
When parity checking and the Encoder are both enabled
(TXMODE[1] ≠ LOW ), the detection of a parity error caus es a
C0.7 character of proper disparity to be passed to the Transmit
Shifter. When the Encoder is bypassed (TXMODE[1] = LOW,
LOW), detection of a parity error causes a positive disparity
version of a C0.7 transmission character to be passed to the
Transmit Shifter.
Table 1. Input Register Bit Assignments [6]
Signal Name Unencoded Encoded
2-bit
Control 3-bit
Control
TXDx[0] (LSB) DINx[0] TXDx[0] TXDx[0]
TXDx[1] DINx[1] TXDx[1] TXDx[1]
TXDx[2] DINx[2] TXDx[2] TXDx[2]
TXDx[3] DINx[3] TXDx[3] TXDx[3]
TXDx[4] DINx[4] TXDx[4] TXDx[4]
TXDx[5] DINx[5] TXDx[5] TXDx[5]
TXDx[6] DINx[6] TXDx[6] TXDx[6]
TXDx[7] DINx[7] TXDx[7] TXDx[7]
TXCTx[0] DINx[8] TXCTx[0] TXCTx[0]
TXCTx[1] (MSB) DINx[9] TXCTx[1] TXCTx[1]
SCSEL N/A N/A SCSEL
Table 2. Input Register Bits Checked for Parity [8]
Signal
Name
Transmit Parity Check Mode (PARCTL)
LOW MID HIGH
TXMODE[1]
= LOW TXMODE[1]
≠ LOW
TXDx[0] X [9] XX
TXDx[1] X X X
TXDx[2] X X X
TXDx[3] X X X
TXDx[4] X X X
TXDx[5] X X X
TXDx[6] X X X
TXDx[7] X X X
TXCTx[0] X X
TXCTx[1] X X
TXOPx X X X
Notes
6. The TXOPx inputs are also captured in the associated Input Register, but their interpretation is under the separate control of PARCTL.
7. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a complete
16-character W ord Sync Sequence for prop er Receive Elasticit y Buf fer alignmen t, it is recommen d that the sequence be fo llowed by a second W ord Sync Sequ ence
to ensure proper operation.
8. Transmit p ath parity errors are reported on the associated TXPERx output.
9. Bits marked as X are XORed together. Result must be a logic-1 for parity to be valid.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 18 of 55
Encoder
The character , received from the Input Register or Phase-align
Buffer and Parity Check Logic, is then passed to the Encoder
logic. This block interprets each character and any associated
control bits, and outputs a 10-bit transmission character.
Depending on the configured operating mode, the generated
transmission character may be
■The 10-bit pre-encoded character accepted in the In put
Register
■The 10-bit equivalent of the eight-bit Data character accepted
in the Input Register
■The 10-bit equivalent of the eight-bit Special Character code
accepted in the Input Register
■The 10-bit equivalent of the C0.7 SVS character if parity
checking was enabled and a parity error was detected
■The 10-bit equivalent of the C0.7 SVS character if a
Phase-align Buffer overflow or underflow error is present
■A character that is part of the 511-cha r acter BIST sequence
■A K28.5 character generated as an individual character or as
part of the 16-character Word Sync Sequence.
The selection of the specific characters generated are controlled
by the TXMODE[1:0], SCSEL, TXCTx[1:0], and TXDx[7:0] inputs
for each character.
Data Encoding
Raw data, as received directly from the Transmit Input Register ,
is seldom in a form suitable for transmission across a serial link.
The characters must usually be processed or transformed to
guarantee
■a minimum transition density (to allow the serial receive PLL to
extract a clock from the data stream).
■a DC-balance in the signaling (to prevent baseline wander).
■run-length limits in the serial data (to limit the bandwidth require-
ments of the serial link).
■the remote receiver a way of determining the correct character
boundaries (framing).
When the Encoder is enabled (TXMODE[1] ≠ LOW), the
characters to be transmitted are converted from Data or S pecial
Character codes to 10-bit transmission characters (as selected
by their respective TXCTx[1:0] and SCSEL inputs), using an
integrated 8B/10B Encoder. When directed to encode the
character as a Special Character code, it is encoded using the
Special Character encoding rules listed in Table 27. When
directed to encode the character as a Data character , it is
encoded using the Data Character encoding rules in Table 26.
The 8B/10B Encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit
Ethernet), the IBM® ESCON® and FICON™ channel s, Digital
Video Broadcast (DVB-ASI), and A TM Forum standards for data
transport.
Many of the Special Character codes listed in Table 27 may be
generated by more than one input character. The
CYP(V)15G0401DXB is designed to support two independent
(but non-overlapping) Special Character code tables. This allows
the CYP(V)15G0401DXB to operate in mixed environments with
other Cypress HOTLink devices using the enhanced Cypress
command code set, and the reduced command sets of other
non-Cypress devices. Even when used in an environment that
normally uses non-Cypress Special Character codes, the
selective use of Cypress command codes can permit operation
where running disparity and error handling must be managed.
Following conversion of each input character from eight bits to a
10-bit transmission character , it is passed to the T ransmit Shifter
and is shifted out LSB first, as required by ANSI and IEEE
standards for 8B/10B coded serial data streams.
Transmit Modes
The operating mode of the transmit path is set through the
TXMODE[1:0] inputs. These static three-level select inputs allow
one of nine transmit modes to be selected. The transmit modes
are listed in Table 3
The encoded modes (TX Modes 3 through 8) support multiple
encoding tables. These encoding tables vary by the specific
combinations of SCSEL, TXCTx[1], and TXCTx[0] that are used
to control the generation of data and control characters. These
multiple encoding fo rms allow maximum flexibility in interfacing
to legacy applications, while also supporting numerous exten-
sions in capabilities.
TX Mode 0—Encoder Bypass
When the Encoder is bypassed, the character captured from the
TXDx[7:0] and TXCTx[1:0] inputs is passed directly to the
Transmit Shifter without modification. If parity checking is
enabled (PARCTL ≠ LOW) and a parity error is detected, the
10-bit character is replaced with the 1001 11 1000 pattern (+C0.7
character).
With the Encoder bypassed, the TXCTx[1:0] inputs are
considered part of the data character and do not perform a
control function that would otherwise modify the interpretation of
the TXDx[7:0] bits. The bit usag e and mapping of these control
bits when the Encoder is bypassed is shown in Table 4.
Table 3. Tran smit Operating Modes
TX Mode Operating Mode
Mode
Number
TXMODE
[1:0]
Word Sync
Sequence
Support SCSEL
Control TXCTx Function
0 LL None None Encoder Bypass
1LM None None Reserved for test
2LH None None Reserved for test
3 ML Atomic Special
Character Encoder Control
4 MM Atomic Word Sync Encoder Control
5 MH Atomic None Encoder Control
6 HL Interruptible S pecial
Character Encoder Control
7 HM Interruptible Word Sync Encoder Control
8 HH I nterruptible None Encoder Control
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 19 of 55
In Encoder Bypass mode, the SCSEL input is ignored. All
clocking modes interpret the data the same, with no internal
linking between channels.
TX Modes 1 and 2—Factory Test Modes
These modes enable specific factory test configurations. They
are not considered normal operating modes of the device. Entry
or configuration of the device into these modes will not damage
the device.
TX Mode 3— Word Sync and SCSEL Control of Special Codes
When configured in TX Mode 3, the SCSEL input is captured
along with the associated TXCTx[1:0] data control inputs. These
bits combine to control the interpretation of the TXDx[7:0] bits
and the characters generated by the m . These bits are inter-
preted as listed in Table 5.
When TXCKSEL = MID, all transmit channels capture data into
their Input Registers using independent TXCLKx clocks. In this
mode, the SCSEL input is sampled only by TXCLKA↑. When the
character (accepted in the Channel-A Input Register) has
passed through the Phase-align Buffer and any selected parity
validation, the level captured on SCSEL is passed to the Encoder
of the remaining channel s during this same cycle.
To avoid the possible ambiguities that may arise due to the
uncontrolled arrival of SCSEL relative to the characters in the
alternate channels, SCSEL is often used as static control input.
Word Sync Sequence
When TXCTx[1:0] = 11, a 16-character sequence of K28.5
characters, known as a Word Sync Sequence, is generated on
the associated channel. This sequence of K28.5 characters may
start with either a positive or negative disparity K28.5 (as deter-
mined by the current running disparity and the 8B/10B coding
rules). The disparity of the second and third K28.5 characters in
this sequence are reversed from what normal 8B/10B coding
rules would generate. The remaining K28.5 char acters in the
sequence follow all 8B/10B coding rules. The disparity of the
generated K28.5 characters in this sequence follow a pattern of
either ++––+–+–+–+–+–+– or ––++–+–+–+–+–+–+.
When TXMODE[1] = MID (open, TX modes 3, 4, and 5), the
generation of this character sequence is an atomic (non-inter-
ruptible) operation. Once it has been successfully started, it
cannot be stopped until all sixteen characters have been
generated. The content of the associated Input Registers is
ignored fo r the duration of this 16-character sequence. At the
end of this sequence, if the TXCTx[1:0] = 1 1 condition is sampled
again, the sequence restarts and remains uninterruptible for the
following fifteen character clocks.
If parity checking is enabled, the character used to start the Word
Sync Sequence must also have correct ODD parity. Once the
sequence is started, parity is not checked on the following fifteen
characters in the Word Sync Sequence.
When TXMODE[1] = HIGH (TX modes 6, 7, and 8), the gener-
ation of the Word Sync Sequence becomes an interruptible
operation. In TX Mode 6, this sequence is started as soon as the
TXCTx[1:0] = 11 condition is detected on a channel. In order for
the sequence to continue on that channel, the TXCTx[1:0] inputs
must be sampled as 00 for the remaining fifteen characters of the
sequence.
If at any time a sample period exists where TXCTx[1:0] ≠ 00, the
Word Sync Sequence is terminated, and a character repre-
senting the associated data and control bits is generated by the
Encoder. This resets the Word Sync Sequence state machine
such that it will start at the beginning of the sequence at the next
occurrence of TXCTx[1:0] = 11.
When parity checking is enabled and TXMODE[1] = HIGH, all
characters (including those in the middle of a Word Sync
Sequence) must have correct parity . The detection of a character
with incorrect parity during a Word Sync Sequence will interrupt
that sequence and force generation of a C0.7 SVS character.
Any interruption of the Word Sync Sequence causes the
sequence to terminate.
When TXCKSEL = LOW , the Input Registers for all four transmit
channels are clocked by REFCLK.[4] When TXCKSEL = HIGH,
the Input Registers for all four transmit channels are clocked with
TXCLKA↑. In these clock modes all four sets of TXCTx[1:0]
inputs operate synchro nous to the SCSEL input. [11]
TX Mode 4—Atomic Word Sync and SCSEL Control of Wo rd
Sync Sequence Generation
When configured in TX Mode 4, the SCSEL input is captured
along with the associated TXCTx[1:0] data control inputs. These
bits combine to control the interpretation of the TXDx[7:0] bits
Table 4. Encoder Bypass Mode (TXMODE[1:0] = LL)
Signal Name Bus Weight 10Bit Name
TXDx[0] (LSB)[10] 20a
TXDx[1] 21b
TXDx[2] 22c
TXDx[3] 23d
TXDx[4] 24e
TXDx[5] 25i
TXDx[6] 26f
TXDx[7] 27g
TXCTx[0] 28h
TXCTx[1] (MSB) 29j
Table 5. TX Modes 3 and 6 Encoding
SCSEL
TXCTx[1]
TXCTx[0]
Characters Generated
XX 0 Encode d data character
0 0 1 K28.5 fi ll character
1 0 1 S pecial character code
X 1 1 16-cha ra c ter Word Sync Sequence
Notes
10.LSB is shifted out first.
11. When operated in any configuration where receive channels are bonded together, TXCKSEL must be either LOW or HIGH (not MID) to ensure that associated
characters are transmitted in the same ch aracter cycle.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 20 of 55
and the characters generated by the m . These bits are inter-
preted as listed in Table 6.
When TXCKSEL = MID, all transmit channels operate indepen-
dently. In this mode, the SCSEL input is sampled only by
TXCLKA↑. When the character accepted in the Channel-A Input
Register has passed any selected validation and is ready to be
passed to the Encoder, the level captured on SCSEL is passed
to the Encoders of the remaining channels during this same
cycle.
Changing the state of SCSEL will change the relationship of the
characters to other channels. SCSEL should either be used as
a static configuration input, or changed only when the state of
TXCTx[1:0] on the alternate channels are such that SCSEL is
ignored during the change.
TX Mode 4 also supports an Word Sync Sequence. Unlike TX
Mode 3, this sequence starts when SCSEL and TXCTx[0] are
both high. With the exception of the combination of control bits
used to initiate the sequence, the generation and operation of
this Word Sync Sequence is the same as for TX Mode 3.
TX Mode 5—Atomic Word Sync generati on without SCSEL.
When configured in TX Mode 5, the SCSEL signal is not used.
In addition to the standard character encodings, two additional
encoding mappings are controlled by th e Channel Bonding
selection made through the RXMODE[1:0] inputs. For
non-bonded operation, the TXCTx[1:0] inputs for each channel
control the characters generated by that channel. The specific
characters generated by these bits are listed in Table 7.
TX Mode 5 also has the capability of generating an atomic Word
Sync Sequence. For the sequence to be started, the TXCTx[1:0]
inputs must both be sampled HIGH. The generation and
operation of this Word Sync Sequence is the same as TX Mode
3Two additional encoding maps are provided for use when
receive channel bonding is enab led. When dual-channel
bonding is enabled (RXMODE[1] = MID), the
CYP(V)15G0401DXB is configured such that channels A and B
are bonded together to form a two-character-wide path, and
channels C and D are bonded together to form a second
two-character-wide path.
When operated in this two-channel bonded mode, the TXCT A[0]
and TXCTB[0] inputs control the interpretation of the data on
both the A and B channels, while the TXCTC[0] and TXCTD[0]
inputs control the interpretation of the data on both the C and D
channels. The characters on each half of these bonded channels
are controlled by the associated TXCTx[1] bit. The specific
characters generated by these control bit combinations are listed
in Table 8.
Note especially that any time TXCTB[0] is sampled HIGH, both
channels A and B start generating an atomic Word Sync
Sequence, regardless of the state of any of the other bits in the
A or B Input Registers. In a similar fashion, anytime TXCTD[0] is
sampled HIGH, both the C and D channels start generation of an
atomic Word Sync Sequence.
When RXMODE[1] = HIGH, the CYP(V)15G0401DXB is
configured for quad-channel bonding, such that channels A, B,
C, and D are bonded together to form a four-character-wide path.
When operated in this mode, the TXCT A[0] and TXCTB[0] inputs
control the interpretation of the data on all four channels. The
characters generated on these bonded channels are controlled
by the associated TXCTx[1] bit. The specific characters
generated by these bits are listed in Table 9.
Unlike dual-channel bonded modes, when all four channels are
bonded together, the TXCTC[0] and TXCTD[0] inputs are
ignored.
Transmit BIST
Each transmit channel contains an internal pattern generator that
can be used to validate both device and link operation. These
generators are enabled by the associated BOE[x] signals listed
in Table 10 (when the BISTLE latch enable input is HIGH). When
enabled, a register in the associated transmit channel becomes
a signature pattern generator by logically converting to a Linear
Feedback Shift Register (LFSR). This LFSR generates a
511-character sequence that includes all Data and Special
Character codes, including the explicit violation symbols. This
provides a predictable yet pseudo-random sequence that can be
matched to identical LFSR in the attached Receiver(s). If the
receive channels are configured for common clock operation
(RXCKSEL ≠MID) and Encoder is enabled (TXMODE[1] ≠
LOW) each pass is preceded by a 16-character Word Sync
Sequence to allow Elasticity Buffer alignment and management
of clock- frequency variations.
When the BISTLE signal is HIGH, any BOE[x] input that is LOW
enables the BIST generator in the associated transmit channel
(or the BIST checker in the associated receive channel). When
BISTLE returns LOW, the values of all BOE[x] sign als are
captured in the BIST Enable Latch. These values remain in the
BIST Enable Latch until BISTLE is returned HIGH to open the
latch. A device reset (TRSTZ sampled LOW), presets the BIST
Enable Latch to disable BIST on all channels.
Table 6. TX Modes 4 and 7 Encoding
SCSEL
TXCTx[1]
TXCTx[0]
Characters Generated
XX 0 Encoded data character
0 0 1 K28.5 fill character
0 1 1 Special character code
1X 1 16-character Word Sync Sequence
Table 7. TX Modes 5 and 8 Encod ing, Non-bonded (RX-
MODE[1] = LOW)
SCSEL
TXCTx[1]
TXCTx[0]
Characters Generated
X 0 0 Encoded data character
X 0 1 K28.5 fill character
X 1 0 Special character code
X 1 1 16-character Word Sync Sequence
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 21 of 55
Table 8. TX Modes 5 and 8, Dual-channel Bonded (RXMODE[1] = MID)
SCSEL
TXCTA[1]
TXCTA[0]
TXCTB[1]
TXCTB[0]
TXCTC[1]
TXCTC[0]
TXCTD[1]
TXCTD[0]
Characters Generated
X0 0 X0XXXX Encoded data character on channel A
X0 1 X0XXXX K28.5 fill character on channel A
X1 0 X0XXXX Special character code on channel A
X1 1 X0XXXX 16-character word sync on channel A
XX000XXXX Encoded data character on channel B
XX100XXXX K28.5 fill character on channel B
XX010XXXX Special character code on channel B
XX110XXXX 16-character word sync on channel B
XXXX1XXXX 16-character word sync on channels A and B
XXXXX00X 0 Encoded data character on channel C
XXXXX01X 0 K28.5 fill character on channel C
XXXXX10X 0 Special character code on channel C
XXXXX11X 0 16-character word sync on channel C
XXXXXX 0 0 0 Encoded data character on channel D
XXXXXX 1 0 0 K28.5 fill character on channel D
XXXXXX 0 1 0 Special character code on channel D
XXXXXX 1 1 0 16-character word sync on channel D
XXXXXXXX 1 16-character word sync on channels C and D
Table 9. TX Modes 5 and 8, Quad-Channel Bonded (RXMODE[1] = HIGH)
SCSEL
TXCTA[1]
TXCTA[0]
TXCTB[1]
TXCTB[0]
TXCTC[1]
TXCTC[0]
TXCTD[1]
TXCTD[0]
Characters Generated
X0 0 X0XXXX Encoded data character on channel A
X0 1 X0XXXX K28.5 fill character on channel A
X1 0 X0XXXX Special character code on channel A
X1 1 X0XXXX 16-character word sync on channel A
XX000XXXX Encoded data character on channel B
XX100XXXX K28.5 fill character on channel B
XX010XXXX Special character code on channel B
XX110XXXX 16-character word sync on channel B
XX0X00X X X Encoded data character on channel C
XX1X00X X X K28.5 fill character on channel C
XX0X01X X X Special character code on channel C
XX1X01X X X 16-character word sync on channel C
XX0X0XX0X Encoded data character on channel D
XX1X0XX0X K28.5 fill character on channel D
XX0X0XX1X Special character code on channel D
XX1X0XX1X 16-character word sync on channel D
XXXX1XXXX 16-character word sync on channels A, B, C, and D
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 22 of 55
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel.
Serial Output Drivers
The serial interface Output Drivers use high-performance differ-
ential CML (Current Mode Logic) to provide source -matched
drivers for the transmission lines. These Serial Drivers accept
data from the Transmit Shifters. These outputs have signal
swings equivalent to that of standard PECL drivers, and are
capable of driving AC-coupled optical modules or transmission
lines.
When configured for local loopback (LPEN = HIGH), all enabled
Serial Drivers are configured to drive a static differential logic-1.
Each Serial Driver can be enabled or disabled separately
through the BOE[7:0] inputs, as controlled by the OELE
latch-enable signal. When OELE is HIGH, the signals present on
the BOE[7:0] inputs are passed through the Serial Output Enable
Latch to control the Serial Driver . The BOE[7:0] input associated
with a specific OUTxy± driver is listed in Table 10. When OELE
is HIGH and BOE[x] is HIGH, the associated Serial Driver is
enabled. When OELE is HIGH and BOE[x] is LOW, the
associated Serial Driver is disabled and internally powered
down. If both Serial Drivers for a channel are in this disabled
state, the associated internal logic for that channel is also
powered down. When OELE returns LOW, the values present on
the BOE[7:0] inputs are latched in the Output Enable Latch, and
remain there until OELE returns HIGH to enable the latch. A
device reset (TRSTZ sampled LOW) clears this latch and
disables all Serial Drivers.
Note When all transmit channels are disabled (i.e., both outputs
disabled in all channels) and a channel is re-enabled, the data
on the Serial Drivers may not meet all timing specifications for up
to 200 μs.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiples that clock by 10 or 20 (as selected by TXRATE) to
generate a bit-rate clock for use by the Transmit Shifter. It also
provides a character-rate clock used by the transmit paths.
This clock multiplier PLL can accept a REFCLK input between
20 MHz and 150 MHz, however , this clock range is limited by the
operating mode of the CYP(V)15G0401DXB clock multiplier
(controlled b y TX R ATE) and by the level on the SPDSEL inpu t.
When TXRATE = HIGH (Half-rate REFCLK), TXCKSEL = HIGH
or MID (TXCLKx or TXCLKA selected to clock input register) is
an invalid mode of operation.
SPDSEL is a static three-level select [5] (ternary) input that
selects one of three operating ranges for the serial data outputs
and inputs. The operating serial signaling-rate and allowable
range of REFCLK frequencies are listed in Table 11.
The REFCLK± input is a differential input with each input inter-
nally biased to 1.4 V. If the REFCLK+ input is connected to a TTL,
LVTTL, or LVCMOS clock source, REFCLK– can be left floating
and the input signal is recognized when it passes through the
internally biased reference point.
When both the REFCLK+ and REFCLK– inputs are connected,
the clock source must be a differential clock. This can be either
a differential L VPECL clock that is DC- or AC-coupled, or a differ-
ential LVTTL or LVCMOS clock.
By connecting the REFCLK– input to an external voltage source
or resistive voltage divider , it is possible to adjust the reference
point of the REFCLK+ input for alternate logic levels. When doing
so, it is necessary to ensure that the input differential crossing
point remains within the parametric range supported by the input.
CYP(V)15G0401DXB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are available
on each channel for accepting serial data streams. The active
Serial Line Receiver on a channel is se lected using the
associated INSELx input. The Serial Line Receiver inputs are
differential, and can accommodate wire interconnect and filtering
losses or transmission line attenuation greater than 16 dB. For
normal operation, these inputs should receive a signal of at least
VIDIFF > 100 mV , or 200 mV peak-to-peak differential. Each Line
Receiver can be DC- or AC-coupled to +3.3 V powered
fiber-optic interface modules (any ECL/PECL family, not limited
to 100K PECL) or AC-coupled to +5 V powered optical modules.
The common-mode tolerance of these line receivers accommo-
dates a wide range of signal termination voltages. Each receiver
provides internal DC-restoration, to the center of the recei ver’s
common mode range, for AC-coupled signa ls.
The local loopback input (LPEN) allows the serial transmit data
to be routed internally back to the Clock and Data Recovery
circuit associated with each channel. When configured for local
Table 10. Output Enable, BIST, and Receive Channel
Enable Signal Map
BOE
Input Output
Controlled
(OELE)
BIST
Channel
Enable
(BISTLE)
Receive PLL
Channel
Enable
(RXLE)
BOE[7] OUTD2±Transmit D X
BOE[6] OUTD1±Receive D Receive D
BOE[5] OUTC2±Transmit C X
BOE[4] OUTC1±Receive C Receive C
BOE[3] OUTB2±Transmit B X
BOE[2] OUTB1±Receive B Receive B
BOE[1] OUTA2±Transmit A X
BOE[0] OUTA1±Receive A Receive A
Table 11. Operating Speed Settings
SPDSEL TXRATE REFCLK
Frequency
(MHz) Signaling
Rate (MBaud)
LOW 1reserved 195–400
0 19.5–40
MID (Open) 1 20–40 400–800
0 40–80
HIGH 1 40–75 800–1500
0 80–150
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 23 of 55
loopback, all transmit Serial Driver outputs are forced to output
a differential logic-1. This prevents local diagnostic patterns from
being broa d c ast to atta ch ed remote receiver s.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
■Analog amplitude above limit specified by SDASEL
■Transition density greater than specifie d limit
■Range controller reports the received data stream within
normal frequency range (±1500 ppm)[12]
■Receive channel enabled
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable. This allows
operation with highly attenuated signals, or in high-noise
environments. This adjustment is made through the SDASEL
signal, a three-level select[5] input, which sets the trip point for
the detection of a valid signal at one of three levels, as listed in
Table 12. This control input affects the analog monitors for all
receive channels.
The Analog Signal Detect Monitors are active for the Line
Receiver selected by the associated INSELx input. When the
channel is configured for local loopback (LPEN = HIGH), no line
receivers are selected, and the LFIx output for each channel
reports only the receive VCO frequency out-of-range and
transition density status of the associated transmit signal. When
local loopback is active, the Analog Signal Detect Monitors are
disabled.
Transition Density
The Transition Detection logic checks for the absence of any
transitions spanning greater than six transmission characters (60
bits). If no transitions are present in the data received on a
channel, the Transition Detection logic for that channel will assert
LFIx. The LFIx output remains asserted until at least one
transition is detected in each of three adjacent received
characters.
Range Controls
The Clock/Data Recovery (CDR) circuit includes logic to monitor
the frequency of the Phase Locked Loop (PLL) Voltage
Controlled Oscillator (VCO) used to sa mple the incoming data
stream. This logic ensures that the VCO operates at, or near the
rate of the incoming data stream for two primary cases:
■when the incoming data stream resumes after a time in which
it has been “missing”
■when the incoming data stream is outside the acceptable
frequency range
To perform this function, the frequency of the VCO is periodically
sampled and compared to the frequency of the REFCLK input. If
the VCO is running at a frequency beyond ±1500 ppm [12] as
defined by the reference clock frequency , it is periodically forced
to the correct frequency (as defined by REFCLK, SPDSEL, and
TXRATE) and then released in an attempt to lock to the input
data stream. The sampling and relock period of the Range
Control is calculated as follows: RANGE CONTROL SAMPLING
PERIOD = (REFCLKPERIOD) * (16000).
During the time that the Range Control forces the PLL VCO to
run at REFCLK*10 (or REFCLK*20 when TXRA TE = HIGH) rate,
the LFIx output will be asserted LOW. While the PLL is
attempting to re-lock to the incoming data stream, LFIx may be
either HIGH or LOW (depending on other factors such as
transition density and amplitude detection) and the recovered
byte clock (RXCLKx) may run at an incorrect rate (depending on
the quality or existence of the input serial data stream). After a
valid serial data stream is applied, it may take up to one RANGE
CONTROL SAMPLING PERIOD before the PLL locks to the
input data stream, after which LFIx should be HIGH.
Receive Channel Enabled
The CYP(V)15G0401DXB contains four receive channels that
can be independently enabled and disabled. Each channel can
be enabled or disabled separately through the BOE[7:0] inputs,
as controlled by the RXLE latch-enable signal. Wh en RXLE is
HIGH, the signals present on the BOE[7:0] inputs are passed
through the Receive Channel Enable Latch to control the PLLs
and logic of the associated receive channel. The BOE[7:0] input
associated with a specific receive channel is listed in Table 10.
When RXLE is HIGH and BOE[x] is HIGH, the associated
receive channel is enabled to receiv e and recover a serial
stream. When RXLE is HIGH and BOE[x] is LOW, the associated
receive channel is disabled and powered down. If a single
channel of a bonded-pair or bonded-quad is disabled, the other
receive channels may not bond correctly . If the disabled channel
is selected as the master channel for insert/delete or recovered
clock select, these functions will not work correctly . Any disabled
channel indicates an asserted LFIx output. When RXLE returns
LOW, the values present on the BOE[7:0] inputs are latched in
the Receive Channel Enable Latch, and remain there until RXLE
returns HIGH to open the latch again. [14]
Table 12. Analog Amplitude Detect Valid Signal Levels[13]
SDASEL Typical si gnal with peak amplitu des above
LOW 140 mV p-p differential
MID (Open) 280 mV p-p differential
HIGH 420 mV p-p differential
Notes
12.REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering ref erence to reduce clock synchronization time. REFCLK
must be within ±15 00 P PM (±0.15 %) o f the r emote t ransmit ter’s PLL ref eren ce (REFCLK) fr equen cy. Although transmitting to a HOTLink II receiver ne cessit ate s the
frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the limits specified
by the appropr iate stand ard when tran smitting to a remote receiver that is complia nt to th at st andard. For e xample, to be IE EE 802.3z Gi gabit Ethe rnet compliant, t he
frequency stability of the crystal needs to be within ±100 PPM.
13.The peak amplitudes listed in t his t able are for typical waveforms that have generally 3 – 4 tr ansitions for every ten bits. In a worse case environmen t the signals may
have a sign-wave appearan ce (highest transit ion density with repeating 0101...). Sign al peak amplitudes level s within this envi ronment type could increase the values
in the table above by approximately 100 mV.
14.When a disabled receive channel is re-enabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate
for up to 2 ms.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 24 of 55
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate Clock/Data
Recovery (CDR) block within each receive channel. The clock
extraction function is performed by embedded phase-locked
loops (PLLs) that track the frequency of the transitions in the
incoming bit streams and align the phase of their internal bit-rate
clocks to the transitions in the selected serial data streams.
Each CDR accepts a character-rate (bit-rate ÷10) or
half-character-rate (bit-rate ÷20) reference clock from the
REFCLK input. This REFCLK input is used to
■ensure that the VCO (within the CDR) is operating at the correct
frequency.
■to reduce PLL acquisition time
■and to limit unlocked frequency excursio ns of the CDR VCO
when there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR will attempt to
recover a data stream from it. If the frequency of the recovered
data stream is outside the limits of the range control monitor , the
CDR will switch to track REFCLK instead of the data stream.
Once the CDR output (RXCLKx) frequency returns back close to
REFCLK frequency , the CDR input will be switched back to track
the input data stream. In case no data is present at the input this
switching behavior may result in brief RXCLKx frequency excur-
sions from REFCLK. However, the validity of the input data
stream is indicated by the LFIx output. The frequency of
REFCLK is required to be within ±1500 ppm[12] of the frequency
of the clock that drives the REFCLK input of the remote trans-
mitter to ensure a lock to the incoming data stream.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When an
LFIx indication is detected, external logic can toggle selection of
the associated INx1± and INx2± inputs through the associated
INSELx input. When a port switch takes place, it is necessary for
the receive PLL for that channel to reacquire the new serial
stream and frame to the incoming character boundaries. If
channel bonding is also enabled, a channel alignment event is
also required before the output data may be considered usable.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the
bit-clock rate. When enabled, the Framer examines the data
stream, looking for one or more Comma or K28.5 characters at
all possible bit positions. The location of this character in the data
stream is used to determine the character boundaries of all
following characters.
Framing Character
The CYP(V)15G0401DXB allows selection of two combinations
of framing characters to support requirements of different inter-
faces. The selection of the framing character is made through the
FRAMCHAR input.
The specific bit combination s of these framing characters are
listed in Table 13. When the specific bit combination of the
selected framing character is detected by the Framer , the bound-
aries of the characters present in the received data stream are
known.
Framer
The Framer on each channel operates in one of three different
modes, as selected by the RFMODE input. In addition, the
Framer itself may be enabled or disabled through the RFEN
input. When RFEN = LOW, the framers in all four receive paths
are disabled, and no combinatio n of bits in a received data
stream will alter the character boundaries. When RFEN = HIGH,
the Framer selected by RFMODE is enabled on all four channels.
When RFMODE = LOW, the Low-Latency Framer is
selected[16]. This Framer operates by stretching the recovered
character clock until it aligns with the received character bound-
aries. In this mode, the Framer starts its alignment process on
the first detection of the selected framing character. To reduce
the impact on external circuits that make use of a recovered
clock, the clock period is not stretched by more than two
bit-periods in any one clock cycle. When operated with a
character-rate output clock (RXRATE = LOW), the output of
properly framed characters may be delayed by up to nine
character-clock cycles from the detection of the selected framing
character. When operated with a half-character-rate output clock
(RXRATE = HIGH), the output of properly framed characters may
be delayed by up to fourteen character-clock cycles from the
detection of the selected framing character.
When RFMODE = MID (open), the Cypress-mode Multi-Byte
Framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to
incorrect framing due to aliased framing characters in the data
stream. In this mode, the Framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered clock
does not contain any significant phase changes or hops during
normal operation or framing, and allows the recovered clock to
be replicated and distributed to other external circuits or compo-
nents using PLL-based clock distribution elements. In this
framing mode, the character boundaries are only adjusted if the
selected framing character is detected at least twic e within a
span of 50 bits, with both instances on identical 10-bit character
boundaries.
Table 13. Framing Character Selector
FRAMCHAR Bits Detected in Framer
Character Name Bits Detected
LOW Reserved for test
MID (Open) Comma+
or Comma−00111110XX [15]
or 11000001XX
HIGH –K28.5
or +K28.5 0011111010 or
1100000101
Notes
15.The standard definit ion of a Comma cont ain s only seven bits. However, since all valid Comma characters within the 8B/ 10B cha racte r se t al so h ave the eighth bit as
an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce t he possibility of a framing error.
16.When Receive BIST is ena bled on a channel, the Lo w-Latency Fram er must not be ena bled. The BIST sequence conta ins an aliased K28.5 frami ng ch aracter, which
would cause the Receiver to update its character boundaries incorrectly.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 25 of 55
When RFMODE = HIGH, the Alternate-mode Multi-Byte Framer
is enabled. Like the Cypress-mode Multi-Byte Framer, multiple
framing characters must be detected before the character
boundary is adjusted. In this mode, the Framer does not adjust
the character clock boundary , but instead aligns the character to
the already recovered character clock. In th is mode, the data
stream must contain a minimum of four of the selected framing
characters, received as consecutive characters, on identical
10-bit boundaries, before character framing is adjusted.
Framing for all channels is enabled when RFEN = HIGH. If RFEN
= LOW, the Framer for each channel is disabled. When the
framers are disabled, no changes are made to the recovered
character boundaries on any channel, regardless of the
presence of framing characters in the data stream.
10B/8B Decoder Block
The Decoder logic block performs three primary functions:
■decoding the received transmission characters back into Data
and Special Character codes
■comparing generated BIST patterns with received characters
to permit at-speed link and device testing
■generation of ODD parity on the decoded characters.
10B/8B Decoder
The framed parallel output of each Deserializer Shifter is passed
to the 10B/8B Decoder where, if the Decoder is enabled
(DECMODE ≠LOW), it is transformed from a 10-bit transmission
character back to the original Data and Special Character codes.
This block uses the 10B/8B Decoder patterns in Table 26 and
Table 27 of this data sheet. Valid data characters are indicated
by a 000b bit-combination on the associated RXSTx[2:0] status
bits, and Special Character codes are indicated by a 001b
bit-combination on these same status outputs. Framing
characters, invalid patterns, disparity errors, and synchronization
status are presented as alternate combinati ons of these status
bits.
The 10B/8B Decoder opera tes in two normal modes, and can
also be bypassed. The operating mode for the Decoder is
controlled by the DECMODE input.
When DECMODE = LOW, the Decoder is bypassed and raw
10-bit characters are passed to the Output Register. In this
mode, channel bonding is not possible, the Receive Elasticity
Buffers are bypassed, and RXCKSEL must be MID. This clock
mode generates separate RXCLKx± outputs for each receive
channel.
When DECMODE = MID (or open), the 10-bit transmission
characters are decoded using Table 26 and Table 27. Received
Special Code characters are decoded using the Cypress column
of Table 27.
When DECMODE = HIGH, the 10-bit transmission characters
are decod ed us i n g Table 26 and Table 27. Received Special
Code characters are decoded using the Alternate column of
Table 27.
In all settings where the Decoder is enabled, the receive paths
may be operated as separate channels or bonded to form
various multi-channel buses.
Receive BIST Operation
The Receiver interfaces contain internal pattern generators that
can be used to validate both device and link operation. These
generators are enabled by the associated BOE[x] signals listed
in Table 10 (when the BISTLE latch enable input is HIGH). When
enabled, a register in the associated receive channel becomes
a pattern generator and checker by logically converting to a
Linear Feedback Shift Register (LFSR). This LFSR generates a
511-character sequence that includes all Data and Special
Character codes, including the explicit violation symbols. This
provides a predictable yet pseudo- random sequence that can
be matched to an identical LFSR in the attached Transmitter(s).
If the receive channels are configured for common clock
operation (RXCKSEL ≠MID) each pass is preceded by a
16-character Word Sync Sequence. When synchronized with the
received data stream, the associated Receiver checks each
character in the Decoder with each character generated by th e
LFSR and indicates compare errors and BIST status at the
RXSTx[2:0] bits of the Output Register . See Table 22 for details.
When the BISTLE signal is HIGH, any BOE[x] input that is LOW
enables the BIST generator/checker in the associated Receive
channel (or the BIST generator in the associated Transmit
channel). When BISTLE returns LOW, the values of all BOE[x]
signals are captured in the BIST En able Latch. These values
remain in the BIST Enable Latch until BISTLE is returned HIGH.
All captured signals in the BIST Enable Latch are set HIGH (i.e.,
BIST is disabled) following a device reset (TRSTZ is sampled
LOW).
When BIST is first recognized as being enabled in the Receiver ,
the LFSR is preset to the BIST-loop start-code of D0.0. This D0.0
character is sent only once per BIST loop. The status of the BIST
progress and any character mismatches is presented on the
RXSTx[2:0] status outputs.
Code rule violations or running disparity errors that occur as part
of the BIST loop do not cause an error indication. RXSTx[2:0]
indicates 010b or 100b for one character period per BIST loop to
indicate loop completion. This status can be used to check test
pattern progress. These same status values are presented when
the Decoder is bypassed and BIST is enabled on a receive
channel.
The status reported on RXSTx[2:0] by the BIST state machine
are listed in Table 22. When Receive BIST is enabled, the same
status is reported on the receive status outputs regardless of the
state of DECMODE.
The specific patterns checked by each receiver are described in
detail in the Cypress application note “HOTLink Built-In
Self-Test.” The sequence compared by the
CYP(V)15G0401DXB when RXCKSEL = MID is identical to that
in the CY7B933 and CY7C924DX, allo wing interoperable
systems to be built when used at compatible serial signaling
rates.
If the number of invalid characters received ever exceeds the
number of valid characters by sixteen, the receive BIST state
machine aborts the compare operations and resets the LFSR to
the D0.0 state to look for the start of the BIST sequence again.
When the receive paths are configured for common clock
operation (RXCKSEL ≠MID), each pass must be preceded by a
16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations. This
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 26 of 55
is automatically generated by the transmi tter whe n its local
RXCKSEL ≠MID and Encoder is enabled (TXMODE[1] ≠ LOW).
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the Low Latency
Framer is enabled (RFMODE = LOW), the Framer will misalign
to an aliased framing character within the BIST sequence. If the
Alternate Multi-Byte Framer is enabled (RFMODE = HIGH) and
the Receiver outputs are clocked relative to a recovered clock, it
is necessary to frame the Receiver before BIST is enabled.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is
designed to support multiple clocking modes. These buffers
allow data to be read using an Elasticity Buffer read-clock that is
asynchronous in both frequency an d phase from the Elasticity
Buffer write clock, or to use a read clock that is frequency
coherent but with uncontrolled phase relative to the Elasticity
Buffer write clock.
Each Elasticity Buffer is 10-characters deep, and suppo rts a
twelve-bit wide data path. It is capable of supporting a decoded
character, three status bits, and a parity bit for each character
present in the buffer. The write clock for these buffers is always
the recovered clock for the associated read channel.
The read clock for the Elasticity Buffers may come from one of
three selectable sources. It may be a
■Character-rate REFCLK (RXCKSEL = LOW and DECMODE ≠
LOW)
■Recovered clock from an alternate receive channel (RXCKSEL
= HIGH and DECMODE ≠ LOW).
These Elasticity Buffers are also used to align the output data
streams when multiple channels are bonded together. More
details on how the Elasticity Buffer is used for Independent
Channel Modes and Channel Bonded Modes is discussed in the
next section. The Elasticity Buffers are bypassed whe never th e
Decoders are bypassed (DECMODE = LOW). When the
Decoders and Elasticity Buffers are bypassed, RXCKSELx must
be set to MID.
Receive Modes
The operating mode of the receive path is set through the
RXMODE[1:0] inputs. The ‘Reserved for test’ settings
(RXMODE0 = M) is not allowed, even if the receiver is not being
used, as it will stop normal function of the device. When the
decoder is disabled, the RXMODE [1:0] settings are ignored as
long as they are not test modes. These modes determine the
type (if any) of channel bonding and status reporting. The
different receive modes are listed in Table 14.
Independent Channel Modes
In independent channel modes (RX Modes 0 and 2, where
RXMODE[1] = LOW), all four receive paths may be clocked in
any clock mode selected by RXCKSEL.
When RXCKSEL = LOW, all four receive channels are clocked
by REFCLK. RXCLKB± and RXCLKD± outputs are disabled
(High-Z), and the RXCLKA± and RXCLKC± outputs present a
buffered and delayed form of REFCLK. In this mode, the Receive
Elasticity Buffers are enabled. For REFCLK clocking, the
Elasticity Buffers must be able to insert K28.5 characters and
delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however , the actual timing on
these insertions and deletions is controlled in part by the how the
transmitter sends its data. Insertion of a K28.5 character can only
occur when the receiver has a framing character in the Elasticity
Buffer . Likewise, to delete a framing character , one must also be
present in the Elasticity Buffer. To prevent a receive buffer
overflow or underflow on a receive channel, a minimum density
of framing characters must be present in the received data
streams.
When RXCKSEL = MID (or open), each received channel Output
Register is clocked by the recovered clock for that channel. Since
no characters may be added or deleted, the receiver Elasticity
Buffer is bypassed.
When RXCKSEL = HIGH in indepen dent channel mode, all
channels are clocked by the selected recovered clock. This
selection is made using the RXCLKB+ and RXCLKD+ signals as
inputs per Table 15. This selected clock is always output on
RXCLKA± and RXCLKC±. In this mode the Receive Elasticity
Buffers are enabled. When data is output using a recovered
clock (RXCKSEL = HIGH), the receive channels are not allowed
to insert and delete characters, except as necessary for Elasticity
Buffer alignment.
When the Elasticity Buffer is used, prior to reception of valid data,
a Word Sync Sequence (or at least four framing characters) must
be received to center the Elasticity Buffers. The Elasticity Buffer
may also be centered by a device reset operation initiated by
TRSTZ input. However, following such an event, the
CYP(V)15G0401DXB also requires a framing event before it will
correctly decode characters. When RXCKSEL = HIGH, since the
Elasticity Buffer is not allowed to insert or delete framing
characters, the transmit clocks on all received channels must all
be from a common source.
Table 14. Re ce i ve O pe r ating Modes
RX Mode Operating Mode
Mode
Number
RXMODE
[1:0]
Channel
Bonding RXSTx Status Reporting
0 LL Independent Status A
1LM Reserved for test
2 LH Independent Status B
3 ML Dual Status A
4MM Reserved for test
5 MH Dual Status B
6 HL Quad Status A
7HM Reserved for test
8 HH Quad Status B
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Document #: 38-02002 Rev. *N Page 27 of 55
Dual-Channel Bonded Modes
In dual-channel bonded modes (RX Modes 3 and 5, where
RXMODE[1] = MID or open), the associated receive channel pair
Output Registers must be clocked by a common clock. This
mode does not operate when RXCKSEL = MID.
Proper operation in this mode requires that the associated
transmit data streams are clocked from a common reference with
no long-term character slippage between the bonded channels.
In dual-channel mode this means that channels A and B must be
clocked from a common reference, and channels C and D must
be clocked from a common reference.
Prior to the reception of valid data, a Word Sync Sequence (or
that portion necessary to align the receive buffers) must be
received on the bonded channels (w ithin the allowable
inter-channel skew window) to allow the Receive Elasticity
Buffers to be centered. While normal characters may be output
prior to this alignment event, they are not necessarily aligned to
the same word boundaries as when they were transmitted.
When RXCKSEL = LOW, all four receive channels are clocked
by REFCLK. RXCLKB± and RXCLKD± outputs are disabled
(High-Z), and RXCLKA± and RXCLKC± present a buffered and
delayed form of REFCLK. In this mode, the Receive Elasticity
Buffers are enabled. For REFCLK clocking, the Elasticity Buffers
must be able to insert K28.5 characters and delete framing
characters as appropriate. While these insertions and deletions
can take place at any time, they must occur at the same time on
both channels that are bonded together. This is necessary to
keep the data in the bonded channel-pairs properly aligned. This
insert and delete process is controlled by the channel selected
using the RXCLKB+ and RXCLKD+ inputs as listed in Table 16.
When RXCKSEL = HIGH, the A and B channels are clocked by
the selected recovered clock, and the C and D channels are
clocked by the selected recovered clock, as shown in Table 16.
The output clock for the channel A/B bonded-pair is output
continuously on RXCLKA±. The clock source for this output is
selected from the recovered clock for channel A or channel B
using the RXCLKB+ input. The output clock for the channel C/D
bonded-pair is output continuously on RXCLKC±. The clock
source for this output is selected from the recovered clock for
channel C or channel D using the RXCLKD+ input.
When data is output using a recovered clock (RXCKSEL =
HIGH), receive channels are not allo wed to insert and delete
characters, except as necessary for Elasticity Buffer alignment.
Quad Channel Modes
In quad-channel modes (RX modes 6 and 7, where RXMODE[1]
= HIGH), all four receive channel Output Registers mu st be
clocked by a common clock. This mode does not operate when
RXCKSEL = MID.
Proper operation in this mode requires that the four transmit data
streams are clocked from a common reference with no long-term
character slippage between the bonded channels. In
quad-channel modes this means that the transmit channels A, B,
C, and D must all be clocked from a common reference.
Prior to the delivery of valid data, at least one Word Sync
Sequence (or that portion necessary to align the receive buffers)
must be received on all four bonded channe ls (within the
allowable inter-channel skew win dow) to allow the Receive
Elasticity Buffers to be centered and aligned.
When RXCKSEL = LOW, all four receive channels are clocked
by the internal derivative of REFCLK. RXCLKB± and RXCLKD±
outputs are disabled (High-Z), and RXCLKA± and RXCLKC±
present a buffered and delayed form of REFCLK. In this mode
the Receive Elasticity Buffers are enabled. For REFCLK
clocking, the Elasticity Buffers must be able to insert K28.5
characters and delete framing characters as appropriate. While
these insertions and deletions can take place at any time, they
must occur at the same time on all four channels. This is
necessary to keep the data in the four bonded channels properly
aligned. This insert and delete process is controlled by the
master channel selected using the RXCLKB+ and RXCLKD+
inputs as listed in Table 15.
When RXCKSEL = HIGH, all four receive-channel Output
Registers are clocked by the selected recovered clock. The clock
select for quad channel mode is the same as that for
independent channel operation. This selection is made using the
RXCLKB+ and RXCLKD+ inputs, as shown in Table 15. The
output clock for the four bonded channels is output continuously
on RXCLKA± and RXCLKC±.
When data is output using a recovered clock (RXCKSEL =
HIGH), receive channels are not allo wed to insert and delete
characters, except as necessary for Elasticity Buffer alignment.
Table 15. Independent and Quad Channel Bonded
Recovered Clock or Master Channel Select
RXCLKB+ RXCLKD+ RXCLKA±/RXCLKC± Clock
Source
0 0 RXCLKA
0 1 RXCLKB
1 0 RXCLKC
1 1 RXCLKD
Table 16. Du al -C hannel Bonde d Rec o vered Clock Se le ct
RXCLKB+ RXCLKD+ Clock Source
RXCLKA±RXCLKC±
0XRXCLKA
1XRXCLKB
X0 RXCLKC
X1 RXCLKD
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Document #: 38-02002 Rev. *N Page 28 of 55
Multi-device Bonding
When configured for quad-channel bo nding (RXMODE[1] =
HIGH) it is also possible to bond channels across multiple
devices. This form of channel bonding is only possible when
RXCKSEL = LOW , selecting REFCLK as the output clock for all
channels on all devices.
In this mode, the BONDST[1:0] signals of all bonding devices
must be connected together to pass Elasticity buffer
management events between the devices. This is necessary to
keep the data on all bonded devices in common alignment. One
device must be selected as the controlling device by driving the
MASTER pin on that device LOW. All other devices must have
their MASTER pin HIGH to prevent having multiple active drivers
on the BONDST bus. Within the master device, a single receive
channel is selected as the master channel for generation of the
different BONDST[1:0] status. This selection is made using the
RXCLKB+ and RXCLKD+ inputs, as shown in Table 15. This
allows the master channel selection to be changed through
external control of the MASTER, RXCLKB+, and RXCLKD+
inputs.[17]
In this mode, the BOND_ALL signal of all bonding devices must
be connected together. The BOND_ALL signal is a wired AND
and the signal is LOW during the bonding resolution process.
After the completion of bonding resolution it returns HIGH.
Power Control
The CYP(V)15G0401DXB supports user control of the powered
up or down state of each transmit and receive channel. The
receive channels are controlled by th e RXLE signal and the
values present on the BOE[7:0] bus. The transmit channels are
controlled by the OELE signal and the values present on the
BOE[7:0] bus. Powering down unused channels will save power
and reduce system heat generation. Controlling system power
dissipation will improve the system performance.
Receive Channels
When RXLE is HIGH, the signals on the BOE[7:0] inputs directly
control the power enables for the receive PLLs and analog
circuits. When a BOE[7:0] input is HIGH, the associated receive
channel [A through D] PLL and analog logic are active. When a
BOE[7:0] input is LOW, the associated receive channel [A
through D] PLL and analog circuits are powered down. When
RXLE returns LOW, the last values present on the BOE[7:0]
inputs are captured in the Receive Channel Enable Latch. The
specific BOE[7:0] input signal associated with a receive channel
is listed in Table 10.
If a single channel of a bonded-pair or quad is disabled, this may
prevent the other receive channels from bonding. If the disabled
channel has been selected as the ma ster channel for
insert/delete functions, or for recovered clock select, these
functions will not operate. Any disabled receive channel will
indicate a constant LFIx output.
When a disabled receive channel is re-enabled, the status of the
associated LFIx output and data on the parallel outputs for the
associated channel may be indeterminate for up to 2 ms.
Transmit Channels
When OELE is HIGH, the signals on the BOE[7:0] inputs directly
control the power enables for the Serial Drivers. When a BOE[x]
input is HIGH, the associated Serial Driver is enabled. When a
BOE[x] input is LOW, the associated Serial Driver is disabled and
powered down. If both Serial Drivers of a channel are disabled,
the internal logic for that transmit channel is powered down.
When OELE returns LOW, the values present on the BOE[7:0]
inputs are latched in the Output Enable Latch.
Device Reset State
When the CYP(V)15G0401DXB is reset by assertion of TRSTZ,
the T ransmit Enable and Receive Enable Latches are both
cleared, and the BIST Enable Latch is preset. In this state, all
transmit and receive channels are disabled, and BIST is disabled
on all channels.
Following a device reset, it is necessary to enable the tra nsmit
and receive channels used for normal operation. This can be
done by sequencing the appropriate values on the BOE[7:0]
inputs while the OELE and RXLE signals are raised and lowered.
For systems that do not require dynamic control of power, or
want the device to power up in a fixed configuration, it is also
possible to strap the RXLE and OELE control signals HIGH to
permanently enable their associated latches. Connection of the
associated BOE[7:0] signals to a stable HIGH will then enable
the respective transmit and receive channels as soon as the
TRSTZ signal is deasserted.
Output Bus
Each receive channel presents a 12-signal output bus consisting
of
■An eight-bit data bus
■A three-bit status bus
■A parity bit.
The bit assignments of the Data and Status are dependent on the
setting of DEC MOD E. The bits are assigned as per Table 17.
Table 17. Output Register Bit Assignments [18]
Signal Name DECMODE = LOW DECMODE = MID or
HIGH
RXSTx[2] (LSB) COMDETx RXSTx[2]
RXSTx[1] DOUTx[0] RXSTx[1]
RXSTx[0] DOUTx[1] RXSTx[0]
RXDx[0] DOUTx[2] RXDx[0]
RXDx[1] DOUTx[3] RXDx[1]
RXDx[2] DOUTx[4] RXDx[2]
RXDx[3] DOUTx[5] RXDx[3]
RXDx[4] DOUTx[6] RXDx[4]
RXDx[5] DOUTx[7] RXDx[5]
RXDx[6] DOUTx[8] RXDx[6]
RXDx[7] (MSB) DOUTx[9] RXDx[7]
Notes
17.Any change in the master device or channel must be followed by assertion of TRSTZ to properly initialize the device.
18.The RXOPx outputs are also driven from the associated Output Register, but their interpretation is under the separate control of PARCTL.
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Document #: 38-02002 Rev. *N Page 29 of 55
When the 10B/8B Decoder is bypassed (DECMODE = LOW),
the framed 10-bit character and a single status bit (COMDET)
are presented at the receiver Output Register . The status output
indicates if the character in the Output Register is one of the
selected framing characters. The bit usage and mapp ing of the
external signals to the raw 10B transmission character is shown
in Table 18.
The COMDETx outputs are HIGH when the character in the
Output Register for the associated channel contains the selected
framing character at the proper character boundary, and LOW
for all other bit combinations.
When the Low-Latency Framer and half-rate receive port
clocking are also enabled (RFMODE = LOW , RXRATE = HIGH,
and RXCKSEL ≠ LOW), the Framer will stretch the recovered
clock to the nearest 20-bit boundary such that the rising edge of
RXCLKx+ occurs when COMDETx is present on the associated
output bus.
.
When the Cypress or Alternate Mode Framer is enabled an d
half-rate receive port clocking is also enabled (RFMODE ≠LOW
and RXRATE = HIGH), the output clock is not modified when
framing is detected, but a single pipeline stage may be added or
subtracted from the data stream by the Framer logic such that
the rising edge of RXCLKx+ occurs when COMDETx is present
on the associated output bus.
This adjustment only occurs when the Framer is enabled (RFEN
= HIGH). When the Framer is disabled, the clock boundaries are
not adjusted, and COMDETx may be asserted during the rising
edge of RXCLK– (if an odd number of characters were received
following the initial framing).
Parity Generation
In addition to the eleven data and status bits that are presented
by each channel, an RXOPx parity output is also available on
each channel. This allows the CYP(V)15G0401DXB to support
ODD parity generation for each channel. To handle a wide range
of system environments, the CYP(V)15G0401DXB supports
different forms of parity generation, including no parity.
When the decoders are enabled (DECMODE ≠ LOW), parity can
be generated on
■The RXDx[7:0] character
■The RXDx[7:0] character and RXSTx[2:0 ] status.
When the decoders are bypassed (DECMODE = LOW), parity
can be generated on
■The RXDx[7:0] and RXSTx[1:0] bits
■The RXDx[7:0] and RXSTx[2:0] bits.
These modes differ in the number of bits which are included in
the parity calculation. Only ODD parity is provided which ensures
that at least one bit of the data bus is always a logic-1. Those bits
covered by parity generation are listed in Table 19.
Parity generation is enabled through the three-level select
PARCTL input. When PARCTL = LOW, parity checking is
disabled, and the RXOPx outputs are all disabled (High-Z).
When PARCTL = MID (open) and the decoders are enabled
(DECMODE ≠LOW), ODD parity is generated for the received
and decoded character in the RXDx[7:0] signals and is
presented on th e associated RXOPx output. When
PARCTL = MID and the decoders are bypassed
(DECMODE = LOW), ODD parity is generated for the received
and decoded character in the RXDx[7:0] and RXSTx[1:0] bit
positions. When PARCTL = HIGH, ODD parity is generated for
the RXDx[7:0] and the associated RXSTx[2:0] status bits.
Table 18. Decoder Bypass Mode (DECMODE = LOW)
Signal Name Bus Weight 10Bit Name
RXSTx[2] (LSB) COMDETx
RXSTx[1] 20a
RXSTx[0] 21b
RXDx[0] 22c
RXDx[1] 23d
RXDx[2] 24e
RXDx[3] 25i
RXDx[4] 26f
RXDx[5] 27g
RXDx[6] 28h
RXDx[7] (MSB) 29j
Table 19. Output Register Parity Generation
Signal
Name
Receive Parity Generate Mode (PARCTL)
LOW
[19] MID HIGH
DECMODE
= LOW DECMODE
≠ LOW
RXSTx[2] X [20]
RXSTx[1] X X
RXSTx[0] X X
RXDx[0] X X X
RXDx[1] X X X
RXDx[2] X X X
RXDx[3] X X X
RXDx[4] X X X
RXDx[5] X X X
RXDx[6] X X X
RXDx[7] X X X
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Document #: 38-02002 Rev. *N Page 30 of 55
Receive Status Bits
When the 10B/8B Decoder is enabled (DECMODE ≠ LOW),
each character presented at the Output Register includes three
associated status bits. These bits are used to identify:
■If the contents of the data bus are valid
■The type of character present
■The state of receive BIST operations (regardless of the state
of DECMODE)
■Character violations
■Channel bonding status.
These condi ti o ns no rmally overl ap ; e. g ., a val i d data char act er
received with incorrect running disparity is not reported as a valid
data character. It is instead reported as a Decoder violation of
some specific type. This implies a hierarchy or priority level to the
various status bit combinations. The hierarchy and value of each
status is listed in Table 20 when chan nel bonding enabled and
in Table 21 when channel bonding is disabled.
Within these status codes, there ar e th re e mo de s of status
reporting. The two data status reporting modes (Type A and Type
B) are selectable through the RXMODE[0] input. These status
types allow compatibility with legacy systems, while allowing full
reporting in new systems. These status values are generated in
part by the Receive Synchronization State Machine, and are
listed in Table 20. The receive status when the channels are
operated independently with channel bonding disabled is shown
in Table 21. The receive status when Receive BIST is enabled is
shown in Table 22.
Receive Synchronization State Machine when
Channel Bonding is enabled
Each receive channel contains a Receive Synchronization S tate
Machine that is enabled whenever the receive channels are
configured for channel bonding (RXMODE[1] ≠ LOW). This
machine handles loss and recovery of bit, channel, and word
framing, and part of the control for channel bonding. Separate
forms of the state machine exist for the two different types of
status reporting. When operated without channel bonding
(RXMODE[1] = LOW , RX Modes 0 and 2), these state machines
are disabled and characters are decoded directly as shown in
Table 21.
Status Type-A Receive State Machine
This machine has four primary states: NO_SYNC, RESYNC,
COULD_NOT_BOND, and IN_SYNC, as shown in Figure 2. The
IN_SYNC state can respond with multiple status types, while
others can respond with only one type.
Status Type-B Receive State Machine
This machine has four primary states: NO_SYNC, RESYNC,
IN_SYNC, and COULD_NOT_BOND, as shown in Figure 3.
Some of these states can respond with only one status value,
while others ca n respond with multiple st atus types.
Table 20. Receive Character Status Bits when Channel Bonding is enabled
RXSTx
[2:0] Priority Description
RX Status A RX Status B
000 7Normal Character Receive d. The valid Data character on the output bu s meets all the formatting require-
ments of Data characters listed in Table 26.
001 7Special Code Detected. The valid special character on the output bus meets all the formatting requirements
of the Special Code characters listed in Table 27, but is not the presently selected framing character or a
decoder violation indication.
010 2Receive Elasticity Buffer Underrun/Overrun Error .
The receive buffer was not able to add/drop a K28.5 or
framing character.
Channel Lock Detected. Asserts when the bonded
channels have detected RESYNC within the allotted
window. Presented only on the last cycle before
aligned data is presented.
011 5Framing Character Detected. This indicates that a character matching the patterns identified as a framing
character (as selected by FRAMCHAR) was detected. The decoded value of this character is present to the
associated output bus.
100 4Codeword Violation. The character on the output bus is a C0.7. This indicates that the received character
cannot be decoded into any valid character.
101 1Loss of Sync. The character on the bus is invalid, due
to an event that has caused the receive channels to
lose synchronization. When channel bonding is
enabled, this indicates that one or more channels have
either lost bit synchronization (loss of character
framing), or that the bonded channels are no longer in
proper character alignment. When the channels are
operated independently (with the decoder enabled),
this indicates a PLL Out of Lock condition.
Loss of Sync. The character on the bus is invalid, due
to an event that has caused the receive channels to
lose synchronization. When channel bonding is
enabled, this indicates that one or more channels have
either lost bit synchronization (loss of charac te r
framing), or that the bonded channels are no longer in
proper character alignment. When the channels are
operated independently (with the decoder enabled),
this indicates a PLL Out of Lock condition. Also used
to indicate Receive Elasticity Buffer underflow/
overflow errors.
110 6Running Disparity Error. Th e character on the output bus is a C4.7, C1 .7, or C2.7.
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Document #: 38-02002 Rev. *N Page 31 of 55
Figure 2. Status Type-A Receive State Machine for Channel Bonding
111 3Resync. The receiver state machine is in the Resynchronization state. In this state the data on the output bus
reflects the presently decoded FRAMCHAR.
Table 20. Receive Character Status Bits when Channel Bonding is enabled (continued)
RXSTx
[2:0] Priority Description
RX Status A RX Status B
Notes
19.Receive path parity output drivers (RXOPx) ar e disabled (High-Z) when PARCTL = LOW.
20.When the Decoder is bypasse d (DECMODE = LOW) an d BIST is not enabled ( Receive BIST Latch output is HIGH ), RXSTx[2] i s driven to a log ic- 0, except when the
character in the output buffer is a framing character.
#State Transition Conditions
1 (BOND_INH = LOW) AND (Deskew Window Expired)
2 FRAMCHAR Detected
3 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Any Decoder Error)
4 Four Consecutive FRAMCHAR Detected
5 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR
(Invalid Minus Valid = 4)
6 Valid Character other than a FRAMCHAR
NO_SYNC
RXSTx=101
IN_SYNC
RESYNC
RXSTx=111
COULD_NOT_BOND
RXSTx=101
Reset
2
1
4
5
4
3
6
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Document #: 38-02002 Rev. *N Page 32 of 55
Figure 3. Status Type-B Receive State Machine for Channel Bonding
#Condition
1(BOND_INH
= LOW OR Master Channel Did Not Bond) AND (Deskew Window Expired) OR (Decoder Error)
2 FRAMCHA R D etected
3 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Any Decoder Error) OR (BOND_INH = LOW) OR
(Master Channel Did Not Bond) AND (Deskew Windo w Expired))
4 Four Consecutive FRAMCHAR Detected
5 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR (Invalid
Minus Valid = 4)
6 (Last FRAMCHAR Before a Valid Character) AND (Bonded to MASTER Channel)
7 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock)
NO_SYNCIN_SYNC
RESYNC
RXSTx=111
RESYNC_IN_SYNC
RXSTx=011
Reset
22
34
RXSTx = 101
5
RXSTx = 010
66
RXSTx = 010
RXSTx = 111
17
RXSTx = 101
4
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Document #: 38-02002 Rev. *N Page 33 of 55
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXSTx[2:0] bits
identify the present state of the BIST compare operation.
The BIST state machine has multiple states, as shown in
Figure 4 and Table 22. When the receive PLL detects an
out-of-lock condition, the BIST state is forced to the Start-of-BIST
state, regardless of the present state of the BIST state machine.
If the number of detected erro rs ever exceeds the number of
valid matches by greater than sixteen, the state machine is
forced to the WAIT_FOR_BIST state w her e it moni tors the
interface for the first character (D0.0) of the next BIST sequence.
Also, if the Elasticity Buffer ever hits an overflow/underflow
condition, the status is forced to the BIST_ST ART until the buffer
is recentered (approximately nine character periods).
To ensure compatibility between the source and destination
systems when operating in BIST modes, the sending and
receiving ends of the link must use the same receive clock setup.
(RXCKSEL = MID or RXCKSEL ≠MID).
JTAG Support
The CYP(V)15G0401DXB contains a JT AG port to allow system
level diagnosis of device interconnect. Of th e available JTAG
modes, only boundary scan is supported. This capability is
present only on the LVTTL inputs, LVTTL outputs and the
REFCLK± clock input. The high-speed serial inputs and outputs
are not part of the JTAG test chain.
JTAG ID
The JTAG device ID for the CYP(V)15G0401DXB is
‘1C800069’x.
Three-level Select Input s
Each Three-level select input reports as two bits in the scan
register . These bits report the LOW, MID, and HIGH state of the
associated input as 00, 10, and 11, respectively.
Table 21. Receive charac ter status when channels are operated in independent mode (RXMODE[1:0 ] = LL or LH)
RXSTx[2:0] Priority Type-A Status Type-B status
000 7 Normal Character Received. The valid data character with the correct running disparity received
001 7 Special Code Detected. Special code other than the selected framing character or decoder
violation received
010 2 Receive Elasticity Buffer underrun/overrun
error. The receive elasticity buffer was not able to
add/drop a K28.5 or framing character.
INVALID
011 5 Framing Character Detected. This indicates that a character matching the patterns identified as
a framing character was detected. The decoded value of this character is present on the associ-
ated output bus.
100 4 Codeword V iolation. The character on the output bus is a C0.7. This indicates that the received
character cannot be decoded into any valid character.
101 1 PLL Out Of Lock Indication
110 6 Running Disparity Error. The chara c t er on th e ou tp ut bus is a C4.7, C1.7 or C2.7
111 3 INVALID
Table 22. Receive charac ter status when channels are operated to receive BIST Data
RXSTx[2:0] Priority Receive BIST Status
(Receive BIST = Enabled)
000 7 BIST Data Compare. Character compared correctly
001 7 BIST Command Compare. Character compared correctly
010 2 BIST Last Good. Last Character of BIST sequence detected and valid.
011 5 RESER VED for TEST
100 4 BIST Last Bad. Last Chara cter of BIST sequence detected invalid.
101 1 BIST Start. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock cond ition, and Elasticity Buffer
overflow/underfl ow conditions.
110 6 BIST Error. While comparing characters, a mismatch was found in one or more of the decoded
character bits.
111 3 BIST W ait. The receiver is comparing characters. but has not yet found the start of BIST character
to enable the LFSR.
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Document #: 38-02002 Rev. *N Page 34 of 55
Figure 4. Receive BIST State Machine
Receive BIST
Detected LOW
Monitor Data
Received RXSTx =
BIST_START (101)
No
RX PLL
Out of Lock
Yes, RXSTx = BIST_COMMAND_COMPARE (001)
OR BIST_DATA_COMPARE (000)
Compare
Next Character
Auto-Abort
Condition
Mismatch
End-of-BIST
State
Yes, RXSTx =
BIST_LAST_BAD (100)
Yes
No
No, RXSTx =
BIST_ERROR (110)
Data or
Command
Match
Command
RXSTx =
BIST_COMMAND_COMPARE (001)
End-of-BIST
State
Data
Yes, RXSTx =
BIST_LAST_GOOD (010)
No
RXSTx =
BIST_DATA_COMPARE (000)
Elasticity
Buffer Error
St art of
BIST Detected
RXSTx =
BIST_WAIT (111)
Yes
RXSTx =
BIST_START (101)
No
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Document #: 38-02002 Rev. *N Page 35 of 55
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User gui d el i ne s are not tested.
Storage temperature................................... –65°C to +150°C
Ambient temperature with power applied....–55°C to +125°C
Supply voltage to ground potential ...............–0.5 V to +3.8 V
DC voltage applied to LVTTL outputs
in High-Z State.................. ... ... .............–0.5 V to VCC + 0.5 V
Output current into LVTTL Outputs (LOW)..................60 mA
DC input voltage.......................... ........–0.5 V to VCC + 0.5 V
Static discharge voltage...........................................> 2000 V
(per MIL-STD-883, Method 3015)
Latch-up current .....................................................> 200 mA
Power-up Requirements
The CYP(V)15G0401DXB requires one power-supply. The
voltage on any input or I/O pin cannot exceed the power pin
during power-u p
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C +3.3 V ±5%
Industrial –40°C to +85°C +3.3 V ±5%
Notes
21.Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
22.This is the minimum difference in vo ltage between the true and complement inputs required to ensure detect ion of a logic-1 or logic-0. A logic-1 exists when the true
(+) input is more positive than the complement (−) input. A logic-0 exi sts when the complement (−) input is more positive than tr ue (+) input.
23.The common mode range define s the al lowable ra nge of REFCLK + and REFCLK− when REFCLK+ = REFCLK−. This marks the zero-crossing between t he tr ue and
complement input s as the signal switches between a logic-1 and a logic-0.
CYP(V)15G0401DXB DC Electrical Characteristics Over the Operating Range
Parameter Description Test Condition s Min Max Unit
LVTTL-compatible Outputs
VOHT Output HIGH Voltage IOH = −4 mA, VCC = Min 2.4 VCC V
VOLT Output LOW Voltage IOL = 4 mA, VCC = Min 0 0.4 V
IOST Output Short Circuit Current VOUT = 0 V[21] –20 –100 mA
IOZL High-Z Output Leakage Current –20 20 μA
LVTTL-compatible Inputs
VIHT Input HIGH Voltage 2.0 VCC + 0.3 V
VILT Input LOW Voltage –0.5 0.8 V
IIHT Input HIGH Current REFCLK Input, VIN = VCC 1.5 mA
Other Inputs, VIN = VCC +40 μA
IILT Input LOW Current REFCLK Input, VIN = 0.0 V –1.5 mA
Other Inputs, VIN = 0.0 V –40 μA
IIHPDT Input HIGH Current with internal pull-down VIN = VCC +200 μA
IILPUT Input LOW Current with internal pull-up VIN = 0 . 0 V –200 μA
LVDIFF Inputs: REFCLK±
VDIFF[22] Input Differential V oltage 400 VCC mV
VIHHP Highest Input HIGH Voltage 1.2 VCC V
VILLP Lowest Input LOW vo ltage 0.0 VCC/2 V
VCOMREF[23] Common Mode Range 1.0 V CC – 1.2 V V
Three-level Inputs
VIHH Three-level Input HIGH Voltage Min ≤ VCC ≤ Max 0.87 * VCC VCC V
VIMM Three-level Input MID Voltage Min ≤ VCC ≤ Max 0.47 * VCC 0.53 * VCC V
VILL Three-level Input LOW Voltage Min ≤ VCC ≤ Max 0.0 0.13 * VCC V
IIHH Input HIGH Current VIN = VCC 200 μA
IIMM Input MID current VIN = VCC/2 –50 50 μA
IILL Input LOW curren t VIN = GND –200 μA
CYP15G0401DXB
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Document #: 38-02002 Rev. *N Page 36 of 55
Test Loads and Waveforms
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
VOHC Output HIGH Voltage
(VCC referenced) 100Ω differential load VCC – 0 . 5 VCC – 0.2 V
150Ω differential load VCC – 0 . 5 VCC – 0.2 V
VOLC Output LOW Voltage
(VCC referenced) 100Ω differential load VCC – 1.4 VCC – 0. 7 V
150Ω differential load VCC – 1.4 VCC – 0. 7 V
VODIF Output Differential Voltage
|(OUT+) – (OUT–)| 100Ω differential loa d 450 900 mV
150Ω differential load 560 1000 mV
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±
VDIFFS [22] Input Differential Voltage |(IN+) − (IN−)| 100 1200 mV
VIHE Highest Input HIGH Voltage VCC V
VILE Lowest Input LOW Voltage VCC – 2.0 V
IIHE Input HIGH Current VIN = VIHE Ma x 1350 μA
IILE Input LOW Current VIN = VILE M i n –700 μA
VCOM [24, 25] Common Mode Input Range VCC – 1.95 VCC – 0.05 V
CYP(V)15G0401DXB DC Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Condition s Min Max Unit
Power Supply Typ[26] Max[27]
ICC Power Supply Current
REFCLK = Max Commercial 870 1060 mA
Industrial 1100 mA
ICC Power Supply Current
REFCLK = 125 MHz Commercial 830 1060 mA
Industrial 1100 mA
Notes
24.The common mode range defines th e all owable ran ge of I NPUT+ an d INPUT− when INPUT+ = INPUT−. This marks the zero- crossin g betwee n t he tru e and comple-
ment inputs as the signal switches between a logic-1 and a logic-0.
25.Not applicable for AC-coupled interfaces. For AC-coupled interfaces, VDIFFS requirement still needs to be satisfied.
26.Maximum ICC is measured with VCC = MAX, RXCKSEL = LOW, with all TX and RX channels and Serial Line Drivers enabled, sending a continuous alternating 01
pattern to the associated receive channel, and outputs unloaded.
27.Typical ICC is measured under similar conditions except with VCC = 3.3 V, TA = 25°C, RXCKSEL = LOW, with all TX and RX channels enabled and one Serial Line
Driver per transmit channel sending a conti nuous alternating 01 pattern t o the associated recei ve channel. The redunda nt outputs o n each channel are powered down
and the parallel outputs are unloaded.
28.Cypress uses constant cu rrent (ATE) load configuration s and f o rcing funct ions. This fig ure i s for refe rence o nly. 5-pF diff er ential load ref lect s t este r cap acit ance, an d
is recommended at low data rates only.
29.The LVTTL switching threshold is 1.4 V. All timing references are made relative to the point where th e signal edges crosses the threshold voltage.
30.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
2.0 V
0.8 V
GND
2.0 V
0.8 V
80% 20%
80%
20%
RL
3.0 V
Vth = 1.4 V
≤ 270 ps ≤ 270 ps
[29]
Vth = 1.4 V
3.3 V
R1
R2
R1 = 590Ω
R2 = 435Ω
(Includes fixture and
probe capacitance)
CL ≤ 7 pF
(a) LVTTL Output Test Load
RL = 100Ω
(b) CML Output Test Load
CL
(c) LVTTL Input Test Waveform (d) CML/LVPECL Input Test Waveform
≤ 1 ns ≤ 1 ns
VIHE
VILE
VIHE
VILE
[28]
[28]
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 37 of 55
CYP(V)15G0401DXB AC Characteristics Over the Operating Range
Parameter Description Min Max Unit
CYP(V)15G0401DXB Transmitter LVTTL Switching Characteristics Over the Operating Range
fTS TXCLKx Clock Frequency 19.5 150 MHz
tTXCLK TXCLKx Period 6.66 51.28 ns
tTXCLKH [30] TXCLKx HIGH Time 2.2 ns
tTXCLKL [30] TXCLKx LOW Time 2.2 ns
tTXCLKR[30, 31, 32] TXCLKx Rise Time 0.2 1.7 ns
tTXCLKF[30, 31, 32] TXCL Kx Fall Time 0.2 1.7 ns
tTXDS Tr ansmit Data Set-Up Time to TXCLKx↑ (TXCKSEL ≠ LOW) 1.7 ns
tTXDH Transmit Data Hold Time from TXCLKx↑ (TXCKSEL ≠ LOW) 0.8 ns
fTOS TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency 20 150 MHz
tTXCLKO TXCLKO Period 6.66 50 ns
tTXCLKOD+ TXCLKO+ Duty Cycle with 60% HIGH time –1.0 +0.5 ns
tTXCLKOD– TXCLKO– Duty Cycle with 40% HIGH time –0.5 +1.0 ns
CYP(V)15G0401DXB Receiver LVTTL Switching Characteristics Over the Operating Range
fRS RXCLKx Clock Output Frequency 9.75 150 MHz
tRXCLKP RXCLKx Period 6.66 102.56 ns
tRXCLKH RXCLKx HIGH Time (RXRATE = LOW) 2.33 [30] 26.64 ns
RXCLKx HIGH Time (RXRATE = HIGH) 5.66 52.28 ns
tRXCLKL RXCLKx LOW Time (RXRATE = LOW) 2.33 [30] 26.64 ns
RXCLKx LOW T ime (RXRATE = HIGH) 5.66 52.28 ns
tRXCLKD RXCLKx Duty Cycle centered at 50% –1.0 +1.0 ns
tRXCLKR [30] RXCLKx Rise Time 0.3 1.2 ns
tRXCLKF [30] RXCLKx Fall Time 0.3 1.2 ns
tRXDV– [33] Status and Data Valid Time to RXCLKx (RXCKSEL HIGH or MID) 5UI – 1.5 ns
Status and Data Valid Time to RXCLKx (HALF RA TE RECOVERED CLOCK) 5UI – 1.0 ns
tRXDV+ [33] Status and Data Valid Time From RXCLKx (RX CK SEL HIGH or MID) 5UI – 1.8 ns
Status and Data Valid Time From RXCLKx (HALF RATE RECOVERED
CLOCK) 5UI – 2.3 ns
Notes
31.The ratio of rise time to falling time must not vary by greater than 2:1.
32.For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
33.Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
34.The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the REFCLK duty cycle
cannot be as large as 30% – 70%.
35.Since this timing parameter is great er than t he min imum time perio d of REFCLK it sets an upper limit to the frequ ency in which REFCLKx can be used to clock th e
receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of tRREFDA and set-up time
of the upstream device. Whe n this condition is not true, RXCLKC± or RXCLKA± (a buf fered or delayed version of REFCLK when RXCKSELx = LOW) could be used
to clock the receive data out of the device.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 38 of 55
CYP(V)15G0401DXB REFCLK Switching Characteristics Over the Operating Range
fREF REFCLK Clock Frequency 19.5 150 MHz
tREFCLK REFCLK Period 6.66 51.28 ns
tREFH REFCLK HIGH Time (TXRATE = HIGH) 5.9 ns
REFCLK HIGH Time (TXRATE = LOW) 2.9 [30] ns
tREFL REFCLK LOW Time (TXRATE = HIGH) 5.9 ns
REFCLK LOW Time (TXRATE = LOW) 2.9 [30] ns
tREFD [34] REFCLK Duty Cycle 30 70 %
tREFR [30, 31, 32] REFCLK Rise Time (20% – 80%) 2ns
tREFF [30, 31, 32] REFCLK Fall Time (20% – 80%) 2ns
tTREFDS Transmit Data Setup Time to REFCLK (TXCKSEL = LOW) 1.7 ns
tTREFDH Transmit Data Hold Time from REFCLK (TXCKSEL = LOW) 0.8 ns
tRREFDA[35] Receive Data Access Time from REFCLK (RXCKSEL = LOW) 9.5 ns
tRREFDV Receive Data Valid Time from REFCLK (RXCKSEL = LOW) 2.5 ns
tREFADV– Received Data Valid Time to RXCLKA (RXCKSEL = LOW) 10UI – 4.7 ns
tREFADV+ Received data valid time from RXCLKA (RXCKSEL = LOW) 0.5 ns
tREFCDV– Received data valid time to RXCLKC (RXCKSEL = LOW) 10UI – 4.3 ns
tREFCDV+ Received data valid time from RXCLKC (RXCKSEL = LOW) –0.2 ns
tREFRX [12] REFCLK frequency referenced to received clock period –1500 +1500 ppm
CYP(V)15G0401DXB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
Parameter Description Condition Min Max Unit
tBBit Time 5100 666 ps
tRISE [30] CML Output Rise Time 20% – 80% (CML Test
Load) SPDSEL = HIGH 60 270 ps
SPDSEL = MID 100 500 ps
SPDSEL = LOW 180 1000 ps
tFALL [30] CML Output Fall Time 80% – 20% (CML Test
Load) SPDSEL = HIGH 50 270 ps
SPDSEL = MID 100 500 ps
SPDSEL = LOW 180 1000 ps
tDJ [30, 36, 38] Deterministic Jitter (peak-peak) IEEE 802.3z[39] 25 ps
tRJ [30, 37, 38 ] Random Jitter (σ)IEEE 802.3z[39] 11 ps
tTXLOCK Tr ansmit PLL lock to REFCLK 200 us
CYP(V)15G0401DXB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range
tRXLOCK Receive PLL lock to input data stream (cold start) 376K UI[40]
Receive PLL lock to input data stream 376K UI
tRXUNLOCK Receive PLL Unlock Rate 46 UI
tJTOL[38] Total Jitter Tolerance IEEE 802.3z[39] 600 ps
tDJTOL[38 ] Deterministic Jitter Tolerance IEEE 802.3z[39] 370 ps
CYP(V)15G0401DXB AC Characteristics Over the Operating Range (continued)
Parameter Description Min Max Unit
Notes
36.While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range.
37.While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating
range.
38.Total jitter is calculated at an assumed BER of 1E –12. Hence: total jitter (tJ) = (tRJ * 14) + tDJ.
39.Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259M, SMPTE 292M, CP RI, ESCON, FICON, Fibre Channel and DVB-ASI.
40.Receiver UI (Unit Interval) is calculated as 1/(fREF * 20) (when RXRATE = HIGH) or 1/(fREF * 10) (when RXRATE = LOW) if no data is being received, or 1/(fREF *
20) (when RXRATE = HIGH) or 1/(fREF * 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to tB.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 39 of 55
Capacitance [30]
Parameter Description Test Conditions Max Unit
CINTTL TTL Input Capacitance TA = 25°C, f0 = 1 MHz, VCC = 3.3 V 7pF
CINPECL PECL input Capacitance TA = 25°C, f 0 = 1 MHz, VCC = 3.3 V 4pF
CYP(V)15G0401DXB HOTLink II Transmitter Switching Waveforms
TXCLKx
TXDx[7:0],
TXCTx[1:0],
t
TXDH
t
TXDS
tTXCLK
tTXCLKH
t
TXCLKL
Transmit Interface Write Timing
TXOPx,
SCSEL
TXCKSEL ≠ LOW
REFCLK
Transmit Interface Write Timing tREFCLK
tREFH
t
REFL
t
TREFDS
t
TREFDH
TXCKSEL = LOW
TXRATE = LOW
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
t
TREFDH
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = HIGH
REFCLK
tREFCLK
t
REFL
tREFH
Note 41
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
t
TREFDS
t
TREFDS
t
TREFDH
Note 41
TXCLKO
t
TXCLKO
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = HIGH
REFCLK
t
REFCLK
t
REFL
t
REFH
Note 42
Note 43 tTXCLKOD+
t
TXCLKOD
–
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 40 of 55
CYP(V)15G0401DXB HOTLink II Transmitter Switching Waveforms (continued )
TXCLKO
tTXCLKO
tTXCLKOD+
t
TXCLKOD
–
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = LOW
REFCLK Note 42
Note 43
tREFCLK
tREFH
t
REFL
Notes
41.When REFCLK is configured for ha lf- rate o perat ion (TXRATE = HIGH) and data is capt ured using REFCLK inst ead of a TXCLKx cl oc k (TXCKS EL = LOW), data is
captured using both the rising and falling edges of REFCLK.
42.The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the duty
cycle of REFCLK.
43.The rising edge of TXCLKO output has no direct phase relationship to th e REFCL K input.
Switching Waveforms for the CYP(V)15G0401DXB HOTLink II Receiver
REFCLK
RXDx[7:0],
RXSTx[2:0],
t
RREFDV
tREFCLK
tREFH
t
REFL
Receive Interface
Read Timing
RXOPx
RXCKSEL = LOW
TXRATE = LOW
RXCLKA
RXCLKC
t
REFADV+
t
REFADV
–
t
REFCDV
–
t
REFCDV+
Note 44
t
RREFDA
REFCLK
RXDx[7:0],
RXSTx[2:0],
t
RREFDV
tREFCLK
tREFH
t
REFL
Receive Interface
Read Timing
RXOPx
RXCKSEL = LOW
TXRATE = HIGH
t
RREFDA
RXCLKA
RXCLKC
t
REFADV+
t
REFADV
–
t
REFCDV
–
t
REFCDV+
Note 44 Note 45
t
RREFDA
t
RREFDV
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 41 of 55
Switching Waveforms for the CYP(V)15G0401DXB HOTLink II Receiver (continued)
RXCLKx+
RXDx[7:0],
RXSTx[2:0],
t
RXDV+
tRXCLKP
tRXCLKH
t
RXCLKL
Receive Interface
Read Timing
RXOPx
RXCKSEL = HIGH or MID
RXRATE = LOW
RXCLKx–
t
RXDV
–
RXCLKx+
RXDx[7:0],
RXSTx[2:0],
t
RXDV+
tRXCLKP
tRXCLKH
t
RXCLKL
Receive Interface
Read Timing
RXOPx
RXCKSEL = HIGH or MID
RXRATE = HIGH
RXCLKx–
t
RXDV
–
Notes
44.RXCLKA and RXCLKC are delayed in phase from REFCLK, and are different in phase from each other.
45.When operated with a half-rate REFCLK, the setup and hold specifications for dat a relative to RXCLKA and RXCLK C are relative to both r ising and falling ed ges of
the respective clock output.
Table 23. Package Coordinate Signal Allocation
Ball
ID Signal Name Signal Type Ball
ID Signal Name Signal Type Ball
ID Signal Name Signal Type
A01 INC1– CML IN C04 INSELB LVTTL IN E19 VCC POWER
A02 OUTC1– CML OUT C05 VCC POWER E20 VCC POWER
A03 INC2– CML IN C06 PARCTL 3-LEVEL SEL F01 TXPERC LVTTL OUT
A04 OUTC2– CML OUT C07 SDASEL 3-LEVEL SEL F02 TXOPC LVTTL IN PU
A05 VCC POWER C08 GND GROUND F03 TXDC[0] LVTTL IN
A06 IND1– CML IN C09 BOE[7] LVTTL IN PU F04 RXCKSEL 3-LEVEL SEL
A07 OUTD1– CML OUT C10 BOE[5] LVTTL IN PU F17 BISTLE LVTTL IN PU
A08 GND GROUND C11 BOE[3] LVTTL IN PU F18 RXSTB[1] LVTTL OUT
A09 IND2– CML IN C12 BOE[1] LVTTL IN PU F19 RXOPB LVTTL 3-S OUT
A10 OUTD2– CML OUT C13 GND GROUND F20 RXSTB[0] LVTTL OUT
A11 INA1– CML IN C14 TXMODE[0] 3-LEVEL SEL G01 TXDC[7] LVTTL IN
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 42 of 55
A12 OUTA1– CML OUT C15 RXMODE[0] 3-LEVEL SEL G02 TXCKSEL 3-LEVEL SEL
A13 GND GROUND C16 VCC POWER G03 TXDC[4] LVTTL IN
A14 INA2– CML IN C17 TXRATE LVTTL IN PD G04 TXDC[1] LVTTL IN
A15 OUTA2– CML OUT C18 RXRATE LVTTL IN PD G17 DECMODE 3-LEVEL SEL
A16 VCC POWER C19 LPEN LVTTL IN PD G18 OELE LVTTL IN PU
A17 INB1– CML IN C20 TDO LVTTL 3-S OUT G19 FRAMCHAR 3-LEVEL SEL
A18 OUTB1– CML OUT D01 TCLK LVTTL IN PD G20 RXDB[1] LVTTL OUT
A19 INB2– CML IN D02 TRSTZ LVT TL IN PU H01 GND GROUND
A20 OUTB2– CML OUT D03 INSELD LVTTL IN H02 GND GROUND
B01 INC1+ CML IN D04 INSELA LVTTL IN H03 GND GROUND
B02 OUTC1+ CML OUT D05 VCC POWER H04 GND GROUND
B03 INC2+ CML IN D06 RFMODE 3-LEVEL SEL H17 GND GROUND
B04 OUTC2+ CML OUT D07 SPDSEL 3-LEVEL SEL H18 GND GROUND
B05 VCC POWER D08 GND GROUND H19 GND GROUND
B06 IND1+ CML IN D09 BOE[6] LVTTL IN PU H20 GND GROUND
B07 OUTD1+ CML OUT D10 BOE[4] LVTTL IN PU J01 TX CTC[1] LVTTL IN
B08 GND GROUND D11 BOE[2] LVTTL IN PU J02 TXDC[5] LVTTL IN
B09 IND2+ CML IN D12 BOE[0] LVTTL IN PU J03 TXDC[2] LVTTL IN
B10 OUTD2+ CML OUT D13 GND GROUND J04 TXDC[3] LVTTL IN
B11 INA1+ CML IN D14 TXMODE[1] 3-LEVEL SEL J17 RXSTB[2] LVTTL OUT
B12 OUTA1+ CML OUT D15 RXMODE[1] 3-LEVEL SEL J18 RXDB[0] LVTTL OUT
B13 GND GROUND D16 VCC POWER J19 RXDB[5] LVTTL OUT
B14 INA2+ CML IN D17 BOND_INH LVTTL IN PU J20 R XDB[2] LVTTL OUT
B15 OUTA2+ CML OUT D18 RXLE LVTTL IN PU K01 RXDC[2] LVTTL OUT
B16 VCC POWER D19 RFEN LVTTL IN PD K02 RXCLKC– LVTTL OUT
B17 INB1+ CML IN D20 MASTER LVTTL IN PD K03 TXCTC[0] LVTTL IN
B18 OUTB1+ CML OUT E01 VCC POWER K04 LFIC LVTTL OUT
B19 INB2+ CML IN E02 VCC POWER K17 RXDB[3] LVTTL OUT
B20 OUTB2+ CML OUT E03 VCC POWER K18 RXDB[4] LVTTL OUT
C01 TDI LVTTL IN PU E04 VCC POWER K19 RXDB[7] LVTTL OUT
C02 TMS LVTTL IN PU E17 VCC POWER K20 RXCLKB+ LVTTL I/O PD
C03 INSELC LVTTL IN E18 VCC POWER L01 RXDC[3] LVTTL OUT
L02 RXCLKC+ LVTTL I/O PD T17 VCC POWER V20 RXSTA[0] LVTTL OUT
L03 TXCLKC LVTTL IN PD T18 VCC POWER W01 TXDD[5] LVTTL IN
L04 TXDC[6] LVTTL IN T19 VCC POWER W02 TXDD[7] LVTTL IN
L17 RXDB[6] LVT TL OUT T20 VCC POWER W03 LFID LVTTL OUT
L18 LFIB LVTTL OUT U01 TXDD[0] LVTTL IN W04 RXCLKD– LVTTL OUT
L19 RXCLKB– LVTTL OUT U02 TXDD[1] LVTTL IN W05 VCC POWER
L20 TXDB[6] LVTTL IN U03 TXDD[2] LVTTL IN W06 RXDD[4] LVTTL OUT
M01 RXDC[4] LVTTL OUT U04 TXCTD[1] LVTTL IN W07 RXSTD[1] LVTTL OUT
M02 RXDC[5] LVTTL OUT U05 VCC POWER W08 GND GROUND
Table 23. Package Coordinate Signal Allocation (continued)
Ball
ID Signal Name Signal Type Ball
ID Signal Name Signal Type Ball
ID Signal Name Signal Type
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 43 of 55
M03 RXDC[7] LVTTL OUT U06 RXDD[2] LVTTL OUT W09 TXCLKO– LVTTL O UT
M04 RXDC[6] LVTTL OUT U07 RXDD[1] LVTTL OUT W10 TXRST LVTTL IN PU
M17 TXCTB[1] LVT TL IN U08 GND GROUND W11 TXOPA LVTTL IN PU
M18 TXCTB[0] LVTTL IN U09 RXOPD LVTTL 3-S OUT W12 SCSEL LVTTL IN PD
M19 TXDB[7] LVTTL IN U10 BOND_ALL OPEN DR W13 GND GROUND
M20 TXCLKB LVTTL IN PD U11 REFCLK– PECL IN W14 TXDA[2] LVTTL IN
N01 GND GROUND U12 TXDA[1] LVTTL IN W15 TXDA[6] LVTTL IN
N02 GND GROUND U13 GND GROUND W16 VCC POWER
N03 GND GROUND U14 TXDA[4] LVTTL IN W17 LFIA LVTTL OUT
N04 GND GROUND U15 TXCTA[0] LVTTL IN W18 R XCLKA– LVTTL OUT
N17 GND GROUND U16 VCC POWER W19 RXDA[4] LVTTL OUT
N18 GND GROUND U17 RXDA[2] LVTTL OUT W 20 RXDA[1] LVTTL O UT
N19 GND GROUND U18 RXOPA LVTTL OUT Y01 TXDD[6] LVTTL IN
N20 GND GROUND U19 RXSTA[2] LVTTL OUT Y02 TXCLKD LVTTL IN
P01 RXDC[1] LVTTL OUT U20 RXSTA[1] LVTTL OUT Y03 RXDD[7] LVTTL OUT
P02 RXDC[0] LVTTL OUT V01 TXDD[3] LVTTL IN Y04 RXCLKD+ LVTTL I/O PD
P03 RXSTC[0] LVTTL OUT V02 TXDD[4] LVTTL IN Y05 VCC POWER
P04 RXSTC[1] LVTTL OUT V03 TXCTD[0] LVTTL IN Y06 RXDD[5] LVTTL OUT
P17 TXDB[5] LVTTL IN V04 RXDD[6] LVTTL OUT Y07 RXDD[0] LV TTL OUT
P18 TXDB[4] LVTTL IN V05 VCC POWER Y08 GND GROUND
P19 TXDB[3] LVTTL IN V06 RXDD[3] LVTTL OUT Y09 TXCLKO+ LVTTL OUT
P20 TXDB[2] LVTTL IN V07 RXSTD[0] LVTTL OUT Y10 N/C NO CONNECT
R01 RXSTC[2] LVTTL OUT V08 GND GROUND Y11 TXCLKA LVTTL IN PD
R02 RXOPC LVTTL 3-S OUT V09 RXSTD[2] LVTTL OUT Y12 TXPERA LVTTL OUT
R03 TXPERD LVTTL OUT V10 BONDST[0] OPEN DR Y13 GND GROUND
R04 TXOPD LVTTL IN PU V11 REFCLK+ PECL IN Y14 TXDA[0] LVTTL IN
R17 TXDB[1] LVTTL IN V12 BONDST[1] OPEN DR Y15 TXDA[5] LVTTL IN
R18 T XDB[0] LVTTL IN V13 GND GROUND Y16 VCC POWER
R19 TXOPB LVTTL IN PU V14 TXDA[3] LVTTL IN Y17 TXCTA[1] LVTTL IN
R20 TXPERB LVTTL OUT V15 TXDA[7] LVTTL IN Y18 RXCLKA+ LVTTL I/O PD
T01 VCC POWER V16 VCC POWER Y19 RXDA[6] LVTTL OUT
T02 VCC POWER V17 RXDA[7] LVTTL OUT Y20 RXDA[5] LVTTL OUT
T03 VCC POWER V18 RXDA[3] LVTTL OUT
T04 VCC POWER V19 RXDA[0] LVTTL OUT
Table 23. Package Coordinate Signal Allocation (continued)
Ball
ID Signal Name Signal Type Ball
ID Signal Name Signal Type Ball
ID Signal Name Signal Type
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 44 of 55
X3.230 Codes and Notation Conventions
Information to be transmitted over a serial link is encoded eight
bits at a time into a 10-bit Transmission Character and then sent
serially, bit by bit. Information receiv e d ov er a se ria l li nk is
collected ten bits at a time, and those Transmission Characters
that are used for data characters are decoded into the correct
eight-bit codes. The 10-bit Transmission Code supports all 256
eight-bit combinations. Some of the remaining Transmission
Characters (Special Characters) are used for functions other
than data transmission.
The primary use of a Transmission Code is to improve the trans-
mission characteristics of a serial link. The encoding defined by
the Transmission Code ensures that sufficient transitions are
present in the serial bit stream to make clock recovery possible
at the Receiver. Such encoding also greatly increases the
likelihood of detecting any single or multiple bit errors that may
occur during transmission and reception of information. In
addition, some Special Characters of the Transmission Code
selected by Fibre Channel S tandard contain a distinct and easily
recognizable bit pattern that assists the receiver in achieving
character alig nment on the inco mi n g bi t stre a m .
Notation Conventions
The documentation for the 8B/10B Transmission Code uses
letter notation for the bits in an eight-bit byte. Fibre Channel
S tandard notation uses a bit notation of A, B, C, D, E, F, G, H for
the eight-bit byte for the raw eight-b i t data, and the letters a, b,
c, d, e, i, f, g, h, j for encoded 10-bit data. There is a correspon-
dence between bit A and bit a, B and b, C and c, D and d, E and
e, F and f, G and g, and H and h. Bits i and j are derived, respec-
tively, from (A,B,C,D,E) and (F,G,H).
The bit labeled A in the description of the 8B/10B Transmission
Code corresponds to bit 0 in the numbering scheme of the FC-2
specification, B corresponds to bit 1, as shown below.
FC-2 bit designation—76543210
HOTLink D/Q designation—76543210
8B/10B bit designation—HGFEDCBA
To clarify this correspondence, the following example shows the
conversion from an FC-2 Valid Data Byte to a Tr ansmission
Character. FC-2 45H
Bits: 7654 3210
0100 0101
Converted to 8B/10B notation, note that the order of bits has
been reversed):
Data Byte Name D5.2
Bits: ABCDE FGH
10100 010
Translated to a transmission Charac ter in the 8B/10B Trans-
mission Code: Bits: abcdei fghj
101001 0101
Each valid Transmission Character of the 8B/10B T ransmission
Code has been given a name using the following convention:
cxx.y, where c is used to show whether the Transmission
Character is a Data Character (c is set to D, and SC/D = L O W) or
a S pecial Character (c is set to K, and SC/D = HIGH). When c is set
to D, xx is the decimal value of the bin ary number composed of
the bits E, D, C, B, and A in that order, and the y is the decimal
value of the binary number composed of the bits H, G, and F in
that order . When c is set to K, xx and y are derived by comparing
the encoded bit patterns of the Special Character to those
patterns derived from encoded Valid Data bytes and selecting
the names of the patterns most similar to the encoded bit
patterns of the Special Character.
Under the above conventions, the Transmission Character used
for the examples above, is referred to by the name D5.2. The
Special Character K29.7 is so named because the first six bits
(abcdei) of this character make up a bit pattern similar to that
resulting from the encoding of the unencoded 11101 pattern (29),
and because the second four bi ts (fghj) make up a bit pattern
similar to that resulting from the encoding of the unencoded 111
pattern (7). This definition of the 10-bit Transmission Code is
based on the following references.
A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-
tioned-Block, 8B/10B Transmission Code” IBM Journal of
Research and Development, 27, No. 5: 440-451 (September, 1983).
U.S. Patent 4,486,739. Peter A. Franaszek and Albert X.
Widmer. “Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned
Block Transmission Code” (December 4, 1984).
Fibre Channel Physical and Signaling Interface (ANS
X3.230-1994 ANSI FC-PH Standard).
IBM Enterprise Systems Architecture/390 ESCON I/O Interface
(document number SA22-7202).
8B/10B Transmission Code
The following information describes how the tables are used for
both generating valid Transmission Characters (encoding) and
checking the validity of received Transmission Characters
(decoding). It also specifies the ordering rules to be followed
when transmitting the bits within a character and the characters
within any higher-level constructs specified by a standard.
Transmission Order
Within the definition of the 8B/10B Transmission Code, the bit
positions of the Transmission Characters are labeled a, b, c, d,
e, i, f, g, h, j. Bit “a” is transmitted first followed by bit s b, c, d, e,
i, f, g, h, and j in that order.
Note that bit i is transmitted between bit e and bit f, rather than
in alphabeti cal order.
Valid and Invalid Transmission Characters
The following tables define the valid Data Characters and valid
Special Characters (K characters), respectively. The tables are
used for both generating valid Transmission Characters and
checking the validity of received Transmission Characters. In the
tables, each Valid-Data-byte or S pecial-Character-code entry
has two columns that represent two Transmission Characters.
The two columns correspond to the current value of the running
disparity. Running disparity is a binary parameter with either a
negative (–) or positive (+) value.
After powering on, the T ransmitter may assume either a positive
or negative value for its initial running disparity. Upon trans-
mission of any Transmission Character, the transmitter will select
the proper version of the Transmission Character based on the
current running disparity value, and the T ransmitter calculates a
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new value for its running disparity based on the contents of the
transmitted character. Special Character codes C1.7 and C2.7
can be used to force the transmission of a specific Special
Character with a specific running disparity as required for some
special sequences in X3.230.
After powering on, the Receiver may assume either a positive or
negative value for its initial running disparity. Upon reception of
any T r ansmission Character, the Receiver decides whether the
Transmission Character is valid or invalid according to the
following rules and tables and calculates a new value for its
Running Disparity based on the contents of the received
character.
The following rules for running disparity are used to calculate the
new running-disparity value for Transmission Characters that
have been transmitted and re ceived.
Running disparity for a Transmission Character is calculated
from sub-blocks, where the first six bits (abcdei) form one
sub-block and the second four bits (fghj) form the other
sub-block. Running disparity at the beginning of the six-bit
sub-block is the running disparity at the end of the previous
Transmission Character. Runn ing disparity at the beginning of
the four-bit sub-block is the running disparity at the end of the
six-bit sub-block. Running disparity at the end of the Trans-
mission Character is the running disparity at the end of the
four-bit sub-block.
Running disparity for the sub-blocks is calculated as follows:
1. Running disparity at the end of any sub-block is positive if the
sub-block contains more ones than zeros. It is also positive at
the end of the six-bit sub-block if the six-bit sub-block is
0001 11, and it is positive at the end of the four-bit sub-block if
the four-bit sub-block is 0011.
2. Running disparity at the end of any sub-block is negative if the
sub-block contains more zeros than ones. It is also negative
at the end of the six-bit sub-block if the six-bit sub-block is
11 1000, and it is negative at the end of the six-bit sub-block if
the four-bit sub-block is 1100.
3. Otherwise, running disparity at the end of the sub-block is the
same as at the beginning of the sub-block.
Use of the Tables for Generating Transmission
Characters
The appropriate entry in Table 26 for the Valid Data byte or
Table 27 for S pecial Character byte identify which Transmission
Character is to be generated. The current value of the Trans-
mitter’s running disparity is used to select the Transmission
Character from its corresponding column. For each Trans-
mission Character transmitted, a new value of the running
disparity is calculated. This new value is used as the Trans-
mitter’s current running disparity for the next Valid Data byte or
S pecial Character byte to be encoded and transmitted. Table 24
shows naming notations and examples of valid transmission
characters.
Use of the T ables for Checking the Validity of Received
Transmission Characters
The column corresponding to the current value of the Receiver’s
running disparity is searched for the received Transmission
Character. If the received Transmission Character is found in the
proper column, then the Transmission Character is valid and the
associated Data byte or Special Character co de is determined
(decoded). If the received Transmission Character is not found
in that column, then the Transmission Character is invalid. This
is called a code violation. Independent of the Transmission
Character’s validity, the received Transmission Character is
used to calculate a new value of running disparity . The new value
is used as the Receiver’s current running disparity for the next
received Transmission Character.
Detection of a code violation does not necessarily show that the
Transmission Character in which the code violation was detected
is in error. Code violations may result from a prior error that
altered the running disparity of the bit stream which did not result
in a detectable error at the T ransmission Character in which the
error occurred. Table 25 shows an example of this behavior.
Table 24. Valid Transmission Characters
Data
Byte Name DIN or QOUT Hex Value
765 43210
D0.0 000 00000 00
D1.0 000 00001 01
D2.0 000 00010 02
.
..
..
..
.
D5.2 010 00101 45
.
..
..
..
.
D30.7 111 11110 FE
D31.7 111 11111 FF
Table 25. Code Violations Resulting from Prior Errors
RD Character RD Character RD Character RD
Transmitted data character –D21.1 –D10.2 –D23.5 +
Transmitted bit stream –101010 1001 –010101 010 1 –111010 1010 +
Bit stream after error –101010 1011 +010101 0101 +1110 10 1010 +
Decoded data character –D21.0 +D10.2 +Code Violation +
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Ta ble 26. Valid Dat a Characters (TXCTx[0] = 0, RXSTx[2:0] = 000)
Data
Byte
Name
Bits Current RD−Current RD+ Data
Byte
Name
Bits Current RD−Current RD+
HGF EDCBA abcdei fghj abcdei fghj HGF EDCBA abcdei fghj abcdei fghj
D0.0 000 00000 100111 0100 011000 1011 D0.1 001 00000 100111 1001 011000 1001
D1.0 000 00001 011101 0100 100010 1011 D1.1 001 00001 011101 1001 100010 1001
D2.0 000 00010 101101 0100 010010 1011 D2.1 001 00010 101101 1001 010010 1001
D3.0 000 00011 110001 1011 110001 0100 D3.1 001 00011 110001 1001 110001 1001
D4.0 000 00100 110101 0100 001010 1011 D4.1 001 00100 110101 1001 001010 1001
D5.0 000 00101 101001 1011 101001 0100 D5.1 001 00101 101001 1001 101001 1001
D6.0 000 00110 011001 1011 011001 0100 D6.1 001 00110 011001 1001 011001 1001
D7.0 000 00111 111000 1011 000111 0100 D7.1 001 00111 111000 1001 000111 1001
D8.0 000 01000 111001 0100 000110 1011 D8.1 001 01000 111001 1001 000110 1001
D9.0 000 01001 100101 1011 100101 0100 D9.1 001 01001 100101 1001 100101 1001
D10.0 000 01010 010101 1011 010101 0100 D10.1 001 01010 010101 1001 010101 1001
D11.0 000 01011 110100 1011 110100 0100 D11.1 001 01011 110100 1001 110100 1001
D12.0 000 01100 001101 1011 001101 0100 D12.1 001 01100 001101 1001 001101 1001
D13.0 000 01101 101100 1011 101100 0100 D13.1 001 01101 101100 1001 101100 1001
D14.0 000 01110 011100 1011 011100 0100 D14.1 001 01110 011100 1001 011100 1001
D15.0 000 01111 010111 0100 101000 1011 D15.1 001 01111 010111 1001 101000 1001
D16.0 000 10000 011011 0100 100100 1011 D16.1 001 10000 011011 1001 100100 1001
D17.0 000 10001 100011 1011 100011 0100 D17.1 001 10001 100011 1001 100011 1001
D18.0 000 10010 010011 1011 010011 0100 D18.1 001 10010 010011 1001 010011 1001
D19.0 000 10011 110010 1011 110010 0100 D19.1 001 10011 110010 1001 110010 1001
D20.0 000 10100 001011 1011 001011 0100 D20.1 001 10100 001011 1001 001011 1001
D21.0 000 10101 101010 1011 101010 0100 D21.1 001 10101 101010 1001 101010 1001
D22.0 000 10110 011010 1011 011010 0100 D22.1 001 10110 011010 1001 011010 1001
D23.0 000 10111 111010 0100 000101 1011 D23.1 001 10111 111010 1001 000101 1001
D24.0 000 11000 110011 0100 001100 1011 D24.1 001 11000 110011 1001 001100 1001
D25.0 000 11001 100110 1011 100110 0100 D25.1 001 11001 100110 1001 100110 1001
D26.0 000 11010 010110 1011 010110 0100 D26.1 001 11010 010110 1001 010110 1001
D27.0 000 11011 110110 0100 001001 1011 D27.1 001 11011 110110 1001 001001 1001
D28.0 000 11100 001110 1011 001110 0100 D28.1 001 11100 001110 1001 001110 1001
D29.0 000 11101 101110 0100 010001 1011 D29.1 001 11101 101110 1001 010001 1001
D30.0 000 11110 011110 0100 100001 1011 D30.1 001 11110 011110 1001 100001 1001
D31.0 000 11111 101011 0100 010100 1011 D31.1 001 11111 101011 1001 010100 1001
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D0.2 010 00000 100111 0101 011000 0101 D0.3 011 00000 100111 0011 011000 1100
D1.2 010 00001 011101 0101 100010 0101 D1.3 011 00001 011101 0011 100010 1100
D2.2 010 00010 101101 0101 010010 0101 D2.3 011 00010 101101 0011 010010 1100
D3.2 010 00011 110001 0101 110001 0101 D3.3 011 00011 110001 1100 110001 0011
D4.2 010 00100 110101 0101 001010 0101 D4.3 011 00100 110101 0011 001010 1100
D5.2 010 00101 101001 0101 101001 0101 D5.3 011 00101 101001 1100 101001 0011
D6.2 010 00110 011001 0101 011001 0101 D6.3 011 00110 011001 1100 011001 0011
D7.2 010 00111 111000 0101 000111 0101 D7.3 011 00111 111000 1100 000111 0011
D8.2 010 01000 111001 0101 000110 0101 D8.3 011 01000 111001 0011 000110 1100
D9.2 010 01001 100101 0101 100101 0101 D9.3 011 01001 100101 1100 100101 0011
D10.2 010 01010 010101 0101 010101 0101 D10.3 011 01010 010101 1100 010101 0011
D11.2 010 01011 110100 0101 110100 0101 D11.3 011 01011 110100 1100 110100 0011
D12.2 010 01100 001101 0101 001101 0101 D12.3 011 01100 001101 1100 001101 0011
D13.2 010 01101 101100 0101 101100 0101 D13.3 011 01101 101100 1100 101100 0011
D14.2 010 01110 011100 0101 011100 0101 D14.3 011 01110 011100 1100 011100 0011
D15.2 010 01111 010111 0101 101000 0101 D15.3 011 01111 010111 0011 101000 1100
D16.2 010 10000 011011 0101 100100 0101 D16.3 011 10000 011011 0011 100100 1100
D17.2 010 10001 100011 0101 100011 0101 D17.3 011 10001 100011 1100 100011 0011
D18.2 010 10010 010011 0101 010011 0101 D18.3 011 10010 010011 1100 010011 0011
D19.2 010 10011 110010 0101 110010 0101 D19.3 011 10011 110010 1100 110010 0011
D20.2 010 10100 001011 0101 001011 0101 D20.3 011 10100 001011 1100 001011 0011
D21.2 010 10101 101010 0101 101010 0101 D21.3 011 10101 101010 1100 101010 0011
D22.2 010 10110 011010 0101 011010 0101 D22.3 011 10110 011010 1100 011010 0011
D23.2 010 10111 111010 0101 000101 0101 D23.3 011 10111 111010 0011 000101 1100
D24.2 010 11000 110011 0101 001100 0101 D24.3 011 11000 110011 0011 001100 1100
D25.2 010 11001 100110 0101 100110 0101 D25.3 011 11001 100110 1100 100110 0011
D26.2 010 11010 010110 0101 010110 0101 D26.3 011 11010 010110 1100 010110 0011
D27.2 010 11011 110110 0101 001001 0101 D27.3 011 11011 110110 0011 001001 1100
D28.2 010 11100 001110 0101 001110 0101 D28.3 011 11100 001110 1100 001110 0011
D29.2 010 11101 101110 0101 010001 0101 D29.3 011 11101 101110 0011 010001 1100
D30.2 010 11110 011110 0101 100001 0101 D30.3 011 11110 011110 0011 100001 1100
D31.2 010 11111 101011 0101 010100 0101 D31.3 011 11111 101011 0011 010100 1100
Ta ble 26. Valid Dat a Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)
Data
Byte
Name
Bits Current RD−Current RD+ Data
Byte
Name
Bits Current RD−Current RD+
HGF EDCBA abcdei fghj abcdei fghj HGF EDCBA abcdei fghj abcdei fghj
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D0.4 100 00000 100111 0010 011000 1101 D0.5 101 00000 100111 1010 011000 1010
D1.4 100 00001 011101 0010 100010 1101 D1.5 101 00001 011101 1010 100010 1010
D2.4 100 00010 101101 0010 010010 1101 D2.5 101 00010 101101 1010 010010 1010
D3.4 100 00011 110001 1101 110001 0010 D3.5 101 00011 110001 1010 110001 1010
D4.4 100 00100 110101 0010 001010 1101 D4.5 101 00100 110101 1010 001010 1010
D5.4 100 00101 101001 1101 101001 0010 D5.5 101 00101 101001 1010 101001 1010
D6.4 100 00110 011001 1101 011001 0010 D6.5 101 00110 011001 1010 011001 1010
D7.4 100 00111 111000 1101 000111 0010 D7.5 101 00111 111000 1010 000111 1010
D8.4 100 01000 111001 0010 000110 1101 D8.5 101 01000 111001 1010 000110 1010
D9.4 100 01001 100101 1101 100101 0010 D9.5 101 01001 100101 1010 100101 1010
D10.4 100 01010 010101 1101 010101 0010 D10.5 101 01010 010101 1010 010101 1010
D11.4 100 01011 110100 1101 110100 0010 D11.5 101 01011 110100 1010 110100 1010
D12.4 100 01100 001101 1101 001101 0010 D12.5 101 01100 001101 1010 001101 1010
D13.4 100 01101 101100 1101 101100 0010 D13.5 101 01101 101100 1010 101100 1010
D14.4 100 01110 011100 1101 011100 0010 D14.5 101 01110 011100 1010 011100 1010
D15.4 100 01111 010111 0010 101000 1101 D15.5 101 01111 010111 1010 101000 1010
D16.4 100 10000 011011 0010 100100 1101 D16.5 101 10000 011011 1010 100100 1010
D17.4 100 10001 100011 1101 100011 0010 D17.5 101 10001 100011 1010 100011 1010
D18.4 100 10010 010011 1101 010011 0010 D18.5 101 10010 010011 1010 010011 1010
D19.4 100 10011 110010 1101 110010 0010 D19.5 101 10011 110010 1010 110010 1010
D20.4 100 10100 001011 1101 001011 0010 D20.5 101 10100 001011 1010 001011 1010
D21.4 100 10101 101010 1101 101010 0010 D21.5 101 10101 101010 1010 101010 1010
D22.4 100 10110 011010 1101 011010 0010 D22.5 101 10110 011010 1010 011010 1010
D23.4 100 10111 111010 0010 000101 1101 D23.5 101 10111 111010 1010 000101 1010
D24.4 100 11000 110011 0010 001100 1101 D24.5 101 11000 110011 1010 001100 1010
D25.4 100 11001 100110 1101 100110 0010 D25.5 101 11001 100110 1010 100110 1010
D26.4 100 11010 010110 1101 010110 0010 D26.5 101 11010 010110 1010 010110 1010
D27.4 100 11011 110110 0010 001001 1101 D27.5 101 11011 110110 1010 001001 1010
D28.4 100 11100 001110 1101 001110 0010 D28.5 101 11100 001110 1010 001110 1010
D29.4 100 11101 101110 0010 010001 1101 D29.5 101 11101 101110 1010 010001 1010
D30.4 100 11110 011110 0010 100001 1101 D30.5 101 11110 011110 1010 100001 1010
D31.4 100 11111 101011 0010 010100 1101 D31.5 101 11111 101011 1010 010100 1010
Ta ble 26. Valid Dat a Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)
Data
Byte
Name
Bits Current RD−Current RD+ Data
Byte
Name
Bits Current RD−Current RD+
HGF EDCBA abcdei fghj abcdei fghj HGF EDCBA abcdei fghj abcdei fghj
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D0.6 110 00000 100111 0110 011000 0110 D0.7 111 00000 100111 0001 011000 1110
D1.6 110 00001 011101 0110 100010 0110 D1.7 111 00001 011101 0001 100010 1110
D2.6 110 00010 101101 0110 010010 0110 D2.7 111 00010 101101 0001 010010 1110
D3.6 110 00011 110001 0110 110001 0110 D3.7 111 00011 110001 1110 110001 0001
D4.6 110 00100 110101 0110 001010 0110 D4.7 111 00100 110101 0001 001010 1110
D5.6 110 00101 101001 0110 101001 0110 D5.7 111 00101 101001 1110 101001 0001
D6.6 110 00110 011001 0110 011001 0110 D6.7 111 00110 011001 1110 011001 0001
D7.6 110 00111 111000 0110 000111 0110 D7.7 111 00111 111000 1110 000111 0001
D8.6 110 01000 111001 0110 000110 0110 D8.7 111 01000 111001 0001 000110 1110
D9.6 110 01001 100101 0110 100101 0110 D9.7 111 01001 100101 1110 100101 0001
D10.6 110 01010 010101 0110 010101 0110 D10.7 111 01010 010101 1110 010101 0001
D11.6 110 01011 110100 0110 110100 0110 D11.7 111 01011 110100 1110 110100 1000
D12.6 110 01100 001101 0110 001101 0110 D12.7 111 01100 001101 1110 001101 0001
D13.6 110 01101 101100 0110 101100 0110 D13.7 111 01101 101100 1110 101100 1000
D14.6 110 01110 011100 0110 011100 0110 D14.7 111 01110 011100 1110 011100 1000
D15.6 110 01111 010111 0110 101000 0110 D15.7 111 01111 010111 0001 101000 1110
D16.6 110 10000 011011 0110 100100 0110 D16.7 111 10000 011011 0001 100100 1110
D17.6 110 10001 100011 0110 100011 0110 D17.7 111 10001 100011 0111 100011 0001
D18.6 110 10010 010011 0110 010011 0110 D18.7 111 10010 010011 0111 010011 0001
D19.6 110 10011 110010 0110 110010 0110 D19.7 111 10011 110010 1110 110010 0001
D20.6 110 10100 001011 0110 001011 0110 D20.7 111 10100 001011 0111 001011 0001
D21.6 110 10101 101010 0110 101010 0110 D21.7 111 10101 101010 1110 101010 0001
D22.6 110 10110 011010 0110 011010 0110 D22.7 111 10110 011010 1110 011010 0001
D23.6 110 10111 111010 0110 000101 0110 D23.7 111 10111 111010 0001 000101 1110
D24.6 110 11000 110011 0110 001100 0110 D24.7 111 11000 110011 0001 001100 1110
D25.6 110 11001 100110 0110 100110 0110 D25.7 111 11001 100110 1110 100110 0001
D26.6 110 11010 010110 0110 010110 0110 D26.7 111 11010 010110 1110 010110 0001
D27.6 110 11011 110110 0110 001001 0110 D27.7 111 11011 110110 0001 001001 1110
D28.6 110 11100 001110 0110 001110 0110 D28.7 111 11100 001110 1110 001110 0001
D29.6 110 11101 101110 0110 010001 0110 D29.7 111 11101 101110 0001 010001 1110
D30.6 110 11110 011110 0110 100001 0110 D30.7 111 11110 011110 0001 100001 1110
D31.6 110 11111 101011 0110 010100 0110 D31.7 111 11111 101011 0001 010100 1110
Ta ble 26. Valid Dat a Characters (TXCTx[0] = 0, RXSTx[2:0] = 000) (continued)
Data
Byte
Name
Bits Current RD−Current RD+ Data
Byte
Name
Bits Current RD−Current RD+
HGF EDCBA abcdei fghj abcdei fghj HGF EDCBA abcdei fghj abcdei fghj
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Table 27. Valid S pecial Character Codes and Sequences (TXCTx = special character code or RXSTx[2:0] = 001) [46, 47]
S.C. Code Name
S.C. Byte Name Current RD−
abcdei fghj Current RD+
abcdei fghj
Cypress Alternate
S.C. Byte
Name [48] Bits
HGF EDCBA S.C. Byte Name
[48] Bits
HGF EDCBA
K28.0 C0.0 (C00) 000 00000 C28.0 (C1C) 000 11100 001111 0100 110000 1011
K28.1 [49] C1.0 (C01) 000 00001 C28.1 (C3C) 001 11100 001111 1001 110000 0110
K28.2 [49] C2.0 (C02) 000 00010 C28.2 (C5C) 010 11100 001111 0101 110000 1010
K28.3 C3.0 (C03) 000 00011 C28.3 (C7C) 01111100 001111 0011 110000 1100
K28.4 [49] C4.0 (C04) 000 00100 C28.4 (C9C) 100 11100 001111 0010 110000 1101
K28.5 [49, 50] C5.0 (C05) 000 00101 C28.5 (CBC) 10111100 001111 1010 110000 0101
K28.6 [49] C6.0 (C06) 000 00110 C28.6 (CDC) 110 11100 001111 0110 110000 1001
K28.7 [49, 51] C7.0 (C07) 000 00111 C28.7 (CFC) 111 11100 0011111000 110000 0111
K23.7 C8.0 (C08) 000 01000 C23.7 (CF7) 111 10111 111010 1000 000101 0111
K27.7 C9.0 (C09) 000 01001 C27.7 (CFB) 111 11011 110110 1000 001001 0111
K29.7 C10.0 (C0A) 000 01010 C29.7 (CFD) 111 11101 101110 1000 010001 0111
K30.7 C11.0 (C0B) 000 01011 C30.7 (CFE) 111 11110 011110 1000 100001 0111
End of Frame Sequence
EOFxx [52] C2.1 (C22) 001 00010 C2.1 (C22) 001 00010 –K28.5, Dn.xxx0 +K28.5, Dn.xxx1
Code Rule Violation and SVS Tx Pattern
Exception[51, 5 3 ] C0.7 (CE0) 111 00000 C0.7 (CE0) 111 00000[57] 100111 1000 011000 0111
−K28.5 [54] C1.7 (CE1) 111 00001 C1.7 (CE1) 111 00001[57] 001111 1010 001111 1010
+K28.5[55] C2.7 (CE2) 111 00010 C2.7 (CE2) 111 00010[57] 110000 0101 110000 0101
Running Disparity Violation Pattern
Exception[56] C4.7 (CE4) 111 00100 C4.7 (CE4) 111 00100[57] 110111 0101 001000 1010
Notes
46.All codes not shown are reserved.
47.Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to
describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through
C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).
48.Both the Cypress and alternate encodin gs may be used for dat a transmission to generate specif ic S pecial Character Codes. The decoding process for received
characters generates Cypress code s or Alternate codes as selected by the DECMODE configuration input.
49.These characters are used for control of ESCON interfaces. They can be sent as embedded commands or other markers when not operating using ESCON
protocols.
50.The K28.5 character is used for framing opera tions by the recei ver. It is also the pad or fill character tra nsmitted to main tain the serial link whe n no user da t a i s
available.
51.Care must be take n when using this Special Cha racter c ode. Wh en a K28.7( C7.0) or SVS(C0.7 ) is followe d by a D11.x or D20. x, an alia s K28. 5 sync character
is created. These sequences can cause erroneous framing and shou ld be avoided while RFEN = HIGH.
52.C2.1 = T ransmit ei the r −K28.5+ or +K28 .5− as det ermined by Current RD and modif y the Transmission Character that foll ows, by setting it s least signifi cant bit
to 1 or 0. If Current RD at t he st art of the foll owing chara cter is p lus (+) t he LSB is set to 0, and if Current RD is minus ( −) the LSB becomes 1. This modificat ion
allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.
For example, to send “EOFdt ” the controller could issue the sequence C2.1−D21.4− D21.4−D21.4, and the HOTLink IITransmitter will send either
K28.5−D21.4−D21.4−D21.4 or K28.5−D21.5− D21.4−D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence
C2.1−D10.4−D21.4−D21.4, and the HOTLink II Transmitter will send either K28.5−D10.4−D21.4− D21.4 or K28.5−D10.5−D21.4− D21.4 based on Current RD.
The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1 .7, or C2.7, and the subsequent bytes are decoded as data.
53.C0.7 = Transmit a delib erate code ru le violat ion. The code chosen for t his function fol lows the normal Running Disp arity rules. The receiver will only output this
Special Character if the Transmission Character being decoded is not found in the tables.
54.C1.7 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong
running disparity. The receiver will output C1.7 if −K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0 or C2.7.
55.C2.7 = Transmit Positive K28.5 (+K28.5 −) disregarding Current RD. The receive r wil l only output this Special Character if K28.5 is received with the wrong
running disparity. The receiver will output C2.7 if +K28.5 is received with RD−, otherwise K28.5 is decoded as C5.0 or C1.7.
56.C4.7 = Transmit a deliberat e code rule violation to indicate a Running Dispari ty violation. The receive r will only ou tput th is Special Character if the T ransmission
Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a prior byte.
57.Supported only for data transmission. The receive status for these conditions will be reported by specific combinations of receive status bits.
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 51 of 55
Ordering Code Definitions
Ordering Information
Speed Ordering Code Package
Name Package Type Operating
Range
Standard CYP15G0401DXB-BGXC BJ256 Pb-free 256-ball thermally enhanced ball grid array Commercial
Standard CYP15G0401DXB-BGXI BJ256 Pb-free 256-ball thermally enhanced ball grid array Industrial
Standard CYV15G0401DXB-BGXC BJ256 Pb-free 256-ball thermally enhanced ball grid array Commercial
CY (P, V ) 15G 0X -0X DX
Fu ll d uplex
01 PHY: 8B /10B E nde c, C han ne l Bonding
04 = Num ber of cha nne l
Speed: 1.5 Gbps
P = Standard PHY, V= Video SMPTE PHY
Company Code: CY = Cypress
B
Silico n re v isio n
BG X(C, I)
Pb-free
Package Type: BG = 256-ball BGA
Temperature grade:
C = Commercial; I = Industrial
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 52 of 55
Package Diagram
Acronyms
The following table lists the acronyms that are used in this
document.
Document Conventions
51-85123 *G
Table 28. Acronyms Used in this Datasheet
Acronym Description
BGA ball grid array
BIST built-in self test
I/O input/output
JTAG joint test action group
PLL phase-locked loop
TMS test mode select
TDO test da ta out
TDI test data in
Table 29. Units of Measure
Acronym Description
°C degree Celsius
kΩKilo ohm
µA microampere
µs microsecond
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
Ωohm
pF picofarad
Vvolt
Wwatt
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 53 of 55
Document History Page
Document Title: CYP15G0401DXB CYV15G0401DXB Quad HOTLink II™ Transceiver
Document Number: 38-02002
Revision ECN Orig. of
Change Submission
Date Description of Change
** 105840 SZV 03/21/01 C hange from Spec number: 38-00876 to 38-02002
*A 108025 AMV 06/20/01 Chang ed Marketing part number
*B 108437 TME 07/19/01 Change Marketing part number from CYP15G0401DX to CYP15G0401
*C 112986 TPS 11/12/01 Changed common mode input information and duty cycle of transmit clocks
Updated max voltage power and release under ecn control
Changed the wording of REFCLK input coupling on both inputs for L VTTL clock
input
Addition of TXCLKO+ and the TXCLKO+ specs
Changed the TXCLKO clock output to refect the new timing
Changed the Half Clock drawing so that the viald time was at clock edges
Changed the input power
Changed the spec for the serial output levels at the different terminations
Changed the common mode input range of the serial input
Increased the Serial input current under the conditions of VCC and min
Added to the Duty cycle of the transmit and receiver clock signals
The rise time of the serial inputs and receiver were changed
The half rate timing drawing changed from not valid at clock edges to viald at clock
edges
Added new timing line for status valid time of half clock signals
Max voltage reduced from 4.2 V to 3.8 V
Matched the common specs with the family of parts
*D TPS 2/26/02 Chang ed many names from lower case to upper case
Changed in five places = to ≠
Changed the power to typical to 2.8 W
Added Escon, DVB-ASI, SMPTE to features
Under PARCTL control reworded statement When HIGH
Under RXLE Reworded and reformatted the text
Under BOND_ALL added when bonding resolution is completed
Removed repeated information in Power Control section
Corrected statement for bonded BIST
*E 118650 LNM 09/30/02 Changed TXCLKO description
Changed TXPERx description
Changed typical power from 2.8 W to 2.9 W
Removed the LOW setting for FRAMCHAR and related references
Changed VODIF and VOLC for CML output
Changed the IOST boundary values
Changed the tTXCLKR and tTXCLKF min. values
Changed tTXDS & tTXDH and tTREFDS & tTREFDH
Changed tREFADV– and tREFCDV–
Changed the JTAG ID from 0C800069 to 1C800 069
*F 121906 CGX 02/12/03 Changed Minimum tRISE/tFALL for CML
Changed tRXLOCK
Changed tDJ, tRJ
Changed tJTOL
Changed tTXLOCK
Changed tRXCLKH, tRXCLKL
Changed tTXCLKOD+, tTXCLKOD
Changed Power Specs
Changed verbiage...Paragraph: Clock/Data Recovery
Changed verbiage...Paragraph: Range Control
Added Power-up Requirements
CYP15G0401DXB
CYV15G0401DXB
Document #: 38-02002 Rev. *N Page 54 of 55
*G 124996 POT 03/21/03 Changed CYP15G0401DXB to CYP(V)15G0 401DXB to abbreviate title. Type
corresponding to the Video compliant parts
Reduced the lower limit of the serial signaling rate from 200 Mbaud to 195 Mbaud
and changed the associated specificatio ns accordingly
Added CYPV15G0401DXB to title
*H 126908 KKV 5/12/03 Corrected fo otnote 1
Implemented corrections to table format
*I 128365 PDS 7/23/03 Revised the value of tRREFDV, tREF ADV+ and tREFCDV+
*J 131897 PDS 12/10/03 When TXCKSEL = MID or HIGH, TXRATE = HIGH is an invalid mode. Made
appropriate changes to reflect this invali d condition.
Removed requirement of AC coupling for Serial I/Os for interfacing with L VPECL
I/Os.
Changed LFIx to Asynchronous output.
Expanded the CDR Range Controller’s permissible frequency offset between
incoming serial signalling rate and Reference clock from ±200-PPM to
±1500-PPM (changed parameter tREFRX).
Added T able for RXSTx[2:0] status for non-bonded (Independent Channel) mode
of operation for clarity. Separated the Receive BIST status to a new Table for
clarity.
Revised Typical Power numbers to match final characterization data.
*K 211429 KKV See ECN Minor change: package diagram disappeared from online pdf
*L 338721 SUA See ECN Added CYW15G040 1DXB part number for OBSAI RP3 complia nce to support
operating data rate upto 1540 MBaud. Made changes to reflect OBSAI RP3 and
CPR compliance. Added Pb-free package option for all parts listed in the
datasheet.
Changed MBd to MBaud in SPDSEL pin description
*M 2 898393 CGX 03 /2 4/10 Removed inactive parts from the ordering information table.Updated package
diagram.
*N 3334849 SAAC 08/02/11 Updated template according to current Cypress standards.
Added ordering code definitions, acronyms, and units of measure.
Updated package diagram spec 51-85123 to *G.
Document History Page (continued)
Document Title: CYP15G0401DXB CYV15G0401DXB Quad HOTLink II™ Transceiver
Document Number: 38-02002
Revision ECN Orig. of
Change Submission
Date Description of Change
Document #: 38-02002 Rev. *N Revised August 18, 2011 Page 55 of 55
All products and company names mentioned in this document may be the trademarks of their respective holders.
CYP15G0401DXB
CYV15G0401DXB
© Cypress Semico nducto r Co rpor ation , 20 04-2 011. The informati on con ta ined herei n is subje ct to cha nge w ithou t no tice. C ypress S emiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress pr oducts in life -support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjuncti on with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permis sion of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cyp ress does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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