MICROCIRCUITSTELEDYNE PHILBRICK HEADQUARTERS Allied Drive at Rte. 128 Dedham, MA 02026 Tel: 617.329.1600 Twx: 710.348.6726 Tix: 212711 FRANCE 85 Rue Anatole France 92300 Levallois Perret France Tel: 14.757.1940 Twx: 842611752 OSAKA Tel: 06.252.5861 Cc ROCiRCuUtlT s& UNITED STATES SOUTHEAST 1640 Huron Trail P.O. Box 1289 Maitland, FL 82751 Tel: 305.629.6490 MIDWEST Contact Factory EUROPE UNITED KINGDOM Heathrow House, Bath Road Cranford, Hounslow, Middlesex TW5 900 UK Tel: 01.897.2501 Tix: 851.935008 JAPAN TOKYO Nihon Seimei Akasaka -1-19, Akasaka Minato-ku, Tokyo 107 Japan WEST 30423 Canwood Street Suite 212 Agoura Hills, CA 91301 Tel: 818.889.3827 Twx: 910.494.1949 WEST GERMANY Abraham-Lincoln-Str. 36-42 6200 Wiesbaden, West Germany Tel: 06121.768.0 Tix: 841.4182631 TOKYO Tel: 093.403.8921 Tix: 781.02424241CONTENTS. PRODUCTS O APPLICATION NOTES O OPERATIONAL AMPLIFIERS TP0032 (D.E.S.C. 80013012) TP0033 = (D.E.S.C. 80014012) 1435 Fastest Settling 1437/37D_ Precision /38 1443 Wideband 1460 IBIAS 30V/150mA Output 1461 30V/750mA Output 1463 30V/1A Output 1464 User Selectable Stages 1467 Low Offset 1480 Fast, High Voltage 1702 5 Femtoampere IBIAS O TRACK/HOLD AMPLIFIERS 4860 Fastest 12-Bit PAGE O DIGITAL/ANALOG : CONVERTERS 4058 12-Bit, Voltage Output 4065 12-Bit, Voltage Output 3 4080 Fastest, 12-Bit 6 9 12 O VOLTAGE/FREQUENCY CONVERTERS 16 19 4739/43 5MHz, Precision 22 25 28 44 O SYNCHRO/DIGITAL 37 RESOLVER/DIGITAL 39 5500 High Speed, Precision 5600 High Speed, Precision 57 PRODUCT SELECTION GUIDE CO OPERATIONAL AMPLIFIERS Microcircuit Wideband, Fast Settling High Speed, High Output General Purpose Logarithmic and Instrumentation Modular O TRACK/HOLD AMPLIFIERS Deglitcher 0 ANALOG/DIGITAL CONVERTERS 66 67 68 68 69 69 70 0 DIGITAL/ANALOG CONVERTERS O FREQUENCY/VOLTAGE CONVERTERS 0 VOLTAGE/FREQUENCY CONVERTERS O MODULAR POWER SUPPLIES O REPLACEMENT GUIDE PAGE 41 47 a3 70 71 72 73 74AN-3 AN-4 AN-7 *AN-23 *AN-29 AN-1 AN-2 AN-6 AN-9 AN-11 AN-20 *AN-22 AN-32 LINEAR AMPLIFIERS Designing Femtoampere Circuits Requires Special Considerations Band-Pass Active Filter with Easy Trim for Center Frequency Typical Operational Amplifier Applications Operational Amplifier Parameter Definition and Measurement Guide The Instrumentation Amp vs. the Op Amp (connected as a differential amplifier); Which, When and How to Use Them VOLTAGE-FREQUENCY-VOLTAGE Voltage-to-Frequency Converters Need a 1kHz Full Scale V/F? Magnitude-Plus-Sign ADC Using a V/F Converter V/Fs as Long-Term Integrators V/Fs, F/Vs and Audio Tape Recorders Solve Your Measurement Problems with V/Fs and F/Vs How to Specify and Test Voltage-to-Frequency and Frequency-to-Voltage Converters V/Fs and F/Vs: Simple Solutions to Everyday Conversion Problems @ NONLINEAR PRODUCTS AN-12 AN-14 AN-15 *AN-27 & AN-17 AN-19 AN-21 AN-24 *AN-25 AN-28 AN-30 AN-31 Designer's Guide to Logarithmic Amplifiers Applications for Models 4350/51 and 4362/63 Logarithmic Amplifiers How to Specify Parameters of Nonlinear Circuits Logarithmic Amplifiers and Operators Parameter Definition and Measurement DATA CONVERTERS Current-Steering Chip Upgrades Performance of D/A Converter Using the 4130 ADC Series, 4855 Sample-Hold, and 4550 Multiplexer in High Speed Data Acquisition Systems Designing High Speed Data Acquisition Systems Specifying and Testing Analog to Digital Converters Specifying and Testing Digital to Analog Converters Repetitive Mode Operation for Models 4109/4111 Integrating A/D Converters Specifying and Testing Sample-Hold Amplifiers Specifying and Testing Multiplexers @ POWER SUPPLIES *AN-26 Modular DC Output Power Supply Parameter Definition and Measurement * These bulletins form a complete package that defines parameters and describes testing for the entire Teledyne Philbrick product line. They allow user and seller to speak the same language", thereby eliminating confusion associated with a lack of industry-wide standardization. TELEDYNE PHILBRICK microciacuitsTP0032 High Speed FET Input Operational Amplifier The TP0032 is a high slew rate, FET input, fully differential operational amplifier. This device features a 70dB minimum open loop gain, a wide BOMHz bandwidth, high input impe- dance (10''Q), and high output drive capabilities. Although it can be used as a direct replacement for other LH0032 type op amps, the TP0032 features the following perfor- mance improvements: 1. Increased open loop gain improves linearity and eliminates output voltage droop. 2. Improved second stage biasing and decreased gain sensitiv- ity to the transconductance of the JFET input yields faster and more consistent settling times. The addition of bias compensation over temperature improves dynamic response vs. temperature. . Improved phase margin allows smaller compensation capac- itance values to be used in low gain applications. This means that for new designs, the TP0032 will provide higher slew rates and faster settling times. The TP0032 is specified over the 25C to +85C tempera- ture range and the TP0032-HR is specified over the 55C to +125C temperature range. oo fs FEATURES * Improved Second Source, Replaces All LHO032G * 100ns Settling to +1% * 650Viusec Slew Rate 70dB Min Open Loop Gain 55C to +125C Operation APPLICATIONS High Speed ADC Comparators * ADC and SHA Integrators High Speed Integrators * Video Amplifiers PACKAGE DIMENSIONS Popeye! itttt | = PIN DESIGNATIONS 1 NC 7. N/C 2. OUTPUT COMP 8. N/C 3. COMP 9. N/C 4. COMP 10. Vee 5.NON-INVERTING INPUT 11, QUT 6. NON-INVERTING INPUT 12. +Vec TELEDYNE PHILBRICK micaocincuitsTP0032 ABSOLUTE MAXIMUM RATINGS Supply Voltage (+Vec} +18V Input Voltage Vee Differential Input Voltage +30V Operating Temperature Range 55C to +125C Storage Temperature Range 65C to +150C SPECIFICATIONS (-55C = Ta = #125C, +Vec = +15V unless otherwise indi ) PARAMETER MIN. TYP. MAX. UNITS OPEN LOOP VOLTAGE GAIN (R, =1kh) Initial (Ta = +25C) 70 a5 dB 55C to +125C 70 83 _ dB INPUT CHARACTERISTICS Differential Input Impedance _ 101 /1.5 QOlpE Offset Voltage: Initial (T, = +25C) = +2 +5 mV 55C to +125C _ +4 +10 mv Drift vs. Temperature _ #25 -- LVEC Offset Current: Initial (Ts = +25C) _ +5 +25 pA 55C to +125C. _ +12 +25 nA Bias Current: Initial (Ta = +25C) = +10 +100 pa 55C to +125C _ +5 +50 nA Common Mode Voltage for DC Linear Operation +10 +12 _ Vv Power Supply Rejection Ratio (AVcc = 10V) 50 70 dB Common Mode Rejection Ratio (AV. = 10V) 50 70 = dB OUTPUT CHARACTERISTICS Voltage Swing (Ri = 1kQ) +10 413.5 _ Vv Current (1) +10 413.5 = mA FREQUENCY RESPONSE (2) Unity-Gain Bandwidth (3) _ 80 _ MHz Slew Rate (Ay = +1, AVa = 20V) 350 650 _ Viusec Settling Time (A, = 1) 20V Step to within 1% oo 100 _ nsec 20V Step to within +0.1% _ 300 -_ nsec Small Signal Rise Time (Ay = +1, AVia = 1V) -- 8 20 nsec Small Signal Delay Time (A, = +1, AVin = 1V) _ 10 25 nsec POWER REQUIREMENTS Quiescent Current (Ts = +25C) -- +17 +20 mA NOTES, 1. The TPOOS2 is not output short circuit protected and neither are other vendors 0002s 2. Frequency Response specifications apply for Ta = +25C. 3. See Bode plot. UNITY GAIN (uncompensated) sees & a 2 z < 3 90 w 40 @ eC) { 135 5 6 = 180 100M FREQUENCY (Hi) Figure 1. Bode Plot (Uncompensated) PHASE (degrees) VOLTAGE GAIN (dB) UNITY GAIN (compensated) 3 & PHASE (degrees) 1k 2k Sk 10 100 0M FREQUENCY (Hz) Figure 2. Bode Plot (Unity Gain Compensation) a TELEDYNE PHILBRICK microciacurtsTPO032 = g - z 1s 3 | AMBIENT f10 4 ~ = 2 a o 25 $0 100 125 10 TEMPERATURE {*C) Figure 3. Maximum Power Dissipation CMAR (08) 80 70 5 Lt a a 50 a 40 s =x = oO ae 2 5 100k 1M 10M 700M FREQUENCY (Hz) Figure 4. CMAR vs. Frequency 20 T T T 24 | I Vee = +18 | | { ++ ay fot af TT = | | Ri 1kO a wy | al al E oof = i 5 i z 3 | e 1 + * = 2 | Sg 2 T z o + o 5 14 2 } a { L | | | 12 Pa ! | 10 oO 100, 200 MO 400 S00 2 TIME {ns} SUPPLY VOLTAGE (* Vee) Figure 5. Large Signal Pulse Response Figure 6. Supply Current vs. Supply Voltage TELEDYNE PHILBRICK micaociacuits 5TP0033 High Speed Unity Gain Buffer/Driver Amplifier The TP0033 is a high speed, high inputimpedance, unity gain buffer amplifier that is a pin, package and performance replace- ment for the LH0033. The new device matches or exceeds the performance of its counterpart in all intended applications, including coaxial cable signal driving, high speed A/D input buffering and delivering fast-changing linear current wave- forms for precision CRT graphic displays. The TP0033 has a FET input stage to provide the user witha high (10) input impedance, a low (.5nA) input bias current and a small +10mV input offset voltage that is externally adjusta- ble to zero. The device operates from non-critical +5V to +20V, with single supply operation permitted. With the nominal +15V supplies, the TP0033 delivers a guaranteed output of #12V into 1KQ. Other key large signal specifications include a typice | 1500V/sec Slew Rate and a 25nsec settling time, during which the unit settles a 2V step (typical Flash ADC full scale input) to within +1% (+20m\V) of final value. A 100MHz bandwidth, a 2.9nsec rise time and a 1.2nsec propagation delay are key typical small signal specifications that further suit the TP0033 for high frequency signal buffering applications. Packaged in a 12-pin TO-8 can, the TP0033 is available over a selection of specified operating temperature ranges and levels of reliability processing/screening that is unique in the hybrid microelectronics industry. The industrial/commercial version is fully specified for operation at 25 C to +85 C. For military/aer- ospace applications, the device is specified over the 55C to +125C temperature range. FEATURES Replacement for All LH0033/LHO0033C * High Speed DC to 100MHz Bandwidth 1500V/usec Slew Rate * Multi-Level Screening Options Industrial: -25C to +85C Extended: 55C to +125C APPLICATIONS * Input Buffering Flash ADCs * CRT Deflection Yoke Drive * Coax Line Driver * Critical Military, Biomedical, & Process Control Environments PACKAGE DIMENSIONS = 0100 TYP OFS -a5s5 'A] | os ae a3 sel PIN DESIGNATIONS 1. +Vce 7, OFFSET TRIM 2. N/G &N/C 3. N/C 9. Vee 4G 10. -V 5. INPUT 11. OUTPUT 6 OFFSET PRESET 12. 4+V TELEDYNE PHILBRICK microciacuitsTPO0033 ABSOLUTE MAXIMUM RATINGS Supply Voltage (+Vec Voc) (1) 40V Input Voltage (Pin 5) Vee Output Current (Pin 11) (2) +100mA Maximum Power Dissipation (See Curves) T.5 Watts Operating Temperature Range (Case) 55C to +125C: Specified Temperature Range (Case) TPO0033 -25C to +85C TPOO033-HR (3) -56C to +125C Storage Temperature Range 65C to +150C SPECIFICATIONS (Te = +25C, +Vce = +15V, pin 6 tied to pin 7 unless otherwise indi d.) PARAMETER MIN. TYP. MAX. UNITS VOLTAGE GAIN (4) 0.96 0.98 1.0 VV INPUT CHARACTERISTICS Input Impedance 1079 10" _ 2 Input Bias Current: Initial (Ta = +25C) (5) == 05 25 nA Over Specified Temperature = 10 nA Input Offset Voltage: Initial (T. = +25C) ao 5 10 mv Over Specifed Temperature -- 15 mv Drift vs. Temperature _ +50 o- uve C OUTPUT CHARACTERISTICS Output Voltage: Ry = 1k +12 #13 o Volts R.1000 +9 = aa Volts Vee = +5V, Ri, =1k0 6 Vp-p Output Impedance (4) ose 6 10 9] FREQUENCY RESPONSE Bandwidth (Via = 1Vimns) _ 100 ad MHz Phase Nonlinearity (BW = 1--20MHz) _ 2 _ Degrees TIME RESPONSE Slew Rate (Vin = +10V) 1000 1500 = Wusec Rise Time (AV. = 0.5V) _ 29 _ nsec Propagation Delay (AV. = 0.5V) o 1.2 aoe nsec Harmonic Distortion (f=1kHz) === <0.1 oo Xe POWER REQUIREMENTS Quiescent Current Drain: *Vcc = +15V 20 22 mA Vee = +5V -_ 18 -- mA Power Consumption: *Vsc = +15V 600 660 mw Veo = $5V ron 180 mw NOTES Vee Must be applied ta both pin 1 and pin 12. Vc. must be applied to both pin 9 and pin 10. 2. The TPOOGS is not output short circuit protected Peak instantaneous output current must not exceed +250mA. Continuous output current must not exceed *100mA. 3. The TPOOSG-HR is fully tested and specifed for 55C to +125C operation 4. Vie = Wwe f= VKHz, Ay = 1K, A, 1O0KO: 5. Measured in still air 7 minutes alter application of power, * Select A = S00 for best pulse response: 1% ~ overshoot 2% For all cases ausuwe that AVin at =O. Sly = '250mA INPUTS For all cases assure that AVin aD <b Slo = +250mA = = Figure 1. Coaxial Cable Driver Figure 2. Capacitive Drive TELEDYNE PHILBRICK microcircuits 7TP0033 +12 +10 -T CL = 120pf +84 uu = = t3t CL = 330pf / o 16 2 Fk +47 = a = of o 42+ << o b oy oo] & -27 < = ~ ri o 4 o RL=1KQ 6 Vee = t15V > i RL =1KQ -10-4 -8 Rs = 502 -10 4 FREQUENCY (MHz) --- -12 FT 1 1 i" 4 i 1 4 4 4 4 4 q T T T T T T T T T T 1 3 10 30 100 o 10 20 30 40 #50 60 70 TIME (n$) TIME nS Figure 3. Frequency Response for Various Loads Figure 4. TP0033 Large Signal Response 60 2.5 50% *Voc 407 = S ~Vec es a 30 + 207 |. 4 4 1 4 1 | 1 i T T Tt t T T T T qT 01 .03 A 3 1 3 25 50 75 100 125 150 FREQUENCY (MHz) TEMPERATURE (C) Figure 5. Power Supply Rejection Ratio Figure 6. Maximum Power Dissipation 8 TELEDYNE PHILBRICK microciacuits1435 High Frequency Fast Settling Operational Amplifier We TELEDYNE ~ PHILBRICK 1435 MADE IN USA The 1435 is an ultra-fast, differential-input operational ampli- fier designed for precision amplification (gain accuracies to 0.01%) of wide-band, complex waveforms with frequency com- ponents from DC to 100MHz. Such performance is made possi- ble by a unique design with high open-loop gain, flat frequency response beyond 10kHz, and smooth 6dB/octave rolloff to greater than 100MHz. Applications for the 1435 are based on using the precision capabilities of the basic differential-input op amp at frequencies higher than previously possible. These include 20 to 40dB gain, differential-input, video mixers with 0.1% gain stability; peak detectors (and sample and holds) that can capture 50ns 10V pulses to 1% accuracy and 70ns pulses to 0.01% accuracy; video A/D and D/A converters; and submicrosecond, precision analog comparators. The standard 1435 is specified for 0 C to 70C operation. The 1435-HRA is specified over the 55C to +125C temperature range and screened for military/aerospace applications. FEATURES * 70ns Settling to 0.01% 1GHz GBW Product CMRR 70dB @ 1MHz * 100dB Open Loop Gain * 55C to +125C Operation APPLICATIONS Radar and Sonar Signal Processing * Microwave Transmitter Modulators * Graphic CRT Displays * Linear Video Mixers * Video A/D, D/A, S/H PACKAGE DIMENSIONS 088 Max (2.24) OWARD PINS: 30 he. Com ee Veo NC ONC ONC 4 (051) 6oo 6 a _ 018 Ose (046) Dia Dimensions in parentheses are expressed in. cm. PIN DESIGNATIONS OPTIONAL CAP +1N OUT 1 8 2 9 NC 3. COMP CAP 10. WC 4. +Vee Wow 5. EOS TRIM 12. Vee 6. EOS TRIM 13. CURRENT SOURCE 7, -IIN 14. CASE COMMON TELEDYNE PHILBRICK microciacuits1435 SPECIFICATIONS (+25C, Vec = +15V, Ri =5000, unless otherwise indi TYPICAL GUARANTEED OUTPUT RANGE Voltage (Peak) (6)(7) +7V +5V Current (6)(7) +14mA +10mA Short Circuit Current (8) +35mA4/16mA _ VOLTAGE GAIN (DC Open Loop) Rated Load 100d B 900dB FREQUENCY RESPONSE (Inverting and Noninverting) (1) Small Signal (Gain-Bandwidth Product) (2)(7) 1000MHz TOOMHz Small Signal (Unity Gain Open Loop) 150MHz os Sine Wave Power Out 10MHz BMHz (C1 = 0.5pF) Peak to Peak Out (Triangle Wave) 12MHz _ Capacitive Load without Oscillation (NG > 2) 1000pF (C. = 3pF) TIME RESPONSE (Inverting and Noninverting) (1) Settling Time (3) 10V Step to within 2.5mV (0.025%)(1435) 60ns 85ns (1435-HR) 60ns 75ns (Cr = 1pF) 10V Step to within imV (0.01%) 7Ons (Ct = 1pF) _ 5V Step to within 50mV (1%) 25ns = Smv (0.1%) 40ns 60ns 1 Step to within 10mV (1%) 10ns. _ imV (0.1%) 20ns = Slew Rate (1)(7) 300V/us 250V/us (C1 = O.SpF) Overshoot 1% _ Propagation Delay 5ns - Rise Time (10V Step) 40ns - Overload Recovery Time 50ns INPUT VOLTAGE RANGE/CMRR/IMPEDANCE Common Mode for DC Linear Operation (7) +8.5V +7V Common Mode Fault, absolute max. - +10V Differential Between Inputs, max. see +4 Common Mode Rejection Ratio at DC (7) 100dB 80dB Common Mode Rejection Ratio at 1MHz (4) 70dB Input Impedance at DC (Common Mode) 1MQ || 2pF - Input Impedance at DC (Differential) 2.5kO||2pF INPUT OFFSET VOLTAGE Initial (without External Trim) (6)(7) +amVv +5mV Zero Adjustment (optional) _ 1kQ pot Vs. Temperature (7) +5uVirC +250 Vs. Power Supply (PSRR) O1SMVVAVee INPUT BIAS CURRENT Initial (without External Trim) (7) 10uA. 20uA Vs. Temperature (7) 50nArC 100nA/* GC Input Offset Current 0.3uA a Input Offset Current T.C. 2anArG a NOISE (Referred to Input) Flicker (0.01Hz to 10Hz) Voltage (Peak to Peak) 15uV Current (Peak to Peak) 2.5nA _ Midband (100Hz to 10kHz) Voltage (RMS) 1.6uV Current (RMS) 2.504 _ Wideband (10Hz to 1MHz) Voltage (RMS) 5.2uV Current (RMS) 3.504 = POWER REQUIREMENTS Nominal Supply Voltage 415 Supply Voltage Range os +12 to +16 Quiescent Current @ Vee = 15V (7) oo +30mA TEMPERATURE RANGE Specified 1435 - orc to 70C 1435-HR -- 55C to +85C; +125C with 18C/watt heat sink Storage _ 65C to +150C MTBF (5) 1435-HR 1.06/10" hours 10 TELEDYNE PHILBRICK micaocincuits1435 NOTES. 1. Frequency response and slew rate measurements made in standard circuit 2. Measured at 10MHz 3. Settling time measured in standard circuit, See Figure 3 for plot settling time vs. noise gain. 4, See Figure 2 for plot of CMAR vs. frequency. 5, Calculated per MIL Handbook 2178 at 85C. 6 100% interim tested for -HR version 7. 100% final electrical tested for -HIA version @ The 1435 has a class A output stage. 120 100 s Pg I = s 8 3 0 a s 5 = 5 2 = a 60 Oo ~ 20 40 100 200 S00 Tk 10% 100% 1M 10M 100M 1G FREQUENCY (He) 20 Figure 1. Open Loop Gain and Phase vs, Frequency igo 6 cite 100% aie ion Tc0M Frequency {Hz} Figure 2. 1435 CMRR vs, Frequency 250 200 - = Supply : pS | pe 10 E a Spy 5 a | 100 = PI] @ 4 X ii 50 4 40 + + 0 20 $0 100 tk 10K 100K Tht 0 2 4 6 8 A, Nowe Gain 1+ aise Gain Ag, Figure 3. Typical Settling Time vs. Noise Gain Frequency (Hz) Figure 4. PSRR vs. Frequency TELEDYNE PHILBRICK microcincuits 111437/37D/38 Wideband Fast-Settling Operating Amplifiers The 1437 and 1438 are designed to offer versatility in wide- band steady state and fast transient applications. The absence of large transients and oscillations in the settling waveform makes these op amps dependable system elements that help solve settling problems associated with A/Ds, D/As,and sam- pling circuits. Among their competitors, the 1437 and 1438 stand out for their speed and predictability, exemplified by their fast and smooth settling. The 1437 and 1438 have excellent DC characteristics with +200pA input bias currents, 95dB open loop gains, and +0.5mV input offset voltages. The choice of a single external compensa- tion capacitor allows for maintenance of a 40MHz bandwidth over a variety of gains, with slew rates up to 400V/ysec. A true differential input ensures equally superior performance in all system configurations whether they are inverting, non- inverting, or differential. With their attractive price/performance ratios, the 1437 and 1438 should prove to be new industry workhorses in the fields of data acquisition and high-speed, high-accuracy signal processing. The 1437 is packaged in a TO-99 can and the 1437D is packaged in a 14 pin metal dip package. Each has a quaranteed +20mA output. The 1438 is packaged in a TO-8 can and has a guaranteed +50mA output. Standard devices are fully specified for 0C to +70C operation, and full Military/Aerospace screen- ing is available. Se 350MHz Gain-Bandwidth Product FET Input 40MHz Operating Bandwidth * 110ns Settling Time to 0.1% +20mA and +50mA Outputs * 14 Pin Dip Dual Op Amp * Small TO-99 and TO-8 Packages Single External Compensation Capacitor APPLICATIONS * Current to Voltage DACs * Pulse Amplifiers * Radar and Sonar Signal Processing * Graphic CRT Displays Video A/D, D/A, and S/Hs PACKAGE DIMENSIONS. 1 0.76 (.030) 051 (020) 5.33 1.2700 a a 4.180) _ 0.48 019) Gay OTE 9.40 (370) Oe LEADS Dia. _PIN DESIGNATIONS _ OFFSET TRIM INVERTING INPUT NONINVERTING INPUT OUTPUT 1 2 3 4. Vec 5. OFFSET TRIM 6 7 8. COMPENSATION Foe em A DIMENSIONS ARE IN MM, THOSE IN PARENTHESES ARE IN INCHES 12 TELEDYNE PHILBRICK microcincuits1437/37D/38 SPECIFICATIONS (Tc = +25C; Vee = +15V; 1437: Ri = 5000; 1438: Ri = 2000) TYPICAL GUARANTEED OUTPUT RANGE Voltage (Peak) (5) +12V +10V Current (5) 1437: +24mA 20mA Current (5) 1438: +60mA +50mA VOLTAGE GAIN (Open Loop @ f = 10Hz) (4)(5) Rated Load 95dB 88dB FREQUENCY RESPONSE Gain-Bandwidth Product (1) 350MHz -- Unity-Gain Bandwidth 40MHz aad Full Power Bandwidth C. = OpF 6.0MHz = C. = 15pF 3.1MHz ane TIME RESPONSE Settling Time (2) 10V Step to 15% 85ns 10V Step to 0.1% (5) 110ns 140ns 10V Step to 0.025% 150ns = Small Signal Rise Time C. = 15pF ns see Slew Rate Ce = OpF 400Vius ae C. = 15pF 225Vius o INPUT VOLTAGE RANGE/CMRR/IMPEDANCE Common Mode for DC Linear Operation (5) +12V +10V Absolute Max. Differential Between Inputs _ +20V CMRA @ DC (315) 78dB 60dB PSRR @ OC 76dB = Input Impedances @ DC (Differential) 10m? ||3pF _ Output Impedance (Open Loop) 900 INPUT OFFSET VOLTAGE Initial (Without External Trim) (5) +0.5mV amv Vs. Temperature (Ri = 2) (5) +15pV/"C +50uv"C INPUT BIAS CURRENT Initial (Without External Trim) +200pA, _ Bias Current over Rated Temperature Doubles every 10C o Offset Current L20pA on NOISE (Referred to Input) O.1Hz to 100Hz 4uVp-p _ 0.5uV (RMS) = 100Hz to 10kHz SuVp-p = uv (AMS) _ 10kHz to 1MHz 50uVp-p = Bu (RMS) _ ISOLATION 1437D 100kHz 80dB = MHz 64dB. = 5MHz 52dB. = POWER REQUIREMENTS Nominal Power Supply Voltage +15 _ Supply Voltage Range = +12V to +20V Quiescent Current @ Veo = +15V (4)(5) +12mA +15mA Short Circuit Current (4)(5)(6) 1437: S0mA, - Short Circuit Current (4)(56) 1438: 125mA TEMPERATURE RANGE Operating 1437, 1438 _ OC to +70C Military Version + 55C to +125C Thermal Resistance(@c) 1437: 95C/Watt _ Thermal Resistance(@c) 1438: 50C/Watt _ Thermal Resistance(@,) 1437: 220C/Watt - Thermal Resistance(@ia) 1438: 125C/Watt Storage All Units 65C to +150C NOTES & 100% final electrical tested for Military verseon 6. Finned heat sink use recommended if long term short circuits can occur Without finned heat sink, short-circuited duration should be limited to ~ 10s. 1. Measured al 10MHz. C. 0. 2. Settling lime measured in circuit of Figure 1 3. See Figure 8 for plot of GMAR vs. frequency. 4 100% interim tested for Military version, TELEDYNE PHILBRICK microciacuits 131437/37D/38 PACKAGE DIMENSIONS 0.88 MAX (2.24) 0.195 MAX (495) 020 MIN (0.51) ! W (28) 0.30 052 MAX VIEW TOWARD PINS (O76) (1.32) 66060666 6 14 4 DUAL 1437 TOP VIEW 1..A-IN 8. BOUT 2. A+IN 9, BCOMP 3. ATRIM 10. BTRIM 4, Vee 11. +Vec 5. B-IN 12, AOUT 6. B+IN 13. ACOMP 7. BTRIM 14. ATRIM 018 DIA. (046) DIA, oi TYP - : Dimensions in parentheses are expressed in em. (0:25) TYP (358) 10.29 4.408) 531 205) 15.37 (605) Pioo3 (3957) 495 (198) + 1 11 (585) 2.67 (105) [7 sas i565) OM 241.095) 2.67 4.105) PIN DESIGNATIONS [7-13.59 (535) *]] 2.41 1.095) 74 "|| 1 N/C 7. N/C 4.45 (175) MAX 4 2, OFFSET ADJ 8. OFFSET ADJ. oe (038) a 3. INVERT IN 9. OUTPUT 127 (50) MIN. ~ L018) 914 (096) 4. NON-INVERT IN 10. +15V 1 51 (.020) MAX 45 660 (026) 5. 15V 11. COMP. INPUT DIMENSIONS ARE IN MM BS aes 6. N/C 12. N/C THOSE IN PARENTHESES ARE IN INCHES 4 ad Reter to 1430 data sheet for discussion 2k Of Settling-lime measurement 2k -15 1 Loo 2kn 2kn AS HP 5082-2811 oF equivalent All resistors 1% All capacitors 10% 39 Input <= Output ae = 20 mV Time Zero 100 ns/cm TYPICAL PERFORMANCE CURVES 100 yp je ' ; SO | sal : a am | ow pF a ROK ser i eo |_ N jee. 180 NX Lo | 10 pf 4, 18 = 4 | RAK 3 AY 20: cl NX \ ov XN 5 V/Div of | SN -6V og tk 2 S 10k o1M u TOM oo Frequency (Mi) FV 20 mV/Div Figure 1. Settling Time Test Circuit and Graph Figure 2. Open Loop Gain and Phase vs. Frequency 14 TELEDYNE PHILBRICK microcircuits1437/37D/38 1 2 4 8 16 a2 64 Inverting Gain Figure 3. Full Power Bandwidth vs. Inverting Gain inverting Gain Figure 4. Slew Rate vs. Inverting Gain - Y| if TIN i, / ee, \ L TK A Sat 7 SN RE, . 2 4 10 12 4 40 80 100 120 140 Ceomp (oF Settling Time (na) Figure 5. Settling Time vs. Output Voltage Change Figure 6. Noise Gain vs. Ccomp for 16% Overshoot bi] 100 / Sy t = = = z 3 = & 50 + _ 60) \ oN 100 1k 10, 100k 1M 1 Te 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure 7. CMRR vs. Frequency Figure 8. PSRA vs. Frequency, APS = 1% TELEDYNE PHILBRICK microciacuits 15Fast Settling Fully Differential FET Input Op Amp The combination of high speed, wide bandwidth, excellent DC characteristics, and low-gain stability place the 1443 at the forefront of high performance operational amplifiers. Its 2GHz gain-bandwidth product, 1000V/usec slew rate (when compen- sated for unity gain), and 130nsec settling time clearly make it an outstanding high speed device. It has been carefully engi- neered to eliminate the low-gain stability problems that have historically plagued high frequency op amps. For example, asa unity gain follower, the 1443 has a small signal 3dB bandwidth of 120MHz, but still has 35 of phase margin with a 54pF capaci- tive load ... using no exotic circuit techniques. The 1443 has a fully differential FET input followed by a bipolar gain stage that together result in excellent DC charac- teristics. CMRR is 90dB minimum. Offset voltage and bias cur- rent are guaranteed less than +2mV and +50pA respectively. Open loop gain is 100dB minimum. External compensation with a single capacitor allows users to tailor 1443 performance for different applications. The 1443 is packaged in a TO-3 can, and the standard device is fully specified for OC to +70C operation. The 1443-HR is fully specified for 55C to +125C operation and screened for military/aerospace applications. FEATURES Excellent Low-Gain Stability 80MHz Unity-Gain Bandwidth * 1000V/us Slew Rate @ Acu= 1 +10V, +100mA Output 130ns Settling to 0.01% 20pA Input Bias Current APPLICATIONS * Video Instrumentation High Speed Follower Low Error Current Integrator Radar * Video Frequency Filters * Video Line Driver PACKAGE DIMENSIONS TO-3 Metal Can 38.62mm (1.56") PIN DESIGNATIONS 16 TELEDYNE PHILBRICK microciacuitsSPECIFICATIONS (Typical @ Te = +25C, Vcc = +15V, unless otherwise indicated). 1443 1443 1443-HR TYPICAL GUARANTEED TYPICAL GUARANTEED OUTPUT RANGE Voltage +13V +10.25V +13V +10.25V Current (4) +130mA +100mA +130mA +100mA Current (5) = +50mA Short Circuit Current (1) +160mA, +160mA = VOLTAGE GAIN (DC Open Loop) Ri = 1000 (4) 105dB 95dB 105dB 9508. Ri = 1000 (5) ae = 90dB FREQUENCY RESPONSE ean: Bandwidth Product (small signal) = 100kHz, Ri = 2000, Cc = open 2.0GHz = 2.0GHz ose { = IMHz, Ri = 2000, Ce = 10pF (4) 120MHz S0MHz 130MHz 1O0MHz f = 1MHz, Ri = 20029, Gc = 10pF (5) = = 80MHz Unity-Gain Bandwidth u = kN, Cc = short BOMHz _ BOMHz = Settling Time Ri = 100, Ce = short Step to 1% 50ns -- 50ns -- 10V Step to 0.1% 80ns _ 80ns a 10V Step to 0.01% (4) 130ns 165ns 130ns 150ns 10V Step to 0.01% (5) _ 250ns Slew Rate (2) Ri ea Ce = short (4) 1O00V/us S00V/ys 1200s 1000V/us Ce = short (5) = = = BOOV/us Destablleing Load Capnete 1000, Ge = short, Ac ~300pF a -300p F eee paar VOLTAGE RANGE/CMRR Common Mode for DC Linear Operation +oV +7 +9V +7 Common Mode Fault, Absolute Max. - Vex _ Vice Differential Between Inputs 25V -- 25V Common Mode Rejection Ratio at DC (4) 90dB 80dB 100dB 80dB at DC (5) _ _ 80dB at 10MHz 35dB o 3508 le INPUT OFFSET VOLTAGE Initial (without external trim) (3)(4) Imv +3mV +0.5mV tam Over Temperature (5) = _ +8mV Vs. Power Supply (PSRR) 90dB 70dB 90dB 75dB INPUT BIAS CURRENT Initial (4) *10pA +S0pA 10pA '50pA Over Temperature (5) _ --- o +20nA Vs. Temperature doubles every aad doubles every 10C - 10C NOISE OC to 10Hz 50uV(p-p) SQuV(p-p) i Above 10Hz 20nVisHz -- 20nViyHz = POWER REQUIREMENTS Nominal Supply Voltage *15V _ +15 _ Supply Voltage Range = *12V to +18V on *12V to +18V Quiescent Current +45mA +55mA, +45mA, +55mA, TEMPERATURE RANGE Specified (Case) ie OPC to +70C _ 55C to +125C Storage 65C to +125C _ 65C to +125C NOTES 1. 1443 is not output short circuil protected. See Thermal Considerations. 4, @ 425C 5 @ -5$to H25C oh 4 Trimmable to zero. See Connection Diagram. 26 T a # = = 5 20 P z 5 @ = 5 = 2 z a eg & | AC SINE WAVE = ais Pe LOAD RESISTANCE ((2) RESISTANCE $0 100 180 200 on) 1d 150 200 Figure 1. Maximum Allowable Case Temperature vs. Figure 2. Worst Case Power Dissipation Load Resistance With Worst Case Power Dissipation vs. Load Resistance TELEDYNE PHILBRICK microciacuits 17100k 200k 500k IM 2M SM 10M 20M 50M 100M 200M FREQUENCY (Hz} Figure 3. Gain and Phase vs. Frequency for Variable Compensation Fi 100k 200k 500k IM 2M SM 10M 20M SOM 100M 200M FREQUENCY (Hz) igure 4. Gain and Phase vs. Frequency for Variable R, 45 7 ] ] 35 1 1c = SHORT | + o 25 | | | 10 ale } | { 21 20 8 | | 2 Zz + t | J 39 = | 3 o BT ape 10 | ' a ao 5 ; + 50 a t + 5 ' is, { 70 1 0pF 10 } we hot 1 H oor 10pF | is 100pF), a | le 2% 50 100 200 2k 20k 200%, 2M. 20M 200M iM 2M OM 20M 50M 100M 200M SOOM FREQUENCY (Hz) FREQUENCY (Hz) Figure 5. CMRR vs. Frequency Fh PSRR VS. MEANS THAT SUPPLY BYPASSES CAN BE USED am 20 200k PSAR VS. FREQUENCY (Hz) Figure 7, PSRR vs. Frequency 2M 20M Follower Figure 6. Gain and Phase vs. Frequency for Variable C, , g 10 20 INVERTING GAIN (a8) Figure 8. Utilizable Full Power Bandwidth TELEDYNE PHILBRICK microcircutsHigh Power VMOS Output Operational Amplifier The 1460 heralds a new era in high power, wideband opera- tional amplifers. Originally designed for ATE signal amplifica- tion and pin driving, the 1460 surpasses its competition in speed and output capabilities with a 1GHz gain-bandwidth product, a 300V/usec slew rate, and a full +30V, +150m<A output. The 1460 is a full differential input, single-ended output device with inter- nal current limiting. External compensation with a single capa- citor allows users to tailor 1460 performance for different applications. With a maximum operating frequency of 10MHz, the 1460 is ideally suited for high speed, high gain configurations that require a +30V, high current output. It has been optimized for gains greater than five, making it a superb choice for either analog or digital signal amplification at video frequencies. Secondary breakdown problems associated with most power op amps are virtually eliminated in the 1460 through the use of a unique VMOS output stage. The output voltages and currents are limited only by power dissipation and not by safe operating area curves. The 1460 is a 0C to +70C device that comes in an 8 pin, TO-3 package. For any condition in which the amplifier will be dissipating more than one watt of power, an external heat sink must be used. The thermal resistance of the device is 20 C/watt 8 and 50C/watt Ga. Junction temperatures should not exceed 150C for normal operation or 200C for a short-circuit condition. For units with military/aerospace screening, please contact factory. FEATURES +30Volt, +150mA Output VMOS Output Stage * No SOA Restrictions 1GHz GBW Product * 300V/usec Slew Rate e Fully Differential Input APPLICATIONS * Video Amplifiers Video Yoke Drivers ATE Pin Drivers Driving Inductive and Capacitive Loads PACKAGE DIMENSIONS. t PIN DESIGNATION OUTPUT OFFSET ADJUST # Ver 1 2. 3 4. +1N 5.-IN 6. Vee 7. COMP 8. COMP. /OFFSET TELEDYNE PHILBRICK microciacuits 191460 SPECIFICATIONS (+25C, Vec = +36V), unless otherwise d. TYPICAL GUARANTEED OUTPUT RANGE Voltage (Ri = 2000) +31V +30V Current +200mA +150mA DYNAMIC RESPONSE Gain Bandwidth Product C. = OpF 1.0GHz C. = 40pF 150MHz _ Rise Time O to +5V Step 70ns = O to +30V Step 400ns = Settling Time 10V Step to 0.1% B00ns -_ 0V Step to 0.1% ws om Slew Rate c.=0 300Vius - C. = 40pF 65V/us 50V/us VOLTAGE GAIN (DC Open Loop) Rated Load 92dB 80dB INPUT VOLTAGE RANGE Common Mode (Fault Condition) +Vee 1.5V to +Vec 55V Differential Input Voltage, max. _- +6V CMRA 85dB 70dB PSRR 100dB 75dB INPUT OFFSET VOLTAGE Initial +1imV +5mV Vs. Temp. 0C to 70C +10uV/C +50uV/C INPUT BIAS CURRENT Initial +5uA +104 Input Offset Current +0.3A, - Input Bias Current T.C. 0.8%" C a POWER REQUIREMENTS Nominal Voltage +36V a Quiescent Current +20mA +25mA Short Circuit Current 250mA 300mA max. Supply Voltage Range ooo +15V to +40V TEMPERATURE RANGE Operating Temperature (Case Temp.) oC to +70C Storage Range 65C to +150C Figure 1. 1460 Bode Plot Ccomp Frequency Phase Frequency Slew pF at Unity Gain at Unity Gain at 180 0 74MHz 275 5MHz 250V/us 10 74MHz 267 25MHz 125V/us 20 55MHz 277 32MHz 84V/us 40 5O0MHz 216 S6MHz 50V/us 80 32MHz 165 37MHz 28V/us 180 17MHz 132 45MHz 25V/us 330 10MHz 118 5OMHz 7Vius TELEDYNE PHILBRICK microcincurtsGAIN (dB) 3 100k 1M FREQUENCY (Hz) Figure 2. Phase Margin ce 1:28MHz B40kHz S20kHz 160kHz BOkHz 40kHz 1 2 4 8 16 32 64 INVERTING GAIN at R, = 2002 MAXIMUM FULL Figure 4, Full Power Bandwidth vs. Inverting Gain ane oc SLEW RATE (V/us) s8a88 1 2 4 8 16 32 Lad INVERTING GAIN at Ry, = 20012 Figure 6. Slew Rate vs. Inverting Gain 128 1460 490 1082 12 2002 load * 100pF for Coomp = 180pF 200pF for Ccomp = 330pF OpF otherwise Figure 3. Standard Configuration @ BO 2 c c & 60 1OHz 100Hz tkHz 10kHz 100kHz FREQUENCY Figure 5. CMAR vs. Frequency 5 160 < 80 S Fe 5 40 < = 20 oO 3 10 Ee 5 a z = 3 1 2 4 8 16 32 64 128 256 R NOISE GAIN (1 + 2f) "Fj Figure 7, PSRR vs. Frequency TELEDYNE PHILBRICK micaociarcurts 211461 High Speed High Power VMOS Output Op Amp The 1461 is an extremely fast, FET input, VMOS output, power op amp. It operates from +15V to +40V supplies and has output voltages up to +34V and output currents up to +750mA. Its unique VMOS output stage eliminates the safe operating area (SOA) restrictions and secondary breakdown problems that plague virtually all other presently available power op amps. The 1461's ability to handle high output currents at any voltage eliminates the normally intricate problems caused by driving capacitive or inductive loads. The 1461s combination of speed and power characteristics is unmatched. Even if it weren't a power amp, its 115dB open loop gain, 1GHz gain-bandwidth product, and 1200V/usec slew rate would make it an outstanding high speed op amp. The 1461 is packaged in an 14 pin dual-in-line with ears for easy mounting to heat sinks. Compensation is accomplished with a single external capacitor. Two external resistors are optional for current limiting. The standard 1461 is specified for 0C to +70C operation. The 1461-HR is available fully specified for 55C to +125C operation and screened for military/aerospace applications. FEATURES * +30 Volt, +600mA Output VMOS Output Stage * No SOA Restrictions * FET Input 1GHz GBW Product 1200Visec Slew Rate * 55C to +125C Operation APPLICATIONS * Video Yoke Drivers * Video Distribution Amplifers * High Speed ATE Pin Drivers High Accuracy Audio Amplification Driving Inductive and Capacitive Loads PACKAGE DIMENSIONS ooo0o000 4 | a as e000006 All dimensions are expressed in inches, P| Evora De -0.002 Tye 1 o 2 3 a Min 6. PIN DESIGNATIONS 7 IN +IN NC NIC Vee CURRENT LIMIT NIG 8, OUTPUT 9. +CURRENT LIMIT 10. +Vex 11. COMP. 12. COMP 13. OFFSET ADJUST 14. OFFSET ADJUST TELEDYNE PHILBRICK microciacuits1461 ABSOLUTE MAXIMUM RATINGS Supply Voltage (+Vee) +45V Differential Input Voltage +25V Common Mode Input Voltage Vee Output Short Circuit Current (1) +800mA Operating Temperature Range (Case) 55C to +125C Specified Temperature Range (Case) (2) 1461 OPC to +70C 1461-HR 56C to +125C Storage Temperature Range 65C to +150C SPECIFICATIONS (+25C, Vcc = +36V, unless otherwise indicated). PARAMETER MIN. TYP. MAX. UNITS OPEN LOOP VOLTAGE GAIN (Ri =10k0) 100 115 _- dB INPUT CHARACTERISTICS Offset Voltage: Initial _ $0.5 +5 mv Drift vs. Temperature +25 +50 BEC Drift vs. Supply (PSRR) wee +10 _ uN Bias Current: Initial _ +1 +100 pA Drift vs. Temperature - Doubles every 10C _ Common Mode Voltage for DC Linear Operation +25 +28 - Vv Common Mode Rejection Ratio (3) 90 100 _ dB Noise (Referred to Input): 0.1Hz to 100Hz _ 45 _ uVp-p 1O0Hz to 10kHz _ 15 -_ uV(RMS) 10kKHz to IMHz _ 6 - uV(RMS) OUTPUT CHARACTERISTICS Voltage Swing: Ru = 500 (5) +27 +29 = v Fi = 10k0) +30 +34 Vv Current, +15V = Vee = +40V +600 +750 mA FREQUENCY RESPONSE Gain-Bandwidth Product, C. = OpF, f = 100kHz B00 1000 - MHz Unity-Gain Bandwidth, C. = 20pF (4) aad 15 -- MHz Slew Rate: C. = OpF, Ru > 1k 900 1200 _ Viusec Ce. = 30pF, Ai > 1k _ 150 = Visec Settling Time, C. = 30pF, Ri = 500 25V Step to 0.1% (25mV) _ 05 1 psec 25V Step to 1% (250m) = 350 = nsec 10V Step to 0.1% (10mV) 400 = nsec 10V Step to 1% (100mvV) -- 250 - nsec POWER REQUIREMENTS Supply Voltage Range +15 +36 +40 v Quiescent Current +20 +25 mA NOTES 1. Internally short circuit current limited 2 See Figure 1 4. See Typecal Performance Curve section for CMAR vs frequency graph. 4. Teledyne Philorick suggests the use of a 20pF compensation capacitor when using the 1461 in an inverting unity gain configuration. The recommended compensation for a follower contiguration is 40pF 5. See graph of maximum output voltage vs. output current. Ee care TELEDYNE PHILBRICK microcircuits 231461 2 38 RATED DISSIPATION (WATTS) CASE TEMPERATURE (C) 25 50 75 100 125 150 Figure 1. Rated Dissipation vs. Case Temperature 120 PN oN 7 FREQUENCY [Mat 100 1% 1, SoD ry 7 Figure 3. CMRR vs. Frequency | 1% 0.1% 20} __ 1 10 |} Ccomp = 15pF RL = 50m Noise Gain = 4 OUTPUT VOLTAGE STEP SIZE (V) 1 3 o | I 8 | ~30 SETTLING TIME (ns) 100 300 500 Figure 5, Output Voltage vs. Settling Time 700 CcomPtpF) Ig (mA) 100 8 ! na co T ol Ne / 9 LSLEW RATE (W/us} Ph | 100 300 500 700 900 1100 1300 1500 Figure 2, Ccomp vs. Slew Rate Le 3 6 10 Vee VourT (Volts) Figure 4. Guaranteed Output Voltage vs. Output Current 100 Tk 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 6. Bode Plot 10 PHASE TELEDYNE PHILBRICK micnocincurs1463 High Speed High Power VMOS Output Op Amp The 1463 is third in a series of high speed, FET input, VMOS output power op amps. It operates from +15V to +40V supplies and has a guaranteed output of +28V at 1A with +36V supplies. The complementary VMOS output stage eliminates the safe operating area (SOA) restrictions and secondary breakdown problems that plague virtually all other presently available power op amps. Internally compensated for unity gain stability, the 1463 still achieves an outstanding 80V/us slew rate (under full load condi- tions), 7.5MHz gain-bandwidth (GBW) product, and 250ns set- tling time to 0.1% (10V step). Input bias current and offset voltage are guaranteed less than +200pA and +5mV respectively. The 1463 is packaged in an 8-pin TO-3 package. The stand- ard device is fully specified for 55C to +125C operation. Complete military/aerospace screening is available. FEATURES +28V, +1A Output * Class AB Complementary VMOS Output Stage (No SOA Restrictions) * 250ns Settling to 0.1% (10V Step) 7.5MHz GBW Product * 80V/us Slew Rate * Unity Gain Stable APPLICATIONS * Video Yoke Drivers Video Distribution Amplifiers CRT Displays Driving Inductive and Capacitive Loads PACKAGE DIMENSIONS b-(0-768"" (1.187 +0.01")- 7.4mm 1 (0.277") T2.29mm 10.16mm 0.09") (0.400"}min. 101mm | } (0.040")dia. TO-3 Metal Can 30.15 + 26mm PIN DESIGNATIONS 1 2 3. t+Hunair 4. ~The 5. -IN 6. +IN 7 8 Vex OFFSET TRIM 12.7 mm (0.500"")dia. pin circle TELEDYNE PHILBRICK microcincuits 251463 ABSOLUTE MAXIMUM RATINGS Supply Voltage (+Vee) Differential Input Voltage Common Mode Input Voltage Operating Temperature Range (Case) Specified Temperature Range (Case) Standard 1463, and -HR Version (1) +42V +25V + Vee 55C to +125C 55C to #125C Storage Temperature Range 65C to +150C Maximum Junction Temperature (Output FETS) +150C SPECIFICATIONS (+25C, Vcc = +36V, unless otherwise indicated). PARAMETER MIN. TYP. MAX. UNITS OPEN LOOP VOLTAGE GAIN: (Ri = 10k) 95 105 _- dB (Fy = 280) = 95 _ dB INPUT CHARACTERISTICS : Offset Voltage: Initial = +2 +5 mV Drift vs. Temperature +20 _ ve Bias Current: Initial -_ +10 +201 pA Drift vs. Temperature _ Doubles every 10C = - Common Mode Voltage Range for OC Linear Operation _ +28 _ Vv Common Mode Rejection Ratio 90 100 = dB OUTPUT CHARACTERISTICS (2)(3) Voltage Swing: (Ri = 10k) +30 +34 _ Vv (Ri = 289) +28 +30 _ v Current (continuous) +4 es! Pee A FREQUENCY RESPONSE Gain-Bandwidth Product: (Ri = 10k) _ 7 me MHz (Pi = 2802) - 75 _ MHz Slew Rate: (Ri = 10k) Ear +165 _ Vius (Ri = 289) +50 +80 _ Vins Settling Time: (Ri = 509) _ 250 a ns 10V Step to 0.1% (10mV) _ _ = ee THERMAL CHARACTERISTICS Thermal Resistance: ic = 3 = CW Gin ~ 33 _ "c/w POWER REQUIREMENTS Supply Voltage Range +15 +36 +40 Vv Quiescent Current _ +60 +70 mA. NOTES: 1. Military/Aerospace Screening. 2. User must provide adequate heat sinking. 3.-55C ST. S +125C. Va Your Nae Figure 1. 1463 with Foldback Current Limiting TELEDYNE PHILBRICK microciacuits1463 10008 ! -o 1 I 4 ! ez B0dB ! ao Z / 4 : z i a 60dB ; 60" w = ; 2 4 o Pd = 40d - 90 Veo = 236V 208 GAIN PHASE Od - : , 1OHz 100Hz 1KHz 10KHz 100KHz IMHz 10MHr Figure 2. 1463 Bode Plot POSITIVE SUPPLY . NEGATIVE SUPPLY OB T T T T rT 1OHz 100Hz 1KHz 10KHz 100KHz 1MHz 10MHz Figure 3. 1463 Power Supply Rejection 10048 + 20 a0dB 60 @ 60dB i B40 = * & 4008 20 2048 Veo = 36 0 ods 10 20 30 40 50 VeelW) WOH: WOH: KHz 10KHz 100KHz IMHz 10MHz Figure 4. 1463 Common Mode Rejection Figure 5. Quiescent Current vs. Supply Voltage TELEDYNE PHILBRICK microcircuits 271464 High Speed Power MOSFET Driver Amplifier The 1464 is ahigh speed, FET input, transconductance ampli- fier, designed to drive an external power MOSFET output stage. The use of an external output stage makes the 1464 extremely versatile, allowing the users to tailor the part to their require- ments. It operates from +10V to +50V supplies. Input bias current and offset voltage are guaranteed less than +200pA and +5mV, respectively. The 1464's high output imped- ance (30MQ, typical) combined with its transconductance of 5,000 uhmos (typical), allows the user easily to construct power op-amps with open loop gains in excess of 100dB. The 1464 is packaged in an 8-pin TO-3 package. The stand- ard device is fully specified for 55C to +125C operation. Complete military/aerospace screening is available. Figure 1. 1464 Standard Configuration FEATURES * FET Input Wide Supply Range: H10V to +50V * User Selected VMOS Output Stage (No SOA Restrictions) * Configure Class AB or Class B APPLICATIONS * Deflection Yoke Drivers PWM Motor Drive Amplifiers Video Distribution Amplifiers * ATE Pin Drivers High Performance Audio Amplifiers PACKAGE DIMENSIONS TO-3 Metal Can ous eos PIN DESIGNATIONS +lour equTRUT SOURCE + Ver * Toanait IN +N Ve Tout souTPUT SINK! 28 TELEDYNE PHILBRICK microciacuitsABSOLUTE MAXIMUM RATINGS Supply Voltage Differential Input Voltage Common Mode Input Voltage Operating Temperature Range (Case) Specified Temperature Range (Case) Standard 1464, and -HR Version (1) +55V +25V Me -55C to +125C 58C to +125C Storage Temperature Range 65C to +150C SPECIFICATIONS (+25C, Vcc = +36V, unless PARAMETER MIN. TYP. MAX. UNITS INPUT CHARACTERISTICS Offset Voltage: Initial _ +2 +5 mv Drift vs. Temperature _ +20 = BiG Bias Current: Initial _ +10 +200 pA Drift vs. Temperature aa Doubles every 10C _ Common Mode Voltage Range for DC Linear Operation _ +28 _ Vv Gommon Mode Rejection Ratio 90 100 o dB TRANSFER CHARACTERISTICS Transconductance 5,000 a pmhos Open Loop Gain (Ri = *) 95 103 _ dB OUTPUT CHARACTERISTICS Output Resistance _ 30 = Mo Output Compliance Voltage (Ri = =) 433 +35 -_ Vv Output Drive Current +8 mA Output Bias Current 5.5 65 7.5 mA POWER REQUIREMENTS Supply Voltage Range +10 +36 +50 Vv Quiescent Current +30 +36 mA NOTES 1. Military/Aerospace Screening DESIGN CONSIDERATIONS The 1464 is designed to drive a complementary power MOSFET output stage. The output stage can be run Class B (for low quiescent power dissi- pation) or Class AB (for low distortion, fast set- tling), as shown in Figure 2. The 1464 supplies a quiescent output bias current of ~6.5mA between pins 1 and 8 in order to drive the output FET bias circuitry (for Class B operation, short pins 1 and 8). The output bias current has a negative temper- ature coefficient of ~12.5uA/*C (Figure 3); if the 1464 is mounted to the same heat sink as the output FETs, this will allow the use of a simple, single resistor bias scheme. If the output FETs are mounted on a separate heat sink, temperature compensation must be provided externally; one way of doing this is shown in Figure 4. This circuit, known as a Vee multiplier, will provide a tempera- ture coefficient of ~3.2mV/C per volt of bias voltage (transistor Q1 must be mounted on the same heat sink as the output FETs). The 1464 is a differential input transconduc- tance amplifier. To construct a high performance operational amplifier, it is only necessary to adda high input impedance output stage. The low- frequency voltage gain of the 1464 is determined by its transconductance and load resistance: Avwv = Qm(Rt|/Ro) where: gm = transconductance of 1464 = 5,000umhos (typical) Ri. = load resistance (input resistance of external output stage) a 6 | = output resistance of 1464 = 30MN (typical) TELEDYNE PHILBRICK microcircuits1464 foe. (6. 5mAj, Ver Vee la=0 | lq = 5-S0mA | Figure 2. Output Stage Biasing (Class B) Figure 2. Output Stage Biasing (Class AB) OUTPUT BIAS CURRENT (mA) BOs Vee = +36V 5.0 40 4 -60 -40 -20 0 20 40 60 80 100 120 CASE TEMPERATURE (C) Figure 3. 1464 loutput Bias vs. TCase 30 TELEDYNE PHILBRICK microcincurtsWee 1 p Ole t 1 "MOUNT ON COMMON HEAT SIN Se Vers = Vaeion Mit Fa 2 Figure 4. Biasing Output Stage Using a V By using a MOSFET output stage, the load re- sistance is maximized, and thus high gain is achieved. The maximum gain achievable is lim- ited to ~103dB (typical) by the output resistance of the 1464 (30MQ typical). The input capacitance of the output stage creates a dominant pole in the amplifier transfer function. Thus, the 1464 is compensated by the input capacitance of the output stage. Increasing this capacitance will increase stability, but will reduce slew rate and frequency response. An alternative method of compensation is to lower the input resistance of the output stage; this does not affect slew rate as much, but does reduce open loop gain at all frequencies. Taking load capacitance into account, the gain of the amplifier will be: Qm(Ru|Ro) TE re eri nace catogies 1+277(Ril|Ro)Ci where C. = load capacitance (input capacitance of output stage) Several typical circuits are shown in Figures 6, 7, 8, and 9; their performance is compared in Figure 10. Ferranti/Supertex FETs were chosen as the output devices due to their comparatively low capacitance, which allows higher slew rates and wider bandwidths. Other FETs may be used if desired, or FETs may be paralleled for increased current output. J Current Limiting The 1464 has provisions for current limiting via pins 3 (+lumm) and 4 (lumir). The basic current limit configuration, shown in Figure 1, requires two transistors and two resistors. The current limit resistors are chosen such that: 0.6V lunit where lumir = desired limit current R = current limit resistor R= 1464 Different positive and negative current limits may be used, if desired. Figure 5 shows a foldback current limiting scheme which limits short circuit current to a small fraction of the full load current. The value of the limiting resistors may be determined as follows: R= 08v Imax Vee Re = om _ ae 06VRalso where Imax = lout at maximum Vout Short circuit current (lout at Vout = OV) Isc = If no current limiting is desired, pins 3 and 4 should be left open and power should be applied directly to pins 2 and 7. Bypassing For optimum performance and noise rejection, power supplies should be bypassed with 1yF tan- talum capacitors in parallel with 0.01uF ceramic capacitors. These should be mounted as close to the 1464 as possible. Additional bypassing should be used at the output stage, with a minimum of 10uF per amp of output current. These capacitors should be tantalum also, and should be mounted close to the drains of the output FETs. Layout and bypassing are critical for short settling times; more bypassing may be required if this parameter is critical. Thermal Considerations In most applications the 1464 and its output stage will require a heat sink. If the 1464 is mounted on the same heat sink as the output stage, the user will have to consider its power dissipation (2.6W maximum at Vec = +36V) as well as the power dissipation of the output transistors. In circuits where the 1464 is not mounted on the same heat sink as the output stage, the 1464 will generally require a separate, small heat sink when operated at supply voltages greater than Vee = +20V. The thermal resistance of the 1464 (case to ambient) is approximately 30C/W. Thus, operat- ing at Vec = +36V (lee = +36MA max., Po = 2.6W max.) without a heat sink would cause the case temperature to rise (2.6W) (30C/W) = 78C above ambient. A small, clip-on heat sink, such as the AAVID 4791B, would reduce this to approxi- mately 38C above ambient. A larger heat sink may be required at higher voltages, or at high ambient temperatures. TELEDYNE PHILBRICK microciacuits 311464 +Vec =Voe Vox Vour Wee 1) O.6V Ralsc Imax a lout Figure 5. 1464 With Foldback Current Limiting +36 10uF TANTALUM ole $4.72) 1q=25mA fw 1 | VNO109 (SUPERTEX) jor ZVNO109 [(FERRANTI) ul ! | ViPO109 ISUPERTEX} lor zvP0109 | (FERRANTI L--p $4.72 4W 10uF TANTALUM 389 our MOUNT 1464 AND OUTPUT DEVICES ON COMMON HEAT SINK ADJUST A, FOR Iq = 25mA Figure 6. +30V, +100mA Output High Speed Op Amp TYPICAL CHARACTERISTICS (Vec = +36V, Te = 25C, Ri = 3000) Slew Rate +500Vius Unity Gain Bandwidth 26MHz Open Loop Gain (DC) 103dB: Output Voltage (lour = 100mA) +30V Output Short Circuit Current +125mA Settling Time (Ac. = 5, +10V Step, 0.1%) 110ns STABLE FOR NOISE GAINS = 3 4+36V 10uF TANTALUM bat | Our bo.an| !a=25mA , IW NON ] INDUCTIVE | yNo209 isuPERTEX) | or ZVNO209 (FERRANTI) | 'yPO209ISUPERTEX) ! or ZVPO209 '(FERRANTI) U 0.82 Ww -NON-INDUCTIVE 10WE TANTALUM | -26v0 oN. MOUNT 1464 AND OUTPUT DEVICES ON COMMON HEAT SINK *ADJUST A, FOR Iq = 25mA Figure 7, +28V, +560mA Output High Speed Op Amp TYPICAL CHARACTERISTICS (Vcc = 436V, Tc = 25C, Ru = 50M) Slew Rate 175Vips Unity Gain Bandwidth 19MHz Open Loop Gain (DC) 1030B Output Voltage (lour = 560mA) +28V Output Short Circuit Current 750mA, Settling Time (Acc 1, t10V Step, 0.1%) 150ns UNITY GAIN STABLE 32 TELEDYNE PHILBRICK microciacuirs1464 SY aur TANTALUM po Ole o2n aw WOM INDUCTIVE Inia a I PWAENIO ISUPERTEX jor ZVN1109 (FERRANTH 1 1 bot jWPTNIO isueEATER jf 2VP1 108 FERRANTH om JW NONINOUCTIVE Owe atuF aay TANTALUM MOUNT Q, AND OUTPUT DEVICES.OM COMMON BEAT SINK **ADIUST Ay FOR Ig Mien Qy = 2N3904 Figure 8 +30V, +2A Output Op Amp TYPICAL CHARACTERISTICS (Vee = #36V, Te = 25C, Ri = 150) "EY toque TANTALUM 1 2 on Os NOM INDUCTIVE | i | 1 pvnn2 IRTEX) oF Fp | 2WN200 FERRANTI 263906 P1210 ISUPERTER o 2VPI2000F ERAANTI 1 | 1 ' 1 -d pots vd ow NONINDUCTIVE Ot 100uF VY TANTALUM MOUNT 0, AND OUTPUT DEVICES ON COMMON HEAT SINK, **ADAUST Ry pon ig= Hee Qy = 2N3904 Figure 9. +28V,+5A Output Op Amp TYPICAL CHARACTERISTICS (Vcc = +36V, Tc = 25C, Ri = 5.69) Slew Rate +100Vius Slew Rate +50Vips Unity Gain Bandwidth SMHz Unity Gain Bandwidth 2MHz Open Loop Gain 100dB Open Loop Gain 96dB Output Voltage (lour = 2A) +30V Output Voltage (lour = SA) +28V Output Short Circuit Current 3A Output Short Circuit Current BA Settling Time (Ac. = 1, +10V Step, 0.1%) 230ns Settling Time (Aa = 1, +10V Step, 0.1%) 750ns UNITY GAIN STABLE UNITY GAIN STABLE TYPICAL PERFORMANCE Vcc = +36V, Te = 25C, Ru = Rated Load (See Notes) Slew Settling Time | Unity Gain Circuit/See + + Note Pour | 2our | dour Rate _| (0.1%, +10V Step) ath| A | Figure No. $ 3W +30v | +100mA | +500Vs | 110ns (Acc =-5) | 26MHz | 10348 6 Ce es 1s7w | +2av | +560mA | +175Vjus | 150ns (An =1) | 19MHz | 10308 7 gee hls 6ow +30V +24 +100Vjus | 230ns (Ac =-1) | 9MHz | 10008 8 Oe aaa 140W +28 +5A +50Vus | 750ns (Aan =1) | 2MHz | 96dB 9 sp aes Figure 10. Comparison of Amplifier Performance TELEDYNE PHILBRICK micaociacurts 331467 Low Drift/High Freq. Fast Settling Video Amplifier The 1467 is an ultra-fast, differential-input video operational amplifier that combines highly stable DC characteristics with exceptional high speed performance. The unit is designed for precision amplification of wide-band, complex waveforms with frequency components from DC to 100MHz. The 1467 provides flat frequency response beyond 10KHz, smooth 6dB/octave rolloff to beyond 100MHz and high open loop gain. The 1467 is unique in that it also provides an ultra-low input offset voltage of only 30uV and drift of 1uWC, typically. Applications include differential input video mixers with 20 to 40dB gain and 0.1% gain stability; high resolution 0.01% gain accuracy, high speed 20MHz data acquisition systems and pulse amplifiers. FEATURES 70ns Settling to 0.01% 1GHz GBW Product * CMRR 70dB @ 1MHz 115dB Open Loop Gain 55C to +125C Operation Low Offset Voltage and T.c1 APPLICATIONS Radar and Sonar Signal Processing * Microwave Transmitter Modulators Graphic CRT Displays Linear Video Mixers Video A/D, D/A, S/H PACKAGE DIMENSIONS O88 Max (2.24) VIEW 6ee0e066 142 Max PIN DESIGNATIONS 1, OPTIONAL CAP 8. +N 2. OUT NC 3. COMP CAP 10. NC 4. +Vec WG 5. EOS TRIM 12, Vee 6 EOS TRIM 13, CURRENT SOURCE 7, -IN 14. CASE COMMON TELEDYNE PHILBRICK microcincuits1467 SPECIFICATIONS (+25C, Vee = +15V, Au = 5000) 1467 1467-HR TYPICAL GUARANTEED GUARANTEED OUTPUT RANGE Voltage (Peak) +7V +5V +5V Current +14mA #10mA +10mA Short Circuit Current (5) +35mA/16MA _ _ VOLTAGE GAIN (DC Open Loop) Rated Load 115dB 90dB 90dB FREQUENCY RESPONSE (inverting and Noninverting) (1) Small Signal (Gain-Bandwidth Product) (2) 1000MHz = TOOMHz Small Signal (Unity Gain Open Loop) 150MHz a Sine Wave Power Out 10MHz _ _ Peak to Peak Out (Triangle Wave) 12MHz _ o Capacitive Load Without Oscillation (NG > 2) = = 1000pF (C, = 3pF) TIME RESPONSE (inverting and Noninverting) (1) Settling Time (3) 10V Step to Within 2.5mV (0.025%) 60ns g5ns 75ns (C, = 1pF) 10V Step to Within Im (0.01%) 7Ons (Cr = 1pF) _ -_ 5V Step to Within 50mV (156) 25ns _ _ 5V Step to Within 5mV (0.1%) 40ns _ 60ns WV Step to Within 10mV (1%) 10ns _ _ 1V Step to Within 1mV (0.1%) 20ns _ o-- Slew Rate (1) 300Vius 250Vius (C, = O.5pF) 250Vius (C, = O.5pF) Overshoot 1% _ _ Propagation Delay 5ns _ _ Rise Time (10V Step) 40ns -_ =< Overload Recovery Time 50ns ~ o INPUT VOLTAGE RANGE/CMRR/IMPEDANCE Common Mode for DC Linear Operation +8.5V _ +7V Common Mode Fault, Absolute Max. _ _ +H10V Differential Between Inputs, Max. _ a +4V Common Mode Rejection Ratio at DC 110dB _ 80dB Common Mode Rejection Ratio at IMHz (4) 70dB ad oo Input Impedance at DC (Common Mode) MQ ||2pF _ Input Impedance at DC (Differential) 2.5k0||2pF - = INPUT OFFSET VOLTAGE Initial (Without External Trim) +30uV +500uV +500uV Zero Adjustment (Optional) 20kNpot ma Vs. Temperature t1nVeC$ - +10pvierc Vs. Power Supply (PSRR) GASMVVAV ce = INPUT BIAS CURRENT Initial (Without External Trim) 100A, 25uA 25uA Vs. Temperature S0nA/*C _ 250nA/C Input Offset Current 200nA _ = Input Offset Current T.C. anArc os oss NOISE (Referred to Input) Flicker (0.01Hz to 10Hz) Voltage (Peak to Peak) 15uV a ae Current (Peak to Peak) 2.5nA _ _ Midband (100Hz to 10kHz) Voltage (RMS) 1.6uV = Current (RMS) 2.5nA -- =~ Wideband (10Hz to 1MHz) Voltage (RMS) 5.2uV Current (RMS) 3.5nA _ POWER REQUIREMENTS Nominal Supply Voltage +15V = oa Supply Voltage Range _ +12 to +16 +12 to +16 Quiescent Current @ Vec = $15V -- +35mA 35mA TEMPERATURE RANGE Specified 7 OPC to +70C 58C to +85C; +126C with 15C/W heat sink specs. guaranteed to +115C Storage = = 65C to +150C TELEDYNE PHILBRICK microcircurts 351467 NOTES 1. Frequency response and shew rate measurements made in standard circuit 2 Measured at 10MHz, 3. Settling time measured in standard circuit. See Figure 4 for plot settling time vs. noise gain 4. See Figure 3 for plot of CMAR vs. Irequency. &. The 1467 has. a class A output stage 1467 BODE PLOT SUPPLY 5 +SUPPLY Open Loop Gain (a8) a "160 200500 tk 1% 100% om one 00s 16 5 2 50 100 1k 10k 100k "1M Frequency (Hr) Figure 1. Open Loop Gain and Phase vs. Frequency Figure 2. PSRR vs. Frequency 120 . 100 250 Ss. - 80 = 3 = S E 180 - e 6 5 ee Ss = ee oe ee 40 | | 50 Ca 20 Ik 2 5 10k 100k 1M 10M 100m 0 2 4 6 8 10 12 Frequency Hz) R Noise Gain 1+ cise Guin 1+ BE Figure 3. 1467 CMRR vs. Frequency Figure 4. Typical Settling Time vs. Noise Gain mmr ram 36 TELEDYNE PHILBRICK microciacuits1480 Fast Settling High Voltage Operational Amplifier The 1480 is a fully differential FET-input op amp capable of operating over a supply voltages of +15V to +150V with common-mode and output voltages ranging to within 10V of the supply voltages and with output currents to +75mA. The 1480 is pin compatible with the Burr-Brown 3583, but has traded off de and drift characteristics for time and frequency perfor- mance. The 1480 settles a full 100V step to +0.01% (10mV) in less than 2.5usec. Gain-bandwidth product is 20MHz. Slew rate is 100V/usec, and full power bandwidth is 100kHz. The input of the 1480 is fully overvoltage protected. It can withstand common mode voltages to +(Vcc +5)V, differential voltages to +450V, and input voltage slew rates to 150kV/usec. Output current is short circuit limited at +125mA. The true differential FET input (typical CMRR is 125dB) limits input bias current to +200pA maximum. The bias and offset current drifts are small enough to reduce greatly the large offset drifts nor- mally associated with high voltage circuits. The 1480 is packaged in a TO-3 can. Standard units are fully specified for 0C to +70C operation. For military/aerospace applications, the 1480-HR is fully specified, screened and tested for 55C to +125C (case) operation. FEATURES +150V, +75mA Output 2.5usec Max. Settling Time (100V Step to +0.01%) +140V Common Mode Voltage Input Overvoltage and Output Short Circuit Protected Standard TO-3 Can BB3583 Compatible 55C to +125C Operation . APPLICATIONS ATE Pin Drivers Electrostatic Deflection High Voltage DACs PACKAGE DIMENSIONS 3.96 10 13mm 10 186 20 006 aa 42 Teno} S00" kha TO-3 Metal Can pan cwcle 3016 a tiene (187 O01) PIN DESIGNATIONS 1. OUTPUT 2. tVce 3. OFFSET TRIM 4. OFFSET TRIM 5. -IN 6. +N 7. Vee & N/C TELEDYNE PHILBRICK microcircuits 371480 ABSOLUTE MAXIMUM RATINGS Supply Voltage (+Vec, pins 2, 7) Input Voltage (pins 2, 7) (1) Differential Input Voltage (1) Input Slew Rate (1, 2) Output Short Circuit Current (3) Operating Temperature Range (case) Specified Temperature Range (case) 1480 1480-HR Storage Temperature Range SPECIFICATIONS (+25C, Vcc = +36V, unless otherwise indicated). +160V +(Vee +5)V +450V +150kViusec +125mA -55C to +125C O to +70C 55C to +125C 65C to +150C PARAMETER MIN. TYP. MAX. UNITS OPEN LOOP VOLTAGE GAIN RF, = 10kn _ 120 = dB Ri = Rated Load 95 115 = dB INPUT CHARACTERISTICS Common Mode Voltage for DC Linear Operation +(Vee 10) _ v Common Mode Rejection Ratio: @ DC 110 125 - dB @ 1MHz - 43 dB Input Offset Voltage: Initial (+25C) (4) a +1 +3 mV Drift vs. Temperature _ +15 +100 BNC Drift vs. Supply (PSRR) _ +0,001 +0.01 mv Input Bias Current: Initial (+25C) a +50 +200 pA Drift vs. Temperature _ Doubles every 10C = _ Input Offset Current: Initial (+25G) _ +40 - pA Drift vs. Temperature a +5 _ pArec OUTPUT CHARACTERISTICS Output Voltage (lo = +75mA) +140 #143 _ Vv Output Current (3) +75 +100 - mA Noise (referred to input) (5) O.1Hz to 10Hz _ 10 me iN eme 10Hz to 10kHz - 25 - Vim Maximum Capacitive Load 100 250 = pF FREQUENCY RESPONSE Gain Bandwidth Product (f = 100kHz, AL = 102//2pF _ 18 os MHz Unity-Gain Bandwidth (Open Loop) - 5 a MHz Full Power Bandwidth (280V,-p, Ri = 10kQ) = 120 _ kHz TIME RESPONSE Slew Rate - 100 -- Viusec Settling Time: 100V Step to +0.01% (+10mV) -- 14 25 usec 100V Step to +0.1% (+100mV) = 1 1.5 psec Overload Recovery Time - 1 ae psec POWER REQUIREMENTS Supply Voltage Range +15 - +150 Vv Quiescent Current am +10 +12 mA. NOTES Includes power-off conditions. ws Such shorts do stress the input, however, and we cannot guarantee protection for durations exceeding a few seconds. wo on The 1480's output is short-circuit protected to ground or either supply for supply voltages totaling less than 100, tis short-circuit protected to ground only for supplies totaling up to 160V. Trimmable to zero with external 100k0 potentiometer between pins 3 and 4 and 4Vcc. Measured in a high-gain configuration with the inpul grounded through a small resistance. The high differential voltage and dv/dt ratings of the input prevent input stage blowout even if the input is directly shorted to either rail, 38 TELEDYNE PHILBRICK microcincuits5 Femtoampere Bias Current Operational Amplifier ae atin el Ze Esai ae Pg Ps Le The 1702, with 5 femtoamp bias current (5 x 10 'A) maxi- mum, is designed to be used in circuits where extremes in low error currents, low current noise, high input impedance, high common mode voltage and high common mode rejection ratio are critical design requirements. Features include a full output frequency response of 40Hz min. common mode voltage of 100V, CMRR of 100,000 and an offset voltage drift of 3Qu\V/C max. These features are comple- mented by its small size (1.5 inches square by 0.6 inches high) and epoxy encapsulation for reliability in areas of shock and vibration. The epoxy also forms an isothermal environment for protection against thermal spikes. The unit is totally enclosed by a metal cup for protection against spurious signals from associated circuitry. Input bias current of the 1702 is measured as the maximum into either input. Therefore, the 1702 can be used for inverting, non-inverting, and differential applications. For DC applica- tions where the initial voltage offset may affect performance, an optional 50k pot will zero this voltage. Complete short circuit protection of the input and output circuitry is provided for added reliability. Note: The 1702 can operate with +100V of common mode voltage when Vee = 12V. FEATURES * 2fA Bias Current Typical * 1fA/C Bias Current T.C., Typical 10uV/C Eos T.C. * 100V Common Mode Voltage @ Vee = +12V APPLICATIONS * Electrometers Photo-Diode Amplifiers pH Meters * Long Term Integrators * Charge Amplifiers Femto-Ammeters PACKAGE DIMENSIONS (0.5 0)MIN ILERANCE BETWEEN PIN ASE EDGE TO CENTER OF PIN 1 NON-CLUMLILATIVE 02 TOLERANCE FRO 020 MIN 1054 OUT 9 TRIM & Weew Toward Pint DIMENSIONS ARE IN MM THOSE IN PARENTHESES ARE IN INCHES TELEDYNE PHILBRICK microciacuits 391702 SPECIFICATIONS (+25C, Vcc = +15V, unless otherwise indicated.) TYPICAL GUARANTEED OUTPUT RANGE Voltage (Peak) Current +40V +5mA VOLTAGE GAIN (OC Open Loop) Rated Load 100dB FREQUENCY RESPONSE (Inverting) Small Signal (Unity Gain, Open Loop) Gain @ SHz Large Signal Full Output (Undistorted) Large Signal Full Output (Peak to Peak) Slew Rate / Max. Capacitive Load Without Instability 500Hz 50Hz 0.5V/msec O.4uF 37dB 20Hz INPUT VOLTAGE RANGE Common Mode DC Linear Operation Common Mode Fault Differential (Betweeen Inputs} Common Mode Rejection Ratio *100V +200V 100dB INPUT VOLTAGE OFFSET Initial (Without External Trim) @ 25C Zero Adjustment (Optional) Vs. Temperature (Avg. 0 to +70C) 50k pot +5mV +3QuViePC NOISE Flicker (0.016Hz to 1.6Hz) Midband (1Hz to 100Hz) TyVp-p 10uV(RMS) INPUT BIAS CURRENT Initial @25C Vs. Temperature (Avg. 0 to +70C) Vs. Power Supply O.001pA/"C O.0005pAV 0.005pA 0.002pA/C INPUT IMPEDANCE Differential Common Mode (Either Input to Common) 3% 10" O)/15pF 10" 0 POWER REQUIREMENTS Nominal Supply Voltage Supply Voltage Range Quiescent Current +15V +12 to +18 +1amA, -BmA TEMPERATURE RANGE Operating (Rated) Operating (Derated) Storage 25C to +85C O to +70C 55C to +125C 30082 s 10D 1 *o" ~ FE JS ott T= RC = 100,000 sec. Figure 1. Long Term Integrator : Connect to Guard Figure 2. Follower With Gain-Guard Drive To minimize errors caused by leakage currents, a foil guard should be put around the input pins. The guard conductor should be connected to a potential that is very close to or equal to the voltage being applied to the input. In this manner any stray leakage currents will be intercepted before they reach the inputs, and since the guard is at approximately the same potential as the inputs, no leakage currents will be generated, Connect the guard to ground for inverters or | to Vs, to the output for unity gain followers, and to a buffered attenuator (see Figure 2) for follower with gain. For additional application information, request AN-3. 40 TELEDYNE PHILBRICK microcircuits4058 Fast, 12 Bit High Reliability D/A Converter The 4058 is a true 12 bit digital to analog converter with TTL compatible inputs. It has user programmable output voltage ranges of 0 to 5V, 0 to -10V, +2.5V, +5V, and +10V and output current ranges of Oto +4mA and +2mA. It is one of the fastest settling D/As available, guaranteeing output settling to +LSB in 2.5usec for a 20V step to 200nsec for a 4mA step. The standard 4058 is fully specified for 0C to +70C operation. The 4058 guarantees full performance over the 55C to +125C temperature range. The 4058 is packaged in an industry-standard, hermetically sealed, metal dual-in-line package. Active laser trimming results in integral and differential linearity errors quaranteed not to exceed +LSB. For the most critical applications, exter- nal gain and offset adjustments are user optional. The 4058 operates from +15V supplies with no need for a +5V logic supply. Power consumption, at 645mW maximum, is extremely low for a device of this speed. FEATURES e +Fast Settling to +0.01% 2.5usec Max. 20V Step 200nsec Max. 4mA Step e +%@LSB Max. Integral and Differential Nonlinearities * Monotonicity Guaranteed Over Temperature * Power Consumption 645mW Max. 55C to +125C Operation APPLICATIONS * Military Environments High Reliability Industrial Equipment * Data Distribution Systems e Precisions Displays e Portable Instrumentation PACKAGE DIMENSIONS 1.39 MAX r (3.53) MAX =| Foo ost) MA | o20 qiosn MIN 0.018 +001 DIA (0.046 + 003 DIA) TELEDYNE PHILBRICK microciacuits 010 (0.25) 1 PIN DESIGNATIONS eeceeoocoeoo6 i } 1. BIT 12 (LSB) 24. -10V REF. OUT 1 12 | 2. BIT 11 23. -15V SUPPLY : | 3. BIT 10 22. POWER GROUND VIEW TOWARD PINS agi oom 4. BIT 9 21, +15V SUPPLY ae 5, BIT 8 20. 5V SCALE ai 5 t 6 ot 7 19, 10V SCALE : | 7. BIT6 18, OUTPUT OFFSET Peeeesee cen? } ! 8. BITS 17, GAIN ADJUST o10 208 Stik 9. BIT 4 16. ANALOG GROUND (0254 + 013) =? (0.368) 10. BIT 3 15. Vout 1. BIT2 14. SUMMING JUNCTION 17 EQUAL SPACES 12. BIT 1 (MSB) 13. +IN TOLERANCE NONCUMULATIVE 44058 ABSOLUTE MAXIMUM RATINGS +15V Supply (+Vec, Pin 21) 15V Supply (+Vee, Pin 23) Digital Input Voltage (Pins 1-12) Output Short Circuit Duration (1) Operating Temperature Range Specified Temperature Range +18V 18V Oto +7V Continuous to Ground -56C to +125C 4058 OC to +70C 1456-HR (2) 55C to +125C Storage Temperature Range 65C to +150C SPECIFICATIONS (Ta = +25C, +Vcc = +15V unless otherwise indi d.) PARAMETER MIN. TYP. MAX. UNITS DIGITAL INPUTS Logic Levels: Logic 1" +2.0 +5.5 Vv Logic o" 0 oo +0.8 Vv Loading (3) _ a 1 TTL Load Logic Coding (4): Voltage Output _ CBIN, COB _ Current Output BIN, OBIN - ANALOG OUTPUT Voltage: Ranges Unipolar _ Oto -5, 0 to -10 Vv Ranges Bipolar = +2.5, +5, +10 -_ v Output Current +5 +20 oo- mA Output Resistance oo 0.05 _ Q Short Circuit Current (1) i +25 _ mA Max. Capacitive Load _ 50 -= pF Current: Range Unipolar _ Oto +4 -- mA Range Bipolar +2 a mA Output Resistance Unipolar o 1.5 = kQ Output Resistance Bipolar 12 _ kQ Compliance Voltage 40.6 -- = Vv TRANSFER CHARACTERISTICS Integral Linearity Error: +25C nas +My Yh LSB oC to 70C (4058) _ + _ LSB -5C to +126C (4058-HR) -_ tM -- LSB Differential Linearity Error _ +u, +M% LSB Guaranteed Monotonicity: 4058 0 _ +70 C Guaranteed Monotonicity: 4058-HR -55 +125 C Zero Offset Error: (5) Voltage Output: Unipolar (000...000) _ | +4 LSB Bipolar (100...000) oo | +4, LSB Current Output: Unipolar (000...000) tM, + LSB Bipolar (100...000) +My a LSB Gain Error (5) (6): Voltage Output a +0.05 +0.2 % Current Output -- +01 +4 % STABILITY Zero Offset Drift: Voltage Output: Unipolar _ +3 415 ppm of FSA/PC Bipolar _ #10 +25 ppm of FSR/C Current Output: Unipolar _ +0.5 4 ppm of FSRA/C Bipolar _ +5 +10 ppm of FSR/C Gain Drift: Voltage Output +10 +20 ppm/?C Current Output _ +7 +20 ppm/C Reference Drift _ 5 +15 ppmieG Power Supply Rejection Ratio = +0.001 0.0024 %FSR/Vs Warm Up Time to Within +1LSB _ 30 cod Seconds DYNAMIC CHARACTERISTICS Settling Time to +%4LSB Voltage Output: 5V Step _ 1.2 2 psec 10V Step _ 12 2 usec 20V Step a+ 19 25 psec Current Output: 4mA Step _ 150 200 nsec Slew Rate _ 16 _ Viusec REFERENCE Voltage = 10.0 _ Vv Accuracy = +1 _ Yo External Load ose a= 2 mA 42 TELEDYNE PHILBRICK microcircuitsPARAMETER MIN. TYP. MAX. UNITS. POWER SUPPLIES Range - +2 % Current Drain: +15V Supply Sard +20 +25 mA Current Drain: -15V Supply _ 13 18 mA Power Consumption _ 495 645 mw L-__-- NOTES 1. The 4058s current and voltage outputs can withstand continous shorts to ground. The reference output (pin 24) can withstand a short for approx. 2 seconds. 2 The 4058-HR is fully specified for -55 to +125C operation. 3A TTL load is defined as sinking 4QuA with a logic 1" applied and sourcing 1,6mA with a logic 0 applied. 4. CBIN = Complementary Binary. COB = Complemetary Offset Binary, BIN = Binary (straight binary). OBIN 5. Adjustable to zero with optional external trim potentiometer. Offset Binary. See Digital Coding Table. 6 Gain error is defined as the error in the slope of the converter transfer function. Itis expressed as a percentage and is equivalent to the deviation (divided by the ideal value) between the actual and the ideal value for the full output voltage/current span from the 0000 0000 0000 output to the 1177 1777 1111 output. APPLICATIONS INFORMATION Grounding and Bypassing High speed systems require added care in power distribution for maximum accuracy and speed. Although power supply inputs on the 4058 are internally bypassed with 0.01uF ceramic capacitors, it is recommended that an additional 1pF tantalum capacitor be added externally between each supply input and analog ground for optimum performance. It is important to realize that power ground (pin 22) is internally connected to the case and must be connected to system analog ground to minimize ground loop errors. It is preferable to have the 4058's analog and power ground pins soldered directly to a large analog ground plane beneath the 4058. Optimizing Settling Time To optimize settling time of the 4058 and to make the settling time independent of the charac- teristics of the digital driver, 2.2kQ \,Watt pull- down resistors are recommended at all logic inputs. Logic Inputs Logic inputs are standard TTL/DTL compati- ble. If any bits are not used, it is recommended they be grounded since an open bit input line is equivalent to a logic 1". Opening the bit lines should not, however, be used as a means of oper- ating a logic 1" due to the possibilities of noise pickup. The table in right column shows the binary input code used by the 4058. If desired, virtually any other binary code can be used with the addition of the necessary external logic. ANALOG OUTPUT DIGITAL INPUT Unipolar Bipolar Voltage Current Binary Offset Binary +F.S. -F.8. 000...000 +4F.S. '6F.S. _ 010...000 +1LSB 1LSB 011...111 0 0 000...000 100...000 1LSB +1LSB 000...001 100...001 +iLF.S. +15F.S. 100...000 110...000 -F.S. +1LSB | +F.S. -1LSB 411...111 194...191 Trim Procedures Initial zero and gain errors may be trimmed to zero using external potentiometers. Adjustments should be made following warm-up, and to avoid interaction, zero should be adjusted before gain. Fixed resistors can be +20% carbon composition or better. Multiturn potentiometers with TCRs of 100ppm/C or less are recommended to minimize drift with temperature. Zero Adjustment For voltage output operation, set the digital input code to 000...000, and adjust the offset trim potentiometer for zero output vol- tage (unipolar) or plus full scale output voltage (bipolar). For current output operation, set the digital input code to 000...000, and adjust the offset trim potentiometer for zero output current (unipolar) or minus full scale output current (bipolar). Gain Adjustment For voltage output operation, set the digital input code to 111...111, and adjust the gain trim potentiometer for minus full scale plus 1LSB output voltage. For current output operation, set the digital input code to 111...111, and adjust the gain trim potentiometer for plus full scale minus 1LSB output current. OUTPUT PIN PROGRAMMING Output Range Output Pin Jumper Pin 14 to Jumper Pin 18 to Jumper Pin 19 to Jumper Pin 20 to Oto -5V Pin 15 Pin 13 Pin 16 (ground) Pin 15 Pin 13 Oto -10V Pin 15 Pin 13 Pin 16 (ground) Pin 15 -- 42.5V Pin 15 Pin 13 Pin 24 Pin 15 Pin 13 +5V Pin 15 Pin 13 Pin 24 Pin 15 + +10V Pin 15 Pin 13 Pin 24 ~ Pin 15 Oto +4mA Pin 13 Pin 15 (1) -- a ot +amA. Pin 13 Pin 15 (1) Pin 24 = me NOTE 1. if oscillations or ringing occur, connect a 100kK0) resistor between pins 14 and 15 TELEDYNE PHILBRICK microcincuits 434065 12 Bit/60nsec Current Output D/A Converter The 4065 is a true 12 bit, straight binary, current-output digital to analog converter with TTL compatible inputs and externally programmable output ranges of Oto +4mA and +2mA. Its speed and the low capacitance of the resistor network are responsible for the 4065's ability to settle a full 4mA step to +0.01%FSR in 100nsec maximum. The standard 4065 is fully specified for 0C to +70C operation. The 4065-HR guarantees full performance over the 55C to +125C temperature range. The 4065 is packaged in an industry-standard, hermetically sealed, metal, 24 pin dual-in-line package. Active laser trimming results in integral and differential linearity errors guaranteed not to exceed +'2LSB and an initial offset error no greater than +%LSB. For the most critical applications, external gain and offset adjustments are user optional. The 4065 operates from +15V supplies with no need for a +5V logic supply. Power consumption, at 645mW maximum, is extremely low for a de- vice of this speed. FEATURES * 60nsec Settling 4mA Step to +%LSB Max. +%2LSB Max. Integral and Differential Nonlinearities Monotonicity Guaranteed Over Temperature * Power Consumption 645mW Max. * 55C to +125C Operation APPLICATIONS * Military Environments High Reliability Industrial Equipment Data Distribution Systems * Fast A to D Converters Precision Displays Portable Instrumentation PACKAGE DIMENSIONS ~ 1.39 MAX ~ (3.59) MAX __PIN DESIGNATIONS TELEDYNE PHILBRICK microcircuitsABSOLUTE MAXIMUM RATINGS +15V Supply (+Vee, Pin 21) =15V Supply (Vee, Pin 23) Digital Input Voltage (Pins 1-12) Output Short Circuit Duration (1) Operating Temperature Range Specified Temperature Range 4065 4065-HR (2) Storage Temperature Range +18V 18V Oto +7V Continuous to Ground 5C to +125C orc to +70C 55C to +126C -65C to +150C 4065 SPECIFICATIONS (Ta = +25C, +Vcc = +15V, unless oth indi d.) PARAMETER MIN TYP. MAX. UNITS. DIGITAL INPUTS Logic Levels: Logic 1" +20 ~ +5.5 Vv Logic 0 0 = +0.8 v Loading (3) = 1 TTL Load Logic Coding: Unipolar Range o Straight Binary _- Bipolar Range = Offset Binary _ ANALOG INPUT Output Range: Unipolar = Oto +4 _ mA Bipolar os +2 o mA Compliance Voltage +0.6 _ _ Vv Output Resistance: Unipolar = 1.5 _ kn Bipolar _ 1.2 ~ kQ TRANSFER CHARACTERISTICS Integral Linearity Error; +25C _ +My +% LSB 0 to +70C (4065) _ +My _ LSB 55C to +125C (4065-HR) -- +% _ LSB Differential Linearity Error -_ +My 4% LSB Guaranteed Monotonicity: 4065 0 _ +70 C 4065-HR 55 -- +125 C Zero Offset Error (4): Unipolar (000...000) o- +, +% LSB Bipolar (100...000) -- + +% LSB Gain Error (4) (5) +0.1 +1 Yo STABILITY Zero Offset Drift: Unipolar _ 40,5 +1 ppm of FSR/C Bipolar = +3 +10 ppm of FSR/"C Gain Drift (6) one +7 +20 ppm/*C Reference Drift _ +5 +15 ppm/*C Power Supply Rejection Ratio = +0.001 40.0024 %FSR/%Vs Warm Up Time to Within +1LSB 30 = Seconds DYNAMIC CHARACTERISTICS Settling Time (4mA Step to +),LSB) = 60 100 nsec REFERENCE Voltage cee 10.0 - Vv Accuracy _ +1 _ % External Load = _ 2 mA POWER SUPPLIES Range =_ +2 oo % Current Drain: +15V Supply = +20 +25 mA 15V Supply = =13 18 mA Power Consumption os 495 645 mw NOTES 1, The 4065's output can withstand a continuous short to ground The reference output (pin 24) can withstand a short for approximately 2 seconds 2. The 4065-HA is fully specified for 55C to +125C operation. 3. A TTL load is defined as sinking 4QuA with a logic 1 applied and sourcing 1.6mA with a logic 0 applied. 4. Adjustable to zero with optional external trim potentiometer. 5. Gain error is defined as the error in the slope of the converter transfer function. It is and is eq) t to ihe (divided by the ideal value) between the actual and the ideal value for the full output current span from the 0000 0000 3000 output to the 119701971 1711 Gutput. 6 Gain drift is measured using the internal feedback resistors, Using an external resistor, the gain drift is typically 35ppm/C. TELEDYNE PHILBRICK microcircuits 454065 APPLICATIONS INFORMATION Grounding and Bypassing High speed systems require added care in power distribution for maximum accuracy and speed. Although power supply inputs on the 4065 are internally bypassed with 0.01yuF ceramic capacitors, it is recommended that an additional iF tantalum capacitor be added externally between each supply input and analog ground for optimum performance. It is important to realize that power ground (pin 22) is internally connected to the case and must be connected to system analog ground to minimize ground loop errors. It is preferable to have the 4065's analog and power ground pins soldered directly to a large analog ground plane beneath the 4065. L.. 2] sro Vv REF OUT Ce oo arn] 7 = 21 | -voe eT] 36 noac oe POWER GND wre | 4oJ zeit ae ON | esvoe are | SO en 25K m | 20vscae at7 | so Minoan 19 | wovseace te | 7oO4 ano aw 18 | mirovam oneset wits | #o ouan VF | Gam anuust wits | 9oJ current BO 18 | anaioc ano SWITCHES, Le | 18 | vour ar? fue 4 4 | by wut y oasoy | 12 oe 13] tur Logic Inputs Logic inputs are standard TTL/DTL compati- ble. If any bits are not used, it is recommended they be grounded since an open bit input line is equivalent to a logic 1. Opening the bit lines should not, however, be used as a means of gen- erating a logic 1 due to the possibilities of noise pickup. The table below shows the binary input code used by the 4065. If desired, virtually any other binary code can be used with the addition of the necessary external logic. DIGITAL INPUT CODING ANALOG OUTPUT DIGITAL INPUT Unipolar Bipolar Current Binary Offset Binary FS. 000...000 '5F.S. 010...000 -1L88 rs O11 0 000...000 100...000 +1LSB 000...001 100...001 +QF.S. 100.,.000 110...000 +F.S.-1LSB 111..191 111,..111 Output Range Selection The table below shows pin connections for 4065 output range selection. OUTPUT PIN PROGRAMMING Output Range | Output Pin Jumper Pin 18 to Oto +4mA Pin 13 _ +2mA Pin 13 Pin 24 Optimizing Settling Time To optimize settling time of the 4065 and to make the settling time independent of the charac- teristics of the digital driver, 2.2kQ \4Watt pull- down resistors are recommended at all logic inputs. Trim Procedures Initial zero and gain errors may be trimmed to zero using external potentiometers as shown in the diagram below. Adjustments should be made following warm-up, and to avoid interaction, zero should be adjusted before gain. Fixed resistors can be +20% carbon composition or better. Multi- turn potentiometers with TCRs of 100ppm/C or less are recommended to minimize drift with temperature. Offset Adjustment When utilizing the internal feedback resistors with an external amplifier, set the digital input code to 000...000, and adjust the offset trim potentiomenter for zero voltage (uni- polar) or plus full scale voltage (bipolar) at the amplifier output. For current output operation, set the digital input code to 000...000, and adjust the offset trim potentiometer for zero output current (unipolar) or minus full scale output current (bipolar). OPTIONAL aM O17] GaIN ADJUST AAA 00K Gain ADJUST OPTIONAL took ZERO ADJUST UNIPOLAR 22M BIPOLAR o67M Gain Adjustment When utilizing the internal feedback resistors with an external amplifier, set the digital input code to 111...111, and adjust the gain trim potentiometer for minus full scale plus 1LSB voltage at the amplifier output. For current output operation, set the digital input code to 111...111, and adjust the gain trim potentiometer for plus full scale minus 1LSB output current. TELEDYNE PHILBRICK micacciacuits4080 Series 12 Bit/250nsec Voltage Output D/A Converters The 4080 Series of 12 bit voltage-output D/A converters pro- vide the ultimate in high speed, high performance digital to analog conversion. Fully three times faster than their nearest competitors, these D/As settle a 10V step to +0.02%FSR (+2mvV) in 250nsec maximum (they typically settle to +0.01%FSR in that time). The 4080 Series consists of three similar devices offering different analog output voltage ranges: the 4080 (0 to -10V and 0 to 5V), 4081 (+2.5V and +5V), and 4082 (0 to +10V and 0 to +5V). 4080 Series devices are housed in industry-standard, hermet- ically sealed, metal dual-in-line packages. Each device contains its own precision reference, and initial gain, offset, and linearity errors are actively laser trimmed to eliminate the need for exter- nal adjusting potentiometers. These adjustments are optional, however, for application requiring greater accuracies. Unlike other presently available high speed D/As 4080 Series devices are TTL (not ECL) compatible and they operate from +15V supplies with no need for a +5V digital supply. Power consump- tion, at 900mMW maximum, is extremely low for devices of this speed. FEATURES @ 250nsec Max. Settling Time e +'LSB Max. Linearity Error * Monotonicity Guaranteed Over Temperature TTL Compatible 900mW Max. Power Consumption APPLICATIONS Digitally Controlled VCOs High Speed Displays High Speed Servo Systems * Multiplexed Data Distribution Systems PACKAGE DIMENSIONS eo00G0000000 -f 1.39 MAX . 1 12 f (3.53) MAX O80 O80 VIEW TOWARD PINS (1.53) (2.03) er] 1 eeeoeee0eee0 ft o145 0.368) PIN DESIGNATIONS 1. BIT 12 (LSB) 24, 10V REF. OUT 2.BIT 1 23, =15V SUPPLY 3. BIT 10 22. POWER GROUND 4.BIT9 21. +15V SUPPLY 5. BIT 8 20. 5V SCALE 6 BI 19. 10V SCALE 7. BIT 6 18. OUTPUT OFFSET a. BITS 17. GAIN ADJUST 9. BIT4 16. ANALOG GROUND 0 BITS 15. Vout 1, BIT 2 14. SUMMING JUNCTION 12. BIT 1 (MSB) 13. +N TELEDYNE PHILBRICK microciacuits 47ABSOLUTE MAXIMUM RATINGS +15V Supply (+Vee, Pin 21) +18V 15V Supply (Vee, Pin 23) 18V Digital Input Voltage (Pins 1-12) Oto +7V Output Current (1) +30mA Operating Temperature Range 55C to +125C Specified Temperature Range: 408X OC to +70C 408X-HR (2) 55C to +126C Storage Temperature Range 65C to +150C SPECIFICATIONS (+25C, +15V supplies unless otherwise d.) PARAMETER MIN. TYP. MAX. UNITS DIGITAL INPUTS Logic Levels (3): Logic 1" +2.0 = +5.5 Vv Logic Oo +0 _ +0.8 Vv Loading (4) _ _ 1 TTL Load Logic Coding (5): Unipolar Ranges Complementary Straight Binary Bipolar Ranges _ Complementary Offset Binary ANALOG OUTPUTS Output Voltage Ranges: 4080 _ Oto -5.0, Oto -10 _ Vv Output Voltage Ranges: 4081 _- 42.5, +5 _ Vv Output Voltage Ranges: 4082 = Oto +5.0 to #10 -- Vv Output Load Current (1) +5 +10 mA Output Resistance = 0.05 = Ohms TRANSFER CHARACTERISTICS (6) Integral Linearity Error _ +1, +, LSB Differential Linearity Error _ +, -- LSB Monotonicity _ Guaranteed Over Temperature - Offset Error (7)(8); 4080 _ +001 o> %FSR 4081 _ 40,05 _ %FSR 4082 -- +0,05 - %FSR Gain Error (7)(9) _ #01 _ Y Reference Output: Voltage se 10.00 = v Accuracy = +0.05 - % External Current oe --- 2 mA STABILITY Integral Linearity Drift _ +1 -- ppm of FSR/C Differential Linearity Drift (10) = +1 ao ppm of FSR/*C Offset Drift: 4080 = +5 ad ppm of FSR/PC 4080-HR o +5 #10 ppm of FSR/C 4081 am +5 _ ppm of FSR/C 4081-HR a +5 #10 ppm of FSA/C 4082 ao +10 _ ppm of FSR/YC 4082-HR. _ +10 +15 ppm of FSA'S Gain Drift +10 #20 ppm/"G Reference Drift - +10 oo ppm/"C DYNAMIC CHARACTERISTICS Slew Rate _ 110 Vipsec Settling Time (2k load): 10V Step to +0.1%FSR(+10mV) oo 125 170 nsec 10V Step to +0.02%FSR(+2mvV) _ 150 250 nsec 10V Step to +0.01%FSR(* 1mvV) - 250 --- nsec 1LSB Step to +0.01%FSA (11) 75 - nsec POWER SUPPLIES Power Supply Range oe +2 % Power Supply Rejection Ratio = +0.6 a LSB/V Current Drains: +15V Supply - +20 +30 mA 15V Supply ao 20 30 mA Power Consumption _ 600 900 mw MTBF _- 2.1 x 106 --- hrs. 48 TELEDYNE PHILBRICK microciacuits4080 NOTES 1. The 4080, 4081, and 4082 are short circuit protected to ground. The reference output (pin 24) can withstand a short to ground for approximately two seconds 2. The 4080-HR, 4081-HR and 4062-HA are specified for 55C to +125C operation. 3. TTL compatible. See Optimizing Settling Time for optional use of pull-down resistors 4. A TTL load is defined as sinking 4QuA with a logic "1" applied and sourcing 1,6mA with a logic "0" applied. 5, See Logic Coding table on page 51, 6. FSR stands for Full Scale Range and is equivalent to the nominal peak-to-peak voltage of the selected output range, i.e, FSA = SV for 0 to +SV, Oto SV, and +2.5V output ranges. FSR = 10V for 0 to +10V, Oto 10V, and +5V output ranges. For a 12-bit converter, 1LSB = 0.024%FSR. 7. Adjustable to zero with external trim. 8. Offset Error is the difference between the actual and the ideal output voltages with a digital input of 0000 0000 0000. 9 Gain error is defined as the error in the slope of the converter transfer function. It is exp asap and is equi ali ideal value) between the actual and the ideal value for the full output voltage span from the 0000 0000 0000 output to the 1111 ane 1111 output. 10. Monotonicity is guaranteed over each device's entire specified temperature range. 11,0997 1991-1991 to 1000 0000 0000 digital input. (divided by the Functional Block Diagram (US) Bis 12 Bint Bia 10 Bao On 8 Qa 7 fe 6 oe 6 er 4 fis 3 fia 2 mse Bir 9 asy F = : ~18h Tl I Our aro = Ota T APPLICATIONS INFORMATION Grounding and Bypassing Unlike mast D/A converters, the 4080 does not have a digital ground pin. It does, however, have separate pins for power supply ground (pin 22) and analog signal ground (pin 16). The device case is connected to the power ground pin. If your system has separate analog power and signal grounds, the 4080 should be connected accord- ingly. If your system employs a single analog ground, both pin 22 and pin 16 should be con- nected to it. For optimum performance and noise rejection, power supplies should be bypassed with 0.1uF tantalum capacitors in parallel with 0.01yuF ceramic capacitors (as shown), and the ca- pacitors should be located as close to the unit as possible. If your system employs a single ground, the D/A's bypass capacitors and load should both be connected to it as close to each other as possible to minimize lead resistance and inductance, The normally low impedance exhi- bited by PC board runs can become significant in Power Supply Bypassing Pin 21 TL. +15V 0.01nF O.1uF a Pins 16, 22 Ground 0.01bF= == O.1uF Pin 23 15V high frequency applications. For high speed D/As, the result may be an inability to achieve the manufacturer's specified linearity and settling time. To minimize these impedances, PC runs should be as wide as possible. This is particularly important for analog and digital ground runs as they are the reference point for all other circuit voltages. For optimum results, ground plane tech- niques are essential in reducing ground impedan- ces and stray capacitance between signal lines. TELEDYNE PHILBRICK microcircuits 434080 Digital Inputs The 4080's digital inputs are standard TTL/OTL compatible. If any input bits are not used, they should either be grounded (4080) or tied to +5V (4081, 4082). Because of noise problems, open inputs should not be used as a means of generat- ing a logic 1. Reference Output 4080 Series devices contain an internal 10V +0.05% reference that is pinned out at pin 24. This reference can sink up to 2mA in addition to the current requirements of connecting pin 24 to pin 18 (4081, 4082). Optional Gain and Offset Adjustments 4080 Series devices will operate as specified without additional adjustments. If desired, input/ output accuracy error can be reduced to +0.025%FSR maximum by following the trimming procedures described below. Adjustments should be made following warmup, and to avoid interaction, offset must be adjusted before gain. Multiturn potentiometers with TCRs of 100ppm/C or less are recommended to minimize drift with temperature. Series resistors can +20% carbon composition or better. If these adjust- ments are not used, pin 17 should be leftopen and pin 13 should be connected as described in the Output Range Selection Table. +15V 390k2 Pin 13 100k2 15V Figure 2. Offset Adjust Circuit Offset Adjustment Connect the offset potenti- ometer as shown above. Apply the code 0000 0000 0000 to the digital input and adjust the out- put for the ideal value listed in the Input Coding Table. +15V 3M2 Pin 17 100k2 -15V Figure 3. Gain Adjust Circuit Gain Adjustment Connect the gain potenti- ometer as shown above. Apply the code 1111 1111 1111 and adjust the output for the ideal value listed in the Input Coding Table. External Resistors Optimize Settling Time and Offset Drift A voltage output D/A converter usually consists of acurrent output D/A driving an inverting op amp that acts as a current to voltage converter. The output impedance of the current D/A is the source impedance the op amp sees, and in the case of the 4080, this impedance is a 16pF capacitance in parallel with a 604N resistance (see pg.51). When the 4080 is operating on its 0 to 10V output range, the device is pin strapped such that the op amp feedback resistor is 2.50, and the op amp capacitor (internal to the device) has been chosen to optimize phase margin and settling time. The effective DC impedance seen by the op amp's inverting input is 60420||2.5kQ, and a 4872 resistor {also internal to the device) has been added between the op amp's noninverting input and ground to minimize offset drift. When the 4080 is pin strapped for 0 to SV operation, the output op amp has a 1.25kQ feedback resistor. It now becomes necessary to add a 6042 resistor (Re) between the inverting input of the output op amp (pin 14) and ground to restore the noise gain of the output op amp to once again optimize phase shift and settling time. Ri (487Q in this example) now has to be added between the noninverting input of the output op amp (pin 13) and ground to match the impedances seen by the op amp inputs and again minimize offset drift. The 4081 and 4082 have similar requirements. Because pin 24 (reference output) is always con- nected to pin 18 (output offset) for these devices, and because internal circuitry is slightly different from that of the 4080, they have different require- ments for Re See the Output Range Selection Table. 50 TELEDYNE PHILBRICK microcircuits4080 487, 6040, 6819, and 7870 resistors can be purchased as 1% metal film resistors, and the use of external resistors R; and Re is required for devi- ces to guarantee their published settling time and offset drift specifications. If Ri: and Re are within +10% of their required values, the effect on set- tling time and offset drift will be negligible. If R; and Rez are not used at all (pins 13 and 14 left open) the consequences could be a 50% increase in settling time and offset -drift. yy oy Reo = 5k for 4081 i Reo Rigo = 2.6k2 for 4082 _j.,, = = Re = 2.5kS2 10V Ranges L Re = 1.25k92 5V Ranges RE = Ro = 6042 Co = 16pF . . _ CF t bia Outpu 0-4mA + Ro Sn : 4870 t it = Figure 1. Current Output DAC with Output Op Amp INPUT CODING Digital Input Analog Output (DC Volts) 4080 4081 4082 MSB LSB 0 to -5V 0 to -10V +2.5V +5V 0 to +5V Oto +10V 0000 0000 oo00 0.0000 0.0000 +2,4988 +4.9976 +4.9988 +9.9976 0000 0000 0001 0.0012 0.0024 +2.4976 +4.9951 +4.9976 +9,9951 O11 144 1111 2.4988 4.9976 0.0000 0.0000 +2.5000 +5,0000 1000 0000 0000 2.5000 5.0000 0.0012 0.0024 +2,4988 +4.9976 1114 Wi 1110 4.9976 -9.9951 2,4988 4.9976 +0.0012 +0,0024 1111 1111 1111 4.9988 9.9976 2.5000 5.0000 0.0000 0.0000 OUTPUT RANGE SELECTION Part Output Voltage Connect Ri Rz it Range Pin (Pin 13 to Ground) (Pin 14 to Ground) 4080 Oto -10V 19 to 15 Open Open Oto -5V 19 to 15, 20 to 14 4870 6040 =z 24 to 18,19 to 15 Open Open 4081 oreo 24 to 18, 19 to 15 4870 6810 oes 20 to 14 24 to 18, 19 to 15 Open Open anes bts 24 to 18, 19 to 15 4870 7870 20 to 14 TELEDYNE PHILBRICK microciacuits 514080 Optimizing Settling Time This section is a general discussion of tech- niques one can employ in the most critical situa- tions to optimize a DAC's settling time by reducing glitch amplitude and digital feed- through. It applies to all D/A converters. When properly grounded and bypassed, 4080 Series DACs will meet all their published performance specifications without taking any of the additional precautions described below. The analog outputs (current or voltage) of all D/A converters display noise spikes, affection- ately called glitches, when their digital inputs are changed. Deglitched and specially designed low- glitch DACs can minimize this noise, but no one has figured out how to eliminate it completely. Glitches can result from, among other things, unequal delays or time skew in the digital logic driving the converter and/or from unequal switch- ing times for the current or voltage switches inter- nal to the converter. In either case, the glitch itself may cause problems in a particular application, such as raster scan or vector displays, or the glitch may lengthen a D/As settling time causing additional problems in other applications, such as closed loop servo systems. The easiest way to reduce a normal (not deglitched or specially designed to be low glitch) DAC's glitches to their lowest level is to follow good grounding and bypassing procedures and to eliminate unequal logic delays with external registers (latches). The most important grounding rule is that a large analog ground plane must be placed under and around the D/A converter, and in most cases, all converter ground pins should be soldered directly to the ground plane. Plastic or ceramic sockets should not be used. Read manufacturer's data sheets carefully. Even though a given converter may have different pins for analog and digital ground, manufacturers will usually recommend tying both to system analog ground. This is required because as an interface between the analog and digital worlds, the A/D or D/A converter cannot avoid mixing analog and digital ground currents, and the least consequences are suffered by having the digital ground currents returning through the analog system, But the analog ground plane and analog ground runs, in general, must be as low impe- dance as possible to absorb the ground currents associated with the converters digital inputs/out- puts. Power supplies should be bypassed with at least 0.1uF tantalum capacitors (for low frequen- cies) or paralleled with 0.014F (for high frequen- cies). Single 0.1uF or larger ceramic capacitors are even better. Avoid switching power supplies their output spikes will work their way into the analog ground system. Use accurate, linear- regulated supplies. For D/A converters, the choice and location of an input latch is critical. Low power Schottky logic is preferred because these devices usually exhibit data delays between rising and falling sig- nals that are more uniform than those of standard or straight Schottky TTL. Physically, the latches should be as close to the converter as possible, and the lead lengths from latch outputs to DAC inputs should all be equal. The diagram below shows a 4080 that has been double buffered for mating to the data bus of an 8 bit microcomputer. The first 4 bit latch holds the 4 most significant bits of a given 12 bit digital word. As the 8 least significant bits are written to the 8 bit latch, the 4 MSBs are latched into the second 4 bit latch, and the DAC has all twelve of its digital inputs updated at once. By double buffering the MSBs instead of the LSBs, we retain the ability to produce LSB size output changes with a single write cycle, and we greatly reduce digital feed- through on the MSBs. MULSITS MLS175 Figure 4, 4080 with Double Buffered Inputs for Mating to a 8 Bit Microcomputer Digital feedthrough occurs when noise on top of a1" or O" at a DAC's input feeds through to its analog output. Digital noise from other sources can also couple its way through to a DACs out- put. For the 4080, this coupling is somewhat reduced by grounding the unit's metal package. It can be further reduced by following the-layout and grounding guidelines described above. Dig- ital feedthrough, like glitches, can add toa DACs 52 TELEDYNE PHILBRICK micaocirncuits4080 settling time by inducing ringing and overshoot in the output. The figure below shows the typical digital feedthrough attenuation (in dB) of the 4080. The digital noise source was a 100mVp-p sine wave. It was added to logic 1 (+3.5V) or logic O (+0.4V) and applied to all bits simultane- ously. Attenuation is less (feedthrough is greater) for inputs high because this is the input state that switches (steers) current to the 4080's output. Inputs low steers current to ground. Because of the binary weighting of a DACs digital inputs, a given noise signal will produce half as much feed- through if it is applied to the bit 2 input than if it is applied to the bit 1 (MSB) input. Therefore, when trying to reduce digital feedthrough, concentrate on higher order digital inputs. The digital feedthrough characteristics of a given DAG, like its glitch characteristics, have to be lived with. The best a user can do is to try to reduce external noise sources. The input regis- ters that helped reduce glitch can also reduce digital feedthrough by reducing digital noise. Again, the latches should physically be located as close to the converter as possible. The short lead lengths that reduced digital time skew also help to avoid additional noise pickup. The latches should be physically oriented so the inputs and outputs for the more significant bits are those of the flip- flops furthest away from the chip's clock (strobe) input. This will reduce clock noise coupling into the DAC. Once again, low power Schottky logic is preferred (74L8174, 74LS175, 74LS273, etc.). In this case, because this logic family creates much less ground current noise than standard or Schottky TTL. Double buffering can even further reduce digital noise. This is another reason why one should double buffer the MSBs and not the LSBs when connecting high resolution DACs to data buses of lower resolution. 100 Digital Inputs Low (+04) Inputs High [+3.5V) Feedthrough Attenuation (dB) 2 5 1M Digital Noise Frequency (kHz! Figure 5. Digital Feedthrough Characteristics The duty cycle of the latch strobe lines should be such that the latches are driven by as narrow pulses as possible. See the figure below. The first strobe trace shows that for positive pulses, the falling edge of each pulse occurs during the DAC's output settling time. This edge becomes one more source of digital noise that can couple through to the DAC's output. The result may be increased glitch height, but it won't affect the set- tling time if the pulse is narrow enough. The second strobe trace shows that for negative pulses, the falling edge of each pulse occurs before the DAC's output begins to change. Glitch and settling time are unaffected; though the DAC output may show a small perturbation prior to changing levels. +F.5. Figure 6. Input Register Strobe Duty Cycle Another way to optimize settling time by reduc- ing digital feedthrough is to clamp the high out- puts of the DACs digital driver as close to the threshold level as is practicably possible. The minimum voltage for a TTL input is +2.4V, yet the typical 1" output rises to about +3.5 or +4.0V. Ifa DACs inputs are switched from "0's" to 1's and they turn on at +2.4V, the continued rise from +2.4 to +3.5 or 4V feeds through to create a greater output glitch and a longer settling time. If the DAC's high input is clamped to +2.4V, the rise above threshold is eliminated. One way to clamp the digital inputs of a TTL DAC is with pulldown resistors from the inputs to ground. These resis- tors force the digital drive circuit to source more current, lowering its output voltage and source impedance. Both reduce noise and pickup and help to optimize settling. The LS gates shown above are guaranteed to source 40QuA for a 1 output and still maintain a +2.4V output voltage. 6-7kQ pulldown resistors will pull the logic 1 output down to just above +2.4V minimizing the digital feedthrough resulting from digital over- drive. Clamping some digital inputs and not oth- ers may introduce unwanted delays resulting in additional glitch. Recall that these effects are reduced with input bit weight. The figure at the bottom of page 52 shows a 4080 with the first four digital inputs clamped. TELEDYNE PHILBRICK microcircuits 534739/43 5MHz and 10MHz Hybrid Voltage to Frequency Converters <a The 4739 and 4743 are Philbricks newest hybrid voltage to frequency converters. Offering full scale outputs of SMHz and 1OMHz, respectively, the 4739 and 4743 can be externally trimmed to any value from their rated full scale outputs down to 2.5MHz. Both units have full differential input capabilities and can be driven with positive voltages, negative voltages, or posi- tive currents. Common mode rejection ratio, with CMV = 10V, is 80dB. With external resistors, the input is easily adapted to accept almost any input signal range. The output stages of both units are single uncommitted transistors that operate as satu- rated switches. Pull-up resistors for TTL compatibility are inter- nal to the 4739's and 4743's 24 pin welded-metal dual-in-line packages. External resistors can be added to make the outputs CMOS compatible. Both units are capable of driving 10 TTL loads. The 4739 and 4743 both have quick response times, settling to within +0.01%FS of a new frequency in 15usec. Overload recov- ery time for both units is approximately 10 output signal peri- ods. Both units operate from +14V to +18V supplies and are specified to 0C to +70C operation. Please contact the factory for specified 55C to +125C operation and military/aero- space screening. FEATURES 5MHz (4739) and 10MHz (4743) Full Scale Outputs Full Differential Input 100dB Dynamic Range Nonlinearity: 4739/4743 +0.05%FS plus +0.001% Signal +0.05%FS plus +0.05% Signal +14V to +18V Supplies +24 Pin Hermetic DIP Easily Modified for Different Input/Output Signals epencenons * Two-Wire Digital Data Transmission * Ratiometric Data Conversion * Long Term Integrators * Fiber Optic Data Links * FM Modulation PACKAGE DIMENSIONS (ns) 1 Seeoac GoGo Roo oS i 139 MAX : " a (3.53) MAX | VIEW TOWARD PINS (0.51) 24 13 t eeoc00000 0000 1 q 001 DIA (0046 + 003 DIA! Jr coun onces @ 0.100 TOLERANCE NONCUMULATIVE PIN DESIGNATIONS 1, +15 SUPPLY (+Veeh 24. TTL 2 GROUND 23. QUTPUT aN 22. GROUND 4a nc 21 WGC 15V SUPPLY (-Vec} 20. +15 SUPPLY (Vee) 6 NC 7. FULL SCALE ADJUST 8. OFFSET ADJUST 9 FULL SCALE ADJUST 10. +h Mo Vin 2. Van N. N. 54 TELEDYNE PHILBRICK microciacuits4739/43 ABSOLUTE MAXIMUM RATINGS +15V Supply Voltage (+Vce, Pins 20, 5) Analog Input Voltage (Pins 11, 12) (1) Differential Input Voltage (Pins 11, 12) Operating Temperature Range Specified Temperature Range: +22V #15V +30V 55C to +126C 4739/4743 OC to +70C 4739-HR/4743-HR 65C to +125C Storage Temperature Range 65C to +150C SPECIFICATIONS (Ta = +25C, +Vcc = +15V, unless otherwise indicated.) PARAMETER 4739 4743 UNITS ANALOG INPUTS Input Range: +Vin +100uV to +10.5V +100nV to +10.5V _ Vin 100nV to -10.5V 100nV to -10.5V _ +in (Vin) +100uV to +10.5V +100uV to +10.5V _ +l +0.1uA to ImA +0.1yA to 1mA _ Overrange 20 10 Yo Input Impedance: +Vi, 10 10 kQ Via 20 20 kD tn Virtual Ground Virtual Ground one Common Mode Voltage +(Vec5) (Veen) v Common Mode Rejection Ratio 80 80 dB Dynamic Range 100 100 dB FREQUENCY OUTPUT Full Scale Frequency 5 10 MHz Output Waveform (2): High Level 5 v Low Level 0.4 o4 Vv Fanout 10 10 TTL Loads Pulse Width 50 to 75 45 to 65 nsec Output Impedance 666 + 5% 666 +5% 9] TRANSFER CHARACTERISTICS Nonlinearity: +Via(+10mV to +10.5V) +0.05 +0.001 0.05 +0.005% FS plus %Signal Vin{(-10m to 10.5V) +0.05 +0.001 +0.05 +0.005% FS plus %Signal +lin(iA to imA) +0.05 +0.001 40.05 +0.005% FS plus %Signal Offset Error +0.08 +0.08 %FS Full Scale Error +50(+1.0) +50(+0.5) kHz(%0FS) STABILITY Offset Drift +100 +100 BVP Offset Power Supply Sensitivity +20 +20 LN AV ec Full Scale Drift +75 +100 ppm/*C Full Scale Power Supply Sensitivity +75 #125 ppm/YeA Vee DYNAMIC CHARACTERISTICS Response Time (10V Input Step to +0.01%) 15 15 psec Overload Recovery Time (+Vin = +20V to +10V) 10 10 Cycles POWER SUPPLIES Power Supply Range +14 to +18 +14 to +18 v Current Drain +75, -25 +75, 25 mA Power Supply Asymmetry +4 +4 v Power Consumption 1500 1500 mw NOTES 1. For supply voltages less than +15V, the input voltage cannot exceed the supply voltage 2 The 4739 and 4743 can withstand an indefinite short to ground of to +V.. for 5 seconds without damage or degradation to performance. However, both units will fail if shorted to the V.. supply. TELEDYNE PHILBRICK microcincuits4739/43 +15V Offset 25k2 Adjust +1 -15V a +Vin -Vin Full Scale 1kQ Adjust (Note) +15V Supply -15V Supply Ground +15V Supply TTL suite, Out Col = System Analog Ground Figure 1. 4739/4743 Block Diagram NOTE: If external full scale accuracy adjustment is not used, pins 7 and 9 must be tied together. Offset and Full Scale Trim Theory >>>> Zero offset and full scale trim techniques are based on the input circuit. Offset is adjusted with a 25k potentiometer between +Ve and Vcec, with its wiper tied to pin 8 The subsequent vol- tage applied to pin 8 falls across a 10MQ resistor to become a constant positive or negative current directly injected into the integrator capacitor. Full scale is adjusted by varying the integrator's input resistor with a 1kQ rheostat connected between pins 7 and 9. This adjustment procedure can only lower the V/Fs full scale output frequency, so units are laser trimmed at the factory to have initial full scale output errors that are always positive. By placing a fixed resistor in series with the adjusting rheostat, the 4739's and 4743's full scale output frequencies can be lowered to 2.5MHz. If full scale adjustment is not employed, pins 7 and 9 must be tied together with as short a jumper as possible. 4739/4743 Output Circuit The TTL logic pulse train from the V/F is designed to drive 10 TTL loads with +15V sup- plies. The output circuit is a single transistor (Q,) connected as a saturated switch with an uncom- mitted 2kQ pull-up resistor. With pins 23 and 24 connected together, the output is approximately zero volts when Q, is on. With Q, off, the output voltage is +Vcc/3 or +5V when +Vec = +15V. If pin 23 is not connected to pin 24, an external divider must be provided. The output circuit is easily adapted to drive CMOS logic by paralleling the 2kQ resistor with an external resistor large enough to bring the output up to the desired level. The additional pull-up resistor also decreases pulse rise time when driving larger capacitive loads. The 4739/4743's output (collector of Q,) may be shorted to ground indefinitely without damage however, since Q, is on most ofthe time, a short to +Vec will cause certain catastrophic failure in about 5 seconds. TELEDYNE PHILBRICK microciacurts4860 Fastest 12 Bit Track-Hold Amplifier The 4860 is the fastest high resolution sample/hold (track/ hold) amplifier available. It is the only high speed sample/hold that guarantees acquisition time and sample-to-hold settling time (a S/H's two throughput limiting specifications) to +0.01% and not to only +0.1% or 1%. The 4860 will acquire a full 10V signal to +0.01%FS (equivalent to +0.005%FSR or +1mV) in 200nsec maximum. The unit will then track signal components up to 16MHz. In the track mode, offset error is typically +0.5mV, and gain error is typically +0.05%. When commanded to the hold mode (aperture time is 6nsec and aperture jitter is +50psec), the 4860's output will settle to within +0.01%FS (+1mV) of its final value in 100nsec maximum. Pedestal is a low +2.5mV. Once in hold, output droop rate is a low 5uV4usec maximum. Feedthrough attenuation at 2.5MHz is an impressive 74dB. A 24 pin dual-in-line package, a gain of 1, an input/output range of +10V, and TTL compatibility make the 4860 pin com- patible with the industry standard devices. Being a second generation design however, it is superior to that unit in almost every performance specification. Faster switching and better feedthrough attenuation are the result of our unique MOSFET switching scheme. Faster acquisition and settling times and considerably lower droop are the result of our own high speed, FET input op amp designs. FEATURES 200nsec Max. Acquisition Time 10V Step to +0.01%FS * 100nsec Max. Sample-to-Hold Settling Time . +50psec Aperture Jitter * 74dB Feedthrough Attenuation TTL Compatible APPLICATIONS Transient Recorders * Fast Fourier Analysis High Speed DASs High Speed DDSs * Analog Delay and Storage PACKAGE DIMENSIONS OO76t OOO. 0125 10.64 + 0.75) (31m ' la 1 2" 1004 LL. o830 | cme 20 (21,08) 0.230 ce (254) 4 (5.84) 2 J 13s | 1.100 O.015 Tl ' C301) | pee (37-94) (0.38) |, 0.600 | 0.120 FIN T._ | (15.247 (3.05) | TP L (0.564 0.200 5.08) PIN DESIGNATIONS 1Analog Output 24, +15V SUPPLY 2 WC 23. GROUND a N/C 22. -15V SUPPLY 4c 21, GROUND SNC 6. NG 18. NC 7 NC 18. N/C a wc 7. WC 9. +5V SUPPLY 16. NC 10. GROUND 15. GROUND 11. HOLD COMMAND 14 NC 12, HOLD COMMAND 13 ANALOG INPUT TELEDYNE PHILBRICK microcircurts 574860. ABSOLUTE MAXIMUM RATINGS *15V Supply Voltage (*Vec, Pins 24, 22) +5V Supply Voltage (+Vua, Pin 9) Analog Input (Pin 13) (1) Digital Input (Pins 11, 12) Output Current (2) Operating Temperature Range Specified Temperature Range 4860 Storage Temperature Range SPECIFICATIONS (Ta = +25C, Vee = +15V, and +5V, unless otherwise indicated.) 18V 0.5 to +7V *18V 05 to +5.5V +65mA 55C to +125C OPC to +70C 56C to +125C 65C to +150C PARAMETER MIN. TYP. MAX. UNITS. ANALOG INPUT/OUTPUT Input/Output Voltage Range +10.25 #415 - Vv Input Impedance --- 1 --- kQ Output Current (2) es pa +40 mA Output Impedance o O41 _ Q Maximum Capacitive Load -_- 250 a pF DIGITAL INPUT Logic Levels (4): Logic 1" +2.0 - +5.0 Vv Logic O" 0 = +0.8 Vv Loading -- 1 - TTL Load TRANSFER CHARACTERISTICS Gain 1.00 vA Gain Accuracy -- +0.05 +04 % Gain Linearity Error ~ +0.003 +0.01 FS Offset Voltage (Sample Mode) - +0.5 +5 mv Pedestal (6) = +25 +20 mV Stability: Gain Drift _ *0.5 +5 peme?c Stability: Offset Drift (Sample Mode) a 3 #15 ppm of FSR/C Stability: Pedestal Drift ~ ppm of FSR/C DYNAMIC CHARACTERISTICS Acquisition Time (7) 10V step to +0.01%FS (+1mV) a 150 200 nsec 10V step to +0.1%FS (10m) o 100 170 nsec 10V step to +1%FS (+100mV) i 90 cs nsec 1V step to +1%FS (*100mvV) - 75 _ nsec Settling Time, Sample to Hold to +0.01%FS (imvV) _ 60 100 nsec to +0.1%FS (+10mV) a 40 _ nsec Sample to Hold Transient _ 180 == mVp-p Aperture Delay Time --- 6 _- nsec Aperture Jitter -- +50 oo- psec Output Slew Rate oo 300 -_ Viusec Small Signal Bandwidth (-3dB) = 16 = MHz Droop: +25C =. +O.5 +5, uviusec +70C _ +15 aod Vise +125C _ +1.2 _ mV/psec Feedthrough (2.5MHz, 20Vp-p input) 74 - dB POWER SUPPLIES. Voltage Range: +15V Supply o- +3 - % +5V Supply +5 % Power Supply Rejection Ratio --- +0.5 = mv Quiescent Current Drain: +15V Supply +21 +25. mA -15V Supply oe 22 25 mA +5V Supply + +17 +25 mA Power Consumption 730 a75 mw NOTES. 1, Analog input signal should not exceed supply voltage. 2 The 4860's outpul is current limited at approximately +65mA, and the unit can withstand a sustained short to ground Shorts to either supply will resull in destruction. For normal operation, load currant should not exceed +40mA. 58 TELEDYNE PHILBRICK micraociacuits4860 4, One TTL load is defined as sinking 4Qu4 with a logic 1 applied and sourcing 1.6mA with a logic O applied 5. FS stands for Full Scale and is equivalent to 10 volts. FSA stands for Full Scale Range and is equivalent to 20 volts. For a 12 bit system, 1LSB = 0.024%F SR 6. Pedestal refers to the unwanted step in output voltage that occurs as a S/H is switched from the sample to hold mode. For many S/H, pedestal amplitude is a function of input/output voltage level. For the 4560, pedestal is constant regardiess of input/output level 7. Acquisition time is tested with no load and is relatively unaffected by capacitive loads to SOpF and resistive loads to 2500 & Sample to hold settling time refers to the time interval between the point at which a device is commanded from the sample to the hold mode and the point at which the analog output (following a transient) settles to within a specified error band around its final value. ANALOG INPUT ANALOG GROUND OUTRLT: GROUND HOLD sv COMMAND +15v A i? 6 BYPASS =15V COMMAND] CAPACITORS a TT T GROUND] 10 oe 23 | GROUND SYSTEM ANALOG GROUND Figure 1. Functional Block Diagram 45 Gain (V/V) 0 0.01 0.03 061 O03 1.0 30 10.0 Frequency (MHz) Figure 2. Track Mode Gain Amplitude and Phase Response 15.0 > = 12.5 g 100 (1.0) 10.0 3% 30 (0.3) ~ 75 ER 10 (0.1) 8 5.0 = z 3 (0.03) wo 25 c 1 (0.01) 0 uw 1 1 150 200 250 300 Input Signal Slew Rate (V/psec) Time (nsec) Aperture Jitter Window = 100psec For vit) = 10sincot, dv/dt (max) = 200f Figure 3. Accuracy Error Due Figure 4. Acquisition Accuracy vs. to Aperture Uncertainty Acquisition Time for a 10V Step ES CCE TELEDYNE PHILBRICK micaocircurrs 59O Series 10/12/14 Bit Synchro to Digital Resolver to Digital Converters S/D converter MADE IN U.S.A Utilizing state-of-the-art techniques, these converters pro- vide fast, accurate responses to changes in shaft velocity. Fea- tures include balanced high signal input impedance which minimizes synchro loading errors, ratio metric conversion and integrating phase sensitive demodulation. In addition to trans- former isolated synchro and reference inputs, the synchro input impedances are purely resistive allowing external voltage scal- ing. The 5500 Series are housed in low profile encapsulated modules and are specified over the 0C to +70C temperature range (5500-0X). For extended temperature operation, the 5500-1X are specified over the 54C to +85C temperature range. The 5500 Series are high speed, precision 10-bit (5500), 12-bit (5501) and 14-bit (5502) synchro to digital and resolver to digital converters. FEATURES Accuracy +10.8, +6, +4 * Low Power Dissipation * Solid State Model Available Industry Standard Pin Out APPLICATIONS * Ordnance Control * Radar Tracking Systems * Navigation Systems Industrial Automation SELECTION GUIDE OC to +70C -54C to +85C 5502 11.8V(RMS)/400Hz 5502-10 11.8V(RMS)}/400Hz 5502-01 26V(RMS)/400Hz 5502-11 26V (RMS) /400Hz 502-02 90V(RMS)/400Hz 5502-12 90V(RMS)/400Hz 5502-03 90V (RMS)/60Hz 5502-13 S90V(RMS5)/60Hz 5502-04 90V(RMS)/60Hz Solid State 5902-14 S0V(RMS)/60Hz Solid State 60 TELEDYNE PHILBRICK microciacuitsABSOLUTE MAXIMUM RATINGS +15V Supply (+Vec) 15V Supply (Vec) +5V Supply (+Vaa) Specified Temperature Range 5500-0% 5500-1 Storage Temperature Range 5500 Series +18V 18V +7 0C to +70C. -54C to +85C -62C to #125C SPECIFICATIONS (All specifications are typical and apply over the specified temperature range, power supply range, reference frequency and amplitude range unless otherwise indicated.) 5500 5500-01 5500-02 500-03 5500-04 PARAMETER 5500-10 | 5500-11 | 5500-12 | 5500-13 | ssoo-14 | UNITS ANALOG INPUTS Synchro 11.8 ay 90 90 90 V(RMS) L-L Resolver 11.8 26 30 (2) (2) V(RMS) L-L Impedance (3) 20 20 600 900 900 KO L-L REFERENCE Input Voltage 26 26 115 115 115 V(RMS) L-L Frequency 400 400 400 50 to 60 50 to 60 Hz Frequency Tolerance +10 +10 +10 +10 +10 % Impedance (Min.) 10 10 40 40 40 KO TRANSFER CHARACTERISTICS Accuracy (4) *10.8 10.8 +10.8 +10.8 +10.8 Minutes Quantization and Hysteresis Error (5) +10.55 +10.55 *10.55 +10.55 #10.55 Minutes Velocity (Min.) 80 50 BO 20 20 RPS Acceleration (Min.) 16 16 16 0.75 0.75 RPS/Sec.* SPECIFICATIONS (All specifications are typical and apply over the specified temperature range, power supply range, reference frequency and amplitude range unless otherwise indicated.) 5501 5501-01 5501-02 5501-03 5501-04 PARAMETER ssoi-10 | 5501-11 | ssor-12_| ssot-13 | ssot-14 | UNITS ANALOG INPUTS Synchro 11.8 (ty 90 90 90 V(RMS) L-L Resolver 11.8 26 90 (4 (2) V(RMS) L-L Impedance (3) 20 20 600 400 400 KO L-L REFERENCE Input Voltage 26 26 15 115 115 V(RMS) L-L Frequency 400 400 400 50 to 60 50 to 60 Hz Frequency Tolerance +10 +10 +10 +10 +10 % Impedance (Min.) 10 10 40 40 40 KQ TRANSFER CHARACTERISTICS Accuracy (4) +6 +6 +6 +6 +6 Minutes Quantization and Hysteresis Error (5) +2.6 +2.6 +2.6 +2.6 +2.6 Minutes Velocity (Min.) 30 30 30 30 7 RAPS Acceleration (Min.) 6 6 6 0.33 0.33 RPS/Sec.2 TELEDYNE PHILBRICK microcircuits 615500 Series SPECIFICATIONS (All specifications are typical and apply over the specified temperature range, power supply range, reference frequency and amplitude range unless otherwise indicated.) 5502 5502-01 5502-02 5502-03 5502-04 PARAMETER 5502-10 | 5502-11 | 5502-12 | 5502-13 | 5502-14 UMTS: ANALOG INPUTS Synchro 11.8 (1) 90 90 390 V(RMS) L-L Resolver 11.8 26 90 (2 (2) V(RMS) L-L Impedance (3) 26 200 200 200 KO REFERENCE Input Voltage 26 26 115 115 115 V(RMS) Frequency 400 400 400 50 to 60 50 to 60 Hz Frequency Tolerance +10 +10 +10 +10 +10 Yo Impedance (Min.) 45 45 45 45 45. KQ TRANSFER CHARACTERISTICS Accuracy (4) +4 +4 +4 +4 +4 Minutes Quantization and Hysteresis Error (5) +1.2 41.2 +12 +1.2 12 Minutes. Velocity (Min.) 12 12 12 25 25 RPS Acceleration (Min.) 2 2 2 O17 O.17 RPS/Sec.? PARAMETER MINIMUM TYPICAL MAXIMUM UNITS DIGITAL INPUTS Track: Logic 1" +2.4 --- +5.0 Vv Hold (Inhibit): Logic 0 (6) 0 = 10.8 Vv Input Load (7) a 1 LSTTL Loads DIGITAL OUTPUTS Resolution ~ - 14 Bits Logic Levels: Logic 1 24 36 v Logic 0 ae 02 o4 Vv Drive Capability (Fan Out) 2 = _ TTL Loads Data Busy (8) 2 = psec POWER SUPPLIES Power Supply Range: +15V (9) +10.8 +15 416.5 Vv +SV +4. +5 +5.5 Vv Current Drain: +15V _ 25 _ mA +5V a 65 _ mA NOTES 1. By design and application, 26V(AMS)/400Hz Synchro input is not available. 2 By design and application, S0V(AMS)/60H2 Resolver input is not available. 3. Input Impedance specifications apply to bolh Synchro and Resolver inpuls. 4, Accuracy is specified over the entire operation temperature range, +5% variation of power Supply vallage, a | 10% signal amplitude and frequency variation 5, Fora 10 Bit Converter, +10.55 minutes is the equivalent of 'SLSB. A 12 Bit Converter, +2.6 minutes is the equivalent of 'LSB. A 14 Bit Converter, +1.2 minutes is the equivalent of 0.9L5B. 6 Digital Output information is stable within 2usec after applying a hold command. 7. 1 LSTTL load is the equivalent of 0.25 standard TTL loads. For +5V CMOS compatibility, pull up resistors (18KQ typ.) are recommended on all output lines (B1- B-14) 8. Data Busy output is true (High) for 2usec bracketing change of angle data. 9. Maximum Tracking Rate is proportional to *V.. power supply voltages. Operation at *12VOC will result in a 20% reduction. 62 TELEDYNE PHILBRICK microcircuits5600 Series 10/12/14 Bit Synchro to Digital Resolver to Digital Converters Series S/D converter MADE IN U.S.A. Utilizing state-of-the-art techniques, these converters pro- vide fast, accurate responses to changes in shaft velocity. Fea- tures include balanced high signal input impedance which minimizes synchro loading errors, ratio metric conversion and integrating phase sensitive demodulation. In addition to trans- former isolated synchro and reference inputs, the synchro input impedances are purely resistive allowing external voltage scal- ing. The 5600 Series are housed in low profile encapsulated modules and are specified over the 0C to +70C temperature range (5600-0X). For extended temperature operation, the 5600-1X are specified over the 54C to +85C temperature range. The 5600 Series are high speed, precision 10-bit (5600), 12-bit (5601) and 14-bit (5602) synchro to digital and resolver to digital converters. ee eee en ene ue alae FEATURES Low Cost +22, +8.5', +4' * Accuracy Low Power Dissipation * Industry Standard Pin Out APPLICATIONS Ordnance Control Radar Tracking Systems * Navigation Systems Industrial Automation SELECTION GUIDE =54C to +85C 5602-12 5602-13 O to +70C 5602-01 11.8V(RMS)/400Hz 5602-11 5602-02 S0V(RMS)/400Hz 5602-03 SOV (RMS) /60Hz 11.8V(RMS)/400Hz 90V (RMS) /400Hz 90V(RMS)/60Hz TELEDYNE PHILBRICK microciacuits5600 Series ABSOLUTE MAXIMUM RATINGS +15V Supply (+Vee) 15V Supply (Vee) +5V Supply (+Mea) Specified Temperature Range 5600-0% 5600-1X Storage Temperature Range +18V 18V +7 OC to +70C 54C to +85C 62C to +125C SPECIFICATIONS (All specifications are typical and apply over the specified temperature range, power supply range, reference frequency and amplitude range unless otherwise Indicated.) 5600-01 5600-02 5600-03 PARAMETER 5600-11 5600-12 5600-13 UNITS ANALOG INPUTS Synchro 11.8 90 90 V(RMS) L-L Resolver 11.8 30 (1) V(RIMS) L-L Impedance (2) 26 200 200 KO L-L REFERENCE Input Voltage 26 15 115 V(RMS) L-L Frequency 400 400 50 to 60 Hz Frequency Tolerance +10 +10 +10 % Impedance (Min.) 200 200 200 KO TRANSFER CHARACTERISTICS Accuracy (3) +22 +22 +22 Minutes Quantization and Hysteresis Error (4) #10.55 +10.55 +10.55 Minutes Velocity (Min.) 100 100 14 RPS SPECIFICATIONS (All specifications are typical and apply over the specified temperature range, power supply range, reference frequency and amplitude range unless otherwise indicated.) 5601-01 5601-02 5601-03 PARAMETER 5601-10 5601-12 601-13 UNITS ANALOG INPUTS Synchro 11.8 90 90 V(RAMS) L-L Resolver 11.8 90 i) V(RMS) L-L Impedance (2) 40 400 400 kQ LL REFERENCE Input Voltage 26 115 115 V(RMS) L-L Frequency 400 400 50 to 60 Hz Frequency Tolerance +10 +10 +10 % Impedance (Min.) 200 200 200 KO TRANSFER CHARACTERISTICS Accuracy(3) +8.5 +8.5 +6.5 Minutes Quantization and Hysteresis Error (4) 42.6 *2.6 +2.6 Minutes. Velocity (Min.) 48 48 10 APS Acceleration (Min.) 6 6 0.33 APS/Sec.? TELEDYNE PHILBRICK microcircuits5600 Series SPECIFICATIONS (All specifications are typical and apply over the specified temperature range, power supply range, reference frequency and amplitude range unless otherwise indicated.) 5602-01 5602-02 5602-03 PanSMEIES 5602-11 5602-12 5602-13 UNITS ANALOG INPUTS Synchro 11.8 90 90 V(RMS) L-L Resolver 11.8 90 rr) V(RMS) L-L I d (2) 26 200 200 kQ REFERENCE Input Voltage 26 115 115 V(RMS) Frequency 400 400 50 to 60 Hz Frequency Tolerance +10 +10 +10 % Impedance (Min.) 200 200 200 KQ TRANSFER CHARACTERISTICS Accuracy (3) +4 +4 +4 Minutes Quantization and Hysteresis Error (4) +12 +12 +12 Minutes Velocity (Min.) 12 12 25 RPS PARAMETER MINIMUM TYPICAL MAXIMUM UNITS DIGITAL INPUTS Track: Logic 1" 42.4 _ 45.0 Vv Hold (Inhibit): Logic "0" (5) oO _ +0.8 Vv Input Load (6) os cee 1 LSTTL Loads DIGITAL OUTPUTS Resolution -_ _ 12 Bits Logic Levels: Logic 1" 24 3.6 _ v Logic o" _ a2 o4 Vv Drive Capability (Fan Out) 2 _ _ TTL Loads Data Busy (7) -- 2 _ psec POWER SUPPLIES Power Supply Range: +15 (8) +10.8 #15 +16.5 Vv +5V +45 +5 +55 Vv Current Drain: +15V _ 25 o mA +5V _ 65 -- mA NOTES 1. By design and application, 90V(AMS)/60Hz Resolver input is not available. 2. Input Impedance specificalions apply to both Synchro and Resolver inputs. 3. Accuracy is specified over the entire operation temperature range, +5% variation of power supply voltage, a +10% signal amplitude and frequency variation, 4. For a 14 Bit Converter, +1.2 minutes is the equivalent of O.9LSB 5. Digital Output information is stable within 2usec after applying a hold command 6 1 LSTTL load is the equivalent of 0.25 standard TTL loads, For +5V CMOS compatibility, pull up resistors (18KQ typ.) are recommended on all output lines (81 - 8-14) 7. Data Busy output is true (High) for 2usec bracketing change of angle data. 8 Maximum Tracking Rate is proportional to +V.c power supply vollages. Operation at +12VDC will result in a 20% reduction. TELEDYNE PHILBRICK microcircuits 65PRODUCT SELECTION GUIDE Microcircuit Operational Amplifiers WIDEBAND, FAST SETTLING Settling Specified Output Minimum | Gain-BW | Minimum | Time to Oltset | Input Bias Temp. Part Range |Open Loop] Product | Slew Rate | +0.1% Voltage Current Range Number} Features | (Volts/mA)| Gain (dB) | (MHz) | (Vissec) (nsec) | (mV, Max) | (pA Max) (c) Pkg. Industry Standard : a FET Input, | +10/+10 70 80(2) 350 300 +5 +100 | -55to +125 | A LHO0032 Compatable High Speed TP0033 | autter/Driver | +5/+100 | 098 | 1003) | 250 20 10 #100 Oi! (1) i 55 to +125 Amplifier Monolithic 1321 | High Gain, ss Oto +75 (4) | Wideband. +10/+10 98 100 20 400 5 +25A | cety +195 | 8 Fast Settling Monolithic High Slew me Rate, 10/410 76 20 80 200 +10 #250nA a co B (4) | .emHz Full Power BW Monolithic bia Wideband +10/+10 83.5 nia 350 250 +15 +100 ee te c Fast Settling Monolithic Nay [25MHz Full | 10/10 | 835 nia 550 350 +15 10 | ote | c Power B/W Monolithic, 1344 | JFET input, | +11/420| $8 100 100 280 +3 mo | OCT .| () | wideband Monolithic JFET Input, 1345 | High Slew 11/420 88 400 50 400 +15 +65 Oto +75 B Rate, Wideband Monolithic 1346 | Ultra Low 4a ci Oto +75 (4) | Bias Current, $12/415 106 nla 4 2000 +0.5 1 55 to +125 | 2 JFET Input Monolithic 1347 | Ultra Low . 45/4 Oto +75 (4) | Bias Current, Btaiels ies nfa 4 a0 ts 7 55 to +125 | JFET Input Fast Settling to +0.01% 1430 | Made for ; i _ cc 4 (5) Current +10/+50 106 100 500(6) 100 2 500 55 to +125 DB Output DACs Fastest Settling to 1435) | 40.01%, r Oto +70 (5) 1OOMHz +5/+10 90 1000 250 40 +5 2QuA 55 to +125 D Working Bandwidth 66 TELEDYNE PHILBRICK microciacuitsMicrocircuit Operational Amplifiers WIDEBAND, FAST SETTLING Settling - Specified Output Minimum | Gain-BW | Minimum | Time to Offset | Input Bias Temp. Part Range |Open Loop| Product | Slew Rate) +0.1% Voltage Current Range Number Features (Volts/mA)| Gain (dB) | (MHz) (Viusec) (nsec) _| (mV, Max)| (pA Max) (ec) Pkg. Best Available 1437 | Combination Oto +70 (5) of Price, +10/+20 88 350 400(6) 110 +2 +200(6) -55 to +125 B Package, Performance Outstanding Performance, + : 1443 | og Low +10/+100 95 2000 900 80 +3 50 Oto +70 E Gain Stability 1443 with a Extended +10/+100 | 100 2000 1000 80 +2 -20 | -55t0+125| E Temp Range Fastest Settling to 1467 = | +0.01%, Fe Oto +70 (5) | 100MHe 5/410 90 1000 250 40 +0.5 +25uA | seta +125 | P Working Bandwidth FLASH 1490 | Buffer, High + + Oto +70 (5) _ | Performance, 65/2100 0.98 100(3) 250 20 +10 100 _ssto+as | Fast Settling BB3554 Equivalent, Tea | Improved +10/+100 | 100 2000 | 1000 100 +2 +50 eet | E Low-Gain Stability HIGH SPEED, HIGH OUTPUT Output Minimum | Gain-BW | Minimum Offset Input Bias | Specified Part Range Open Loop| Product | Slew Rate | Voltage Current | Temperature Number Features (Volts/mA) | Gain (dB) (MHz) (Visec) | (mV, Max) | (pA, Max) | Range (C) | Pkg. VMOS Output, No 1460(8) | SOA Restrictions, #30/+150 80 1000 300(6) +5 210A Oto +70 E High Speed VMOS Output, FET Oto +70 1461(5) | Input, No SOA, +30/+600 100 1000 900 +5 +100 | scig 4125 | F Higher Speed 1A VMOS Output sonia 3 Oto +70 1463(5) | pe input, No SOA +30/+1000 | 100 Typ 6 80 Typ +10 50 55 to +125 E Selectable VMOS if Oto +70 1464(5) Output, FET input +30/(9) 100 Typ (10) (10) +10 50 55 to +125 E +Vee = +15V to +150V, . Oto +70 1480(5) FET Input, Fast 1140/475 95 18 100(6) 3 +200 55 to +125 E Settling NOTES PACKAGES 1. Add *-HA" for specified 55C to +125C operation 4, TO-8 2, Unity Gain Bandwidth. 8. 10-99 : 3. Full Power Bandwadth C. 14 pin ceramic dual-indine, O79" * 0.31" = o20 4 Add -01" to part number for specified 55C to +125C operation, . 14 pin metal dual-in-line, 0.83" 052" 02 5, Add ~-HR to part number for specified 55C to +125C. operation & TO-3 . . . 6, Typical specification F. 14 pin metal dual-in-line with ears, 1.18" ~ 056 = 0.2 7, User Selectable oulput current +1A to +104. 4& Dependent on output stage selected TELEDYNE PHILBRICK microciacuits 67Microcircuit Operational Amplifiers GENERAL PURPOSE Output Minimum | Unity Gain | Minimum Offset Input Bias Specitied Part Range | Open Loop| Bandwidth | Slew Rate | Voltage Current | Temperature Number | Features Volts/mA | Gain(dB) | (MHz, Typ)| Viusec (mV, Max) | (pA, Max) | Range (C) | Pkg. Monolithic, FET, 1421 10mA Output, 741 #10/410 94 2 3 +15 50 25 to +85 A Pin Compatible Monolithic, FET, 1421-01 | 1421 with Lower +10/+10 o4 2 3 +15 15 25 to +85 A Offset Drift 1421 with Lower 1421-02 | Bias Current and +10/+10 94 2 3 +15 10 25 to +85 A Offset Drift FET Input, Low 1426 =| Offset and Bias, 10/45 94 2 3 +2 25 25 to +85 A 741 Compatible 1426 with Lower 1426-01 | Offset, Offset Drift +10/+5 94 2 3 +1 10 25 to +85 A And Bias Current 1426 with Lower 1426-02 | Offset and Offset +10/+5 94 2 3 +1 25 25 to +85 A Drift 1426 with Lower 1426-03 | Offset and Offset 210/45 94 2 a +1 25 25 to +85 A Dritt Logarithmic Amplifiers Dynamic Range (dB) Log Conf y (3) Frequency Specified Part Input Response | Temperature Number | Description | Current | Voltage | Input Current |% Max| Voltage |(% Typ) (Hz) Range (C) | Pkg. Positive Input 1nA to 10nA +1 . 4362 | Logarithmic 120 80 | 10nAto 100uA | +05 ee . 80k oto+70 | B Amplifier 100WA to ImA +41 Negative Input 1nA to 10nA +1 ; 4363 | Logarithmic 120 80 | 10nAto 10a | +05 [ITV to WW) 205 80k oto+70 | B Amplifier 100WA to imA | +1 e - : Instrumentation Amplifiers Unity Gain Settling to Input Bias Specitied Part Output Range | Bandwidth +0.1% Offset Voltage} Current (4) | Temperature Number Description (V/mA) (KHz Typ) | (sec) (mV, Max) | (pA, Max) Range (C) | Pkg. High Performance z 7 4253 FET Input +10/+5 7 5 1 10 Oto +50 c NOTES PACKAGES 1. Gain-bandwidih product (G = 10). - A. TO-99 2. Typical specification B Module, 1.5" 1.5" = 04" 3. Log Confomily is the deviation from a stright line (ideal . Module, 2.0" =~ 20 = ga" logarithmic behavior) on a semi-log plot over the specified range. Three input ranges with associated errors are listed since error is nol consiant over 1nA to imA input range. Input bias Current doubles every 10C. & 68 TELEDYNE PHILBRICK microciacurtsModular Operational Amplifiers Input Offset Voltage Input Bias Current Output | Minimum | Full Power BW/ Part | Features Range | Open Loop Slew Rate Initial Drift Initial Drift Category | No. (V/mA) | Gain (dB) | (kHz/Vusec) | (mV, Max) | (uV/C, Max) | (pA, Max)! (pA/C, Max) | Pkg. Chopper ire Low Stabilized | sia/+5 | 112 40/1.2 +15yV +0.25 +50 1 A Offset | 1701) 40kH2 Full | yayes 112 40/1.2 +15yV +0.1 +50 41 A and Drift Power BW, High CMRR Parametric Ultra Low Op Amps | s1a/+5 100 (1) +5 +30 +0.005 | +0.002 A Bias and | 1702] Lowest Bias | 1 J, fr Z cA sc Drift Current +1045 100 (1) +5 +10 +0.005 +0.002 A Available *#140V 1022] Output High (2) 120 30/30 +2 +50 30 (3) B High Aa. CMV Voltage os Output 115V 1032] Output Low (4) 100 10/10 +5 +50 10 (3) 8 Bias Instru- FET Input, men- | 4253] High OMAR H1O/+5 (5) (6) +1 +10 10 (3) c tation NOTES PACKAGES 1. Undistorted full power bandwidth is 20Hz minimum A 152" = 1.52" = 0.62" Slew Rate = 2.5V/msec. 2 Vou = +|Vee -10| volts, lou = +20MA, Vex = +40V to +150V B. 2.42" x 1.82" x 0.62" 4 Doubles every 10C C. 2.02" x 2.02" x 0.41" 4. Vea = +/Mec 10] volts, Ine = $10MA, Voc = +18V to +125V, 5. Closed-loop gains from 1 fo 10,000 delermined by choice of a single external resistor. 6 Undistorted full power bandwidth is 5kHz minimum. Track/Hold Amplifiers Acquistion Sample-Hold Maximum Aperture Maximum Specified Part Time (10V Step | Settling Time Droop Rate Jitter (1) Gain Typical Input | Temperature Number | to +0.01%FS) to +0.01%FS) (uVipsec) (nsec) _|Error (2) (%)| Impedance Range (C) | Pkg. 4853 dwsec Max 300sec Max tf +1 Max +0,05 (2) Oto +70 A 4855 300nsec Max 100sec Max +25 +0.2 Typ +0,02 10) Q/2pF Oto +70 A 4856 Susec Typ (3) (3) (3) +7 Typ (4) 10'0 0 to +75 B 4860 sg 0 to +70 (5) 200nsec Max 100sec Max 5 +0.05 Typ 01 1kA -55 to +125 Cc 4866 0 to +70 (6) lwsec Typ 185nsec Typ 0.08 Typ +30 Typ 0.0005, 5MOM/3pF 55 to +125 Cc DEGLITCHER 4902 : 0 to +70 (5) | Ipsec Max 200nsec Max +25 N/A 0.05 | N/A 55 to +125 | Cc NOTES PACKAGES 1, Defined as the sample to sample variation in aperture Gelay time. A. Module, 2" * 2" 0.4" 2 2kO(20pF in series with 20) B. 14 pin plastic weal-in-line, 0.7" 0.3" ~ O14" 3. Determined by value of external hold capacitor C.24 pin ceramic dual-in-line, 134" ~ 0.83" 0.23" 4. All units have a gain of 1 except the 4856. The gain of the 4856 is determined by a choice of external resistors. 5, Add"-HR" to part number for specified 55C to +125C operation TELEDYNE PHILBRICK microciacuits 69Analog to Digital Converters Temperature Maximum Maximum Integral Differential | Range for No Power Resolution Part Conversion | Input Voltage | Linearity Error | Linearity Error | Missing Codes | Consumption (Bits) Number Time (1) Ranges (V) (LSBs, Max) LSBs, Max) (ec) (mW) Pkg. 4130 -, -10 sa is 8 Series (2) 750nsec +5 +10 +14 +V, 0 to +70 3275 A 4131 -5, 10 i a Series (3) RSG +5, +40 1 My (Typ) Oto +70 3275 A TP5210 10, +10 ai - ; 12 Series (4) 13 usec +5, +10 + (Typ) Oto +70 915 8 12 4132-22 | 3.5,sec ae 1 b+ (Typ) | Oto +80 3275 A 10, -20 : 12 4133-22 2.5usec i 440 +1 +, (Typ) Oto +50 3275 A NOTES 3. Includes part numbers 4131-10 (0 to 5V}, 4131-20 (0 to 10), 1. All Teledyne Philbrick A/D converters, with the exception of the TP5210 Series, have internal clocks, and maximum conversion time refers to the slowest conversion time a user can expect from these devices, They may run aster. For the TPS210 Series, maximum conversion time refers to the fastest conversion rate at which these devices can be externally clocked and still guarantee accuracy and linearity. Includes part numbers 4130-10 (Oto SV input). 4130-20 ro 4131-30 (*5V), and 4131-40 (+ 10V). 4. Includes part numbers TPS210/TPS213 ( 0 to 10V input) TPS211/5214 (+5V), TPS212/5215 (+ 10V). TRPS216/TPS217 (0 to +10V) Add -HR" to part number for specified 55C to +125C operation. PACKAGES A, Module, 4 * ros" (0 to 10V), 4930-30(+5V), and 4130-40 (+ 10V). 6. 24 Pin ceramic dual-in-line, 134" = 0.83" = 026 Digital to Analog Converters Maximum Temperature Settling Time Integral Differential Range For Maximum (Step Size/ Linearity Linearity Guaranteed Power Resolution Part Output Ranges Error Band/ Error Error Monotonicity | Consumption (Bits) Number (Volts, mA) Time) (LSBs, Max) | (LSBs, Max) (C) (mW) Pkg. Voltage: 5, +10, | 20V/0.01%/2. Sys Oto +70 12 4058 (1) 2.5, 5, $10 4mA/0.01%/ +My M5 55 to +125 645 A Current: +4, +2 200nsec : 4mA/'0.014/ is 1y Oto +70 12 4065 (1) Current: +4, +2 100ns +i +My 55 to +125 645 A 5mA/0.01%/ 12 4068 Current: -5, +25] aotre +My Oto +70 465 (Typ) B 12 4072 Multiplying (2) | 20V/0.01%/650ns + +14 Oto +50 1500 c Voltage: 4080 4080: 5, -10 ay i Oto +70 12 | series (1) | 4081: 22.5, +5 | 10W/0.02%0/250ns ; a 55 to +125 mn A 4082: +5, +10 TP7541 sarc + a Oto +75 12 Series (3) Multiplying (2) | 20V/0.01%/1pS ", +i, Beta fos 450 D Voltage 12 TPDACBSOV #5, +10, $2.5 TOVALOI I +N 1, Oto +75 1000 B 8, +10 1.5uS Typ , i 2mA/0.01%/ 4} . 12 TPDAC801 |) Current: =2, +1 300nsec Typ tM e Oto +75 1000 B io 2mA/0.003%/ 1 i 12 4088 Current: 2, +1 1uS Typ a % Oto +75 1000 E NOTES PACKAGES 1. Add -HA" to part number lor specified 55C to #125C A. 24 pin metal dual-in-line 1.39" * 0.8" = G2" operation. 8. 24 Pin ceramic dual-indine, 1.25" 0.61" = 0.19" 2. The 4072 and 4085 are multiplying DACs. Their output voltages C. Module 3 = 25" a4" (+ 10) will be equal to the product of their input voliages D. 18 pin ceramic dual-in-line 0.95" * 0.31" 0.20" (-1V to +10) and their digitally programmable scale factors (-1to +1). 3. Add 02 for -25C to +85C temperature range and -04" for 55C to +125C temperature range. E. 40 pin ceramic dual-in-line 70 TELEDYNE PHILBRICK micaociacuitsFrequency to Voltage Converters GENERAL PURPOSE Absolute A y Temperature Stability Frequency Part Nonlinearity Zero Full Scale | Zero Offset | Full Scale (ppm| Temperature Range Number (%FS, Max) (%FS, Max) (%0FS, Max) | (uV/C, Max) | of FS/C, Max)| Range (C) Pkg. 10kHz 4722 +0.03 plus +0.03 (1) +0.1 +1 *50 +300 Oto +70 A 4702 +0.03 +0.1 +1 +50 +100 40 to +70 B 4704 +0.05 +0.1 +1 +50 +150 40 to +85 B 1OO0KHz 4780 (2) +0.05 +0.5 +10 Typ +50 +40 Oto +70 Cc 4781 (2) +0.02 +0,5 +10 Typ +50 +40 Oto +70 Cc IMHz 4706 +0.008 plus +0.02 (1) +0.1 *0.5 +100 #150 Oto +70 BD PRECISION Absolute Accuracy T Stability Specified Frequency Part Nonlinearity Zero Offset] Full Scale | Zero Offset | Full Scale (ppm| Temperature Range Number ({0FS, Max) (%FS, Max)|(%FS, Max) | (uV/C, Max) | of FS/C, Max)| Range (C) Pkg. 4708 +0.007 plus +0.013 (1) 40.05 +0.5 +50 +50 Oto +70 B: 10KHz 4732 +0.005 10.05 +0.5, +25 +25 ~25 to +85. E 4732-HR *0,005 +0.05 +0.5 +50 +50 -55 to +125 E 4710 +0.007 plus +0.013(1) +0.05 40.5 +50 +50 Oto +70 8B 100kKHz 4734 *0.005 *0.05 40.5, +25 +25 25 to +85 E 4734-HR +0.005 +0.05 +0.5 +50 +50 55 to +125 E 1MHz 4736 *0.008 +0.05 +0.1 +50 +50 Oto +70 E 4736-HR *0.008 $0.05 +0.1 +80 +100 55 to +125 E NOTES PACKAGES 1. Nonlinearity specification includes *%FS plus *% signal. A. Module, 114 = 1.14" = 0.4" 2. 4780 and 4781 perform both voltage to frequency and frequency to vollage conversion in same package. B. Module, 1.5 * 1.5 = 0.4" C. 14 pin plastic dual-in-line, 0.79" = 0.33" = 02" D. Module, 20 = 2.0" x a4" E. 24 pin ceramic dual-in-line, 1.39" = 0.8" = 0.2" TELEDYNE PHILBRICK microcincurrsVoltage to Frequency Converters GENERAL PURPOSE Accuracy Taine: Stability Output Frequency Part Nonlinearity Zero Offset) Full Scale | Zero Offset Full Scale (ppm| Temperature Range Number (FS, Max) ({0FS, Max) |(%FS, Max)| (uWC, Max) of FS/C,Max)| Range (C) | Pkg. 10kKHz 4701 0.05 +0.1 +0.75 +100 _ +100 Oto +70 A 100kHz 4703 40.05 +0.1 +0.75 +100 +100 ~25 to +85 A PRECISION Absolute Accuracy Temperature Stability Output Frequency Part Nonlinearity Zero Oftset| Full Scale | Zero Offset Full Scale (ppm| Temperature Range Number ("0FS, Max) (*6FS, Max)|(%eFS, Max)| (uW/C, Max) of FS/C, Max)} Range (C) | Pkg. 4715 +0.01 plus +0.01 (1) +0.03 #050 +20 +50 Oto +70 B 10kHz 4715-01 | +0.005 plus +0.005 (1) +0.03 +0.50 +20 +15 Oto +70 B 4731 +0.005 *0.05 +0.50 +20 +15 Oto +70 Cc 4731-HR +0.005 +0.05 +0.50 +20 +15 55 to +125 c 4709 +#0,005 plus +0.02 (1) +0.03 +0.30 n44 +50 Oto +70 B 100kHz +0,005 plus +0.02 (1) +0.03 +0.50 + #12 Oto +70 B 4733 +0.005 *0.05 +0.50 +20 +20 0 to +70 c 4733-HR 40.005 0.05 +0.50 +20 +20 -55 to +125 c 4705 +0,001 plus +0.05 (1) +0.1 +0.50 +50 +200 Oto +70 B {MHz 0.0005 plus 0.02 (1) +01 +0.50 +50 +200 Oto +70 B 4735 40.015. +0.05 +0.50 +50 +30 Oto +70 c 4735-HR 0,015 +0.05 +0.50 +50 +30 55 to +125 c SMHz 4707 0.01 plus +0.05 (1) +01 +0.50 #100 +150 Oto +70 D 4739 (2) | +0.05 plus +0.001 (1) | +0.08 Typ | +1.0 Typ +100 Typ +75 Typ Oto +70 c JOMHz | _ 4743 (2) | +0.05 plus +0.05 (1) | +0.08 Typ | +0.50 Typ | +100 Typ +100 Typ O to +70 c NOTES PACKAGES 1. Nonlinearity specification includes +%FS plus *% signal A. Module, 1.5 * 1.5" x 0.4" 2 Contact factory for extended temperature range and high B. Module, 2.0" = 2.0" x ga" reliability screening. C. 24 pin metal dual-in-line, 1.39" 0.8" 0.2" BD, Module, 3.0" x 2.0" = @.4" 72 TELEDYNE PHILBRICK microcircurrsModular Power Supplies 2200 SERIES 50Hz to 400Hz, 115V +10V. For optional 230V +20V operation, add 21 to 2400 SERIES model number. Models 2203, 2204 and 2206 operate from 115V or 230 Vac. Output Reg Max Ripple Limit and Current MA Case Model Voltage Current Line Load Noise (Typ) Size 5 2213 5V DC 1000mA +0.6% +0.1% imVp-p 1750 cs Volts 2223 5V DC 2000mA +0.02% +0.05% imV(RMS) 2700 c7 3 2203 +15V DC +100mA +0,03% +0,03% imV(RMS) 50 ci 5 2204 +15V DC +50mA +0.03% +0.015% | 1mV(RMS) 25 C1 =| +15 [2208 | +1svoc | 2100ma +0.03% +0,03% | imV(RMS) 50 C3 z Volts 2209 +15V DC +50mA +0.03% +0.015% ImV(RMS} 25 C4 o 2215 +15V DC +200mA +0.02% +0.05% imV(RMS) 60 cs & 2218 +15V DC +350mA +0.02% +0.02% | 0.5mV(RMS) 800 c7 we aaiz | *120N DC | 40a +0.1% 40.1% | 2mv(RMS) 60 ce Triple aa +15V +100 +0.02% +0.03% imv(RMS) 175 ca Output av 500mA, +0.02% +0.05% imV(RMS) 850 33 5V 2413 +5V DC +1000MA +0.5% +0.15% 2mV(RMS) 1750 z 5 +15 2415 +15V DC +200mA +0,05% +0.05% imV(RMS) 350 z =| Volts 2419 +18V DC +500mA +0.05% +0.05% imV(RMS) 1100 Zz 2300 SERIES DC TO DC CONVERTERS Output Input Regulation, Max. 2 Current 5 Limit = No Full Current Case 2 Model | Voltage Current Voltage Load Load Line Load mA (Typ) Size s 2301 | +15vV0C | +100mA | +5vDC | 200mA | 1000mA | +0.07% +0.07% 150 x a 2302 +15V DG +150mA4 +5V DC 200mA 1380mA 0.07% +0.07% 225 x "| essi | #18v oC trsoma | *80C | S00ma | s4soma | 20.1% | 20.1% a Y CASE SIZES (Inches (mm)) Cre 355 %25 1.06 (9.02 x 648 = 2.68) C3 = 355 * 255 1.00 (9.02 = 648 x 2.54) C4 = 255 = 2.55 = 0.88 (9.02 = 648 x 2.23) C5 = 356 x 255 = 1.25 (9.02 x 6.48 x 3.17) G6 = 3.55 * 2.55 = 2.00 (9.02 = 6.48 = 5.08) C7 = 355 * 2.55 * 1.62 (9.02 x 6.48 x 4.11) (CB = 3.55 = 2.55 = 1.88 (9.02 = 6.48 4.77) X= 2 2% 0.99 (5.13 x 6.13 = 0.99) Y=3% 25 O75 (7.62 = 650% 1 Zea 90) 06 * 275% 1.50 (10.29 = 6.99 x 3.81) TELEDYNE PHILBRICK microcircurts 73REPLACEMENT GUIDE The following is a list of Teledyne Philbricks older products, some of which are not available. Where applicable, we have indicated a replacement model that offers equivalent or better performance. Not all of these products are recommended for new design. Please contact the factory if additional information ts required. MODEL RECOMMENDED MODEL RECOMMENDED MODEL RECOMMENDED NUMBER REPLACEMENT NUMBER REPLACEMENT NUMBER REPLACEMENT 1003 1027 4112 4132 DL-21 1022 1005 1032/1332 4113 4131 ESL-1 1421-02 1006 1026 4114 4130 FA-222 1026 1008 1025 412902 4132 K2w None 1009 1026 4129-100Z 4132 K2XxXA 1022 1009 -02 1026 4140 4143 LGP-4 4363 1011 1027 4141 4144 LGP-475 4362 1012 1032 4142 4145 MAK-2F None 1016 1443/TP3554 4251 4253 PP254 1027 1017 1443/TP3554 4350 4362 PP45 1025/1027 1018 1020-01 4351 4363 PP45U 1025/1027 1018-01 1020-01 4352 None PP45LU 1025/1027 1020-02 1020-01 4356 None P65A 1323 1021 1027 4360 4362 P65AU 1323 1023 1027 4361 4363 PP65A 1323 1023-01 1027 4366 4362 PP65AU 1026 1024 1027 4367 4363 PP65AHU 1322 1026-01 1026 4369 None P66A None 1026-21 1026 4370 None PP66A None 1028 1026 4450 None P85AU 1421 1030 1025 4452 None PP&SAU 1421 1030-10 1025 4454 None QA-1 1421 1034 1022 4455 None QA-22 None 104 None 4456 None QFT-2 1027 1700 1701 4457 None QFT-2A4 1027 1703 1701 4552 None QFT-2B 1027 2001 2003, 4552-01 None QFT-5 1026/1421 2003-10 2003 4553 None SA-1 1025/1421-02 368 None 4553-01 None SA-2 1421-02 4020 None 4554 None SA-24 1421-02 4021 None 4554-01 None SA-25 1022/1460 4022 None 4702-10 4702 SD-5 1421-02 4023 None 4705-37 4705 SD-183 None 4024 4065 4850 None SL-6 1027 4025 4058 4856-01 4856. SL-7A 1027 4026 None BQ-100 2003 SP656M 1701 4027 None CCK-MF None SPFXN None 4058-10 4058 CDA-169 None SPFXP None 4065-10 4065 CKA-22M 1020 sQ-1 1025/1421-02 4068-83 4065 -HR CLA-442 1027 $Q-3 1020 4109 4132 CLA-476 1421-02 $Q-10A 1026/1425 4109-10 4132 DA-1A 1421-02 $Q-210 1025 4110 4130 DA-170 1421 $Q-517 1319 411i None U5801 1027 4111-10 None USA-3 1022/1480 Tobedyne Phitbrick makes that wee of its modules on the or use of biher technicial information Contained herein will Mot ifrenge on exigting oF future patent rights hor ao othe eacrioions contained herein imply the partion Of licenses 10 make, use, oF sell equipment Sorin accordance Iherawiih: 74 TELEDYNE PHILBRICK microciacuits