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Time delay for the di/dt Circuit is derived from
cascaded op−amps U2B and U5 (waveforms F and G of
Figure 5.6). The output gate, in turn, drives NPN
transistor Q8, followed by PNP transistor Q9, whose
output provides the gate drive for the three parallel
connected N−channel power MOSFET transistors
Q10 −Q12 (waveforms H of Figure 5.6). These three
FETs (MTM15N06), are rated at 15 A continuous drain
current and 40 A pulsed current and thus can readily
divert the maximum 60 A constant current that the
Fixture can generate. The results of this diversion from
the DUT is described by waveforms E, H and I of
Figure 5.6, with the di/dt of of ITM dictated by the series
inductance L1. For all subsequent testing, the inductor
was a shorting bar, resulting in very little inductance
and consequently, the highest di/dt (limited primarily
by wiring inductance). When a physical inductor L1 is
used, a clamp diode, scaled to the diverted current,
should be placed across L1 to limit “inductive kicks.”
dv/dt CIRCUIT
The last major portion of the Fixture, the dv/dt Circuit,
is variable time delayed by the multi−turn, front panel tq
Time Control potentiometer R7, operating as part of an
integrator on the input of comparator U6. Its output
(waveform J of Figure 5.6) is used to turn−off, in order, a)
normally on NPN transistor Q13, b) PNP transistor Q14
and c) N−channel power MOSFET Q15 (waveform L of
Figure 5.6). This FET is placed across ramp generating
capacitor C1, and when unclamped (turned off), the
capacitor is allowed to charge through resistor R1 to the
supply voltage +V1. Thus, the voltage appearing on the
drain will be an exponentially rising voltage with a dv/dt
dictated by R1, C1, whose position in time can be
advanced or delayed. This waveform is then applied
through a blocking diode to the anode of the DUT for the
forward blocking voltage test.
Another blocking diode, D1, also plays an important
role in tq measurements and must be properly selected. Its
purpose is to prevent the dv/dt ramp from feeding back
into the Current Source and di/dt Circuit and also to
momentarily apply a reverse blocking voltage (a function
of −V2 of the di/dt circuit) to the DUT. Consequently, D1
must have a reverse recovery time trr greater than the
DUT, but less than the tq time. When measuring standard
recovery SCRs, its selection — fast recovery rectifiers or
standard recovery — is not that critical, however, for fast
recovery, low tq SCRs, the diode must be tailored to the
DUT to produce accurate results. Also, the current rating
of the diode must be compatible with the DUT test
current. These effects are illustrated in the waveforms
shown in Figure 5.7 where both a fast recovery rectifier
and standard recovery rectifier were used in measuring tq
of a standard 2N6508 SCR. Although the di/dt’s were the
same, the reverse recovery current IRM and trr were
greater with the standard recovery rectifier, resulting in a
somewhat shorter tq (59 μs versus 63 μs). In fact, tq is
affected by the initial conditions (ITM, di/dt, IRM, dv/dt,
etc.) and these conditions should be specified to maintain
measurement repeatability. This is later described in the
published curves and tables.
Finally, the resistor R1 and the resultant current I1 in the
dv/dt circuit must meet certain criteria: I1 should be
greater than the SCR holding current so that when the
DUT does indicate tq limitation, it latches up, thus
suppressing the dv/dt ramp voltage; and, for fast SCRs
(low tq), I1 should be large enough to ensure measurement
repeatability. Typical values of I1 for standard and fast
SCRs may be 50 mA and 500 mA, respectively.
Obviously, for high forward blocking voltage + V1 tests,
the power requirements must be met.
EFFECTS OF GATE BIAS ON tq
Examples of the effects of I1 on tq are listed in
Table 5.III whereby standard and fast SCRs were tested
with about 50 mA and 1 A, respectively. Note that the low
tq SCR’s required fast recovery diodes and high I1 current.
TEST FIXTURE POWER SUPPLIES
Most of the power supplies for the system are self
contained, including the +12 V supply for the Constant
Current Circuit. This simple, unregulated supply furnishes
up to 60 A peak pulsed current, primarily due to the line
synchronized operation of the system. Power supplies
+V1 and −V2, for this exercise, were external supplies,
since they are variable, but they can be incorporated in the
system. The reverse blocking voltage to the DUT is
supplied by − V2 and is typically set for about −10 V to
−20 V, being limited to the breakdown voltage of the
diverting power MOSFETS (VDSS = 60 V). The +12 V
unregulated supply can be as high as +20 V when
unloaded; therefore, −V2 (MAX), in theory, would be
−40 V but should be limited to less than −36 V due to the
56 V protective Zener across the drain−source of the
FETs. Also, −V2 must be capable of handling the peak
60 A, diverting current, if so required.
The reapplied forward blocking voltage power supply
+V1, may be as high as the DUT VDRM which
conceivably can be 600 V, 1,000 V or greater and, since
this supply is on most of the time, must be able to supply
the required I1. Due to the sometimes high power
requirements, +V1 test conditions may have to be reduced
for extremely fast SCRs.