AD5100YRQZ-1RL7 - Analog Devices, Inc.

System Management IC with Factory Programmed

Quad Voltage Monitoring and Supervisory Functions

AD5100

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Qualified for automotive applications

2 device-enabling outputs with 6 factory programmed

monitoring inputs (see Table 1)

Two 30 V monitoring inputs with shutdown control of

external devices

Factory programmed overvoltage, undervoltage, turn-on

and turn-off thresholds, and shutdown timings

Shutdown warning with fault detection

Reset control of external devices

5 V and 7.96 V monitoring inputs with reset control of

external devices

Factory programmed reset thresholds and hold time

eMOST-compatible inputs

Diagnostic application using V2MON and V4MON

Two supervisory functions

Watchdog reset controller with timeout and selectable

floating input

Manual reset control for external devices

Digital interface and programmability

I2C-compatible interface

OTP can be overwritten for dynamic adjustments

Power-up by edge triggered signal

Power-down over I2C bus

Operating range

Supply voltage: 6.0 V to 30 V

Temperature range: −40°C to +125°C

Shutdown current: 5 μA max

Operating current: 2 mA max

High voltage input antimigration shielding pinouts

APPLICATIONS

Automotive systems

Network equipment

Computers, controllers, and embedded systems

GENERAL DESCRIPTION

The AD5100 is a factory programmed system management

IC that combines four channels of voltage monitoring and

watchdog supervision. The AD5100 can be used to shut down

external supplies, reset processors, or disable any other system

electronics when the system malfunctions. The AD5100 can

also be used to protect systems from improper device power-up

sequencing. The AD5100 is a robust watchdog reset controller,

and can monitor two 30 V inputs with shutdown and reset

controls, one 2.3 V to 5.0 V input, and one 1.6 V to 7.96 V

input. Most monitoring input thresholds and timing settings

have a range of settings which are factory programmed by

Analog Devices, Inc. in the one-time programmable EPROM

(OTP) memory, or can be programmed on-the-fly over the

serial interface.

The AD5100 is versatile for system monitoring applications

where critical microprocessor, DSP, and embedded systems

operate under harsh conditions, such as automotive, industrial,

or communications network environments.

The AD5100 is available in a compact 16-lead QSOP package

and can operate in an extended automotive temperature range

from −40°C to +125°C.

Analog Devices provides non-OTP programmed AD5100

parts for use in evaluating the desired threshold and delay

settings. Only factory programmed AD5100 parts are shipped

in production quantities. Contact Analog Devices directly to

inquire about factory programmed models.

Table 1. AD5100 General Input and Output Information

Input

Monitoring

Range1

Shutdown

Control

Reset

Control

Fault

Detection

V1MON 6 V to 28.29 V Yes Yes Yes

V2MON 3 V to 24.75 V Yes Yes Yes

V3MON 2.32 V to 4.97 V No Yes Yes

V4MON 1.67 V to 7.96 V No Yes Yes

WDI 0 V to 5 V Yes Yes No

MR 0 V to 5 V No Yes No

1 With programmable threshold and programmable delay.

AD5100

Rev. A | Page 2 of 36

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4 

Electrical Specifications ............................................................... 4

Timing Specifications .................................................................. 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

One-Time Programmable (OTP) Options ............................. 10

Theory of Operation ...................................................................... 12

Monitoring Inputs .......................................................................... 13

V1MON ............................................................................................ 13

V2MON ............................................................................................ 14

V3MON ............................................................................................ 15

V4MON ............................................................................................ 16

Watchdog Input .......................................................................... 16

Manual Reset Input .................................................................... 18

Outputs ............................................................................................ 19

Shutdown Output, SHDN ......................................................... 19

Reset Output, RESET ................................................................. 19

Shutdown Warning, SHDNWARN .......................................... 20

V4OUT Output ................................................................................ 20

Power Requirements ...................................................................... 21

Internal Power, VREG ................................................................... 21

Protection .................................................................................... 22

AD5100 Register Map .................................................................... 23

I2C Serial Interface .......................................................................... 26

Writing Data to AD5100 ........................................................... 27

Reading Data from AD5100 ..................................................... 27

Temporary Override of Default Settings ................................. 28

Applications Information .............................................................. 29

Car Battery and Infotainment System Supply Monitoring ... 29

Battery Monitoring with Fan Control ..................................... 32

Battery State of Charge Indicator and Shutdown Early

Warning Monitoring .................................................................. 32

Rising Edge Triggered Wake-Up Mode ................................... 33

Outline Dimensions ....................................................................... 35

Ordering Guide .......................................................................... 35

Automotive Products ................................................................. 35

REVISION HISTORY

6/10—Rev. 0 to Rev. A

Changed Programmable to Factory Programmed

Throughout ....................................................................................... 1

Changes to Features Section and General Description Section ....... 1

Changes to RIN_V2MON, RIN_V3MON, RIN_V4MON, and MR Resistance

Specifications Throughout .............................................................. 4

Changes to Table 2 ............................................................................ 4

Changes to Table 5 ............................................................................ 9

Deleted Figure 18; Renumbered Sequentially ............................ 21

Changes to Rising Edge Triggered Wake-Up Mode Section .... 21

Changes to Overcurrent Protection Section ............................... 22

Changes to ADI Register Map Section ........................................ 23

Changes to Table 11 ....................................................................... 23

Changes to I2C Serial Interface Section and Table 12 ................ 26

Changes to Table 14 and Reading Data from AD5100 Section ... 27

Deleted Figure 25 ............................................................................ 28

Deleted Permanent Setting ofAD5100 Registers Section ......... 30

Changes to Ordering Guide and added Automotive Products

Sect ion .............................................................................................. 35

9/08—Revision 0: Initial Version

AD5100

Rev. A | Page 3 of 36

FUNCTIONAL BLOCK DIAGRAM

05692-001

55kΩ

640kΩ

130kΩ

665kΩ

SHUTDOWN

CONTROLLER

RESET

GENERATOR

WDI DETECTION

AND

RESET G ENE RATOR

C CO NT R O LLER OTP F USE ARRAY

FD REGISTER

FAUL T DET E CTION

1MON

(6V TO 30V)

4OUT

RESET

SHDNWARN

SHDN

AD0

SDA

SCL

OTP

WDI

4MON

(0.9V TO 30V)

3MON

(2.5V TO 5V)

2MON

(3V TO 30V)

OV/UV

AD5100

ON/OFF

Figure 1.

AD5100

Rev. A | Page 4 of 36

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

6 V ≤ V1MON ≤ 30 V and 3 V ≤ V2MON ≤ 30 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

HIGH VOLTAGE MONITORING INPUTS

V1MON

Voltage Range V1MON 6 30 V

Input Resistance RIN_V1MON 36 55 70 kΩ

OV, UV Threshold Tolerance

(See Figure 7 and Table 6)

ΔOV, ΔUV TA = 25°C −1.6 +1.6 %

A = −40°C to +85°C −1.8 +1.8 %

A = −40°C to +125°C −2 +2 %

Hysteresis 1.5 %

Programmable Shutdown Hold Time

Tolerance (See Figure 7 and Table 8)

Δt1SD_HOLD T

A = 25°C; does not apply to

Code 0x7

−10 +10 %

Programmable Shutdown Delay Tolerance

(See Figure 7 and Table 8)

Δt1SD_DELAY T

A = 25°C; does not apply to

Code 0x7

−10 +10 %

A = −40°C to +125°C; does not

apply to Code 0x7

−17 +17 %

Fault Detection Delay tFD_DELAY 60 μs

Glitch Immune Time tGLITCH Guaranteed by evaluation 45 μs

V2MON

Input Voltage V2MON Minimum voltage on V2MON to

ensure AD5100 VREG power-up

2.2 V

Voltage Range2 V

2MON 3 30 V

Input Resistance RIN_V2MON 500 675 860 kΩ

On, Off Threshold Tolerance3

(See Figure 7 and Table 6)

ΔOn, ΔOff TA = 25°C −2 +2 %

A = −40°C to +85°C −2.4 +2.4 %

A = −40°C to +125°C −2.5 +2.5 %

Hysteresis 1.5 %

Turn-On Programmable SHDN Hold Time

Tolerance (See and ) Figure 7 Table 8

Δt2SD_HOLD T

A = 25°C; does not apply to

Code 0x7

−10 +10 %

Turn-Off Programmable SHDN Delay Time

Tolerance (See and ) Figure 7 Table 8

Δt2SD_DELAY T

A = 25°C; does not apply to

Code 0x07

−10 +10 %

A = −40°C to +125°C; does not

apply to Code 0x7

−17 +17 %

Fault Detection Delay tFD_DELAY V

2MON_OFF only 60 μs

Glitch Immune Time tGLITCH 45 μs

SHDN

SHDN Output High VOH V

RAIL = VREG, ISOURCE = 40 μA 2.4 V

RAIL = V1MON, ISOURCE = 600 μA V1MON − 0.5 V

SHDN Output Low VOL I

SINK = 1.6 mA 0.4 V

1MON = 12 V, ISINK = 40 mA 1.5 3 V

SHDN Sink Current ISINK V1MON = 12 V, SHDN forced to 12 V 10 13.5 mA

SHDNWARN (Open-Drain Output)

SHDNWARN Inactive Leakage Current IOH_SHDNWARN 0.9 μA

SHDNWARN Active VOL_SHDNWARN I

SINK = 3 mA 0.4 V

AD5100

Rev. A | Page 5 of 36

Parameter Symbol Conditions Min Typ1 Max Unit

LOW VOLTAGE MONITORING INPUTS

V3MON, V4MON

V3MON Voltage Range V3MON 2.0 5.5 V

Input Resistance RIN_V3MON 85 130 180 kΩ

V3MON Threshold Tolerance

(See Figure 10 and Table 6)

ΔV3MON T

A = 25°C −2.5 +2.5 %

TA = −40°C to +85°C −2.75 +2.75 %

TA = −40°C to +125°C −3 +3 %

V3MON Hysteresis V3_HYSTERESIS

1.2 %

V4MON Voltage Range4 V

4MON 0.9 30 V

Input Resistance RIN_V4MON 500 675 860 kΩ

V4MON Threshold Tolerance

(See Figure 12 and Table 6)

ΔV4MON T

A = 25°C −2.5 +2.5 %

TA = −40°C to +85°C −2.75 +2.75 %

TA = −40°C to +125°C −3 +3 %

V4MON Hysteresis V4_HYSTERESIS 5 %

RESET

RESET Hold Time Tolerance

(See , , and ) Figure 10 Figure 12 Table 8

ΔtRS_HOLD T

A = 25°C; does not apply to

Code 0x6 and Code 0x7

−10 +10 %

A = −40°C to +125°C; does not

apply to Code 0x6 and Code 0x7

−17 +17 %

V3MON/V4MON-to-RESET Delay tRS_DELAY 60 μs

RESET Output Voltage High VOH V

3MON ≥ 4.38 V, ISOURCE = 120 μA V3MON − 1.5 V

2.7 V < V3MON ≤ 4.38 V,

ISOURCE = 30 μA

0.8 × V3MON V

2.3 V < V3MON ≤ 2.7 V,

ISOURCE = 20 μA

0.8 × V3MON V

1.8 V ≤ V3MON ≤ 2.3 V,

ISOURCE = 8 μA

0.8 × V3MON V

RESET Output Voltage Low VOL V

3MON > 4.38 V, ISINK = 3.2 mA 0.4 V

3MON < 4.38 V, ISINK = 1.2 mA 0.3 V

RESET Output Short-Circuit Current5 ISOURCE RESET = 0, V3MON = 5.5 V 825 μA

RESET = 0, V3MON = 3.6 V 400 μA

Glitch Immune Time tGLITCH 50 μs

V4OUT Maximum Output V4OUT_MAX Open drain 5.5 V

V4OUT Propagation Delay tV4OUT_DELAY 70 μs

V4OUT Maximum Frequency fV4OUT Applies to RESET disabled only 10 kHz

WDI (WATCHDOG INPUT)

WDI Programmable Timeout Tolerance

(see Figure 13 and Table 8)

ΔtWD T

A = 25°C −10 +10 %

A = −40°C to +125°C −17 +17 %

WDI Pulse Width tWDI 50 ns

Watchdog Initiated RESET Pulse Width tWDR When no WDI tWD/50 ms

Watchdog Initiated SHDN tWD_SHDN When no WDI activity > 4 tWD 1 sec

WDI Input Voltage Low VIL_WD 0.3 × V3MON V

WDI Input Voltage High VIH_WD 0.7 × V3MON V

WDI Input Current WDI = V3MON 160 μA

WDI = 0 −20 μA

MR (MANUAL RESET) INPUT

MR Input Voltage Low VIL_MR 0.3 × V3MON V

MR Input Voltage High VIH_MR 0.7 × V3MON V

Input Current 1 μA

MR Pulse Width tMR 1 μs

MR Deglitching tMR_GLITCH 100 ns

MR-to-RESET Delay tMR_DELAY 1 μs

AD5100

Rev. A | Page 6 of 36

Parameter Symbol Conditions Min Typ1 Max Unit

MR Pull-Up Resistance (Internal to V3MON) 37 60 82 kΩ

RESET Hold Time Tolerance

(see and ) Figure 12 Table 8

ΔtRS_HOLD T

A = 25°C; does not apply to Code

0x6 and Code 0x7

−10 +10 %

A = −40°C to +125°C; does not

apply to Code 0x06 and Code 0x7

−17 +17 %

SERIAL INTERFACES

Input Logic High (SCL, SDA)6 V

IH External RPULL-UP = 2.2 kΩ 2.0 5.5 V

Input Logic Low (SCL, SDA) VIL External RPULL-UP = 2.2 kΩ 0 0.8 V

Output Logic High (SDA) VOH V

RAIL = 2 V to 5.5 V 0.7 × VRAIL V

Output Logic Low (SDA) VOL I

OL = 3 mA 0 0.4 V

Input Current VIN = 0 V to 5.5 V 1 μA

Input Capacitance CI 5 pF

POWER SUPPLY

Supply Voltage Range V1MON 6.0 30 V

Sleep Mode Supply Current ISLEEP_V1MON V

2MON = 0 V 5 μA

Active Mode Supply Current IPOWER_V1MON V

2MON = 12 V 2 mA

2MON edge triggered mode selected 2 mA

Device Power-On Threshold V2MON, IH 2.2 V

2MON, IL 0.4 V

Device Power-Up V2MON, Minimum Pulse Width tV2MON_PW 4 ms

Device Power-Down Delay TVREG_OFF_DELAY V

2MON < 0.4 V (normal mode) 2 sec

2C-initiated power-down 10 μs

1 Represent typical values at 25°C, V1MON = 12 V, and V2MON = 12 V.

2 Initial V2MON turn-on minimum remains as 2.2 V but the 3 V to 30 V specifications apply afterward.

3 Does not apply if V2MON is a digital signal.

4 V4MON threshold limits (see Table 6) are designed to primarily allow V4MON to monitor low voltage inputs. The V4MON input pin is capable of withstanding voltages up to

30 V. One application where this 30 V capability is useful is electronic media-oriented systems transport (eMOST) diagnostic circuits.

5 The RESET short-circuit current is the maximum pull-up current when RESET is driven low by a microprocessor bidirectional reset pin.

6 It is typical for the SCL and SDA to have resistors pulled up to V3MON. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are

driven directly from a low voltage logic controller without pull-up resistors.

AD5100

Rev. A | Page 7 of 36

TIMING SPECIFICATIONS

Table 3.

Parameter Description Min Typ Max Unit

I2C INTERFACE TIMING CHARACTERISTICS1, 2

fSCL SCL clock frequency 400 kHz

t1 t

BUF, bus free time between start and stop 1.3 μs

t2 tHD;STA, hold time after (repeated) start condition; after this

period, the first clock is generated

0.6 μs

t3 t

LOW, low period of SCL clock 1.3 μs

t4 t

HIGH, high period of SCL clock 0.6 50 μs

t5 t

SU;STA, setup time for start condition 0.6 μs

t6 t

HD;DAT, data hold time 0.9 μs

t7 t

SU;DAT, data setup time 0.1 μs

t8 t

F, fall time of both SDA and SCL signals 0.3 μs

t9 t

R, rise time of both SDA and SCL signals 0.3 μs

t10 t

SU;STO, setup time for stop condition 0.6 μs

1 Guaranteed by design and not subject to production test.

2 See Figure 2.

SCL

PS SP

05692-002

Figure 2. Digital Interface Timing Diagram

AD5100

Rev. A | Page 8 of 36

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

V1MON to GND −0.3 V, +33 V

V2MON to GND −0.3 V, +33 V

V3MON to GND −0.3 V, +7 V

V4MON to GND −0.3 V, +33 V

VOTP to GND −0.3 V, +7 V

Digital Input Voltage to GND

(MR, WDI, SCL, SDA, AD0)

0 V, +7 V

Digital Output Voltage to GND

(RESET, V4OUT, SHDNWARN)

0 V, +7 V

Digital Output Voltage to GND (SHDN) 0 V, +33 V

Operating Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C

ESD Rating (HBM) 3.5 kV

Maximum Junction Temperature (TJmax) 150°C

Power Dissipation1 (TJmax − TA2)/θJA

Thermal Impedance3

θJA Junction-to-Ambient 105.44°C/W

θJC Junction-to-Case 38.8°C/W

IR Reflow Soldering (RoHS-Compliant Package)

Peak Temperature 260°C (+0°C)

Time at Peak Temperature 20 sec to 40 sec

Ramp-Up Rate 3°C/sec max

Ramp-Down Rate −6°C/sec max

Time from 25°C to Peak Temperature 8 minutes max

1 Values relate to the package being used on a 4-layer board.

2 TA = ambient temperature.

3 Junction-to-case resistance is applicable to components featuring a

preferential flow direction, for example, components mounted on a

heat sink. Junction-to-ambient resistance is more useful for air-cooled

PCB-mounted components.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

AD5100

Rev. A | Page 9 of 36

05692-003

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1MON 1

GND

NC = NO CONNECT

OTP 3

3MON 4

2MON

GND/NC

4MON

AD0

WDI

SHDN

SCL

SHDNWARN

4OUT

SDA

RESET

AD5100

TOP VIEW

(No t to Scale)

Figure 3. Pin Configuration

Table 5. AD5100 Pin Function Descriptions

Pin No. Mnemonic Description

1 V1MON High Voltage Monitoring Input. AD5100 internal supply is derived from V1MON. There must be a 10 μF electrolytic

capacitor between this pin and GND, placed as close as possible to the V1MON pin.

2 GND Ground.

3 VOTP One-Time Programmable Supply Voltage for EPROM. A 10 μF decoupling capacitor (low ESR) to GND is required.

4 V3MON Low Voltage Monitoring Input.

5 MR Manual Reset Input. Active low.

6 WDI Watchdog Input.

7 SCL I2C Serial Input Register Clock. Open-drain input. If it is driven directly from a logic driver without the pull-up

resistor, ensure that the VIH minimum is 3.3 V.

8 SDA I2C Serial Data Input/Output. Open-drain input/output. If it is driven directly from a logic driver without the pull-

up resistor, ensure that the VIH minimum is 3.3 V.

9 RESET Reset. Push-pull output with rail voltage of V3MON.

10 V4OUT Open-Drain Output. Triggered by V4MON.

11 SHDNWARN Shutdown Warning. Active low, open-drain output.

12 SHDN Shutdown Output. Push-pull output with selectable rail voltage of V1MON or VREG, the AD5100 internal power (30 V

maximum).

13 AD0 I2C Slave Address Configuration. If tied high, this pin can only be tied to 3.3 V maximum.

14 V4MON Low Voltage Monitoring Input. Capable of withstanding 30 V.

15 GND/NC Ground/No Connect. Can be grounded or left floating but do not connect to any other potentials.

16 V2MON High Voltage Monitoring Input. It is also the internal supply voltage enabling input.

05692-004

8 9

AD5100

TOP VIEW

(Not to Scal e)

GND

Figure 4. Recommended PCB Layout for Shielded High Voltage Inputs

AD5100

Rev. A | Page 10 of 36

ONE-TIME PROGRAMMABLE (OTP) OPTIONS

All values are typical ratings; see Table 2 for tolerances.

Table 6. Available Programmable Thresholds at TA = 25°C

V1MON OV Threshold1 V

1MON UV Threshold V2MON On Threshold V2MON Off Threshold2 V

3MON Threshold V4MON Threshold

7.92 V 6.00 V 3.00 V 3.00 V 2.32 V 1.67 V

9.00 V 6.49 V 3.5 V 3.5 V 2.64 V 2.31 V

9.90 V 6.95 V 4.00 V 4.00 V 2.93 V3 3.05 V

11.00 V 7.47 V 4.77 V 4.77 V 3.10 V 4.62 V

12.00 V 7.92 V 6.00 V 6.00 V 4.36 V 6.51 V

13.20 V 8.43 V3 6.49 V 6.49 V 4.65 V 7.16 V

14.14 V 9.00 V 6.95 V 6.95 V3 4.75 V 7.54 V3

15.23 V 9.43 V 7.47 V3 7.47 V 4.97 V 7.96 V

15.84 V 9.90 V 7.92 V 7.92 V Reserved Reserved

17.22 V 10.42 V 8.43 V 8.43 V Reserved Reserved

18.00 V3 11.00 V 9.00 V 9.00 V Reserved Reserved

18.86 V 11.65 V 9.43 V 9.43 V Reserved Reserved

19.80 V 12.00 V 9.90 V 9.90 V Reserved Reserved

22.00 V 12.38 V 15.23 V 15.23 V Reserved Reserved

24.75 V 13.20 V 19.80 V 19.80 V Reserved Reserved

28.29 V 13.66 V 24.75 V Rising edge triggered

wake-up mode

Reserved Reserved

1 V1MON_OV must be > V1MON_UV.

2 V2MON_OFF is ignored if > V2MON_ON, but V2MON_OFF cannot be = V2MON_ON.

3 AD5100-0 default settings. Contact Analog Devices if other default settings are required.

Table 7. Look-Up Table of Programming Code vs. Typical Thresholds Shown in Table 6

Code

V1MON OV

Threshold

V1MON UV

Threshold

V2MON On

Threshold V2MON Off Threshold V3MON Threshold V4MON Threshold

0000 18.00 V1 8.43 V1 7.47 V1 6.95 V1 2.93 V1 7.54 V1

0001 18.86 V 7.92 V 6.95 V 7.47 V 4.65 V 1.67 V

0010 15.84 V 9.43 V 6.49 V 6.00 V 4.75 V 2.31 V

0011 17.22 V 9.00 V 6.00 V 6.49 V 4.97 V 3.05 V

0100 24.75 V 6.49 V 4.77 V 4.00 V 2.32 V 4.62 V

0101 28.29 V 6.00 V 4.00 V 4.77 V 2.64 V 6.51 V

0110 19.80 V 7.47 V 3.50 V 3.00 V 4.36 V 7.16 V

0111 22.00 V 6.95 V 3.00 V 3.50 V 3.10 V 7.96 V

1000 9.90 V 12.38 V 24.75 V 19.80 V Reserved Reserved

1001 11.00 V 12.00 V 19.80 V Rising edge triggered

wake-up mode

Reserved Reserved

1010 7.92 V 13.66 V 15.23 V 9.90 V Reserved Reserved

1011 9.00 V 13.20 V 9.90 V 15.23 V Reserved Reserved

1100 14.14 V 10.42 V 9.43 V 9.00 V Reserved Reserved

1101 15.23 V 9.90 V 9.00 V 9.43 V Reserved Reserved

1110 12.00 V 11.65 V 8.43 V 7.92 V Reserved Reserved

1111 13.20 V 11.00 V 7.92 V 8.43 V Reserved Reserved

1AD5100-0 default settings. Contact Analog Devices if other default settings are required.

AD5100

Rev. A | Page 11 of 36

Table 8. Available Programmable Hold Time and Delay

t1SD_HOLD t

1SD_DELAY t

2SD_HOLD t

2SD_DELAY t

RS_HOLD t

0.07 ms 0.07 ms 0.07 ms 0.07 ms 0.1 ms 100 ms

20 ms 50 ms 10 ms1 50 ms 1 ms 250 ms

40 ms 100 ms 20 ms 100 ms1 15 ms 500 ms

60 ms 200 ms 30 ms 200 ms 30 ms 750 ms

80 ms 400 ms 40 ms 400 ms 50 ms 1000 ms

100 ms 800 ms 50 ms 800 ms 100 ms 1250 ms

150 ms 1000 ms 100 ms 1000 ms 150 ms 1500 ms1

200 ms1 1200 ms1 200 ms 1200 ms 200 ms1 2000 ms

1 AD5100-0 default settings. Contact Analog Devices if other default settings are required.

Table 9. Look-Up Table of Programming Code vs. Typical Timings Shown in Table 8

Code t1SD_HOLD t1SD_DELAY t

2SD_HOLD t

2SD_DELAY t

RS_HOLD t

000 200 ms1 1200 ms1 10 ms1 100 ms1 200 ms1 1500 ms1

001 150 ms 1000 ms 20 ms 50 ms 150 ms 2000 ms

010 100 ms 800 ms 30 ms 200 ms 100 ms 1250 ms

011 80 ms 400 ms 40 ms 400 ms 50 ms 1000 ms

100 60 ms 200 ms 50 ms 800 ms 30 ms 750 ms

101 40 ms 100 ms 100 ms 1000 ms 15 ms 500 ms

110 20 ms 50 ms 200 ms 1200 ms 1 ms 250 ms

111 0.07 ms 0.07 ms 0.07 ms 0.07 ms 0.1 ms 100 ms

1 AD5100-0 default settings. Contact Analog Devices if other default settings are required.

AD5100

Rev. A | Page 12 of 36

THEORY OF OPERATION

The AD5100 is a programmable system management IC that

has four channels of monitoring inputs. Three inputs have

high voltage (30 V) capability. For example, if the AD5100 is

used in an automotive application, V1MON (Monitoring Input 1)

can be connected to the battery and the V2MON can be connected

to the ignition switch, a rising edge trigger wake-up signal, or

the media-oriented systems transport (MOST) wake-up signal

(V4MON is connected to V2MON for MOST applications). Two

other inputs, V3MON and V4MON, are designed for low voltage

monitoring, with programmable thresholds from 2.93 V to

7.96 V. The two high voltage monitoring inputs control the

shutdown signal, SHDN and reset signal, RESET, while the two

low voltage monitoring inputs control the reset signal, RESET.

SHDN and RESET are both disabling signals for external devices.

The differences between these two outputs are in output level

and driving capabilities, as described in the section.

The WDI (watchdog) and

Outputs

MR (manual reset) inputs also

control the RESET output, for use with an external digital

processor. shows the general flow chart and

summarizes the AD5100 functions and features.

Figure 5 Table 10

05692-005

YES

NO SHDN = 0*

SHDN = 0

RESET = 0

YES

NO SHDN = 0*

1MON

> UV

1MON

< OV

YES

NO SHDN = 0

SHDN = 1

2MON

> ON

2MON

> OFF

2MON

RISI NG EDG E

SENSIT I VE SE LE CTE D)

2MON

LEVEL

SENSITIVE

SELECTED

YES

CONTINUE

MONITORING

YES

4MON

THRESHOLD V

4OUT

= 0

4OUT

= 1

YES

USING V

4OUT

FOR PWM NO

YES

4MON

THRESHOLD

YES

3MON

THRESHOLD

YES

VALID WDI

YES

VALID WDI

YES

FLOATING

WDI DISABL E D

YES

STANDARD

WDI SELECTED

YES

MR = 1

RESET = 0

YES

FLOATING WDI

NO ( ADVANCE WDI S E LECT E D)

* SEE TABLE 11 RESET CONFIG URATION REG ISTER:

IF [0] = 0, T HE N S HDN = 0 AND RESET = 0

IF [0] = 1, T HE N S HDN = 0 AND RESET = 1

DEFAULT PATHS

Figure 5. General Flow Chart

Table 10. AD5100 Functions and Features

Input

Monitoring

Range

Shutdown

Control

Reset

Control

Fault

Detection Functions and Features If Not Used

V1MON 6 V to 28.29 V Yes Yes Yes Overvoltage/undervoltage thresholds Does not apply

V2MON 3 V to 24.75 V Yes Yes Yes On/off voltage thresholds; pseudo rising edge

triggered, wake-up selectable; MOST wake-up

signal (V2MON connected to V4MON)

Connect to V1MON,

minimum input 6 V

V3MON 2.32 V to 4.97 V No Yes Yes Connect to VOTP and

set threshold to

minimum

V4MON 1.67 V to 7.96 V No Yes Yes Additional output Connect to GND

WDI 0 V to 5 V Yes Yes No Standard, advance, or floating; watchdog

selectable

Leave floating

MR 0 V to 5 V Yes Yes No Highest priority on RESET over other inputs Leave floating

AD5100

Rev. A | Page 13 of 36

MONITORING INPUTS

V1MON

V1MON is a high voltage monitoring input that controls the

SHDN and RESET functions of the external devices. In addition,

it provides a shutdown warning to the system. V1MON monitors

inputs from 6 V to 30 V.

The V1MON pin is monitored by two comparators, one for overvol-

tage and one for undervoltage detection. Both are designed with

1.5% hysteresis.

When the V1MON input goes above the programmed overvoltage

(OV) threshold, the comparator becomes active immediately,

indicating that an OV condition has occurred. Due to hysteresis,

the V1MON input must be brought below the programmed OV

threshold by 1.5% before the comparator becomes inactive,

indicating that the OV condition has gone away (see Figure 6).

5692-007

1MON

1MON_UV

COMPARATOR

ACTIVE

COMPARATOR

INACTIVE

COMPARATOR

ACTIVE

COMPARATOR

INACTIVE

1MON_OV

HYSTERESIS

Figure 6. V1MON Hysteresis

When the V1MON input drops below the programmed under-

voltage (UV) threshold, the comparator becomes active

immediately, indicating that a UV condition has occurred.

Similarly, due to hysteresis, the V1MON input must be brought

above the programmed UV threshold by 1.5% before the

comparator becomes inactive, indicating that the UV condition

has gone away.

Both V1MON comparators are used (in conjunction with hold and

delay timers) to control the SHDN and RESET pins.

V1MON has a 16-level programmable OV threshold (Register 0x01)

and UV threshold (Register 0x02) with an 8-step 0.07 ms to

200 ms shutdown hold time (t1SD_HOLD) and 0.07 ms to 1200 ms

shutdown delay (t1SD_DELAY). The shutdown hold time means that

the SHDN signal is held low for t1SD_HOLD after V1MON returns

within its UV and OV thresholds. The shutdown delay means

that the SHDN signal activation is delayed until the programmed

t1SD_DELAY has elapsed. SHDN activates once the voltage on V1MON

is outside the OV or UV threshold for a time longer than tGLITCH.

RESET follows SHDN delay and hold timings when triggered

by VIMON.

The OV threshold chosen must be greater than the UV threshold.

When the shutdown is triggered, either because the input has

reached the OV or UV threshold, such fault conditions are

temporarily recorded in the fault detection register.

The SHDNWARN output transitions low for signaling before

the shutdown output, SHDN, activates. The timing of the SHDN

output is dependent on how long the shutdown-programmed

delay (t1SD_DELAY ) is set relative to the SHDNWARN propagation

delay (tFD_DELAY). This feature attempts to allow the system to

finish any critical housekeeping tasks before shutting down the

external device.

The V1MON, shutdown, and shutdown warning timing diagrams

are shown in Figure 7.

The ranges of OV and UV thresholds are shown in Table 6 , and

the programming codes for the selected thresholds are found in

Table 7. The defaulted OV threshold is 18.00 V and, for UV

threshold, it is 8.43 V. Similarly, the ranges of shutdown hold

and delay times are shown in Table 8 , and the programming

codes for the selected timings are shown in Table 9.

V1MON exhibits typical input resistance of 55 kΩ that users

should take into account for loading effect.

The voltage at V1MON provides the power for the AD5100, but

a valid signal on V2MON must be present before the internal

power rail, VREG, starts operation. Details are explained in the

Power Requirements section.

AD5100

Rev. A | Page 14 of 36

05692-006

1MON

2MON

1MON_OV*

1MON_UV*

2MON_OFF*

2MON_ON*

2SD_HOLD*

FD_DELAY

SHDNWARN

SHDN

AND RESET

NOTES

1. * = P ROGRAM M ABLE.

2. # = THE DURAT IO N OF THE

MIN

MUST BE S HO RTER THAN

VREG_OFF_DELAY

OR E LSE THE AD5100 WI LL BE PO WERE D OF F.

GLITCH

2SD_HOLD*

1SD_HOLD*

1SD_DELAY*

FD_DELAY

2SD_DELAY*

MIN

2SD_DELAY*

Figure 7. V1MON and V2MON Shutdown Timing Diagrams in Level-Sensitive Mode (Note that RESET Follows SHDN)

V2MON

V2MON is a high voltage monitoring input that controls the SHDN

and RESET functions of the external devices. V2MON monitors

inputs from 3 V to 30 V. It has a 16-level programmable turn-on

and turn-off (on, off) hysteresis thresholds (Register 0x03 and

time (t2SD_HOLD) and 0.07 ms to 1200 ms shutdown delay

(t2SD_DELAY).

The V2MON pin is monitored by two comparators, one for turn-

on and one for turn-off detection, in the level-sensitive power-

up mode. Both are designed with 1.5% hysteresis. Only the

turn-on monitoring comparator is used if the rising edge

triggered wake-up mode is selected.

When the V2MON input goes above the programmed V2MON on

threshold, the comparator becomes active immediately, indicat-

ing that an on condition has occurred. Due to hysteresis, the

V2MON input must be brought below the programmed threshold

by 1.5% before the comparator becomes inactive, indicating that

the on condition has gone away (see Figure 8).

When the V2MON input drops below the programmed threshold,

the comparator becomes active immediately, indicating that a

V2MON off condition has occurred. Similarly, due to hysteresis,

the V2MON input must be brought above the programmed threshold

by 1.5% before the comparator becomes inactive, indicating that

the off condition has gone away.

5692-008

2MON

2MON_OFF

COMPARATOR

ACTIVE

COMPARATOR

INACTIVE

OFF

COMPARATOR

ACTIVE

OFF

COMPARATOR

INACTIVE

2MON_ON

HYSTERESIS

Figure 8. V2MON Hysteresis

By default, V2MON is level sensitive and the on and off thresholds

are both monitored. The on threshold chosen must be greater

than the off threshold.

When the SHDN output is activated by the input reaching

the V2MON_OFF threshold, such fault condition is temporarily

recorded in the fault detection register. The SHDNWARN

output transitions low for signaling before the shutdown output,

SHDN, activates. The timing of the SHDN output is dependent

on how long the shutdown programmed delay (t2SD_DELAY) is set

relative to the SHDNWARN propagation delay (tFD_DELAY ). This

feature allows the system to finish any critical housekeeping

tasks before shutting down the external device. SHDN activates

once the voltage on V2MON is outside the threshold for a time longer

than tGLITCH. RESET follows SHDN delay and hold timings when

triggered by V2MON.

The V2MON, shutdown, and shutdown warning timing diagrams

are shown in Figure 7.

AD5100

Rev. A | Page 15 of 36

The ranges of on and off thresholds are shown in Table 6 and

the programming codes for the selected-thresholds are found in

Table 7. The default on threshold is 7.47 V and off threshold is

6.95 V. Similarly, the ranges of shutdown hold and delay times

are shown in Table 8, and the programming codes of the selected

timings are found in Table 9 . The default shutdown hold time is

10 ms and the delay time is 100 ms.

V2MON_OFF is ignored if V2MON_OFF is greater than V2MON_ON but

V2MON_OFF cannot equal V2MON_ON.

If V2MON is selected with rising edge triggered wake-up mode,

only the on threshold is monitored and the off threshold

is ignored. V2MON is put into rising edge triggered mode by

setting V2MON off threshold, Register 0x04[3:0] to 1001

The voltage at V1MON provides the power for the AD5100, but a

valid signal on V2MON must be present before the internal VREG

starts operating. Details are explained in the Power Requirements

section.

V2MON exhibits typical input resistance of 675 kΩ that users

should take into account for loading effect.

V3MON

V3MON is a low voltage monitoring input that controls the

RESET function of an external device.

The V3MON pin is monitored by a comparator to detect an

undervoltage condition. It is designed with 1.5% hysteresis.

When the V3MON input drops below the programmed UV

threshold, the comparator becomes active immediately, indi-

cating that a UV condition has occurred. Due to hysteresis,

the V3MON input must be brought above the programmed UV

threshold by 1.5% before the comparator becomes inactive,

indicating that the UV condition has gone away (see Figure 9).

05692-010

3MON

3MON_UV

COMPARATOR

INACTIVE

COMPARATOR

INACTIVE

HYSTERESIS

Figure 9. V3MON Hysteresis

The V3MON comparator is used (in conjunction with a hold

timer) to control the RESET pin.

V3MON monitors inputs from 2.0 V to 5.5 V. It has an 8-step

programmable reset threshold (Register 0x05) with an 8-step

0.1 ms to 200 ms reset hold time (tRS_HOLD). The reset hold time

means that the RESET output remains activate when V3MON goes

above its UV threshold, until tRS_HOLD has elapsed. This allows

the reset of an external device to be held until the programmed

time is reached.

The V3MON and RESET timing diagrams are shown in .

The range of thresholds is shown in and the programming

code for the selected threshold is found in . The range of

reset hold times is shown in and the programming code

of the selected timing is found in .

Figure 10

Table 6

Table 7

Tab le 8

Table 9

V3MON exhibits typical input resistance of 130 kΩ that users

should take into account for loading effect.

The MR input has an internal resistor pull-up toV3MON. The

RESET output is push-pull, between V3MON and GND.

05692-009

V3MON

3MON

GLITCH

RESET

NOTES

1. * = P ROGRAM M ABL E

RS_HOLD*

RS_DELAY

RS_HOLD*

RS_DELAY

Figure 10. V3MON, RESET Timing Diagrams

AD5100

Rev. A | Page 16 of 36

V4MON

V4MON is a low voltage monitoring input that controls the RESET

function of an external device or provides a comparator output,

V4OUT. The V4MON pin is monitored by a comparator to detect an

undervoltage condition. It is designed with 5% hysteresis.

When the V4MON input drops below the programmed UV thresh-

old, the comparator becomes active immediately, indicating that

a UV condition has occurred. Due to hysteresis, the V4MON input

must be brought above the programmed UV threshold by 5%

before the comparator becomes inactive, indicating that the UV

condition has gone away (see Figure 11).

5692-012

4MON

4MON_UV

COMPARATOR

INACTIVE

COMPARATOR

INACTIVE

HYSTERESIS

Figure 11. V4MON Hysteresis

The V4MON comparator is used to control the V4OUT pin and (in

conjunction with a hold timer) to control the RESET pin. To

configure V4MON to control the RESET pin, set Register 0x0D[3]

to 0. Setting this bit to 1 prevents V4MON from causing RESET to

activate. The default setting is V4MON does not cause RESET to

activate.

V4MON input voltage range is up to 30 V. It has an 8-step

programmable reset threshold (Register 0x06) from 1.67 V

to 7.96 V, with an 8-step 0.1 ms to 200 ms reset hold time

(tRS_HOLD).

The V4MON, RESET, and V4OUT timing diagrams are shown in

. The range of thresholds is shown in , and the

programming code for the selected threshold is found in .

The default monitoring threshold is 7.54 V. Similarly, the range

of reset hold time is shown in , and the programming

code of the selected timing is found in .

Figure 12 Table 6

Table 8

Table 9

V4MON exhibits typical input resistance of 675 kΩ that users

should take into account for loading effect.

WATCHDOG INPUT

The watchdog input (WDI) circuit attempts to reset the system

to a known good state if a software or hardware glitch renders

the system processor inactive for a duration that is longer than

the timeout period. The timeout period, tWD, is programmable

in eight steps from 100 ms to 2000 ms. The watchdog circuit is

independent of any CPU clock that the watchdog is monitoring.

The range of watchdog timeout is shown in Table 8, and the

programming code of the selected timeout is found in Table 9.

The default timeout is 1500 ms.

The watchdog is disabled during power-up. WDI starts monitor-

ing once RESET is high. The AD5100 provides a standard or

advanced watchdog monitoring function. Register 0x0F[3] sets

the watchdog function to either standard or advanced mode.

This bit can be fixed in OTP memory.

• Register 0x0F[3] = 0: standard watchdog mode (Default)

• Register 0x0F[3] = 1: advanced watchdog mode

4MON

4OUT

tGLITCH

RESET

NOTES

1. * = PROGRAMMABLE.

2. M OST APPLICATIO NS US ING V

4OUT

REQUIRE DISABLING OF V

4MON

TRIGGERED RE SE T.

05692-011

tRS_HOLD* tRS_HOLD*

tRS_DELAY tRS_DELAY

Figure 12. V4MON , RESET, and V4OUT Timing Diagrams

AD5100

Rev. A | Page 17 of 36

Standard Watchdog Mode

In the default standard watchdog mode, if WDI remains either

high or low for longer than the timeout period, tWD, a RESET

pulse is generated in an attempt to allow the system processor

to reestablish the WDI signal. The RESET pulses continue

indefinitely until a valid watchdog signal, a rising or falling edge

signal at the WDI, is received. The internal watchdog timer

clears whenever a reset is asserted. The standard WDI and

RESET timing diagrams are shown in . Figure 13

Advanced Watchdog Mode

The AD5100 can be programmed into an advanced watchdog

mode. In this mode, if WDI remains either high or low for longer

than the timeout period, tWD, a RESET pulse is generated, as per

standard mode. However, if the WDI input remains inactive after

three such RESET pulses, concurrent with the fourth RESET pulse,

SHDN is also asserted. SHDN is released after 1 second. These

actions repeat indefinitely (unless action is taken by the user), if

the processor is not responding. The advanced WDI and RESET

timing diagrams are shown in . Figure 14

5692-013

WDI

WDR

WDI

RESET PULSE CONTINUOUS PULSES UNTIL WATCHDOG AWAKES

RESET

WDR

= WATCHDOG-INITIATED RESET PULSE WIDTH

WDI

= WATCHDOG PULSE WI DTH

= WATCHDOG PRO GRAMMABLE T IME

Figure 13. Standard Watchdog—Pulsing Reset Until Watchdog Awakes

05692-014

WDI

WD_SHDN

WDR

3 RESET PULSES1 RESET PUL SE

SHUTDOW N AT 4T H RES E T PULSE RELEASE AFT E R 1s

WDI

RESET

SHDN

Figure 14. Advanced Watchdog—SHDN Asserted After Three Trials of Resetting the Watchdog (SHDN Released After 1 Second and the Cycle Repeats)

AD5100

Rev. A | Page 18 of 36

Floating WDI Input

If the WDI pin is floating, the watchdog function is disabled by

default. However, floating watchdog can be enabled in the RESET

configuration register such that a broken WDI connection or

any unusual condition that makes WDI float triggers the reset.

• Register 0x0D[3] = 0: floating WDI input does not activate

RESET (Default)

• Register 0x0D[3] = 1: floating WDI input activates RESET

This feature is fixed in OTP memory. Enabling or disabling the

floating WDI feature can be changed dynamically, using the

OTP overridden function is selected.

MANUAL RESET INPUT

Manual reset (MR) is an active low input to the AD5100 and

has an internal pull-up resistor to V3MON. If the input signal on

the MR pin goes low, RESET is activated. MR can be driven

from a CMOS logic signal.

The MR and RESET timing diagrams are shown in .

Note that

Figure 15

RESET is activated after tMR_DELAY and is held for

tRS_HOLD after the MR signal has gone high again.

MR has the highest priority in triggering the RESET over any

other monitoring inputs.

05692-015

MR_DELAY

MR_GLITCH

RS_HOLD*

* = PRO G RAM MABLE

RESET

Figure 15. Manual Reset (MR) Timing Diagram

AD5100

Rev. A | Page 19 of 36

OUTPUTS

SHUTDOWN OUTPUT, SHDN

The shutdown output, SHDN, is triggered by V1MON or V2MON

over- or underthreshold values, or as the result of a failed

watchdog input. SHDN can also be asserted low at any time

by writing to certain registers on the AD5100.

The shutdown generator asserts a logic low SHDN signal based

on the following conditions:

• During power-up

• When V1MON goes over or under the threshold (see Figure 7)

• When V2MON is below the turn-on threshold during the

rising edge or the turn-off threshold during the falling

edge in level-sensitive mode (see Figure 7)

• When the external monitoring processor cannot issue

the necessary WDI signal and advanced WDI mode is

selected (see Figure 10 and Figure 9)

• I2C® programmed shutdown

To act ivate SHDN by writing to the part, the user must first

enable this feature by writing to Register 0x18[4].

• Register 0x18[4] = 0: enable software control of SHDN

• Register 0x18[4] = 1: disable software control of SHDN

Once the feature is enabled, control of SHDN is achieved by

writing to Register 0x16[2].

• Register 0x16[2] = 0: SHDN output not controlled by

software

• Register 0x16[2] = 1: SHDN output is pulled low

The SHDN signal is released after the programmable hold time,

tSD_HOLD. The SHDN output is push-pull configured with an I2C-

selectable rail voltage of either V1MON in default or internal VREG.

can be fixed in OTP memory.

• Register 0x0E[3] = 0: SHDN uses V1MON rail (Default)

• Register 0x0E[3] =1: SHDN uses VREG rail

Figure 16 shows the SHDN output configuration. Pull-down

Resistor R1 ensures that SHDN is pulled to ground when the

AD5100 is not powered. When AD5100 is powered, M2a and

M2b are both on. M2a has relatively lower impedance than

M2b and R1 so the SHDN remains low at shutdown. When

the AD5100 settles, SW1 is turned on. M1 is stronger than

M2a so SHDN is pulled to the rail, which takes AD5100 out

of the shutdown mode.

In some applications, the AD5100 may monitor and control

power regulators where the input and enable pins are next to

each other in a fine pitch. This may pose reliability concerns

under some abnormal conditions. To prevent errors from happen-

ing, the AD5100 shutdown output features smart-load detection

to ensure that the shutdown responds. For example, if the car

battery has not started for a long time, a resistive dendrite may

have formed across the SHDN pin and the battery terminal

(V1MON). The dendrite is blown immediately because M2a is

designed with adequate current sinking capability and remains

in the on position to offer such protection. In another situation,

if the SHDN pin is hard-shorted to the 12 V battery, the short-

circuit detector opens SW2 and limits the current by the high

impedance M2b.

05692-016

1MON

M2A M2B

SW3

SW1

SW2 LOW-Z HIGH-Z

SHDN

# *

REG

LEVEL

SHIFTER

SHORT-CIRCUIT

DETECT

NOTES

1. # = I2C SE LECT ABLE

2. * = DEFAULT

Figure 16. Shutdown Output

RESET OUTPUT, RESET

The reset output, RESET, is triggered by V3MON or V4MON

underthreshold values. RESET activation can also be the result

of the processor not generating the proper watchdog signal, if

MR input is triggered, or if SHDN is activated.

The reset generator asserts the RESET signal based on the

following conditions:

• During power-up

• When V3MON drops below the threshold (see Figure 10)

• When V4MON drops below the threshold (see Figure 12)

• When SHDN output is asserted (see and ); Figure 7 Figure 14

RESET follows SHDN hold and delay timings if triggered by

the SHDN output

• When the external monitoring processor cannot issue the

necessary WDI signal (see Figure 13 and Figure 14)

• When MR is asserted (see ) Figure 15

RESET is active low by default, but can be configured for active

high operation. Register 0x0D[1] controls the activation

polarity of RESET. It is possible to fix the value of this bit in

OTP memory.

• Register 0x0D[1] = 0: RESET is active low (Default)

• Register 0x0D[1] = 1: RESET is active high

AD5100

Rev. A | Page 20 of 36

The RESET signal is asserted and maintained except when it is

triggered by the WDI, which is described in the

section. The

Watc hdog Input

RESET signal is released after the programmable

hold time, tRS_HOLD.

As shown in Figure 17, the RESET output is push-pull

configured with the rail voltage of V3MON.

05692-017

3MON

RESET

Figure 17. Reset Output

SHUTDOWN WARNING, SHDNWARN

An early shutdown warning is available for the system processor

to identify the source of failure and take appropriate action

before shutting down the external devices. Whenever the

voltage at V1MON is detected as overvoltage or undervoltage,

or the voltage at V2MON falls below the threshold, SHDNWARN

outputs a Logic 0. If the processor sees a logic low on this pin,

the processor may issue an I2C read command to identify the

cause of failure reported in the fault detect/status register, at

Address 0x19. The processor may store the information in

external EEPROM as a record of failure history.

V4OUT OUTPUT

V4OUT is an open-drain output triggered by V4MON with a mini-

mum propagation delay, tV4OUT_DELAY. V4OUT can be used as a PWM

control over an external device or used as a monitoring signal.

Most applications using V4OUT require disabling of the V4MON

triggered reset function. This function is disabled by writing to

OTP memory.

RESET

• Register 0x0D[2] = 1: prevents V4MON under threshold from

activating RESET

AD5100

Rev. A | Page 21 of 36

POWER REQUIREMENTS

INTERNAL POWER, VREG

The AD5100 internal power, VREG, is derived from V1MON and

becomes active when V2MON reaches 2.2 V. V2MON is used to turn

AD5100 on and off with a different behavior depending on the

V2MON monitoring mode selection.

By default, the AD5100 turns on when the voltage at V2MON rises

above the logic threshold, V2MON_ON. When V2MON falls below the

logic threshold, V2MON_OFF, AD5100 turns off 2 seconds after

SHDN is deasserted. Note that AD5100 requires 5 μs to start up

and that V1MON must be applied before V2MON. Extension of the

AD5100 turn-off allows the system to complete any housekeeping

tasks before the system is powered off. shows the

default V2MON and VREG waveforms.

Figure 18

Rising Edge Triggered Wake-Up Mode

If rising edge triggered wake-up V2MON mode is selected instead,

the AD5100 does not turn off when V2MON returns to a logic low.

To configure the part into rising edge triggered mode, set the

V2MON off threshold register, Register 0x04[3:1], to 1001.

In this mode, once the part is powered on, it can only be powered

down by an I2C power-down instruction or by removing the

supply on the V1MON pin. To power down the part over the I2C

bus while in rising edge triggered mode, the user must first

ensure that the software power down feature is enabled.

• Register 0x18[3] = 0: enable software power-down feature

• Register 0x18[3] =1: disable software power-down feature

The user must then write to Register 0x17[0], to actually power

down the AD5100.

• Register 0x17[0] = 0: AD5100 not in software power-down

• Register 0x17[0] = 1: power down AD5100

This feature is for applications that use a wake-up signal.

05692-018

2MON

2MON_ON*

2MON,IH

2SD_HOLD*

VREG_OFF_DELAY

GLITCH

2SD_DELAY*

2MON_ON*

2MON_OFF*

VREG_ON_DELAY

SHDN

REG

NOTES

1. 6V < V

1MON

< 30V

2. * = P RO GRAMMABLE

2SD_DELAY*

Figure 18. Internal Power VREG vs. V2MON Timing Diagrams (Default)

AD5100

Rev. A | Page 22 of 36

PROTECTION

For automotive applications, proper external protections on the

AD5100 are needed to ensure reliable operation. The V1MON is

likely to be used for battery monitoring. The V2MON is likely to

be used for ignition switch or other critical inputs. As a result,

these inputs may need additional protections such as EMI, load

dump, and ESD protections. In addition, battery input requires

reverse battery protection and short-circuit fuse protection (see

Figure 19).

Overcurrent Protection

If the V1MON is shorted internally in the AD5100 to GND, the

short-circuit protection kicks in and limits subsequent current

to 150 mA in normal operation.

Thermal Shutdown

When the AD5100 junction temperature is near the junction

temperature limit, it automatically shuts down and cuts out the

power from V1MON. The part resumes operation when the device

junction temperature returns to normal.

ESD Protection

It is common to require a contact rating of ±8 kV and a no

contact or air rating of ±15 kV ESD protection for the

automotive electronics. As a result, an ESD-rated protection

device must be used, such as MMBZ27VCL, a dual 40 W

transient voltage suppressor (TVS) at the V1MON and V2MON.

Load Dump Protection

A load dump is a severe overvoltage surge that occurs when the

car battery is being disconnected from a spinning alternator and

a resulting long duration, high voltage surge is introduced into

the supply line. Therefore, external load dump protection is

recommended. Typically, the load dump overvoltage lasts for a

few hundred milliseconds and peaks at around 40 V to 70 V,

while current can be as high as 1 A. As a result, a load dump-

rated TVS D1 and D2, such as SMCJ17, are used to handle the

surge energy. A series resistor is an inline current limiting

resistor; it should be adequate to limit the current without

significant drop and yet small enough to not affect the input

monitoring accuracy.

Reverse Battery Protection

Reverse battery protection can be provided by a regular diode

if the battery monitoring accuracy can be relaxed. Otherwise,

a 60 V P-channel power MOSFET, like the NDT2955, can be

used. Because of the MOSFET internal diode, the battery first

conducts through the P1 body diode as soon as the voltage reaches

its source terminal. The voltage divider provides adequate gate-

to-source voltage to turn on P1, and the voltage drop across the

FET is negligible. The resistor divider values are chosen such

that the maximum VGS of the P1 is not violated and the current

drawn through the battery is only a few microamps.

EMI Protection

For EMI protection, a ferrite bead or EMC rated inductor, such

as DR331-7-103, can be used.

05692-020

DIGIPOT

2MON

1MON

SMCJ17 MMBZ27VCL

SMCJ17

2.2Ω

VREF

REG

2MΩ

1.5MΩ

0.1µF

NDT2955

10µH

DR331-7-103

0.1µF

10µF

IGNITION SWITCH

VMAIN

+–

B+

AD5100

Figure 19. Protection Circuits

AD5100

Rev. A | Page 23 of 36

AD5100 REGISTER MAP

Table 11 outlines the AD5100 register map, used to configure

and control all parameters and functions in the AD5100, and

indicates whether registers are writable, readable, or permanently

settable. All registers have the same address for read and write

operations.

The AD5100 ships from the factory with default power-up values

set in OTP memory. These default values are different for each

AD5100 model. However, nonprogrammed samples are avail-

able for evaluation purposes. The user can experiment with

different settings in the various threshold, delay, and

configuration registers.

Once evaluation is complete, the user should contact Analog

Devices with their desired OTP memory default values. Analog

Devices will create an AD5100 model with the desired default

settings and factory program the AD5100 OTP memory with

these defaults.

Some users may use the AD5100 as a set-and-forget device, that

is, program some default values and never need to change these

over the life of the application. However, some users may require

on-the-fly flexibility, that is, the ability to change settings to

values other than those they choose as their defaults. Register

writing, reading, OTP, and override are explained in the I2C

Serial Interface section.

Table 11. AD5100 Register Map

Address

Read/

Write

Permanently

Settable Register Name and Bit Description

NonOTP Power-On

Default1

0x01 R/W Yes V1MON overvoltage threshold 0x00 (18.00 V)

Bit No. Description

[3:0] Four bits used to program V1MON OV threshold

[7:4] Reserved

0x02 R/W Yes V1MON undervoltage threshold 0x00 (8.43 V)

Bit No. Description

[3:0] Four bits used to program V1MON UV threshold

[7:4] Reserved

0x03 R/W Yes V2MON turn-on threshold 0x00 (7.47 V)

Bit No. Description

[3:0] Four bits used to program V2MON on threshold

[7:4] Reserved

0x04 R/W Yes V2MON turn-off threshold 0x00 (6.95 V)

Bit No. Description

[3:0] Four bits used to program V2MON off threshold

[7:4] Reserved

0x05 R/W Yes V3MON RESET Threshold 0x00 (2.93 V)

Bit No. Description

[2:0]

Three bits used to program V3MON RESET threshold

[7:3] Reserved

0x06 R/W Yes V4MON RESET threshold 0x00 (7.54 V)

Bit No. Description

[2:0]

Three bits used to program V4MON RESET threshold

[7:3] Reserved

0x07 R/W Yes V1MON OV/UV triggered SHDN hold (t1SD_HOLD) 0x00 (200 ms)

Bit No. Description

[2:0]

Three bits used to program V1MON OV/UV triggered SHDN hold time

[7:3] Reserved

0x08 R/W Yes V1MON OV/UV triggered SHDN delay (t1SD_DELAY) 0x00 (1200 ms)

Bit No. Description

[2:0]

Three bits used to program V1MON OV/UV triggered SHDN delay

time

[7:3] Reserved

AD5100

Rev. A | Page 24 of 36

Address

Read/

Write

Permanently

Settable Register Name and Bit Description

NonOTP Power-On

Default1

0x09 R/W Yes V2MON turn-on triggered SHDN hold (t2SD_HOLD) 0x00 (10 ms)

Bit No. Description

[2:0]

Three bits used to program V2MON tON triggered SHDN hold time

[7:3] Reserved

0x0A R/W Yes V2MON turn-off triggered SHDN delay (t2SD_DELAY) 0x00 (100 ms)

Bit No. Description

[2:0]

Three bits used to program V2MON tOFF triggered SHDN delay time

[7:3] Reserved

0x0B R/W Yes RESET hold (tRS_HOLD) 0x00 (200 ms)

Bit No. Description

[2:0]

Three bits used to program RESET hold time

[7:3] Reserved

0x0C R/W Yes Watchdog timeout (tWD) 0x00 (1500 ms)

Bit No. Description

[2:0] Three bits used to program watchdog timeout time

[7:3] Reserved

0x0D R/W Yes RESET configuration 0x00

Bit No. Description

[0]

0: RESET is active when SHDN is active

1: RESET is not active when SHDN is active

[1]

0: RESET active low

1: RESET active high

[2]

0: enables V4MON under threshold, causing RESET

1: prevents V4MON under threshold from causing RESET (for V4OUT

applications)

[3]

0: floating WDI does not activate RESET

1: floating WDI activates RESET

[7:4] Reserved

0x0E R/W Yes SHDN rail voltage configuration 0x00

Bit No. Description

[2:0] Reserved

[3]

0: SHDN rail = V1MON

1: SHDN rail = VREG

[7:4] Reserved

0x0F R/W Yes Watchdog mode 0x00

Bit No. Description

[2:0] Reserved

[3] 0: standard mode

1: advanced mode

[7:4] Reserved

0x15 R/W Yes Program lock (inhibit further programming) 0x00

Bit No. Description

[2:0] Reserved

[3] Reserved

[7:4] Reserved

AD5100

Rev. A | Page 25 of 36

Address

Read/

Write

Permanently

Settable Register Name and Bit Description

NonOTP Power-On

Default1

0x16 R/W No Special function 1 0x00

Bit No. Description

[0] Reserved

[1] Reserved

[2]

0: software assertion of SHDN pin is inactive

1: pulls SHDN pin low

[3] 0: override of permanent settings inactive

1: override of permanent settings active

[7:4] Reserved

0x17 R/W No Special function 2 0x00

Bit No. Description

[0] 0: software power-down of AD5100 inactive

1: software power-down of AD5100 active2

[7:1] Reserved

0x18 R/W No Disable special functions3 0x00

Bit No. Description

[0]

0: allows override of any of the registers in memory except

1: disables override of any of the registers in memory except

[1] Reserved

[2] Reserved

[3] 0: allows software power-down function

1: disables software power-down function

[4]

0: allows software assertion of SHDN pin

1: disables software assertion of SHDN pin

[7:5] Reserved

0x19 Read-

only

No Fault detect and status

(Bits[3:0] are level triggered bits that indicate the current state of the

comparators monitoring the V1MON and V2MON input pins; Bits[6:4] are edge

triggered fault detection bits that indicate what error conditions were present

when a SHDN event occurred)

0x40

Bit No. Description

[0] 1 = V2MON input < V2MON off threshold

[1] 1 = V2MON input > V2MON on threshold

[2] 1 = V1MON input < V1MON UV threshold

[3] 1 = V1MON input > V1MON OV threshold

[6:4] 000: none

001: V1MON UV only

010: V1MON OV only

011: never occurred

100: V2MON below off only (default)

101: V1MON UV and V2MON below off both occurred

110: V1MON OV and V2MON below off both occurred

111: never occurred

[7] Reserved

1 Default settings of AD5100-0 evaluation model only.

2 V2MON must be 0 V (that is, V2MON must be configured in edge sensitive mode) for software power-down.

3 These register bits are set only. To clear them, the AD5100 must be power cycled. In some cases, the AD5100 can be connected to an I2C bus with lots of activity.

Setting these bits is an added means of ensuring that any erroneous activity on the bus does not cause AD5100 special functions to become active.

AD5100

Rev. A | Page 26 of 36

I2C SERIAL INTERFACE

Control of the AD5100 is via an I2C-compatible serial bus. The

AD5100 is connected to this bus as a slave device (the AD5100

has no master capabilities).

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, which occurs when SDA goes from high to low

while SCL is high. The following byte is the slave address

byte, which consists of the 7-bit slave address followed by

an R/W bit that determines whether data is read from or

written to the slave device

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during

the low period of SCL and remain stable during the high

period of SCL.

3. When all data bits have been read or written, a stop

condition is established by the master. A stop condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master pulls the SDA line

high during the 10th clock pulse to establish a stop condi-

tion. In the read mode, the master issues a no acknowledge

for the ninth clock pulse (that is, the SDA line remains

high). The master then brings the SDA line low before the

10th clock pulse and high during the 10th clock pulse to

establish a stop condition.

For the AD5100, write operations contain either one or two

bytes, while read operations contain one byte. The AD5100

makes use of an address pointer register. This address pointer

sets up one of the other registers for the second byte of the write

operation or for a subsequent read operation. Table 12 shows

the structure of the address pointer register. Bits [6:0] signify

the address of the register that is to be written to or read from.

Bit 7 is a reserved bit and should be 0 for normal write/read

operations.

Table 12. Address Pointer Register Structure

Bit Number Function

7 Reserved

6 Address Bit 6

5 Address Bit 5

4 Address Bit 4

3 Address Bit 3

2 Address Bit 2

1 Address Bit 1

0 Address Bit 0 (LSB)

SCL

The serial input register clock pin shifts in one bit at a time

on positive clock edges. An external 2.2 kΩ to 10 kΩ pull-up

resistor is needed. The pull-up resistor should be tied to V3MON,

provided V3MON is sub-5 V.

SDA

The serial data input/output pin shifts in one bit at a time on

positive clock edges, with the MSB loaded first. An external

2.2 kΩ to 10 kΩ pull-up resistor is needed. The pull-up resistor

should be tied to V3MON , provided V3MON is sub-5 V.

AD0

The AD5100 has a 7-bit slave address. The six MSBs are 010111,

and the LSB is determined by the state of the AD0 pin. When the

I2C slave address pin, AD0, is low, the 7-bit AD5100 slave address

is 0101110. When AD0 is high, the 7-bit AD5100 slave address

is 0101111 (pulled up to 3.3 V maximum).

The AD0 pin allows the user to connect two AD5100 devices

to the same I2C bus . Table 1 3 and Figure 20 show an example

of two AD5100 devices operating on the same serial bus

independently.

Table 13. Slave Address Decoding Scheme

AD0 Programming Bit AD0 Device Pin Device Addressed

0 0 V 0x2E (U1)

1 3.3 V max 0x2F (U2)

05692-021

SCL

SDA

AD0

SCL

AD5100

SDA

AD0

SCL

AD5100

MASTER

3.3V MAX

Figure 20. Two AD5100 Devices on One Bus

AD5100

Rev. A | Page 27 of 36

WRITING DATA TO AD5100

When writing data to the AD5100, the user begins by writing

an address byte followed by the R/W bit set to 0. The AD5100

acknowledges (if the correct address byte is used) by pulling

the SDA line low during the ninth clock pulse. The user then

follows with two data bytes. The first data byte is the address of

the internal data register to be written to, which is stored in the

address pointer register. The second byte is the data to be written

to the internal data register. After each byte, the AD5100

acknowledges by pulling the SDA line low during the ninth

clock pulse. illustrates this operation. Figure 21

READING DATA FROM AD5100

When reading data from an AD5100 register, there are two

possibilities.

• If the AD5100 address pointer register value is unknown

or not at the desired value, it is first necessary to set it to

the correct value before data can be read from the desired

data register. This is done by performing a write to the

AD5100, but only a value containing the register address

is sent because data is not to be written to the register. This

is shown in Figure 22. A read operation is then performed

consisting of the serial bus address, R/W bit set to 1,

followed by the data byte from the data register. This is

shown in . Figure 23

• If the address pointer is known to be already at the desired

address, data can be read from the corresponding data

Table 14 shows the readback data byte structure. Bits[6:0] con-

tain the data from the register just read. Bit 7 is a reserved bit

and should be ignored for normal read operations. The majority

of AD5100 registers are four bits wide, with only the fault detect

and status register and disable special functions register at seven

bits and five bits wide, respectively.

Table 14. Readback Data Byte Structure

Bit Number Function

7 Reserved

6 D6

5 D5

4 D4

3 D3

2 D2

1 D1

0 D0 (LSB)

5692-022

SDA

FRAME 1

SLAVE ADDRESS BYTE FRAME 2

ADDRESS POINTER BY T E FRAME 3

DATA BYTE

SCL

ACK. BY

AD5100 ACK. BY

AD5100 ACK. B Y

AD5100

STOP BY

MASTER

START B Y

MASTER

01 0111AD0 R/W OTP AP6 AP5 AP4 AP3 AP2 AP1 AP0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 21. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register

5692-023

SDA

FRAME 1

SLAVE ADDRESS BYTE FRAME 2

ADDRESS POINTER BYTE

SCL

ACK. B Y

AD5100 ACK. BY

AD5100

STOP BY

MASTER

START BY

MASTER

01 0111AD0 R/W OTP AP6 AP5 AP4 AP3 AP2 AP1 AP0

Figure 22. Dummy Write to Set Proper Address Pointer

5692-024

SDA

FRAME 1

SLAVE ADDRESS BYTE FRAME 2

READ D ATA BYTE

SCL

ACK. B Y

AD5100 NO ACK. BY

MASTER

STOP BY

MASTER

START BY

MASTER

01 0111AD0 R/W OTP

OK D6 D5 D4 D3 D2 D1 D0

Figure 23. Read Data from the Address Pointer Register

AD5100

Rev. A | Page 28 of 36

TEMPORARY OVERRIDE OF DEFAULT SETTINGS

Even with OTP-Programmed parts, it is possible to temporarily

override the default values of any of the permanently program-

mable registers. To override a permanent setting in a particular

should be used:

1. Set Bit 3 = 1 in Register 0x16 (special function 1).

2. Write the desired temporary data to the register of choice.

While the override bit (Bit 3) is set in Register 0x16, the user

can override any registers by simply writing to them with new data.

To reset an overridden register to its default setting, the

following sequence should be used:

1. Set Bit 3 = 0 in Register 0x16.

2. Write a dummy byte to the register of choice.

Clearing the override bit in Register 0x16 does not cause all

overridden registers to revert to their defaults at the same time.

For example, imagine that the user overrides Register 0x01,

If the user subsequently clears the override bit in Register 0x16

and writes a dummy byte to Register 0x01, Register 0x01 reverts

to its default value. However, Register 0x02 and Register 0x03

still contain their override data. To revert both registers to their

default values, the user must write dummy data to each register

individually.

Power cycling the AD5100 also resets all registers to their

programmed defaults.

AD5100

Rev. A | Page 29 of 36

APPLICATIONS INFORMATION

CAR BATTERY AND INFOTAINMENT SYSTEM

SUPPLY MONITORING

The AD5100 has two high voltage monitoring inputs with shut-

down and reset controls over external devices. For example, the

V1MON and V2MON can be used to monitor the signals from

a car battery and an ignition key in an automobile, respectively

(see Figure 24). The shutdown output can be connected to the

shutdown pin of an external regulator to prevent false condi-

tions such as a weak battery or overcharging of a battery by an

alternator. The reset output can be used to reset the processor in

the event of a hardware or software malfunction. An example of

the input and output responses of this circuit is shown in Figure 25.

AD5100

Rev. A | Page 30 of 36

05692-025

DIGIPOT

4MON

3MON

DIGIPOT

SHDN

REG

2MON

1MON

SMCJ17 MMBZ27VCL

SMCJ17

2.2Ω

VREF

REG

EN OSC

2MΩ

1.5MΩ

0.1µF

NDT2955

10µH

DR331-7-103

0.1µF

10µF

IGNITION SWITCH

VMAIN

+–

B+

P1 OV

OFF

3MON

SHUTDOWN

CONTROLLER

AND

ADJUSTABLE

SHDN

HOLD

AND

DELAY

RESET

GENERATOR

AND

ADJUSTABLE

RESET

HOLD

DRIVER

PROGRAMMABLE

DRIVER

LOAD

DESELECT

RESET

GENERATOR

PROGRAMMABLE

WATCHDOG

OTP FUSE ARRAY

MEMORY MAP

FD REGISTER

(FAUL T DETE CTI ON)

4 TI MES

CONTROLLER

SET CONFIGURAT IONS

PROG RAM P ARAME TERS

READ STAT US

SHDN SHDNWARN

4OUT

RESET

VCC

DAC

VOUT

GND

VIN VOUT

REG2

SD GND

VIN

+3.3

+5V

REG1

VDD

DVDD

1.8V

3.3V

I/O

DSP/

MICROPROCESSOR

IN OUT

CODEC

SIGNAL

RESET

SCL

SDA

AD0

0.1µF

10µF

WDI

VOTP

3MON

DAC

AD5100

SHDN

Figure 24. Typical DSP in Car Infotainment Application

AD5100

Rev. A | Page 31 of 36

05692-026

BATTERY

IGNITION

REG

GLITCH

3.3V

WDI

HIGH-Z

+5V

BROWNOUT

RESET WDI

RESET

WDI RESET

2MON

OFF

SHUTDOWN

ENABLE

RESET

SHDN

RESET

VREG_OFF_DELAY

VREG_ON_DELAY

MICROPROCESSOR

FAILED

RESET HIGH-Z

SHUTDOWN

ENABLE

RESET

MICROPROCESSOR

FAILED

SHUTDOWN

Figure 25. Example of SHDN and RESET Responses of Circuit Shown in Figure 24

AD5100

Rev. A | Page 32 of 36

BATTERY MONITORING WITH FAN CONTROL

V4MON can be used with V4OUT in tandem to form a simple PWM

control circuit. For example, as shown in Figure 26, when a

temperature sensor output connects to the V4MON input, with

the proper threshold level set, V4OUT outputs high whenever the

temperature goes above the threshold. This turns on the FET

switch, which activates the fan. When VTEMP drops below the

threshold, V4OUT decreases, which turns off the fan.

BATTERY STATE OF CHARGE INDICATOR AND

SHUTDOWN EARLY WARNING MONITORING

In the automotive application, the system designer may set the

battery threshold to the lowest level to allow an automobile to

start at the worst-case condition. If the battery remains at the

low voltage level, it is indeed a poor battery. However, there is

no way to warn the driver. As a result, the system designer can

use V4OUT as the battery warning indicator. By stepping down

the battery voltage monitored at V4MON, the LED is lit, which

gives a battery replacement warning. The circuit is shown in

Figure 28.

05692-027

AD5100

V2MON

V3MON

V4MON

WDI

SDA

SCL

V1MON

V4OUT

SHDNWARN

SHDN

RESET

WDI

BATTERY

IGNITION

VREG

VTEMP

WDI

CLK

VREG

BATTERY

MICROPROCESSOR

CLK MISO/MOSI

TMP35

VTEMP

Figure 26. Power Amp Monitoring and Fan Control

05692-028

TEMP

4OUT

NOTES

1. V

4MON

RESET DIS ABLED.

4MON

THRESHOLD

Figure 27. V4OUT with Respect to VTEMP, with V4MON RESET Disabled in Circuit Shown in Figure 26

05692-029

AD5100

4MON

SDA

SCL

4OUT

SHDNWARN

SHDN

1MON

BATTERY

2MON

IGNITION

CLK

MICROPROCESSOR

CLK MISO/MOSI

Figure 28. Battery State of Charge Indication

AD5100

Rev. A | Page 33 of 36

RISING EDGE TRIGGERED WAKE-UP MODE

As indicated in Figure 29, the microprocessor can control its

own power-down sequence using the rising edge triggered

wake-up signal. The operator must select the rising edge

triggered wake-up mode setting for the V2MON turn-off

threshold value, as shown in Tabl e 6, by setting Register

0x04[3:1] = 1001.

When the rising edge wake-up signal is detected by V2MON,

the AD5100 is powered up with the SHDN pin pulled high.

The external regulator is turned on to supply power to the

microprocessor. A reset pulse train is generated at the reset

output if there is no watchdog activity. The pulse continues

until the correct watchdog signal appears at the AD5100 WDI

pin. The shutdown pin remains high as long as the AD5100

continues to receive the correct watchdog signal.

When the microprocessor finishes its housekeeping tasks or

powers down the software routine, it stops sending a watchdog

signal. In response, the AD5100 generates a reset. The shut-

down pin is pulled low 2 seconds after, and the regulator output

drops to 0 V, which shuts down the microprocessor. At that

point, the AD5100 enters sleep mode.

AD5100

Rev. A | Page 34 of 36

05692-030

AD5100

2MON

WDI

SDA

SCL

1MON

SHDN

RESET

BATTERY

CAN WAKE

UP PULSE(S)

REG

MICROPROCESSOR

I/O

Figure 29. Rising Edge Triggered Wake-Up Mode

05692-031

SCL

NOTES

1. 6V <

1MON

< 30V.

. SELECT

2MON

OFF

= RI SING EDGE TRIGGE R/CAN WAKE UP M ODE.

SDA W RITE

2MON

WDI

SCL

SDA

RESET

SHDN

Figure 30. Rising Edge Triggered Operation of Circuit Shown in Figure 29

AD5100

Rev. A | Page 35 of 36

OUTLINE DIMENSIONS

COMPLIANT TO JE DE C S TANDARDS MO-137 - AB

012808-A

CONTROL LI NG DIM E NSIO NS ARE IN INCHES; M IL L IMETERS DIMENS IONS

(I N PARENT HE S E S ) ARE ROUNDED-OFF I NCH EQUI VALENTS FO R

REFE RE NCE ONLYAND ARE NOT APPROP RIATE FOR USE IN DESIGN.

16 9

SEATING

PLANE

0.010 (0.25)

0.004 (0.10)

0.012 (0.30)

0.008 (0.20)

0.025 (0.64)

BSC

0.041 (1.04)

REF

0.010 (0.25)

0.006 (0.15)

0.050 (1.27)

0.016 (0.41)

0.020 (0.51)

0.010 (0.25)

8°

0°

COPLANARITY

0.004 (0.10)

0.065 (1.65)

0.049 (1.25) 0.069 (1.75)

0.053 (1.35)

0.197 (5.00)

0.193 (4.90)

0.189 (4.80)

0.158 (4.01)

0.154 (3.91)

0.150 (3.81) 0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

Figure 31. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches

ORDERING GUIDE

Model1, 2 Temperature Range Package Description Package Option Ordering Quantity

AD5100YRQZ-0 −40°C to +125°C 16-Lead QSOP RQ-16

AD5100YRQZ-1RL7 −40°C to +125°C 16-Lead QSOP RQ-16 1,000

AD5100YRQZ-1REEL −40°C to +125°C 16-Lead QSOP RQ-16 2,500

EVAL-AD5100EBZ Evaluation Board

1 Z = RoHS Compliant Part.

2AD5100YRQZ-0 = Non-OTP programmed part, intended for evaluation purposes only.

AUTOMOTIVE PRODUCTS

The AD5100 models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

AD5100

Rev. A | Page 36 of 36

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D05692-0-6/10(A)