Order Number: 313272-06
November 2007
Numonyx™ Wireless Flash Memory (W18)
with AD Multiplexed IO
Datasheet
Product Features
High Performance Read-While-Write/Erase
— Burst frequency at 66 MHz
— 60 ns Initial Access Read Speed
— 11 ns Burst-Mode Read Speed
— 20 ns Page-Mode Read Speed
— 4-, 8-, 16-, and Continuous-Word Burst
Mode Reads
— Burst and Page Mode Reads in all Blocks,
across all partition boundaries
— Burst Suspend Feature
— Enhanced Factory Programming at
3.1 µs/word (typ. for 0.13 µm)
Architecture
— Multiple 4 Mbit Partitions
— Dual Operation: Read-while-Write and
Read-while-Erase
— 8 KB parameter blocks
—64KB main blocks
— Top or Bottom Parameter Configurations
— 16 bit wide data bus
— Multiplexed Address data bus
Power
—V
CC = 1.70 V to 1.95 V
—V
CCQ = 1.70 V to 2.24 V or 1.35 V to 1.80 V
— Standby current (0.13 µm): 8 µA (typ.)
— Read current: 7 mA (typ.)
Security
— 128 bit Protection Register
— 64 Unique Bits Programmed by Numonyx
— 64 User-Programmable Bits
— Absolute Write Protection with VPP at
Ground
— Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
Capability
Software
— 5 µs (typ.) Program and Erase Suspend
Latency Time
— Numonyx™ Flash Data Integrator
(Numonyx™ FDI) and Common Flash
Interface Compatible
— Programmable WAIT Signal Polarity
Quality and Reliability
—Temperature Range: –40 °C to +85 °C
— 100k Erase Cycles per Block
— 130 nm ETOX™ VIII Process
— 90 nm ETOX™ IX Process
—
Density and Package Ballout
— 130 nm: 32-, 64-, and 128-Mbit
— 90 nm: 32-, 64-Mbit
— 44-ball VF BGA
— 88-ball QUAD+
Datasheet November 2007
2Order Number: 313272-06
Legal L ines and Disclaim ers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Numonyx B.V., All Rights Reserved.
November 2007 Datasheet
Order Number: 313272-06 3
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Contents
1.0 Introduction .............................................................................................................. 6
1.1 Document Purpose .............................................................................................. 6
1.2 Nomenclature ..................................................................................................... 6
1.3 Conventions ....................................................................................................... 6
2.0 Functional Overview..................................................................................................8
2.1 Memory Map and Partitioning ................................................................................ 9
3.0 Package Information ............................................................................................... 12
4.0 Ballout and Signal Descriptions ............................................................................... 14
4.1 Ballouts ........................................................................................................... 14
4.2 Signal Descriptions ............................................................................................ 15
5.0 Maximum Ratings and Operating Conditions............................................................ 20
5.1 Absolute Maximum Ratings................................................................................. 20
5.2 Operating Conditions ......................................................................................... 20
6.0 Electrical Specifications ........................................................................................... 21
6.1 DC Current Characteristics.................................................................................. 21
6.2 DC Voltage Characteristics.................................................................................. 22
7.0 AC Characteristics ................................................................................................... 24
7.1 AC I/O Test Conditions....................................................................................... 24
7.2 Device Capacitance ........................................................................................... 24
7.3 AC Read Characteristics, AD-Mux ........................................................................ 25
7.4 AC Write Characteristics, AD-Mux ........................................................................ 32
7.5 Program and Erase Characteristics....................................................................... 34
7.6 Reset Specifications........................................................................................... 35
8.0 Power and Reset Specifications ............................................................................... 37
8.1 Active Power..................................................................................................... 37
8.2 Automatic Power Savings ................................................................................... 37
8.3 Standby Power.................................................................................................. 37
8.4 Power-Up/Down Characteristics........................................................................... 37
8.4.1 System Reset and RST#.......................................................................... 37
8.4.2 VCC, VPP, and RST# Transitions............................................................... 38
8.5 Power Supply Decoupling ................................................................................... 38
9.0 Device Operations ................................................................................................... 39
9.1 Bus Operations ................................................................................................. 39
9.1.1 Read .................................................................................................... 39
9.1.2 Burst Suspend ....................................................................................... 40
9.1.3 Standby ................................................................................................ 40
9.1.4 Reset.................................................................................................... 40
9.1.5 Write .................................................................................................... 41
9.2 Device Commands............................................................................................. 41
9.3 Command Sequencing ....................................................................................... 44
10.0 Read Operations ...................................................................................................... 45
10.1 Read Array ....................................................................................................... 45
10.2 Read Device ID ................................................................................................. 45
10.3 Read Query (CFI) .............................................................................................. 46
10.4 Read Status Register ......................................................................................... 46
10.5 Clear Status Register ......................................................................................... 47
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
4Order Number: 313272-06
11.0 Program Operations .................................................................................................48
11.1 Word Program ...................................................................................................48
11.2 Factory Programming .........................................................................................49
11.3 Enhanced Factory Program (EFP) .........................................................................50
11.3.1 EFP Requirements and Considerations .......................................................50
11.3.2 Setup....................................................................................................51
11.3.3 Program ................................................................................................51
11.3.4 Verify....................................................................................................51
11.3.5 Exit.......................................................................................................52
12.0 Program and Erase Operations.................................................................................53
12.1 Program/Erase Suspend and Resume ...................................................................53
12.2 Block Erase.......................................................................................................55
12.3 Read-While-Write and Read-While-Erase...............................................................57
13.0 Security Modes ........................................................................................................59
13.1 Block Lock Operations ........................................................................................59
13.1.1 Lock......................................................................................................60
13.1.2 Unlock...................................................................................................60
13.1.3 Lock-Down ............................................................................................60
13.1.4 Block Lock Status ...................................................................................61
13.1.5 Lock During Erase Suspend......................................................................61
13.1.6 Status Register Error Checking .................................................................61
13.1.7 WP# Lock-Down Control ..........................................................................62
13.2 Protection Register.............................................................................................62
13.2.1 Reading the Protection Register ................................................................63
13.2.2 Programing the Protection Register ...........................................................63
13.2.3 Locking the Protection Register.................................................................63
13.3 VPP Protection ...................................................................................................65
14.0 Set Configuration Register .......................................................................................66
14.1 Read Mode (CR[15]) ..........................................................................................67
14.2 First Access Latency Count (CR[13:11])................................................................67
14.2.1 Latency Count Settings............................................................................68
14.3 WAIT Signal Polarity (CR[10]) .............................................................................68
14.4 WAIT Signal Function .........................................................................................68
14.5 Data Hold (CR[9])..............................................................................................69
14.6 WAIT Delay (CR[8]) ...........................................................................................70
14.7 Burst Sequence (CR[7])......................................................................................70
14.8 Clock Edge (CR[6]) ............................................................................................71
14.9 Burst Wrap (CR[3])............................................................................................71
14.10 Burst Length (CR[2:0]).......................................................................................72
15.0 Write State Machine States ......................................................................................73
16.0 Common Flash Interface ..........................................................................................76
16.1 Query Structure Output ......................................................................................76
16.2 Query Structure Overview...................................................................................77
16.3 Block Status Register .........................................................................................77
16.4 CFI Query Identification String ............................................................................78
16.5 Device Geometry Definition.................................................................................80
16.6 Numonyx-Specific Extended Query Table ..............................................................81
A Ordering Information...............................................................................................87
November 2007 Datasheet
Order Number: 313272-06 5
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Revision History
Date Revision Description
June 2006 001 Initial Release.
July 2006 002 Made minor formatting changes.
December 2006 003
Changed Burst Frequency from 54 MHz to 66 MHz and Burst Mode Read speed from 14 ns to 11 ns
per specification improvements.
Removed 80 ns and extended voltage range (1.35-1.8) I/O specifications because feature is no
longer supported.
Added the 44 Ball VF BGA package and ballouts and line items.
February 2007 004 Updated ordering information: HR28F320W18BE
August 2007 005 Updated ordering information.
November 2007 06 Applied Numonyx branding.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
6Order Number: 313272-06
1.0 Introduction
The Numonyx™ Wireless Flash Memory device provides high-performance
asynchronous and synchronous burst reads, ideal for low-voltage burst CPUs.
Combining high read performance with flash memory’s intrinsic non-volatility, the W18
device reduces the total memory requirement while increasing reliability and reducing
overall system power consumption and cost. Its flexible, multi-partition architecture
allows programming or erasing to occur in one partition while reading from another
partition, providing higher data write throughput compared to single partition
architectures. The dual-operation architecture also allows two processors to interleave
code operations while program and erase operations take place in the background. The
designer can also choose the size of the code and data partitions via the flexible multi-
partition architecture.
1.1 Document Purpose
This datasheet contains information about the Numonyx™ Wireless Flash Memory
(W18) with AD Multiplexed IO device family.
1.2 Nomenclature
Many acronyms that describe product features or usage are defined as follows:
1.3 Conventions
The following abbreviated terms and phrases are used throughout this document:
APS Automatic Power Savings
BBA Block Base Address
CFI Common Flash Interface
CUI Command User Interface
EFP Enhanced Factory Programming
FDI Flash Data Integrator
NC No Connect
OTP One-Time Programmable
PBA Partition Base Address
RWE Read-While-Erase
RWW Read-While-Write
SCSP Quad ballout
SRD Status Register Data
WSM Write State Machine
1.8 V Refers to the full VCC voltage range of 1.7 V – 1.95 V (except where noted) and “VPP = 12
V” refers to 12 V ±5%.
Set
Clear
When referring to registers, the term set means the bit is a logical 1, and clear means the
bit is a logical 0.
Pin
Signal
The terms pin and signal are often used interchangeably to refer to the external signal
connections on the package. (ball is the term used for SCSP).
Word 2 bytes or 16 bits.
Signal Names All CAPS
November 2007 Datasheet
Order Number: 313272-06 7
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Voltage Voltage applied to the signal is subscripted, for example, VPP
.
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify these references, the
following conventions have been adopted:
Block A group of bits (or words) that erase simultaneously with one block erase instruction.
Main block Contains 32 Kwords.
Parameter Block Contains 4 Kwords.
Block Base Address (BBA) The first address of a block.
Partition A group of blocks that share erase and program circuitry and a common status register.
Partition Base Address (PBA) The first address of a partition. For example, on a 32-Mbit top-parameter device,
partition number 5 has a PBA of 140000h.
Top Partition Located at the highest physical device address. This partition may be a main partition or
a parameter partition.
Bottom Partition Located at the lowest physical device address. This partition may be a main partition or a
parameter partition.
Main Partition Contains only the main blocks.
Parameter Partition Contains a mixture of main blocks and parameter blocks.
Top Parameter Device (TPD) TPD has the parameter partition at the top of the memory map with the parameter blocks
at the top of that partition. This was formerly referred to as top-boot flash device.
Bottom Parameter Device (BPD)
BPD has the parameter partition at the bottom of the memory map with the parameter
blocks at the bottom of that partition. This was formerly referred to as bottom-boot flash
device.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
8Order Number: 313272-06
2.0 Functional Overview
This section provides an overview of the Numonyx™ Wireless Flash Memory (W18) with
AD Multiplexed IO device features, packaging, signal naming, and device architecture.
The W18 device provides Read-While-Write (RWW) and Read-While-Erase (RWE)
capability with high-performance synchronous and asynchronous reads on package-
compatible densities with a 16-bit data bus. Individually-erasable memory blocks are
optimally sized for code and data storage. Eight 4-Kword parameter blocks are located
in the parameter partition at either the top or bottom of the memory map. The rest of
the memory array is grouped into 32-Kword main blocks.
The memory architecture for the W18 device consists of multiple 4 Mbit partitions, the
exact number depending on device density. By dividing the memory array into
partitions, program or erase operations can take place simultaneously during read
operations. Burst reads can traverse partition boundaries, but the user application code
is responsible for ensuring that they do not extend into a partition that is actively
programming or erasing. Although each partition has burst read, write, and erase
capabilities, simultaneous operation is limited to write or erase in one partition while
other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this
device. An erase can be suspended to perform a program or read operation within any
block, except that which is erase-suspended. A program operation nested within a
suspended erase can subsequently be suspended to read yet another memory location.
After device power-up or reset, the W18 device defaults to asynchronous read
configuration. Writing to the device’s configuration register enables synchronous burst-
mode read operation. In synchronous mode, the CLK input increments an internal burst
address generator. CLK also synchronizes the flash memory with the host CPU and
outputs data on every, or on every other, valid CLK cycle after an initial latency. A
programmable WAIT output signals to the CPU when data from the flash memory
device is ready.
In addition to its improved architecture and interface, the W18 device incorporates
Enhanced Factory Programming (EFP), a feature that enables fast programming and
low-power designs. The EFP feature provides the fastest currently-available program
performance, which can increase a factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at
1.8 V or 12 V. With the 1.8 V option, VCC and VPP can be tied together for a simple,
ultra-low-power design. In addition to voltage flexibility, the dedicated VPP input
provides complete data protection when VPP ≤ VPPLK.
A 128-bit protection register enhances the user’s ability to implement new security
techniques and data protection schemes. Unique flash device identification and fraud-,
cloning-, or content- protection schemes are possible through a combination of factory-
programmed and user-OTP data cells. Zero-latency locking/unlocking on any memory
block provides instant and complete protection for critical system code and data. An
additional block lock-down capability provides hardware protection where software
commands alone cannot change the block’s protection status.
The W18 device Command User Interface (CUI) is the system processor’s link to
internal flash memory operation. A valid command sequence written to the CUI initiates
device Write State Machine (WSM) operation that automatically executes the
algorithms, timings, and verifications necessary to manage flash memory program and
erase. An internal status register provides ready/busy indication results of the
operation (success, fail, and so on).
November 2007 Datasheet
Order Number: 313272-06 9
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Three power-saving features, Automatic Power Savings (APS), standby, and RST#, can
significantly reduce power consumption. The device automatically enters APS mode
following read cycle completion. Standby mode begins when the system deselects the
flash memory by de-asserting CE#. Driving RST# low produces power savings similar
to standby mode. It also resets the part to read-array mode (important for system-
level reset), clears internal status registers, and provides an additional level of flash
write protection.
2.1 Memory Map and Partitioning
The W18 device is divided into 4-Mbit physical partitions, which allows simultaneous
RWW or RWE operations and allows users to segment code and data areas on 4 Mbit
boundaries. The device’s memory array is asymmetrically blocked, which enables
system code and data integration within a single flash device. Each block can be erased
independently in block erase mode. Simultaneous program and erase operations are
not allowed; only one partition at a time can be actively programming or erasing. See
Table 1, “Bottom Parameter Memory Map” on page 10 and Table 2, “To p Pa rame ter
Memory Map” on page 11.
The 32-Mbit device has eight partitions; the 64-Mbit device has 16 partitions, and the
128-Mbit device has 32 partitions. Each device density contains one parameter
partition and several main partitions. The 4-Mbit parameter partition contains eight
4-Kword parameter blocks and seven 32-Kword main blocks. Each 4-Mbit main
partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and
parameter blocks that allow storage of frequently updated small parameters that are
normally stored in EEPROM. By using software techniques, the word-rewrite
functionality of EEPROMs can be emulated.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
10 Order Number: 313272-06
.
Table 1: Bottom Parameter Memory Map
Size
(KW) Blk # 32 Mbit Blk # 64 Mbit Blk # 128 Mbit
Main Partitions
Sixteen
Partitions
32 262 7F8000-7FFFFF
..
..
..
32 135 400000-407FFF
Eight
Partitions
32 134 3F8000-3FFFFF 134 3F8000-3FFFFF
..
..
..
..
..
32 71 200000-207FFF 71 200000-207FFF
Four
Partitions
32 70 1F8000-1FFFFF 70 1F8000-1FFFFF 70 1F8000-1FFFFF
..
..
..
..
..
..
..
32 39 100000-107FFF 39 100000-107FFF 39 100000-107FFF
One
Partition
32 38 0F8000-0FFFFF 38 0F8000-0FFFFF 38 0F8000-0FFFFF
..
..
..
..
..
..
..
32 31 0C0000-0C7FFF 31 0C0000-0C7FFF 31 0C0000-0C7FFF
One
Partition
32 30 0B8000-0BFFFF 30 0B8000-0BFFFF 30 0B8000-0BFFFF
..
..
..
..
..
..
..
32 23 080000-087FFF 23 080000-087FFF 23 080000-087FFF
One
Partition
32 22 078000-07FFFF 22 078000-07FFFF 22 078000-07FFFF
..
..
..
..
..
..
..
32 15 040000-047FFF 15 040000-047FFF 15 040000-047FFF
Parameter Partition
One Partition
32 14 038000-03FFFF 14 038000-03FFFF 14 038000-03FFFF
..
..
..
..
..
..
..
32 8 008000-00FFFF 8 008000-00FFFF 8 008000-00FFFF
4 7 007000-007FFF 7 007000-007FFF 7 007000-007FFF
..
..
..
..
..
..
..
4 0 000000-000FFF 0 000000-000FFF 0 000000-000FFF
128 Mbit is not available at 90 nm.
November 2007 Datasheet
Order Number: 313272-06 11
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Table 2: Top Parameter Memory Map
Size
(KW) Blk # 32 Mbit Blk # 64 Mbit Blk # 128 Mbit
Parameter
Partition
One Partition
4 70 1FF000-1FFFFF 134 3FF000-3FFFFF 262 7FF000-7FFFFF
..
..
..
..
..
..
..
4 63 1F8000-1F8FFF 127 3F8000-3F8FFF 255 7F8000-7F8FFF
32 62 1F0000-1F7FFF 126 3F0000-3F7FFF 254 7F0000-7F7FFF
..
..
..
..
..
..
..
32 56 1C0000-1C7FFF 120 3C0000-3C7FFF 248 7C0000-7C7FFF
Main Partitions
One
Partition
32 55 1B8000-1BFFFF 119 3B8000-3BFFFF 247 7B8000-7BFFFF
..
..
..
..
..
..
..
32 48 18000-187FFF 112 380000-387FFF 240 780000-787FFF
One
Partition
32 47 178000-17FFFF 111 378000-37FFFF 239 778000-77FFFF
..
..
..
..
..
..
..
32 40 140000-147FFF 104 340000-347FFF 232 740000-747FFF
One
Partition
32 39 138000-13FFFF 103 338000-33FFFF 231 738000-73FFFF
..
..
..
..
..
..
..
32 32 100000-107FFF 96 300000-307FFF 224 700000-707FFF
Four
Partitions
32 31 0F8000-0FFFFF 95 2F8000-2FFFFF 223 6F8000-6FFFFF
..
..
..
..
..
..
..
32 0 000000-007FFF 64 200000-207FFF 192 600000-607FFF
Eight
Partitions
32 63 1F8000-1FFFFF 191 5F8000-5FFFFF
..
..
..
..
..
32 0 000000-007FFF 128 400000-407FFF
Sixteen
Partitions
32 127 3F8000-3FFFFF
..
..
..
32 0 000000-007FFF
Note: 128 Mbit is not available at 90 nm.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
12 Order Number: 313272-06
3.0 Package Information
•Figure 1, ”88-ball QUAD+ Ballout (8x10x1.2 mm) Package and Dimensions”
•Figure 2, ”44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package” and
Table 3, “44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package
Dimensions”
Figure 1: 88-ball QUAD+ Ballout (8x10x1.2 mm) Package and Dimensions
Millimeters Inches
Dimen s ions S ymbol M in N om Max Notes M in N om M ax
Pa ckag e H eight A 1.200 0.0472
Ball H eig h t A 1 0.200 0.0079
Pa ckag e Body T hickne ss A 2 0.860 0.03 39
Ball (Lead ) W id th b 0.325 0.375 0.425 0.0128 0.01 48 0.0167
Pa ckag e B o d y Len g th D 9.900 10.000 10.1 00 0.3898 0.39 37 0.3976
Pa ckag e Bo d y W idth E 7.900 8.000 8.100 0.3110 0.31 50 0.3189
Pitch e 0.800 0.03 15
Ba ll (Le ad ) C o u n t N 88 88
Se ating Plane Coplanarity Y 0.100 0.0039
Co rne r to B all A 1 Dis tan ce A long E S1 1.100 1.200 1.300 0.0433 0.04 72 0.0512
Co rne r to Ball A 1 Distance A lon
g
D S2 0.500 0.600 0.700 0.0197 0.02 36 0.0276
Top View - Ball D own Bottom View - Ball
Up
A
A2
D
E
Y
A1
Draw ing not to scale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1 Index
Mark
12 345 678
November 2007 Datasheet
Order Number: 313272-06 13
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Figure 2: 44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package
E
Sea ti ng
Plan e
Bottom View - Ball Side Up
Y
A
A1
D
A2
Top View - Plastic Backside
Pin 1
Corner
Su pport
Solder
Balls
S
1
S2
e
b
Pin 1
Co rn er
1235678941011121314123 5678941011121314
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
Note: Drawing not to Scale
Table 3: 44-Ball (40 Active) VF BGA Ballout (7.7x6.2x1.0 mm) Package Dimensions
Symbol Min Nom Max Min Nom Max
Package Height A - - 1.000 - - 0.0394
Ball Height A1 0.150 - - 0.0059 - -
Package Body Thickness A2 - 0.665 - - 0.0262 -
Ball (Lead) Width b 0.259 0.309 0.359 0.0102 0.0122 0.0141
Package Body Width D 7.600 7.700 7.800 0.2992 0.3031 0.3071
Package Body Length E 6.100 6.200 6.300 0.2402 0.2441 0.2480
Pitch [e] - 0.500 - - 0.0197 -
Ball Coun t N - 44 - - 44 -
Seating Plane Coplanarity Y - - 0.080 - - 0.0031
Corner to Ball A1 Distance Along D S1 0.500 0.600 0.700 0.0197 0.0236 0.0276
Corner to Ball A1 Distance Along E S2 1.250 1.350 1.450 0.0492 0.0531 0.0571
Millimeters Inches
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
14 Order Number: 313272-06
4.0 Ballout and Signal Descriptions
4.1 Ballouts
•Figure 3, ”QUAD+ Ballout”
•Figure 4, ”40-Ball VF BGA Ballout”
Figure 3: QUAD+ Ballout
Pin 1
12345678
ADU DU DU DU A
BA4 A18 A19 VSS F1-VCC F2-VCC A21 A11 B
CA5 R-LB# A23 VSS S-CS2 CLK A22 A12 C
DA3 A17 A24 F-VPP R-WE# P1-CS# A9 A13 D
EA2 A7 A25 F-WP# ADV# A20 A10 A15 E
FA1 A6 R-UB# F-RST# F-WE# A8 A14 A16 F
GA0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G
HR-OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H
JS-CS1# F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J
KF1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode# /
P-CRE K
LVSS VSS VCCQ F1-VCC VSS VSS VSS VSS L
MDU DU DU DU M
12345678
Legend:
Top View - Ball Side Down
Active Signals
De-Populated Balls
Do Not Use
November 2007 Datasheet
Order Number: 313272-06 15
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
4.2 Signal Descriptions
•Table 4, “Signal Descriptions, QUAD+ Ballout”
•Table 5, “Signal Descriptions”
Figure 4: 40-Ball VF BGA Ballout
VCCQ
VSS
A/DQ15
A21
A16
A/DQ7
A/DQ14
VSS
A20
A/DQ6
VSSQ
CLK
ADV#
A/DQ13
A/DQ5
VCC
NC
A/DQ12
A/DQ4
WE#
RST#
A/DQ3
A/DQ11
VPP
WP#
A/DQ2
A/DQ10
A19
A18
A/DQ9
VCCQ
A17
CE#
A/DQ8
A/DQ1
NC
VSSQ
OE#
A/DQ0
WAIT
A
B
C
D
64-Mbit
32-M bit
12345678910
VCCQ
VSS
A/DQ15
A21
A16
A/DQ7
A/DQ14
VSS
A20
A/DQ6
VSSQ
CLK
ADV#
A/DQ13
A/DQ5
VCC
NC
A/DQ12
A/DQ4
WE#
RST#
A/DQ3
A/DQ11
VPP
WP#
A/DQ2
A/DQ10
A19
A18
A/DQ9
VCCQ
A17
CE#
A/DQ8
A/DQ1
NC
VSSQ
OE#
A/DQ0
WAIT
64-Mbit
32-M bit
Bottom View — Ball side U
p
Top View — Ball side Down
10987654321
D
C
B
A
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
16 Order Number: 313272-06
Table 4: Signal Descriptions, QUAD+ Ballout (Sheet 1 of 3)
Symbol Type Signal Descriptions Notes
Address and Data Signals, A/D-Mux
A[MAX:16] Input
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
• 128-Mbit: AMAX = A22
• 64-Mbit: AMAX = A21
• 32-Mbit: AMAX = A20
• A0 is the lowest-order word address.
• Unused address inputs should be treated as RFU.
A/DQ[15:0] Input /
Output
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: A/D-Mux I/O flash signals.
During A/D-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-
data output. During A/D-Mux Write cycles, DQ[15:0] are used to input the lower address
followed by commands or data.
• DQ[15:0] are High-Z when the device is deselected or its output is disabled.
• DQ[15:0] is only used with A/D-Mux I/O flash device.
1
Control Signals
ADV# Input
ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.
• During a synchronous flash Read operation, the address is latched on the rising edge of
ADV# or the first active CLK edge whichever occurs first. In an asynchronous flash Read
operation, the address is latched on the rising edge of ADV# or continuously flows through
while ADV# is low.
• During synchronous PSRAM read and synchronous write modes, the address is either
latched on the first rising clock edge after ADV# assertion or on the rising edge of ADV#
whichever edge comes first. In asynchronous read and asynchronous write modes, ADV#
can be used to latch the address, but can be held low for the entire operation as well.
Note: During A/D-Mux I/O operation, ADV# must remain deasserted during the data phase.
F[3:1]-CE# Input
FLASH CHIP ENABLE: Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the
associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT
outputs are placed in a High-Z state.
• F1-CE# is dedicated to flash die #1.
• F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise,
any unused flash chip enable should be treated as RFU.
CLK Input
CLOCK: Flash- and Synchronous PSRAM-specific input signal.
CLK synchronizes the flash and/or synchronous PSRAM with the system clock during
synchronous operations.
F[2:1]-OE# Input
FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.
When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE#
disables the output drivers of the selected flash die and places the output drivers in High-Z.
• F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is
highly recommended to always common F1-OE# and F2-OE# on the PCB.
R-OE# Input
RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE#
disables the output drivers of the selected memory die and places the output drivers in High-Z.
If device not present, treat as RFU.
2
F-RST# Input
FLASH RESET: Flash-specific signal; low-true input.
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
November 2007 Datasheet
Order Number: 313272-06 17
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
WAIT Output
WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output.
When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid
output data.
• WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output
enable is low.
• WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output
enable is high.
F-WE# Input
FLASH WRITE ENABLE: Flash-specific signal; low-true input.
When low, F-WE# enables Write operations for the enabled flash die. Address and data are
latched on the rising edge of F-WE#.
R-WE# Input
RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-WE# enables Write operations for the selected memory die. Data is latched on
the
rising edge of R-WE#. If device not present, treat as RFU.
2
F-WP# Input
FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-
Down function, enabling locked-down blocks to be unlocked with the Unlock command.
• F-WP1# is dedicated to flash die #1.
• F-WP2# is common to all other flash dies, if present. Otherwise it is an RFU.
P-CRE Input
PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input.
When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control
Register (P-BCR). When low, P-CRE enables normal Read or Write operations. If PSRAM not
present, treat as RFU.
3
P-MODE# Input
PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input.
When low, P-MODE# enables access to the configuration register, and to enter or exit Low-
Power mode. When high, P-MODE# enables normal Read or Write operations. If PSRAM not
present, treat as RFU.
3
P[2:1]-CS# Input
PSRAM CHIP SELECT: PSRAM-specific signal; low-true input.
When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the
associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT
outputs are placed in a High-Z state.
• P1-CS# is dedicated to PSRAM die #1. If PSRAM not present, treat as RFU.
• P2-CS# is dedicated to PSRAM die #2. If PSRAM not present, treat as RFU.
S-CS1#
S-CS2 Input
SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input.
When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or
S-CS2 is deasserted, the SRAM die is deselected.
• S-CS1# and S-CS2 are dedicated to SRAM when present. If SRAM not present, treat as
RFU.
2
R-UB#
R-LB# Input
RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs.
When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read
and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0]. If device not
present, treat as RFU./
2
Power Signals
F-VPP Power FLASH PROGRAM/ERASE VOLTAGE: Flash specific.
F-VPP supplies program or erase power to the flash die.
F[2:1]-VCC Power
FLASH CORE POWER SUPPLY: Flash specific.
F[2:1]-VCC supplies the core power to the flash die.
F2-VCC is recommended to be tied to F1-VCC, else it is an RFU.
VCCQ Power I/O POWER SUPPLY: Global device I/O power.
VCCQ supplies the device input/output driver voltage.
P-VCC Power PSRAM CORE POWER SUPPLY: PSRAM specific.
P-VCC supplies the core power to the PSRAM die. If PSRAM not present, treat as RFU. 2
S-VCC Power SRAM POWER SUPPLY: SRAM specific.
S-VCC supplies the core power to the SRAM die. If SRAM not present, treat as RFU. 2
Table 4: Signal Descriptions, QUAD+ Ballout (Sheet 2 of 3)
Symbol Type Signal Descriptions Notes
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
18 Order Number: 313272-06
Notes:
1. Only used when A/D-Mux I/O flash is present.
2. Only available on stacked device combinations with PSRAM, and/or SRAM die. Otherwise treated as RFU.
3. P-CRE and P-MODE# share the same package ball at location K8. Only one signal function is available, depending on the
stacked device combination.
VSS Groun
d
DEVICE GROUND: Global ground reference for all signals and power supplies.
Connect all VSS balls to system ground. Do not float any VSS connections.
DU —
DO NOT USE:
This ball should not be connected to any power supplies, signals, or other balls. This ball can
be left floating.
RFU —
RESERVED for FUTURE USE:
Reserved by Numonyx for future device functionality and enhancement. This ball must be left
floating.
Table 4: Signal Descriptions, QUAD+ Ballout (Sheet 3 of 3)
Symbol Type Signal Descriptions Notes
Table 5: Signal Descriptions
Symbol Type Name and Function
A[21:16] Input ADDRESS INPUTS: for memory addresses. 32 Mbit: A[20:16]; 64 Mbit: A[21:16].
A/D[15:0] Input/
Output
ADDRESS/DATA INPUT/OUTPUTS:
• Multiplexed address/data pins act as address inputs while ADV# is low.
• Addresses are internally latched when ADV# goes high; these signals then become data inputs/
outputs.
ADV# Input
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous read
operations, all addresses are latched on the ADV# rising edge or on the CLK rising (or falling) edge,
whichever occurs first.
CE# Input
CHIP ENABLE:
• CE#-low activates internal control logic, I/O buffers, decoders, and sense amps.
• CE#-high deselects the device, places it in standby state, and places data and WAIT outputs at
High-Z.
CLK Input
CLOCK: CLK synchronizes the device to the bus frequency in synchronous-read configuration, and
increments an internal burst address generator. During synchronous read operations, addresses are
latched on the ADV# rising edge or on the CLK rising (or falling) edge, whichever occurs first.
OE# Input OUTPUT ENABLE: Active low OE# enables the device’s output data buffers during a read cycle. With OE#
at VIH, the device data outputs are placed in a High-Z state.
RST# Input
RESET: When low, RST# resets internal automation and inhibits write operations. This reset provides data
protection during power transitions. De-asserting RST# enables normal operation and places the flash
device in asynchronous read array mode.
WAIT Output
WAIT: The WAIT signal indicates valid data during synchronous read modes. This signal can be configured
to be active-high or active-low based on bit 10 of the Configuration Register. WAIT is tristated if CE# is de-
asserted. WAIT is not gated by OE#.
WE# Input WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the WE#
rising edge.
WP# Input
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See Section
13.1, “Block Lock Operations” on page 59 for details about block locking.
VPP Power
Erase and Program Power: A valid voltage on this pin allows erase or programming. Memory contents
cannot be altered when VPP < VPPLK. Do not attempt block erase and program operations at invalid VPP
voltages.
Set VPP = VCC for in-circuit program and erase operations. To accommodate resistor or diode drops, the
VIH level of VPP can be as low as VPP1 (min). VPP must remain above VPP1 min to perform in-circuit flash
array modification. VPP can be 0 V during read operations.
VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles
maximum. VPP can be connected to VPP2 for a cumulative total not to exceed 80 hours maximum.
Extended use of this pin at VPP2 might reduce block cycling capability.
November 2007 Datasheet
Order Number: 313272-06 19
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
VCC Power Device Power Supply: Writes are inhibited at VCC < VLKO. Do not attempt flash device operations at
invalid VCC voltages.
VCCQ Power Output Power Supply: Enables all outputs to be driven at VCCQ. This input can be tied directly to VCC.
VSS Power Ground: Pins for all internal device circuitry; must be connected to ground.
VSSQ Power Output Ground: Provides ground to all outputs which are driven by VCCQ. This signal can be tied directly
to VSS.
DU — Do Not Use: Do not use this pin. Do not connect this pin to any power supplies, signals, or other pins.
This pin must be floated.
Table 5: Signal Descriptions
Symbol Type Name and Function
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
20 Order Number: 313272-06
5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only.
5.2 Operating Conditions
Warning: Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability.
Table 6: Absolute Maximum Ratings
Parameter Maximum Rating Notes
Temperature under Bias –40 °C to +85 °C —
Storage Temperature –65 °C to +125 °C —
Voltage on Any Pin (except VCC, VCCQ, VPP) –0.5 V to +2.45 V —
VPP Voltage –0.2 V to +14 V 1,2,3
VCC and VCCQ Voltage –0.2 V to +2.45 V 1
Output Short Circuit Current 100 mA 4
Notes:
1. All specified voltages are relative to VSS. Minimum DC voltage is –0.5 V on input/output pins and
–0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods < 20 ns which, during
transitions, may overshoot to VCC +2.0 V for periods < 20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. VPP program voltage is normally VPP1. VPP can be 12 V ± 0.6 V for 1000 cycles on the main blocks and 2500 cycles on
the parameter blocks during program/erase.
4. Output shorted for no more than one second. No more than one output shorted at a time.
Table 7: Extended Temperature Operation
Symbol Parameter1Min Nom Max Unit Notes
TAOperating Temperature –40 25 85 °C —
VCC VCC Supply Voltage 1.7 1.8 1.95 V 2
VCCQ I/O Supply Voltage 1.7 1.8 2.24 V 2
VPP1 VPP Voltage Supply (Logic Level) 0.90 1.80 1.95 V 1
VPP2 Factory Programming VPP 11.4 12.0 12.6 V 1
tPPH Maximum VPP Hours VPP = 12 V — — 80 Hours 1
Block
Erase
Cycles
Main and Parameter Blocks VPP ≤ VCC 100,000 — —
Cycles
1
Main Blocks VPP = 12 V — — 1000 1
Parameter Blocks VPP = 12 V — — 2500 1
Notes:
1. VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for extended temperatures
and 2500 cycles on parameter blocks at extended temperature.
2. Contact your Numonyx field representative for VCC/VCCQ operations down to 1.65 V.
November 2007 Datasheet
Order Number: 313272-06 21
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
6.0 Electrical Specifications
6.1 DC Current Characteristics
Note: Specifications are for 130 nm and 90 nm devices unless otherwise stated; the 128 Mbit
density is supported ONLY on 90 nm.
Table 8: DC Current Characteristics (Sheet 1 of 2)
Symbol Parameter (1)
VCCQ= 1.8 V
Unit Test Condition Note32/64-Mbit 128-Mbit
TypMaxTypMax
ILI Input Load — ±1 — ±1 µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
8
ILO
Output
Leakage D[15:0] — ±1 — ±1 µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
—
130 nm
ICCS VCC Standby
850870
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCC
RST# =VCCQ
9
90 nm
ICCS
22 50
130 nm
ICCAPS APS
850870
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VSSQ
RST# =VCCQ
All other inputs =VCCQ or VSSQ
10
90 nm
ICCAPS
22 50
ICCR
Average
VCC Read
Asynchronous
Page Mode
f=13 MHz
3647mA4 Word Read 3
Synchronous CLK
= 40 MHz
6 13 6 13 mA Burst length = 4
3
8 14 8 14 mA Burst length = 8
10 18 11 19 mA Burst length =16
11 20 11 20 mA Burst length = Continuous
Synchronous CLK
= 54 MHz
7 16 7 16 mA Burst length = 4
3
10 18 10 18 mA Burst length = 8
12 22 12 22 mA Burst length = 16
13 25 13 25 mA Burst length = Continuous
ICCR
Average
VCC Read
Synchronous CLK
= 66 MHz
8 17 — — mA Burst length = 4
3, 4
11 20 — — mA Burst length = 8
14 25 — — mA Burst length = 16
16 30 — — mA Burst length = Continuous
ICCW VCC Program
18 40 18 40 mA VPP = VPP1, Program in Progress
4,5,6
815815mA
VPP = VPP2, Program in Progress
ICCE VCC Block Erase
18 40 18 40 mA VPP = VPP1, Block Erase in
Progress
4,5,6
815815mA
VPP = VPP2, Block Erase in
Progress
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
22 Order Number: 313272-06
6.2 DC Voltage Characteristics
Note: Specifications are for 130 nm and 90 nm devices unless otherwise stated.
130nm
ICCWS VCC Program Suspend
850525µA
CE# = VCC, Program Suspended
7
90nm
ICCWS
22 50 µA
130nm
ICCES VCC Erase Suspend
850525µA
CE# = VCC, Erase Suspended
7
90nm
ICCWS
22 50 µA
IPPS
(IPPWS,
IPPES)
VPP Standby
VPP Program Suspend
VPP Erase Suspend
0.2 5 0.2 5 µA VPP <VCC 4
IPPR VPP Read 215215µA
VPP ≤ VCC —
IPPW VPP Program
0.05 0.10 0.05 0.10
mA
VPP = VPP1, Program in Progress
5
8 221637 V
PP = VPP2, Program in Progress
IPPE VPP Erase
0.05 0.10 0.05 0.10
mA
VPP = VPP1, Erase in Progress
5
822822 V
PP = VPP2, Erase in Progress
Notes:
1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25° C.
2. VCCQ = 1.35 V - 1.8V is available on 130 nm products only.
3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ specification
for details.
4. Sampled, not 100% tested.
5. VCC read + program current is the sum of VCC read and VCC program currents.
6. VCC read + erase current is the sum of VCC read and VCC erase currents.
7. ICCES is specified with device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.
8. If VIN>VCC the input load current increases to 10 µA max.
9. ICCS is the average current measured over any 5 ms time interval 5 μs after a CE# de-assertion.
10. Refer to section Section 8.2, “Automatic Power Savings” on page 37 for ICCAPS measurement details.
Table 9: DC Voltage Characteristics (Sheet 1 of 2)
Sym Parameter (1)
VCCQ= 1.8 V
Unit Test Condition Notes32/64 Mbit 128 Mbit
Min Max Min Max
VIL Input Low 00.400.4V — 3
VIH Input High VCCQ – 0.4 VCCQ VCCQ – 0.4 VCCQ V——
VOL Output Low
—0.1—0.1V
VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
—
VOH Output High
VCCQ – 0.1 — VCCQ – 0.1 — V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
—
Table 8: DC Current Characteristics (Sheet 2 of 2)
Symbol Parameter (1)
VCCQ= 1.8 V
Unit Test Condition Note32/64-Mbit 128-Mbit
TypMaxTypMax
November 2007 Datasheet
Order Number: 313272-06 23
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
VPPLK VPP Lock-Out —0.4—0.4V
—
2
VLKO VCC Lock 1.0 — 1.0 — V —
VILKOQ VCCQ Lock 0.9 — 0.9 — V —
Note:
1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25 °C
2. VPP <= VPPLK inhibits erase and program operations. Don’t use VPPL and VPPH outside their valid ranges.
3. VIL can undershoot to –0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less.
Table 9: DC Voltage Characteristics (Sheet 2 of 2)
Sym Parameter (1)
VCCQ= 1.8 V
Unit Test Condition Notes32/64 Mbit 128 Mbit
Min Max Min Max
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
24 Order Number: 313272-06
7.0 AC Characteristics
7.1 AC I/O Test Conditions
Note: Input timing begins, and output timing ends, at VCCQ/2.
7.2 Device Capacitance
Figure 5: AC Input/Output Reference Waveform
Figure 6: Transient Equivalent Testing Load Circuit
Table 10: Test Configuration Component Values
Test Configuration CL (pF) R1 (kΩ)R
2 (kΩ)
VCCQMin (1.7 V) Standard Test 30 16.7 16.7
Note: CL includes jig capacitance.
Figure 7: Clock Input AC Waveform
Symbol Parameter§Typ Max Unit Condition
CIN Input Capacitance 6 8 pF VIN = 0.0 V
COUT Output Capacitance 8 12 pF VOUT = 0.0 V
CCE CE# Input Capacitance 10 12 pF VIN = 0.0 V
§TA = +25 °C; f = 1 MHz; Sampled, not 100% tested.
V
CCQ
0V
V
CCQ
/2 V
CCQ
/2
Test Points
Input Outpu
t
Device
Under Test
V
CCQ
C
L
R
2
R
1
Ou
t
CLK [C]
V
IH
V
IL
R203R202
R201
November 2007 Datasheet
Order Number: 313272-06 25
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
7.3 AC Read Characteristics, AD-Mux
For timing measurements and maximum allowable slew rate, see Figure 5, “AC Input/
Output Reference Waveform” on page 24. AC specifications assume the data bus
voltage is less than or equal to VCCQ when a read operation is initiated.
Note: Specifications are for 130 nm and 90 nm devices unless otherwise stated.
Table 11: AC Read Characteristics, AD-Mux (Sheet 1 of 2)
# Sym Parameter (1,2)
60 ns
Unit Notes
Min Max
Asynchronous Specifications
R1 tAVAV Read Cycle Time 60 — ns 5
R2 tAVQV Address to Output Delay — 60 ns 5
R3 tELQV CE# Low to Output Delay — 60 ns 5
R4 tGLQV OE# Low to Output Delay — 20 ns 2
R5 tPHQV RST# High to Output Delay — 150 ns —
R6 tELQX CE# Low to Output in Low-Z 0 — ns 3
R7 tGLQX OE# Low to Output in Low-Z 0 — ns 2,3
R8 tEHQZ CE# High to Output in High-Z — 14 ns 3
R9 tGHQZ OE# High to Output in High-Z — 14 ns 2,3
R10 tOH CE# (OE#) High to Output in Low-Z 0 — ns 2,3
Latching Specifications
R101 tAVVH Address Setup to ADV# High 7 — ns —
R102 tELVH CE# Low to ADV# High 10 — ns —
R103 tVLQV ADV# Low to Output Delay — 60 ns 5
R104 tVLVH ADV# Pulse Width Low 7 — ns —
R105 tVHVL ADV# Pulse Width High 7 — ns —
R106 tVHAX Address Hold from ADV# High 7 — ns 1
R107 tVHGL ADV# High to OE# Low 7 — ns —
Note:
1. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first.
2. OE# may be delayed by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV
.
3. Sampled, not 100% tested.
4. Applies only to subsequent synchronous reads.
5. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data bus
as early as the first clock edge after tAVQV.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
26 Order Number: 313272-06
Clock Specifications
R200 fCLK CLK Frequency — 66 MHz —
R201 tCLK CLK Period 15 ns —
R202 tCH/L CLK High or Low Time 3.5 ns —
R203 tCHCL CLK Fall or Rise Time — 3 ns —
Synchronous Specifications
R301 tAVCH Address Valid Setup to CLK 7 — ns —
R302 tVLCH ADV# Low Setup to CLK 7 — ns —
R303 tELCH CE# Low Setup to CLK 7 — ns —
R304 tCHQV CLK to Output Valid 11 ns —
R305 tCHQX Output Hold from CLK 3 — ns —
R306 tCHAX Address Hold from CLK 7 — ns 1
R307 tCHTV CLK to WAIT Valid — 11 ns —
R308 tELTV CE# Low to WAIT Valid — 11 ns 4
R309 tEHTZ CE# High to WAIT High-Z — 11 ns 3,4
R310 tEHEL CE# Pulse Width High 14 — ns 4
Table 11: AC Read Characteristics, AD-Mux (Sheet 2 of 2)
# Sym Parameter (1,2)
60 ns
Unit Notes
Min Max
Note:
1. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first.
2. OE# may be delayed by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV
.
3. Sampled, not 100% tested.
4. Applies only to subsequent synchronous reads.
5. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data bus
as early as the first clock edge after tAVQV.
November 2007 Datasheet
Order Number: 313272-06 27
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
.
Note: WAIT signal asserted low [CR.10 = 0]. WAIT signal shown de-asserted.
Figure 8: Single Word Asynchronous Read, AD-Mux
Valid
Address
Valid
Address
V
IH
V
IL
V
IH/OH
V
IL/OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
ADV# [V]
CE# [E]
OE# [G]
WE# [W]
RST# [P]
Valid
Output
R101
R105 R106
R107
R103
R3
R5
R4
R10
R8
High Z
R2
R1
R9
R104
R102 R7
V
OH
V
OL
High Z
WAIT [T]
High Z
Note 1
A/DQ[15:0] [A/Q]
A[MAX:16] [A]
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
28 Order Number: 313272-06
Notes:
1. Section 14.2, “First Access Latency Count (CR[13:11])” on page 67 describes how to insert clock cycles
during the initial access.
2. This waveform only illustrates the case in which an x-word burst is initiated to the Main Array and it is terminated by a
CE# de-assertion after the first word in the burst. If this access had been done to Status, ID, or Query Space, the active-
low WAIT signal would have remained de-asserted (high) as long as CE# is asserted (low).
Figure 9: Single Word Synchronous Array Read, AD-Mux
Note 1
Val id
Address
Val id
Address
Valid
Output
High Z High Z
V
IH
V
IL
V
IH
V
IL
V
IH/OH
V
IL/OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
R306R301 R304
R105
R101
R2
R107
R103
R106
R8
R3
R4
R10
R9
V
IH
V
IL
R5
WE# [W]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
CLK [C]
RST# [P]
R104
R302
R102
R303
R305
R7
High Z High Z
R308 R309
Note 2
A/DQ[15:0] [A/Q]
A[MAX:16] [A]
November 2007 Datasheet
Order Number: 313272-06 29
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Notes:
1. Section 14.2, “First Access Latency Count (CR[13:11])” on page 67 describes how to insert clock cycles
during the initial access.
2. WAIT (shown asserted low) can be configured to assert either during or one data cycle before valid data.
Figure 10: Synchronous Four-Word Burst Read, AD-Mux
Note 1
Valid
Addre ss
Valid
Addre ss
Valid
Output
Valid
Output
Valid
Output
Valid
Output
High Z
V
IH
V
IL
V
IH
V
IL
V
IH/OH
V
IL/OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
R301 R306
R105
R101
R2
R107
R106
R304
R103
R3
R4
R305
R10
R8
ADV# [V]
CE# [E]
OE# [G]
WE# [W]
WAIT [T]
CLK [C]
V
IH
V
IL
RST# [P]
R5
R7R104
R302
R102
R303
R9
Note 2
R307
High Z
R308
R309
High Z
High Z
R310
A/DQ[15:0] [A/Q]
A[MAX:16] [A]
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
30 Order Number: 313272-06
Notes:
1. Section 14.2, “First Access Latency Count (CR[13:11])” on page 67 describes how to insert clock cycles
during the initial access.
2. WAIT (shown asserted low) can be configured to assert either during or one data cycle before valid data.
Figure 11: WAIT Functionality for EOWL (End of Word Line) Condition, AD-Mux
Valid
Add14
Valid
Data14
Vali d
Data15
Valid
Data16
Valid
Data 17
High Z Vali d
Data18
Valid
Data19
R8
R9
R10
R106
R305R306
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
R105
R3
R5
R101
R103
R102
R107
R301
R302
R2
R7
High Z
A/DQ[15:0] [A/Q]
RST# [P]
WAIT [T]
WE# [W]
OE# [G]
CE# [E]
ADV# [V]
CLK [C]
R304
R104
R4
R303
R308
R310
R310
R309
November 2007 Datasheet
Order Number: 313272-06 31
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Notes:
1. Section 14.2, “First Access Latency Count (CR[13:11])” on page 67 describes how to insert clock cycles
during the initial access.
2. WAIT signal asserted low [CR.10 = 0]. WAIT signal shown de-asserted.
Figure 12: WAIT Signal in Synchronous Non-Read Array, AD-Mux
Note 1
Valid
Address
Valid
Address
Valid
Output
High Z High Z
V
IH
V
IL
V
IH
V
IL
V
IH/OH
V
IL/OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
R306R301 R304
R105
R101
R2
R107
R103
R106
R8
R3
R4
R10
R9
V
IH
V
IL
High Z
R5
A/DQ[15:0] [A/Q]
WAIT [T]
ADV# [V]
CE# [E]
OE# [G]
WE# [W]
A[MAX:16] [A]
CLK [C]
RST# [P]
R307
R308
Note 2
R104
R302
R102
R303
R305
R7
R309
R310
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
32 Order Number: 313272-06
Note:
1. During burst suspend, CLK can be held high or low.
7.4 AC Write Characteristics, AD-Mux
Write timing characteristics during an Erase Suspend operation are the same as during
Write-Only operations. A Write operation can be terminated with either CE# or WE#.
Note: Specifications are for 130 nm and 90 nm devices unless otherwise stated.
Figure 13: Burst Suspend Waveform, AD-Mux
Note 1
A
Q0 Q1 Q1 Q2
R12
R4R9
R106
R101
R105R105
R304R304
CLK [C]
A
/DQ [A/DQ]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
WE# [W]
Table 12: AC Write Characteristics, AD-Mux (Sheet 1 of 2)
# Sym Parameter (1,2)
60 ns
Unit Notes
Min Max
W1 tPHWL
(tPHEL)RST# High Recovery to WE# (CE#) Low 150 — ns 1
W2 tELWL
(tWLEL)CE# (WE#) Setup to WE# (CE#) Low 0 — ns —
W3 tWLWH
(tELEH)WE# (CE#) Write Pulse Width Low 40 — ns 2
W4 tDVWH
(tDVEH)Data Setup to WE# (CE#) High 40 — ns —
W5 tAVWH
(tAVEH)Address Setup to WE# (CE#) High 40 — ns —
Notes:
1. Sampled, not 100% tested.
2. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
3. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
(whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.
4. tWHQV is tAVQV + 50 ns. Designers should take this into account and may insert a software No-Op instruction to delay
the first read after issuing a command.
5. For non-resume commands.
6. VPP should be held at VPP1 or VPP2 until block erase or word program success is determined.
7. Applicable during asynchronous reads following a write.
8. tWHCV and tWHVH refer to the address latching event during a synchronous read. Either tWHCV or tWHVH, whichever comes
first, must be met.
November 2007 Datasheet
Order Number: 313272-06 33
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
W6 tWHEH
(tEHWH)CE# (WE#) Hold from WE# (CE#) High 0 — ns —
W7 tWHDX
(tEHDX)Data Hold from WE# (CE#) High 0 — ns —
W8 tWHAX
(tEHAX)Address Hold from WE# (CE#) High 0 — ns —
W9 tWHWL
(tEHEL)WE# (CE#) Pulse Width High 20 — ns 3,4,5
W10 tVPWH
(tVPEH)VPP Setup to WE# (CE#) High 200 — ns 1
W11 tQVVL VPP Hold from Valid SRD 0 — ns 1, 5
W12 tQVBL WP# Hold from Valid SRD 0 — ns 1, 6
W13 tBHWH
(tBHEH)WP# Setup to WE# (CE#) High 200 — ns 1
W14 tWHGL
(tEHGL)Write Recovery before Read 0 — ns —
W15 tVHWH ADV# Setup to WE# High N/A — ns —
W16 tWHQV WE# High to Valid Data tAVQV +20 — ns 4
W18 tWHAV WE# High to Address Valid 0 — ns 7
W19 tWHCV WE# High to CLK Valid 12 — ns 8
W20 tWHVH WE# High to ADV# High 12 — ns 8
Table 12: AC Write Characteristics, AD-Mux (Sheet 2 of 2)
# Sym Parameter (1,2)
60 ns
Unit Notes
Min Max
Notes:
1. Sampled, not 100% tested.
2. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
3. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
(whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.
4. tWHQV is tAVQV + 50 ns. Designers should take this into account and may insert a software No-Op instruction to delay
the first read after issuing a command.
5. For non-resume commands.
6. VPP should be held at VPP1 or VPP2 until block erase or word program success is determined.
7. Applicable during asynchronous reads following a write.
8. tWHCV and tWHVH refer to the address latching event during a synchronous read. Either tWHCV or tWHVH, whichever comes
first, must be met.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
34 Order Number: 313272-06
Notes:
1. VCC power-up and standby.
2. Write Program or Erase Setup command.
3. Write valid address and data (for program) or Erase Confirm command.
4. Automated program/erase delay.
5. Read status register data (SRD) to determine program/erase operation completion.
6. OE# and CE# must be asserted and WE# de-asserted for read operations.
7. CLK is ignored (but may be kept active/toggling).
7.5 Program and Erase Characteristics
Unless noted otherwise, all Erase and Progrm parameters are measured at TA = +25 °C
and nominal voltages, and they are sampled, not 100% tested. Some EFP performance
degradation may occur if block cycling exceeds 10 attempts.
Note: Specifications are for 130 nm and 90 nm devices unless otherwise stated.
Figure 14: Write Operations Waveform, AD-Mux
A/DQ[15:0] [A/Q]
ADV# [V]
CE# [E]
OE# [G]
WE# [W]
RST# [P]
V
PP
[V]
V
PPH
V
PPLK
V
IL
WP# [B]
A[MAX:16] [A]
Note 1 Note 2 Note 3 Note 4 Note 5
Valid
Address
Valid
Address
Valid
Address
Data In Valid
Data
Data In
Valid
Address
Valid
Address
Valid
Address
Note 6
V
IH
V
IL
V
IH/OH
V
IL/OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
R105
R101
W2
R106
W5
W7
W6
W9
W1 W3
W13
W10
W14
W16
W12
W11
W4
R104 W20
W18
W19
CLK [C]
V
IH
V
IL
November 2007 Datasheet
Order Number: 313272-06 35
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
7.6 Reset Specifications
Note: Specifications are for 130 nm and 90 nm devices unless otherwise stated.
Table 13: Erase and Program Times
Operation Symbol Parameter Description
VPP1 VPP2
Unit Notes
TypMaxTypMax
Erasing and Suspending
Erase Time
W500 tERS/PB 4-Kword Parameter Block 0.3 2.5 0.25 2.5 s 1,2
W501 tERS/MB 32-Kword Main Block 0.7 4 0.4 4 s 1,2
Suspend
Latency
W600 tSUSP/P Program Suspend 5 10 5 10 µs 1
W601 tSUSP/E Erase Suspend 5 20 5 20 µs 1
Programming
Program Time
W200 tPROG/W Single Word 12 150 8 130 µs 1
W201 tPROG/PB 4-Kword Parameter Block 0.05 0.23 0.03 0.07 s 1,2
W202 tPROG/MB 32-Kword Main Block 0.4 1.8 0.24 0.6 s 1,2
Enhanced Factory Programming
Program
W400 tEFP/W Single Word N/A N/A 3.1 16 µs 3
W401 tEFP/PB 4-Kword Parameter Block N/A — 15 — ms 1,2
W402 tEFP/MB 32-Kword Main Block N/A — 120 — ms 1,2
Operation
Latency
W403 tEFP/SETUP EFP Setup — N/A — 5 µs —
W404 tEFP/TRAN
Program to Verify
Tra nsi tio n N/A N/A 2.7 5.6 µs —
W405 tEFP/VERIFY Verify N/A N/A 1.7 130 µs —
Notes:
1. Excludes external system-level overhead.
2. Exact results may vary based on system overhead.
3. W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming
within a new word-line.
Table 14: Reset Specifications
# Symbol Parameter Notes Min Max Unit
P1 tPLPH RST# Low to Reset during Read 1, 2, 3, 4 100 — ns
P2 tPLRH
RST# Low to Reset during Block Erase 1, 3, 4, 5 — 20 µs
RST# Low to Reset during Program 1, 3, 4, 5 — 10 µs
P3 tVCCPH VCC Power Valid to Reset 1,3,4,5,6 60 — µs
Notes:
1. These specifications are valid for all product versions (packages and speeds).
2. The device may reset if tPLPH< tPLPHMin, but this is not guaranteed.
3. Not applicable if RST# is tied to VCC.
4. Sampled, but not 100% tested.
5. If RST# is tied to VCC, the device is not ready until tVCCPH occurs after when VCC ≥ VCCMin.
6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC ≥
VCCMin.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
36 Order Number: 313272-06
Figure 15: Reset Operations Waveforms
(
A) Reset during
read mode
(B) Reset during
program or block erase
P1
≤
P2
(C) Reset during
program or block erase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
VCC
(D) VCC Power-up to
RST# high
P1 R5
P2
P3
P2 R5
R5
November 2007 Datasheet
Order Number: 313272-06 37
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
8.0 Power and Reset Specifications
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO devices have a
layered approach to power savings that can significantly reduce overall system power
consumption. The APS feature reduces power consumption when the device is selected
but idle. If CE# is deasserted, the memory enters its standby mode, where current
consumption is even lower. Asserting RST# provides current savings similar to standby
mode. The combination of these features can minimize memory power consumption,
and therefore, overall system power consumption.
8.1 Active Power
With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to Section 6.1,
“DC Current Characteristics” on page 21, for ICC values. When the device is in “active”
state, it consumes the most power from the system. Minimizing device active current
therefore reduces system power consumption, especially in battery-powered
applications.
8.2 Automatic Power Savings
Automatic Power Saving (APS) provides low-power operation during a read’s active
state. During APS mode, ICCAPS is the average current measured over any 5 ms time
interval 5 µs after the following events happen:
• There is no internal sense activity;
• CE# is asserted;
• The address lines are quiescent, and at VSSQ or VCCQ.
OE# may be asserted during APS.
8.3 Standby Power
With CE# at VIH and the device in read mode, the flash memory is in standby mode,
which disables most device circuitry and substantially reduces power consumption.
Outputs are placed in a high-impedance state independent of the OE# signal state. If
CE# transitions to VIH during erase or program operations, the device continues the
operation and consumes corresponding active power until the operation is complete.
ICCS is the average current measured over any 5 ms time interval 5 µs after a CE# de-
assertion.
8.4 Power-Up/Down Characteristics
The device is protected against accidental block erasure or programming during power
transitions. Power supply sequencing is not required if VCC, VCCQ, and VPP are
connected together; so it doesn’t matter whether VPP or VCC powers-up first. If VCCQ
and/or VPP are not connected to the system supply, then VCC should attain VCCMIN
before applying VCCQ and VPP. Device inputs should not be driven before supply
voltage = VCCMIN. Power supply transitions should only occur when RST# is low.
8.4.1 System Reset and RST#
The use of RST# during system reset is important with automated program/erase
devices because the system expects to read from the flash memory when it comes out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
38 Order Number: 313272-06
will not occur because the flash memory may be providing status information instead of
array data. To allow proper CPU/flash initialization at system reset, connect RST# to
the system CPU RESET# signal.
System designers must guard against spurious writes when VCC voltages are above
VLKO. Because both WE# and CE# must be low for a command write, driving either
signal to VIH inhibits writes to the device. The CUI architecture provides additional
protection because alteration of memory contents can only occur after successful
completion of the two-step command sequences. The device is also disabled until RST#
is brought to VIH, regardless of its control input states. By holding the device in reset
(RST# connected to system PowerGood) during power-up/down, invalid bus conditions
during power-up can be masked, providing yet another level of memory protection.
8.4.2 VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Read-array mode is its power-up default state after exit
from reset mode or after VCC transitions above VLKO (Lockout voltage).
After completing program or block erase operations (even after VPP transitions below
VPPLK), the Read Array command must reset the CUI to read-array mode if flash
memory array access is desired.
8.5 Power Supply Decoupling
When the W18 device is accessed, many internal conditions change. Circuits are
enabled to charge pumps and switch voltages. This internal activity produces transient
noise. To minimize the effect of this transient noise, device decoupling capacitors are
required. Transient current magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling capacitor selection
suppresses these transient voltage peaks. Each flash device should have a 0.1 µF
ceramic capacitor connected between each power (VCC, VCCQ, VPP), and ground (VSS,
VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as close
as possible to package signals.
November 2007 Datasheet
Order Number: 313272-06 39
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
9.0 Device Operations
This section provides an overview of device operations. The Numonyx™ Wireless Flash
Memory (W18) with AD Multiplexed IO family includes an on-chip WSM to manage
block erase and program algorithms. Its CUI allows minimal processor overhead with
RAM-like interface timings.
9.1 Bus Operations
9.1.1 Read
The W18 device has several read configurations:
• Asynchronous page mode read.
• Synchronous burst mode read — outputs four, eight, sixteen, or continuous words,
from main blocks and parameter blocks.
Several read modes are available in each partition:
•Read-array mode: read accesses return flash array data from the addressed
locations.
•Read identifier mode: reads return manufacturer and device identifier data,
block lock status, and protection register data. Identifier information can be
accessed starting at 4-Mbit partition base addresses; the flash array is not
accessible in read identifier mode.
•Read query mode: reads return device CFI data. CFI information can be accessed
starting at 4-Mbit partition base addresses; the flash array is not accessible in read
query mode.
•Read status register mode: reads return status register data from the addressed
partition. That partition’s array data is not accessible. A system processor can
check the status register to determine an addressed partition’s state or monitor
program and erase progress.
All partitions support the synchronous burst mode that internally sequences addresses
with respect to the input CLK to select and supply data to the outputs.
Identifier codes, query data, and status register read operations execute as single-
synchronous or asynchronous read cycles. WAIT is asserted during these reads.
Table 15: Bus Operations
Mode RST# CE# OE# WE# ADV# WAIT DQ[15:0] Notes
Reset VIL XXXX High-ZHigh-Z1,2
Write VIH VIL VIH VIL VIL Asserted DIN 3
Read VIH VIL VIL VIH VIL Active DOUT 4
Output Disable VIH VIL VIH VIH X Asserted High-Z 1
Standby VIH VIH X X X High-Z High-Z 1
Notes:
1. X = Don’t Care (VIL or VIH).
2. RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current.
3. Refer to the Table 17, “Bus Cycle Definitions” on page 43 for valid DIN during a write operation.
4. WAIT is only valid during synchronous array read operations.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
40 Order Number: 313272-06
Access to the modes listed above is independent of VPP
. An appropriate CUI command
places the device in a read mode. At initial power-up or after reset, the device defaults
to asynchronous read-array mode.
Asserting CE# enables device read operations. The device internally decodes upper
address inputs to determine which partition is accessed. Asserting ADV# opens the
internal address latches. Asserting OE# activates the outputs and gates selected data
onto the I/O bus. In asynchronous mode, the address is latched when ADV# is
deasserted (when the device is configured to use ADV#). In synchronous mode, the
address is latched by either the rising edge of ADV# or the rising (or falling) CLK edge
while ADV# remains asserted, whichever occurs first. WE# and RST# must be at
deasserted during read operations.
Note: If only asynchronous reads are to be performed in your system, CLK should be tied to a
valid VIH level, WAIT signal can be floated and ADV# must be tied to ground.
9.1.2 Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous
burst operation if the system needs to use the flash address and data bus for other
purposes. Burst accesses can be suspended during the initial latency (before data is
received) or after the device has output data. When a burst access is suspended,
internal array sensing continues and any previously latched internal data is retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched
(either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK
can be halted when it is at VIH or VIL. To resume the burst access, OE# is reasserted
and CLK is restarted. Subsequent CLK edges resume the burst sequence where it left
off.
Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT remains
asserted and does not revert to a high-impedance state when OE# is deasserted. This
can cause contention with another device attempting to control the system’s READY
signal during a Burst Suspend. System using the Burst Suspend feature should not
connect the device’s WAIT signal directly to the system’s READY signal. Refer to
Figure 13, “Burst Suspend Waveform, AD-Mux” on page 32.
9.1.3 Standby
De-asserting CE# deselects the device and places it in standby mode, substantially
reducing device power consumption. In standby mode, outputs are placed in a high-
impedance state independent of OE#. If deselected during a program or erase
algorithm, the device shall consume active power until the program or erase operation
completes.
9.1.4 Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal
circuitry is turned off and outputs are placed in a high-impedance state.
After returning from reset, a time tPHQV is required until outputs are valid, and a delay
(tPHWV) is required before a write sequence can be initiated. After this wake-up
interval, normal operation is restored. The device defaults to read-array mode, the
status register is set to 80h, and the configuration register defaults to asynchronous
page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the
memory contents at the aborted block or address are invalid.
November 2007 Datasheet
Order Number: 313272-06 41
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Like any automated device, it is important to assert RST# during system reset. When
the system comes out of reset, the processor expects to read from the flash memory
array. Automated flash memories provide status information when read during program
or erase operations. If a CPU reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx Flash memories allow proper CPU
initialization following a system reset through the use of the RST# input. In this
application, RST# is controlled by the same CPU reset signal, RESET#.
9.1.5 Write
A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash control
commands are written to the CUI using standard microprocessor write timings. Proper
use of the ADV# input is needed for proper latching of the addresses. Write operations
are asynchronous; CLK is ignored (but still may be kept active/toggling).
The CUI does not occupy an addressable memory location within any partition. The
system processor must access it at the correct address range depending on the kind of
command executed. Programming or erasing may occur in only one partition at a time.
Other partitions must be in one of the read modes or erase suspend mode.
Table 16, “Command Codes and Descriptions” on page 41 shows the available
commands. Appendix , “Write State Machine States” on page 73 provides information
on moving between different operating modes using CUI commands.
9.2 Device Commands
The W18 device on-chip WSM manages erase and program algorithms. This local CPU
(WSM) controls the device’s in-system read, program, and erase operations. Bus cycles
to or from the flash memory conform to standard microprocessor bus cycles. RST#,
CE#, OE#, WE#, and ADV# control signals dictate data flow into and out of the device.
WAIT informs the CPU of valid data during burst reads. Table 15, “Bus Operations” on
page 39 summarizes bus operations.
Device operations are selected by writing specific commands into the device’s CUI.
Table 16, “Command Codes and Descriptions” on page 41 lists all possible command
codes and descriptions. Table 17, “Bus Cycle Definitions” on page 43 lists command
definitions. Because commands are partition-specific, it is important to issue write
commands within the target address range.
Table 16: Command Codes and Descriptions (Sheet 1 of 2)
Operation Code Device
Command Description
Read
FFh Read Array Places selected partition in read-array mode.
70h Read Status
Register
Places selected partition in status register read mode. The partition enters this
mode after a Program or Erase command is issued to it.
90h Read Identifier
Puts the selected partition in read identifier mode. Device reads from partition
addresses output manufacturer/device codes, configuration register data, block
lock status, or protection register data on D[15:0].
98h Read Query Puts the addressed partition in read query mode. Device reads from the partition
addresses output CFI information on D[7:0].
50h Clear Status
Register
The WSM can set the status register’s block lock (SR[1]), VPP (SR[3]), program
(SR[4]), and erase (SR[5]) status bits, but it cannot clear them. SR[5:3,1] can
only be cleared by a device reset or through the Clear Status Register command.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
42 Order Number: 313272-06
Program
40h Word Program
Setup
This preferred program command’s first cycle prepares the CUI for a program
operation. The second cycle latches address and data, and executes the WSM
program algorithm at this location. Status register updates occur when CE# or
OE# is toggled. A Read Array command is required to read array data after
programming.
10h Alternate Setup Equivalent to a Program Setup command (40h).
30h EFP Setup
This program command activates EFP mode. The first write cycle sets up the
command. If the second cycle is an EFP Confirm command (D0h), subsequent
writes provide program data. All other commands are ignored after EFP mode
begins.
D0h EFP Confirm If the first command was EFP Setup (30h), the CUI latches the address and data,
and prepares the device for EFP mode.
Erase
20h Erase Setup
This command prepares the CUI for Block Erase. The device erases the block
addressed by the Erase Confirm command. If the next command is not Erase
Confirm, the CUI sets status register bits SR[5:4] to indicate command sequence
error and places the partition in the read status register mode.
D0h Erase Confirm
If the first command was Erase Setup (20h), the CUI latches address and data,
and erases the block indicated by the erase confirm cycle address. During
program or erase, the partition responds only to Read Status Register, Program
Suspend, and Erase Suspend commands. CE# or OE# toggle updates status
register data.
Suspend
B0h
Program
Suspend or
Erase Suspend
This command, issued at any device address, suspends the currently executing
program or erase operation. Status register data indicates the operation was
successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend)
and SR[7] are set. The WSM remains in the suspended state regardless of
control signal states (except RST#).
D0h Suspend Resume This command, issued at any device address, resumes the suspended program
or erase operation.
Block Locking
60h Lock Setup
This command prepares the CUI lock configuration. If the next command is not
Lock Block, Unlock Block, or Lock-Down, the CUI sets SR[5:4] to indicate
command sequence error.
01h Lock Block If the previous command was Lock Setup (60h), the CUI locks the addressed
block.
D0h Unlock Block
If the previous command was Lock Setup (60h), the CUI latches the address and
unlocks the addressed block. If previously locked-down, the operation has no
effect.
2Fh Lock-Down If the previous command was Lock Setup (60h), the CUI latches the address and
locks-down the addressed block.
Protection C0h
Protection
Program
Setup
This command prepares the CUI for a protection register program operation. The
second cycle latches address and data, and starts the WSM’s protection register
program or lock algorithm. Toggling CE# or OE# updates the flash status register
data. To read array data after programming, issue a Read Array command.
Configuration
60h Configuration
Setup
This command prepares the CUI for device configuration. If Set Configuration
Register is not the next command, the CUI sets SR[5:4] to indicate command
sequence error.
03h
Set
Configuration
Register
If the previous command was Configuration Setup (60h), the CUI latches the
address and writes the data from A[15:0] into the configuration register.
Subsequent read operations access array data.
Note: Do not use unassigned commands. Numonyx reserves the right to redefine these codes for future functions.
Table 16: Command Codes and Descriptions (Sheet 2 of 2)
Operation Code Device
Command Description
November 2007 Datasheet
Order Number: 313272-06 43
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Table 17: Bus Cycle Definitions
Operation Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr1Data2,3 Oper Addr1Data2,3
Read
Read Array/Reset ≥1 Write PnA FFh Read Read
Address
Array
Data
Read Identifier ≥ 2 Write PnA 90h Read PBA+IA IC
Read Query ≥ 2 Write PnA 98h Read PBA+QA QD
Read Status Register 2 Write PnA 70h Read PnA SRD
Clear Status Register 1 Write XX 50h — — —
Program
and
Erase
Block Erase 2 Write BA 20h Write BA D0h
Word Program 2 Write WA 40h/10h Write WA WD
EFP >2 Write WA 30h Write WA D0h
Program/Erase Suspend1WriteXXB0h———
Program/Erase Resume 1 Write XX D0h — — —
Lock
Lock Block 2 Write BA 60h Write BA 01h
Unlock Block 2 Write BA 60h Write BA D0h
Lock-Down Block 2 Write BA 60h Write BA 2Fh
Protection
Protection Program 2 Write PA C0h Write PA PD
Lock Protection Program 2 Write LPA C0h Write LPA FFFDh
Configuration Set Configuration Register 2 Write CD 60h Write CD 03h
Notes:
1. First-cycle command addresses should be the same as the operation’s target address. Examples: the first-cycle address
for the Read Identifier command should be the same as the Identification code address (IA); the first-cycle address for
the Word Program command should be the same as the word address (WA) to be programmed; the first-cycle address
for the Erase/Program Suspend command should be the same as the address within the block to be suspended; etc.
XX = Any valid address within the device.
IA = Identification code address.
BA = Block Address. Any address within a specific block.
LPA = Lock Protection Address is obtained from the CFI (through the Read Query command). The W18 family’s LPA is at
0080h.
PA = User programmable 4-word protection address.
PnA = Any address within a specific partition.
PBA = Partition Base Address. The very first address of a particular partition.
QA = Query code address.
WA = Word address of memory location to be written.
2. SRD = Status register data.
WD = Data to be written at location WA.
IC = Identifier code data.
PD = User programmable 4-word protection data.
QD = Query code data on DQ[7:0].
CD = Configuration register code data presented on device addresses A/DQ[15:0]. A[MAX:16] address bits can select
any partition. See Table 25, “Configuration Register Definitions” on page 66 for configuration register
bits descriptions.
3. Commands other than those shown above are reserved by Numonyx for future device implementations and should not
be used.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
44 Order Number: 313272-06
9.3 Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation is allowed
to occur between the two write cycles. The setup phase of a 2-cycle write sequence
places the addressed partition into read-status mode, so if the same partition is read
before the second “confirm” write cycle is issued, status register data will be returned.
Reads from other partitions, however, can return actual array data assuming the
addressed partition is already in read-array mode. Figure 16 on page 44 and Figure 17
on page 44 illustrate these two conditions.
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so
causes a command sequence error to appear in the status register. Figure 18 illustrates
a command sequence error.
Figure 16: Normal Write and Read Cycles
Figure 17: Interleaving a 2-Cycle Write Sequence with an Array Read
Partition A Partition A Partition A
20h D0h FFh
Block Erase Setup Block Erase Conf irm Read Array
A
ddress [A]
WE# [W]
OE# [G]
Data [Q]
Partition B Partition A Partition B Partition A
FFh 20h
A
rray Dat
a
D0h
Read Array Erase Setup Bus Read Erase Confirm
A
ddress [A]
WE# [W]
OE# [G]
Data [Q]
Figure 18: Improper Command Sequencing
Partition X Partition Y Partition X Partition X
20h FFh D0h SR Data
Address [A]
WE# [W]
OE# [G]
Data [D/Q]
November 2007 Datasheet
Order Number: 313272-06 45
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
10.0 Read Operations
10.1 Read Array
The Read Array command places (or resets) the partition in read-array mode and is
used to read data from the flash memory array. Upon initial device power-up, or after
reset (RST# transitions from VIL to VIH), all partitions default to asynchronous read-
array mode. To read array data from the flash device, first write the Read Array
command (FFh) to the CUI and specify the desired word address. Then read from that
address. If a partition is already in read-array mode, the Read Array command need
not be reissued to read from that partition.
If the Read Array command is written to a partition that is erasing or programming, the
device presents invalid data on the bus until the program or erase operation completes.
After the program or erase finishes in that partition, valid array data can then be read.
If an Erase Suspend or Program Suspend command suspends the WSM, a subsequent
Read Array command places the addressed partition in read-array mode. The Read
Array command functions independently of VPP
.
10.2 Read Device ID
The read identifier mode outputs the manufacturer/device identifier, block lock status,
protection register codes, and configuration register data. The identifier information is
contained within a separate memory space on the device and can be accessed along
the 4-Mbit partition address range supplied by the Read Identifier command (90h)
address. Reads from addresses in Ta b l e 1 8 retrieve ID information. Issuing a Read
Identifier command to a partition that is programming or erasing places that partition’s
outputs in read ID mode while the partition continues to program or erase in the
background.
Table 18: Device Identification Codes (Sheet 1 of 2)
Item
Address(1)
Data Description
Base Offset
Manufacturer ID Partition 00h 0089h Numonyx
Device ID (Top Parameter) Partition 01h
8872h 32-Mbit TPD
8874h 64-Mbit TPD
8876h 128-Mbit TPD
Device ID (Bottom Parameter) Partition 01h
8873h 32-Mbit BPD
8875h 64-Mbit BPD
8877h 128-Mbit BPD
Block Lock Status(2) Block 02h
A/DQ[0] = 0 Block is unlocked
A/DQ[0] = 1 Block is locked
Block Lock-Down Status(2) Block 02h
A/DQ[1] = 0 Block is not locked-down
A/DQ[1] = 1 Block is locked down
Notes:
1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block
number 39 in a TPD, set the address to the BBA (138000h) plus the offset (02h), i.e. 138002h. Then examine bit 0 of
the data to determine if the block is locked.
2. See Section 13.1.4, “Block Lock Status” on page 61 for valid lock status.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
46 Order Number: 313272-06
10.3 Read Query (CFI)
This device contains a separate CFI query database that acts as an “on-chip datasheet.”
The CFI information within this device can be accessed by issuing the Read Query
command and supplying a specific address. The address is constructed from the base
address of a partition plus a particular offset corresponding to the desired CFI field.
Section 16.0, “Common Flash Interface” on page 76 shows accessible CFI fields and
their address offsets. Issuing the Read Query command to a partition that is
programming or erasing puts that partition in read query mode while the partition
continues to program or erase in the background.
10.4 Read Status Register
The device’s status register displays program and erase operation status. A partition’s
status can be read after writing the Read Status Register command to any location
within the partition’s address range. Read-status mode is the default read mode
following a Program, Erase, or Lock Block command sequence. Subsequent single reads
from that partition will return its status until another valid command is written.
The read-status mode supports single synchronous and single asynchronous reads
only; it doesn’t support burst reads. The first falling edge of OE# or CE# latches and
updates status register data. The operation doesn’t affect other partitions’ modes.
Because the status register is 8 bits wide, only DQ [7:0] contains valid status register
data; DQ [15:8] contains zeros. See Table 19, “Status Register Definitions” on page 46
and Table 20, “Status Register Descriptions” on page 47.
Each 4-Mbit partition contains its own status register. Bits SR[6:0] are unique to each
partition, but SR[7], the Device WSM Status (DWS) bit, pertains to the entire device.
SR[7] provides program and erase status of the entire device. By contrast, the Partition
WSM Status (PWS) bit, SR[0], provides program and erase status of the addressed
partition only. Status register bits SR[6:1] present information about partition-specific
program, erase, suspend, VPP
, and block-lock states. Table 21, “Status Register Device
WSM and Partition Write Status Description” on page 47 presents descriptions of DWS
(SR[7]) and PWS (SR[0]) combinations.
Configuration Register Partition 05h Register Data —
Protection Register Lock Status Partition 80h Lock Data —
Protection Register Partition 81h - 88h Register Data
Multiple reads required to read
the entire 128-bit Protection
Register.
Table 18: Device Identification Codes (Sheet 2 of 2)
Item
Address(1)
Data Description
Base Offset
Notes:
1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block
number 39 in a TPD, set the address to the BBA (138000h) plus the offset (02h), i.e. 138002h. Then examine bit 0 of
the data to determine if the block is locked.
2. See Section 13.1.4, “Block Lock Status” on page 61 for valid lock status.
Table 19: Status Register Definitions
DWS ESS ES PS VPPS PSS DPS PWS
76543210
November 2007 Datasheet
Order Number: 313272-06 47
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
10.5 Clear Status Register
The Clear Status Register command clears the status register and leaves all partition
output states unchanged. The WSM can set all status register bits and clear bits
SR[7:6,2,0]. Because bits SR[5,4,3,1] indicate various error conditions, they can only
be cleared by the Clear Status Register command. By allowing system software to reset
these bits, several operations, such as cumulatively programming several addresses or
erasing multiple blocks in sequence, can be performed before reading the status
register to determine error occurrence. If an error is detected, the Status Register must
be cleared before beginning another command or sequence. Device reset (RST# = VIL)
also clears the status register. This command functions independently of VPP.
Table 20: Status Register Descriptions
Bit Name State Description
7
DWS
Device WSM
Status
0 = Device WSM is Busy
1 = Device WSM is Ready
SR[7] indicates erase or program completion in the
device. SR[6:1] are invalid while SR[7] = 0.
6
ESS
Erase Suspend
Status
0 = Erase in progress/completed
1 = Erase suspended
After issuing an Erase Suspend command, the WSM halts
and sets SR[7] and SR[6]. SR[6] remains set until the
device receives an Erase Resume command.
5ES
Erase Status
0 = Erase successful
1 = Erase error
SR[5] is set if an attempted erase failed. A Command
Sequence Error is indicated when SR[7,5:4] are set.
4PS
Program Status
0 = Program successful
1 = Program error SR[4] is set if the WSM failed to program a word.
3VPPS
VPP Status
0 = VPP OK
1 = VPP low detect, operation aborted
The WSM indicates the VPP level after program or erase
completes. SR[3] does not provide continuous VPP
feedback and isn’t guaranteed when VPP ≠ VPP1/2.
2
PSS
Program
Suspend Status
0 = Program in progress/completed
1 = Program suspended
After receiving a Program Suspend command, the WSM
halts execution and sets SR[7] and SR[2]. They remain
set until a Resume command is received.
1
DPS
Device Protect
Status
0 = Unlocked
1 = Aborted erase/program attempt on
locked block
If an erase or program operation is attempted to a locked
block (if WP# = VIL), the WSM sets SR[1] and aborts the
operation.
0
PWS
Partition Write
Status
0 = This partition is busy, but only if
SR[7]=0
1 = Another partition is busy, but only if
SR[7]=0
Addressed partition is erasing or programming. In EFP
mode, SR[0] indicates that a data-stream word has
finished programming or verifying depending on the
particular EFP phase.
Table 21: Status Register Device WSM and Partition Write Status Description
DWS:
SR[7]
PWS:
SR[0] Description
00
The addressed partition is performing a program/erase operation.
EFP: device has finished programming or verifying data, or is ready for data.
01
A partition other than the one currently addressed is performing a program/erase operation.
EFP: the device is either programming or verifying data.
10
No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2])
indicate whether other partitions are suspended. EFP: the device has exited EFP mode.
1 1 Won’t occur in standard program or erase modes. EFP: this combination does not occur.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
48 Order Number: 313272-06
11.0 Program Operations
11.1 Word Program
When the Word Program command is issued, the WSM executes a sequence of
internally timed events to program a word at the desired address and verify that the
bits are sufficiently programmed. Programming the flash array changes specifically
addressed bits to 0; 1 bits do not change the memory cell contents.
Programming can occur in only one partition at a time. All other partitions must be in
either a read mode or erase suspend mode. Only one partition can be in erase suspend
mode at a time.
The status register can be examined for program progress by reading any address
within the partition that is busy programming. However, while most status register bits
are partition-specific, the Device WSM Status bit, SR[7], is device-specific; that is, if
the status register is read from any other partition, SR[7] indicates program status of
the entire device. This permits the system CPU to monitor program progress while
reading the status of other partitions.
CE# or OE# toggle (during polling) updates the status register. Several commands can
be issued to a partition that is programming: Read Status Register, Program Suspend,
Read Identifier, and Read Query. The Read Array command can also be issued, but the
read data is indeterminate.
After programming completes, three status register bits can signify various possible
error conditions. SR[4] indicates a program failure if set. If SR[3] is set, the WSM
couldn’t execute the Word Program command because VPP was outside acceptable
limits. If SR[1] is set, the program was aborted because the WSM attempted to
program a locked block.
After the status register data is examined, clear it with the Clear Status Register
command before a new command is issued. The partition remains in status register
mode until another command is written to that partition. Any command can be issued
after the status register indicates program completion.
If CE# is deasserted while the device is programming, the devices will not enter
standby mode until the program operation completes.
November 2007 Datasheet
Order Number: 313272-06 49
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
11.2 Factory Programming
The standard factory programming mode uses the same commands and algorithm as
the Word Program mode (40h/10h). When VPP is at VPP1, program and erase currents
are drawn through VCC. If VPP is driven by a logic signal, VPP1 must remain above the
VPP1Min value to perform in-system flash modifications. When VPP is connected to a
12 V power supply, the device draws program and erase current directly from VPP. This
eliminates the need for an external switching transistor to control the VPP voltage.
Figure 28, “Examples of VPP Power Supply Configurations” on page 65 shows examples
of flash power supply usage in various configurations.
Figure 19: Word Program Flowchart
Suspend
Program
Loop
Start
Write 40h,
Word Address
Write Data
Word Address
Read Status
Register
SR[7] =
Full Program
Status Check
(if desired)
Program
Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Suspend
Program
Read Status
Register
Program
Successful
SR[3] =
SR[1] =
0
0
SR[4] =
0
1
1
1
1
0
No
Yes
V
PP
Range
Error
Device
Protect Error
Program
Error
WORD PROGRAM PROCEDURE
SR[3] MUST be cleared before the WSM will allow further
program attempts
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Standby
Standby
Bus
Operation Command
Check SR[3]
1 = V
PP
error
Check SR[4]
1 = Data program error
Comments
Repeat for subsequent programming operations.
Full status register check can be done after each program or
after a sequence of program operations.
Comments
Bus
Operation Command
Data = 40h
Addr = Location to program (WA)
Write Program
Setup
Data = Data to program (WD)
Addr = Location to program (WA)
Write Data
Read SRD
Toggle CE# or OE# to update SRD
Read
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
Standby
Check SR[1]
1 = Attempted program to locked block
Program aborted
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
50 Order Number: 313272-06
The 12 V VPP mode enhances programming performance during the short time period
typically found in manufacturing processes; however, it is not intended for extended
use.12 V may be applied to VPP during program and erase operations as specified in
Section 5.2, “Operating Conditions” on page 20. VPP may be connected to 12 V for a
total of tPPH hours maximum. Stressing the device beyond these limits may cause
permanent damage.
11.3 Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of
enhancements to the conventional 12 Volt word program algorithm. EFP's more
efficient WSM algorithm eliminates the traditional overhead delays of the conventional
word program mode in both the host programming system and the flash device.
Changes to the conventional word programming flowchart and internal WSM routine
were developed because of today's beat-rate-sensitive manufacturing environments; a
balance between programming speed and cycling performance was attained.
The host programmer writes data to the device and checks the Status Register to
determine when the data has completed programming. This modification essentially
cuts write bus cycles in half. Following each internal program pulse, the WSM
increments the device's address to the next physical location. Now, programming
equipment can sequentially stream program data throughout an entire block without
having to setup and present each new address. In combination, these enhancements
reduce much of the host programmer overhead, enabling more of a data streaming
approach to device programming.
EFP further speeds up programming by performing internal code verification. With this,
PROM programmers can rely on the device to verify that it has been programmed
properly. From the device side, EFP streamlines internal overhead by eliminating the
delays previously associated to switch voltages between programming and verify levels
at each memory-word location.
EFP consists of four phases: setup, program, verify and exit. Refer to Figure 20,
“Enhanced Factory Program Flowchart” on page 52 for a detailed graphical
representation of how to implement EFP.
11.3.1 EFP Requirements and Considerations
Table 22: EFP Requirements and Considerations
EFP Requirements
Ambient temperature: TA = 25 °C ±5 °C
VCC within specified operating range
VPP within specified VPP2 range
Ta rge t b lo ck un l o cke d
EFP Considerations
Block cycling below 100 erase cycles 1
RWW not supported2
EFP programs one block at a time
EFP cannot be suspended
Notes:
1. Recommended for optimum performance. Some degradation in performance may occur if this limit is exceeded, but the
internal algorithm will continue to work properly.
2. Code or data cannot be read from another partition during EFP.
November 2007 Datasheet
Order Number: 313272-06 51
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
11.3.2 Setup
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7]
transitions from a 1 to a 0 indicating that the WSM is busy with EFP algorithm startup.
A delay before checking SR[7] is required to allow the WSM time to perform all of its
setups and checks (VPP level and block lock status). If an error is detected, status
register bits SR[4], SR[3], and/or SR[1] are set and EFP operation terminates.
Note: After the EFP Setup and Confirm command sequence, reads from the device
automatically output status register data. Do not issue the Read Status Register
command; it will be interpreted as data to program at WA0.
11.3.3 Program
After setup completion, the host programming system must check SR[0] to determine
“data-stream ready" status (SR[0]=0). Each subsequent write after this is a program-
data write to the flash array. Each cell within the memory word to be programmed to 0
receives one WSM pulse; additional pulses, if required, occur in the verify phase.
SR[0]=1 indicates that the WSM is busy applying the program pulse.
The host programmer must poll the device's status register for the "program done"
state after each data-stream write. SR[0]=0 indicates that the appropriate cell(s)
within the accessed memory location have received their single WSM program pulse,
and that the device is now ready for the next word. Although the host may check full
status for errors at any time, it is only necessary on a block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside the
target block immediately terminates the program phase; the WSM then enters the EFP
verify phase.
The address can either hold constant or it can increment. The device compares the
incoming address to that stored from the setup phase (WA0); if they match, the WSM
programs the new data word at the next sequential memory location. If they differ, the
WSM jumps to the new address location.
The program phase concludes when the host programming system writes to a different
block address, and data supplied must be FFFFh. Upon program phase completion, the
device enters the EFP verify phase.
11.3.4 Verify
A high percentage of the flash bits program on the first WSM pulse. However, for those
cells that do not completely program on their first attempt, EFP internal verification
identifies them and applies additional pulses as required.
The verify phase is identical in flow to the program phase, except that instead of
programming incoming data, the WSM compares the verify-stream data to that which
was previously programmed into the block. If the data compares correctly, the host
programmer proceeds to the next word. If not, the host waits while the WSM applies an
additional pulse(s).
The host programmer must reset its initial verify-word address to the same starting
location supplied during the program phase. It then reissues each data word in the
same order as during the program phase. Like programming, the host may write each
subsequent data word to WA0 or it may increment up through the block addresses.
The verification phase concludes when the interfacing programmer writes to a different
block address; data supplied must be FFFFh. Upon completion of the verify phase, the
device enters the EFP exit phase.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
52 Order Number: 313272-06
11.3.5 Exit
SR[7]=1 indicates that the device has returned to normal operating conditions. A full
status check should be performed at this time to ensure the entire block programmed
successfully. After EFP exit, any valid CUI command can be issued.
Figure 20: Enhanced Factory Program Flowchart
EFP Setup EFP Program EFP Verify
EFP Exit
1. WA
0
= first Word Address to be programmed within the target block. The BBA (Block Base
Address) must remain constant throughout the program phase data stream; WA can be held
constant at the first address location, or it can be written to sequence up through the addresses
within the block. Writing to a BBA not equal to that of the block currently being written to
terminates the EFP program phase, and instructs the device to enter the EFP verify phase.
2. For proper verification to occur, the verify data stream must be presented to the device in the
same sequence as that of the program phase data stream. Writing to a BBA not equal to WA
terminates the EFP verify phase, and instructs the device to exit EFP.
3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive
additional program-pulse attempts during the EFP verify phase. The device will report any
program failure by setting SR[4]=1; this check can be performed during the full status check after
EFP has been exited for that block, and will indicate any error within the entire data stream.
Comments
Bus
State
Repeat for subsequent operations.
After EFP exit, a Full Status Check can
determine if any program error occurred.
See the Full Status Check procedure in the
Word Program flowchart.
Write
Standby
Read
Write
Write
(note 2)
Read
Standby
Write
Read
Standby
EFP
Setup
Program
Done?
Exit
Program
Phase
Last
Data?
Exit
Verify
Phase
EFP
Exited?
Write EFP
Confirm
Read
Standby
EFP
Setup
Done?
Read
Standby
Verify
Stream
Ready?
Write Unlock
Block
Write
(note 1)
Standby Last
Data?
Standby
(note 3)
Verify
Done?
S R [0 ]= 1 = N
Write Data
Address = WA
0
Last
Data?
Write FFFFh
Address
≠
BBA
Program
Done?
Read
Status Register
SR[0]=0=Y
Y
S R [0 ]= 1 = N
N
Write Data
Address = WA
0
Verify
Done?
Last
Data?
Read
Status Register
Write FFFFh
Address
≠
BBA
Y
Verify Stream
Ready?
Read
Status Register
SR[7]=0=N
Full Status Check
Procedure
Operation
Complete
Read
Status Register
EFP
Exited?
SR[7]=1=Y
SR[0]=1=N
Start
Write 30h
Address = WA
0
V
PP
= 12V
Unlock Block
Write D0h
Address = WA
0
EFP Setup
Done?
Read
Status Register
SR[7]=1=N
Exit
N
EFP Program EFP Verify EFP ExitEFP Setup
Comments
Bus
State
Data = 30h
Address = WA
0
Data = D0h
Address = WA
0
Status Register
Check SR[7]
0 = EFP ready
1 = EFP not ready
V
PP
= 12V
Unlock block
Check SR[0]
0 = Program done
1 = Program not done
Status Register
Data = FFFFh
Addressnot within same
BBA
Data = Data to program
Address = WA
0
Device automatically
increments address.
Comments
Bus
State
Data = Word to ve rify
Address = WA
0
Status Register
Device automatically
increments address.
Data = FFFFh
Addressnot within same
BBA
Status Register
Check SR[0]
0 = Ready for verify
1 = Not ready for verify
Check SR[0]
0 = Verify done
1 = Verify not done
Status Register
Check SR[7]
0 = Exit not finished
1 = Exit completed
Check V
PP
& Lock
errors (SR[3,1])
Data Stream
Ready?
Read
Status Register
SR[0] =0=Y
S R [7 ]= 0 = Y
SR[0]=1=N
Standby
Read
Data
Stream
Ready?
Check SR[0]
0 = Ready for data
1 = Not ready for data
Status Register
SR[0]=0=Y
SR[0] =0=Y
EFP setup time
Standby EFP setup time
Standby
Error
Condition
Check
If SR[7] = 1:
Check SR[3,1]
SR[3] = 1 = V
PP
error
SR[1] = 1 = locked block
November 2007 Datasheet
Order Number: 313272-06 53
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
12.0 Program and Erase Operations
12.1 Program/Erase Suspend and Resume
The Program Suspend and Erase Suspend commands halt an in-progress program or
erase operation. The command can be issued at any device address. The partition
corresponding to the command’s address remains in its previous state. A suspend
command allows data to be accessed from memory locations other than the one being
programmed or the block being erased.
A program operation can be suspended only to perform a read operation. An erase
operation can be suspended to perform either a program or a read operation within any
block, except the block that is erase suspended. A program command nested within a
suspended erase can subsequently be suspended to read yet another location. Once a
program or erase process starts, the Suspend command requests that the WSM
suspend the program or erase sequence at predetermined points in the algorithm. The
partition that is actually suspended continues to output status register data after the
Suspend command is written. An operation is suspended when status bits SR[7] and
SR[6] and/or SR[2] are set.
To read data from blocks within the partition (other than an erase-suspended block),
you can write a Read Array command. Block erase cannot resume until the program
operations initiated during erase suspend are complete. Read Array, Read Status
Register, Read Identifier (ID), Read Query, and Program Resume are valid commands
during Program or Erase Suspend. Additionally, Clear Status Register, Program,
Program Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-Down Block are
valid commands during erase suspend.
To read data from a block in a partition that is not programming or erasing, the
operation does not need to be suspended. If the other partition is already in read array,
ID, or Query mode, issuing a valid address returns corresponding data. If the other
partition is not in a read mode, one of the read commands must be issued to the
partition before data can be read.
During a suspend, CE# = VIH places the device in standby state, which reduces active
current. VPP must remain at its program level and WP# must remain unchanged while
in suspend mode.
A resume command instructs the WSM to continue programming or erasing and clears
status register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written
to any partition. When read at the partition that is programming or erasing, the device
outputs data corresponding to the partition’s last mode. If status register error bits are
set, the status register can be cleared before issuing the next instruction. RST# must
remain at VIH. See Figure 21, “Program Suspend / Resume Flowchart” on page 54, and
Figure 22, “Erase Suspend / Resume Flowchart” on page 55.
If a suspended partition was placed in read array, read status register, read identifier
(ID), or read query mode during the suspend, the device remains in that mode and
outputs data corresponding to that mode after the program or erase operation is
resumed. After resuming a suspended operation, issue the read command appropriate
to the read operation. To read status after resuming a suspended operation, issue a
Read Status Register command (70h) to return the suspended partition to status mode.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
54 Order Number: 313272-06
Figure 21: Program Suspend / Resume Flowchart
Read Status
Register
SR.7 =
SR.2 =
Write FFh
Susp Partition
Read Array
Data
Program
Completed
Done
Reading
Write FFh
Pgm'd Partition
Write D0h
Any Addr ess
Program
Resumed
Read Array
Data
0
No
0
Yes
1
1
PROGRAM SUSPEND / RESUME PROCEDURE
Wr i te Program
Resume
Data = D0h
Addr = Suspended block (BA)
Bus
Operation Command Comments
Wr i te Program
Suspend
Data = B0h
Addr = Block to suspend (BA)
Standby
Check SR.7
1 = WSM ready
0 = WSM busy
Standby
Check SR.2
1 = Program suspended
0 = Program com pl eted
Wr i te Read
Array
Data = FFh
Addr = Any address within the
suspended par titi on
Read Read array data from block other than
the one being programmed
Read
Status r egister data
Toggle CE# or OE# to update Status
register
Addr = Suspended block (BA)
PGM_SUS.WMF
Start
Write B0h
Any Addr ess
Program Suspend
Read Status
Program Resume Read Array
Read Array
Wr i te 70h
Same Partition
Wr i te Read
Status
Data = 70h
Addr = Same partition
If t he suspen ded part it ion was placed in Read Array mode:
Wr i te Read
Status
Return partition to Status mode:
Data = 70h
Addr = Same partition
Wr i te 70h
Same Partition
Read Status
November 2007 Datasheet
Order Number: 313272-06 55
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
12.2 Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase
Confirm (D0h), initiates one block erase at the addressed block. Only one partition can
be in an erase mode at a time; other partitions must be in a read mode. The Erase
Confirm command internally latches the address of the block to be erased. Erase forces
all bits within the block to 1. SR[7] is cleared while the erase executes.
After writing the Erase Confirm command, the selected partition is placed in read status
register mode and reads performed to that partition return the current status data. The
address given during the Erase Confirm command does not need to be the same
address used in the Erase Setup command. So, if the Erase Confirm command is given
to partition B, then the selected block in partition B will be erased even if the Erase
Setup command was to partition A.
Figure 22: Erase Suspend / Resume Flowchart
Erase
Completed
Write FFh
Erased Partition
Read Array
Data
0
0
No
Read
1
Program
Program
Loop
Read Array
Data
1
Yes
Start
Write B0h
Any Address
Read Status
Register
SR.7 =
SR.6 =
Write D0h
Any Address
Erase Resumed
Read or
Program?
Done?
Write
Write
Standby
Standby
Write
Erase
Suspend
Read Array
or Program
Program
Resume
Data = B0h
Addr = Any address
Data = FFh or 40h
Addr = Block to program or read
Check SR.7
1 = WSM ready
0 = WSM busy
Check SR.6
1 = Erase suspended
0 = Erase completed
Data = D0h
Addr = Any address
Bus
Operation Command Comments
Read
Status register data. Toggle CE# or
OE# to update Status register
Addr = Same partition
Read or
Write
Read array or program data from/to
block other than the one being erased
ERASE SUSPEND / RESUME PROCEDURE
ERAS_SUS.WMF
Write 70h
Same Partition
Write Read
Status
Data = 70h
Addr = Same partition
Erase Resume
Erase Suspend
Read Status
Read Array
Write 70h
Same Partition
Read Status
If the suspended partition was placed in
Read Array mode or a Program Loop:
Write Read
Status
Return partition to Status mode:
Data = 70h
Addr = Same partition
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
56 Order Number: 313272-06
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For
example, an Erase Setup command must be immediately followed by the Erase Confirm
command in order to execute properly. If a different command is issued between the
setup and confirm commands, the partition is placed in read-status mode, the status
register signals a command sequence error, and all subsequent erase commands to
that partition are ignored until the status register is cleared.
The CPU can detect block erase completion by analyzing SR[7] of that partition. If an
error bit (SR[5,3,1]) was flagged, the status register can be cleared by issuing the
Clear Status Register command before attempting the next operation. The partition
remains in read-status mode until another command is written to its CUI. Any CUI
instruction can follow after erasing completes. The CUI can be set to read-array mode
to prevent inadvertent status register reads.
November 2007 Datasheet
Order Number: 313272-06 57
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
12.3 Read-While-Write and Read-While-Erase
The Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO supports flexible
multi-partition dual-operation architecture. By dividing the flash memory into many
separate partitions, the device can read from one partition while programing or erasing
in another partition; hence the terms, RWW and RWE. Both of these features greatly
enhance data storage performance.
Figure 23: Block Erase Flowchart
SR[3,1]
must
be cleared before the WSM will allow further
erase attempts.
Only the Clear Status Register command clears SR[5:3,1].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Start
FULL ERASE STATUS CHECK PROCEDURE
Repeat for subsequent block erasures.
Full status register check can be done after each block erase
or after a sequence of block erasures.
No
Suspend
Erase
1
0
0
0
1
1
1
1
0Yes
Suspend
Erase
Loop
0
Write 20h
Block Address
Write D0h and
Block Address
Read Status
Register
SR[7] =
Full Erase
Status Check
(if desired)
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR[1] =
Erase of
Locked Block
Aborted
BLOCK ERASE PROCEDURE
Bus
Operation Command Comments
Write
Block
Erase
Setup
Data = 20h
Addr = Block to be erased (BA)
Write Erase
Confirm
Data = D0h
Addr = Block to be erased (BA)
Read Read SRD
Toggle CE# or OE# to update SRD
Standby
Check SR[7]
1 = WSM ready
0 = WSM busy
Bus
Operation Command Comments
SR[3] = V
PP
Range
Error
SR[5:4] = Command
Sequence Error
SR[5] = Block Erase
Error
Standby Check SR[3]
1 = V
PP
error
Standby Check SR[5:4]
Both 1 = Command sequence error
Standby Check SR[5]
1 = Block erase error
Standby
Check SR[1]
1 = Attempted erase of locked block
Erase aborted
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
58 Order Number: 313272-06
The product does not support simultaneous program and erase operations. Attempting
to perform operations such as these results in a command sequence error. Only one
partition can be programming or erasing while another partition is reading. However,
one partition may be in erase suspend mode while a second partition is performing a
program operation, and yet another partition is executing a read command. Ta ble 1 6 ,
“Command Codes and Descriptions” on page 41 describes the command codes
available for all functions.
November 2007 Datasheet
Order Number: 313272-06 59
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
13.0 Security Modes
The Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO offers both
hardware and software security features to protect the flash data. The software
security feature is used by executing the Lock Block command. The hardware security
feature is used by executing the Lock-Down Block command and by asserting the WP#
signal.
Refer to Figure 24, “Block Locking State Diagram” on page 60 for a state diagram of
the flash security features. Also see Figure 25, “Locking Operations Flowchart” on
page 62.
13.1 Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be
locked or unlocked with no latency. This locking scheme offers two levels of protection.
The first allows software-only control of block locking (useful for frequently changed
data blocks), while the second requires hardware interaction before locking can be
changed (protects infrequently changed code blocks).
The following sections discuss the locking system operation. The term “state [abc]”
specifies locking states; for example, “state [001],” where a = WP# value, b = block
lock-down status bit
D1, and c = Block Lock status register bit D0. Figure 24, “Block Locking State
Diagram” on page 60 defines possible locking states.
The following summarizes the locking functionality.
• All blocks power-up in a locked state.
• Unlock commands can unlock these blocks, and lock commands can lock them
again.
• The Lock-Down command locks a block and prevents it from being unlocked when
WP# is asserted.
— Locked-down blocks can be unlocked or locked with commands as long as WP#
is deasserted
— The lock-down status bit is cleared only when the device is reset or powered-
down.
Block lock registers are not affected by the VPP level. They may be modified and read
even if VPP ≤ VPPLK.
Each block’s locking status can be set to locked, unlocked, and lock-down, as described
in the following sections. See Figure 25, “Locking Operations Flowchart” on page 62.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
60 Order Number: 313272-06
13.1.1 Lock
All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks
are fully protected from alteration. Attempted program or erase operations to a locked
block will return an error in SR[1]. Unlocked blocks can be locked by using the Lock
Block command sequence. Similarly, a locked block’s status can be changed to
unlocked or lock-down using the appropriate software commands.
13.1.2 Unlock
Unlocked blocks (states [x00] and [110]) can be programmed or erased. All unlocked
blocks return to the locked state when the device is reset or powered-down. An
unlocked block’s status can be changed to the locked or locked-down state using the
appropriate software commands. A locked block can be unlocked by writing the Unlock
Block command sequence if the block is not locked-down.
13.1.3 Lock-Down
Locked-down blocks (state [011]) offer the user an additional level of write protection
beyond that of a regular locked block. A block that is locked-down cannot have it’s
state changed by software if WP# is asserted. A locked or unlocked block can be
locked-down by writing the Lock-Down Block command sequence. If a block was set to
locked-down, then later changed to unlocked, a Lock-Down command should be issued
prior asserting WP# will put that block back to the locked-down state. When WP# is
deasserted, locked-down blocks are changed to the locked state and can then be
unlocked by the Unlock Block command.
Figure 24: Block Locking State Diagram
[X00]
[X01]
Power-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down4,5
Software
Locked
[011]
Hardware
Locked5
Unlocked
WP# Hardware Control
Notes: 1. [a,b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D1 indicates block Lock-down status. D1 = ‘0’, Lock-down has not been issued to
this block. D1 = ‘1’, Lock-down has been issued to this block.
3. D0 indicates block lock status. D0 = ‘0’, block is unlocked. D0 = ‘1’, block is locked.
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked by system software to determine difference between
Hardware Locked and Locked-Down states.
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
November 2007 Datasheet
Order Number: 313272-06 61
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
13.1.4 Block Lock Status
Every block’s lock status can be read in read identifier mode. To enter this mode, issue
the Read Identifier command to the device. Subsequent reads at Block Base Address +
02h will output that block’s lock status. For example, to read the block lock status of
block 10, the address sent to the device should be 50002h (for a top-parameter
device). The lowest two data bits of the read data, D1 and D0, represent the lock
status. D0 indicates the block lock status. It is set by the Lock Block command and
cleared by the Block Unlock command. It is also set when entering the lock-down state.
D1 indicates lock-down status and is set by the Lock-Down command. The lock-down
status bit cannot be cleared by software–only by device reset or power-down. See
Ta b le 2 3 .
13.1.5 Lock During Erase Suspend
Block lock configurations can be performed during an erase suspend operation by using
the standard locking command sequences to unlock, lock, or lock-down a block. This
feature is useful when another block requires immediate updating.
To change block locking during an erase operation, first write the Erase Suspend
command. After checking SR[6] to determine the erase operation has suspended, write
the desired lock command sequence to a block; the lock status will be changed. After
completing lock, unlock, read, or program operations, resume the erase operation with
the Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the
locking status bits change immediately. When the erase operation is resumed, it will
complete normally.
Locking operations cannot occur during program suspend. Appendix , “Write State
Machine States” on page 73 shows valid commands during erase suspend.
13.1.6 Status Register Error Checking
Using nested locking or program command sequences during erase suspend can
introduce ambiguity into status register results.
Because locking changes require 2-cycle command sequences, for example, 60h
followed by 01h to lock a block, following the Configuration Setup command (60h) with
an invalid command produces a command sequence error (SR[5:4]=11b). If a Lock
Block command error occurs during erase suspend, the device sets SR[4] and SR[5] to
1 even after the erase is resumed. When erase is complete, possible errors during the
erase cannot be detected from the status register because of the previous locking
command error. A similar situation occurs if a program operation error is nested within
an erase suspend.
Table 23: Write Protection Truth Table
VPP WP# RST# Write Protection
XXV
IL Device inaccessible
VIL XV
IH Word program and block erase prohibited
XV
IL VIH All lock-down blocks locked
XV
IH VIH All lock-down blocks can be unlocked
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
62 Order Number: 313272-06
13.1.7 WP# Lock-Down Control
The Write Protect signal, WP#, adds an additional layer of block security. WP# only
affects blocks that once had the Lock-Down command written to them. After the lock-
down status bit is set for a block, asserting WP# forces that block into the lock-down
state [011] and prevents it from being unlocked. After WP# is deasserted, the block’s
state reverts to locked [111] and software commands can then unlock the block (for
erase or program operations) and subsequently re-lock it. Only device reset or power-
down can clear the lock-down status bit and render WP# ineffective.
13.2 Protection Register
The W18 device includes a 128-bit protection register. This protection register is used
to increase system security and for identification purposes. The protection register
value can match the flash component to the system’s CPU or ASIC to prevent device
substitution.
The lower 64 bits within the protection register are programmed by Numonyx with a
unique number in each flash device. The upper 64 OTP bits within the protection
register are left for the customer to program. Once programmed, the customer
segment can be locked to prevent further programming.
Note: The individual bits of the user segment of the protection register are OTP, not the
register in total. The user may program each OTP bit individually, one at a time, if
desired. After the protection register is locked, however, the entire user segment is
locked and no more user bits can be programmed.
Figure 25: Locking Operations Flowchart
No
Optional
Start
Write 60h
Block Address
Write 90h
BBA + 02h
Read Block Lock
Status
Locking
Change?
Lock Change
Complete
Write 01,D0,2Fh
Block Address
Write FFh
Partition Address
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Standby
(Optional)
Write
Lock
Setup
Lock,
Unlock, or
Lockdown
Confirm
Read ID
Plane
Block Lock
Status
Read
Array
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Data = 01h (Lock block)
D0h (Unlock block)
2Fh (Lockdown block)
Addr = Block to lock/unlock/lock-down (BA)
Data = 90h
Addr = BBA + 02h
Block Lock status data
Addr = BBA + 02h
Confirm locking change on DQ[1:0].
(See Block Locking State Transitions Table
for valid combinations.)
Data = FFh
Addr = Any address in same partition
Bus
Operation Command Comments
LOCKING OPERATIONS PROCEDURE
November 2007 Datasheet
Order Number: 313272-06 63
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
The protection register shares some of the same internal flash resources as the
parameter partition. Therefore, RWW is only allowed between the protection register
and main partitions. Ta b le 2 4 describes the operations allowed in the protection
register, parameter partition, and main partition during RWW and RWE.
13.2.1 Reading the Protection Register
Writing the Read Identifier command allows the protection register data to be read 16
bits at a time from addresses shown in Table 18, “Device Identification Codes” on
page 45. The protection register is read from the Read Identifier command and can be
read in any partition.Writing the Read Array command returns the device to read-array
mode.
13.2.2 Programing the Protection Register
The Protection Program command should be issued only at the parameter (top or
bottom) partition followed by the data to be programmed at the specified location. It
programs the upper 64 bits of the protection register 16 bits at a time. Table 18,
“Device Identification Codes” on page 45 shows allowable addresses. See also
Figure 26, “Protection Register Programming Flowchart” on page 64. Issuing a
Protection Program command outside the register’s address space results in a status
register error (SR[4]=1).
13.2.3 Locking the Protection Register
PR-LK.0 is programmed to 0 by Numonyx to protect the unique device number. PR-LK.1
can be programmed by the user to lock the user portion (upper 64 bits) of the
protection register (See Figure 27, ”Protection Register Locking”). This bit is set using
the Protection Program command to program “FFFDh” into PR-LK.
After PR-LK register bits are programmed (locked), the protection register’s stored
values can’t be changed. Protection Program commands written to a locked section
result in a status register error (SR[4]=1, SR[5]=1).
Table 24: Simultaneous Operations Allowed with the Protection Register
Protection
Register
Parameter
Partition
Array Data
Main
Partitions Description
Read See
Description Write/Erase
While programming or erasing in a main partition, the protection register can
be read from any other partition. Reading the parameter partition data is not
allowed if the protection register is being read from addresses within the
parameter partition.
See
Description Read Write/Erase
While programming or erasing in a main partition, read operations are allowed
in the parameter partition. Accessing the protection registers from parameter
partition addresses is not allowed.
Read Read Write/Erase
While programming or erasing in a main partition, read operations are allowed
in the parameter partition. Accessing the protection registers in a partition that
is different from the one being programmed or erased, and also different from
the parameter partition, is allowed.
Write No Access
Allowed Read
While programming the protection register, reads are only allowed in the other
main partitions. Access to the parameter partition is not allowed. This is
because programming of the protection register can only occur in the
parameter partition, so it will exist in status mode.
No Access
Allowed Write/Erase Read
While programming or erasing the parameter partition, reads of the protection
registers are not allowed in any partition. Reads in other main partitions are
supported.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
64 Order Number: 313272-06
Figure 26: Protection Register Programming Flowchart
FULL STATUS CHECK PROCEDURE
Protection Program operations addresses must be within the
protection register address space. Addresses outside this
space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each program or
after a sequence of program operations.
SR[3] MUST be cleared before the WSM will allow further
program attempts.
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Yes
No
1,1
1,0
1,1
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start
Write C0h
Addr=Prot addr
Write Protect.
Register
Address / Data
Read Status
Register
SR[7] = 1?
Full Status
Check
(if desired)
Program
Complete
Read SRD
Program
Successful
SR[4:3] =
SR[4,1] =
SR[4,1] =
V
PP
Range Error
Programming Error
Locked-Register
Program Aborted
Standby
Standby
Bus
Operation Command
SR[1] SR[3] SR[4]
011V
PP
Error
0 0 1 Protection register
program error
Comments
Write
Write
Standby
Protection
Program
Setup
Protection
Program
Data = C0h
Addr = Protection address
Data = Data to program
Addr = Protection address
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Bus
Operation Command Comments
Read Read SRD
Toggle CE# or OE# to update SRD
Standby 1 0 1 Register locked;
Operation aborted
November 2007 Datasheet
Order Number: 313272-06 65
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
13.3 VPP Protection
The Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO provides in-
system program and erase at VPP1. For factory programming, it also includes a low-
cost, backward-compatible 12 V programming feature.(See “Factory Programming” on
page 49.) The EFP feature can also be used to greatly improve factory program
performance as explained in Section 11.3, “Enhanced Factory Program (EFP)” on
page 50.
In addition to the flexible block locking, holding the VPP programming voltage low can
provide absolute hardware write protection of all flash-device blocks. If VPP is below
VPPLK, program or erase operations result in an error displayed in SR[3]. (See
Figure 28.)
Note: If the VCC supply can sink adequate current, you can use an appropriately valued resistor.
Figure 27: Protection Register Locking
0x84
0x88
0x85
0x81
0x80
PR Lock Register 0
User-Programmable
Intel Factory-Programmed
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 28: Examples of VPP Power Supply Configurations
•
12 V fast programming
•
Absolute write protection with VPP ≤ VPPLK
System supply
(Note 1)
VCC
VPP
12 V supply
•
Low voltage and 12 V fast programming
System supply
12 V supply
• Low-voltage programming
• Absolute write protection via logic signal
System supply
Prot# (logic signal)
• Low-voltage programming
System supply
≤
10K Ω
VCC
VPP
VCC
VPP
VCC
VPP
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
66 Order Number: 313272-06
14.0 Set Configuration Register
The Set Configuration Register command sets the burst order, frequency configuration,
burst length, and other parameters. A two-bus cycle command sequence initiates this
operation. The configuration register data is placed on the lower 16 bits of the address
bus (A[15:0]) during both bus cycles. The Set Configuration Register command is
written along with the configuration data (on the address bus). This is followed by a
second write that confirms the operation and again presents the configuration register
data on the address bus. The configuration register data is latched on the rising edge of
ADV#, CE#, or WE# (whichever occurs first). This command functions independently of
the applied VPP voltage. After executing this command, the device returns to read-array
mode. The configuration register’s contents can be examined by writing the Read
Identifier command and then reading location 05h. Undocumented combinations of bits
are reserved by Numonyx for future implementations.
Table 25: Configuration Register Definitions
Read
Mode Res’d First Access Latency
Count
WAIT
Polarity
Data
Output
Config
WAIT
Config
Burst
Seq
Clock
Config Res’d Res’d Burst
Wrap Burst Length
RM R LC2 LC1 LC0 WT DOC WC BS CC R R BW BL2 BL1 BL0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 26: Configuration Register Descriptions
Bit Name Description Notes
15 RM (Read Mode) 0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default) 1
14 R Reserved 4
13-11 LC2-0
(First Access Latency Count)
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
6
10 WT
(WAIT Signal Polarity)
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default) 2
9DOC
(Data Output Configuration)
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default) 6
8 WC (WAIT Configuration) 0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default) 6
7 BS (Burst Sequence) 1 = Linear Burst Order (Default)
6CC
(Clock Configuration)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
5RReserved 4
4RReserved 4
3BW (Burst Wrap)
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)
2-0 BL2-0 (Burst Length)
001 = 4-Word Burst
010 = 8-Word Burst
011 = 16-Word Burst
111 = Continuous Burst (Default)
3
Notes:
1. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status register
and configuration reads support single read cycles. CR[15]=1 disables configuration set by CR[14:0].
2. Data is not ready when WAIT is asserted.
3. Set the synchronous burst length. In asynchronous page mode, the page size equals four words.
4. Set all reserved configuration register bits to zero.
5. Setting the configuration register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data hold
for 2 clocks (RCR.9 = 1), and WAIT asserted one data cycle before delay (RCR8 =1) is not supported.
November 2007 Datasheet
Order Number: 313272-06 67
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
14.1 Read Mode (CR[15])
All partitions support two high-performance read configurations: synchronous burst
mode and asynchronous page mode (default). CR[15] sets the read configuration to
one of these modes.
Status register, query, and identifier modes support only asynchronous and single-
synchronous read operations.
14.2 First Access Latency Count (CR[13:11])
The First Access Latency Count (CR[13:11]) configuration tells the device how many
clocks must elapse from ADV# de-assertion (VIH) before the first data word should be
driven onto its data pins. The input clock frequency determines this value. See
Table 25, “Configuration Register Definitions” on page 66 for latency values. Figure 29
shows data output latency from ADV# assertion for different latencies. Refer to Section
14.2.1, “Latency Count Settings” on page 68 for Latency Code Settings.
Note: Other First Access Latency Configuration settings are reserved.
)
The 16-word boundary is the end of the device sense word-line.
Figure 29: First Access Latency Configuration
Figure 30: Word Boundary
Code 5
Code 4
Code 3
Code 2
Val id
Address
Valid
Output
Val id
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Val id
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Address [A]
ADV# [V]
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
0123456789ABCDEF
16 Word Boundary
Word 0 - 3 Word 4 - 7 Word 8 - B Word C - F
4 Word Boundary
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
68 Order Number: 313272-06
14.2.1 Latency Count Settings
14.3 WAIT Signal Polarity (CR[10])
If the WT bit is cleared (CR[10]=0), then WAIT is configured to be asserted low. This
means that a 0 on the WAIT signal indicates that data is not ready and the data bus
contains invalid data. Conversely, if CR[10] is set, then WAIT is asserted high. In either
case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted during
asynchronous page mode reads.
14.4 WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous read
array mode (CR[15] is set to 0), and when addressing a partition that is currently in
read array mode.
In synchronous read array mode, when the device is active (CE# = VIL) and data is
valid, CR[10] (WT) determines if WAIT goes to VOH or VOL. The WAIT signal is only de-
asserted when data is valid on the bus. Invalid data drives the WAIT signal to the
asserted state.
When the device is operating in synchronous non-array read mode (Read ID, Read
Query, Read Status, etc.), the WAIT signal is de-asserted throughout the entire read
operation.
Table 27: Latency Count Setting for VCCQ = 1.7 V - 2.24 V (.13 µm lithography)
VCCQ = 1.7 - 2.24 V
Unit
tAVQV/tCHQV (60 ns/11 ns)
Latency Count Settings 2 3, 4, 5
Frequency Support < 40 < 54 MHz
Figure 31: Example: Latency Count Setting at 3
AMAX-0 (A)
DQ15-0 (D/Q)
CLK (C)
CE# (E)
ADV# (V)
R103
Valid
Output
Valid
Output
High Z
tADD-DELAY tDATA
1nd0st 2rd 3th 4th
Valid Address
Code 3
November 2007 Datasheet
Order Number: 313272-06 69
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
From a system perspective, the WAIT signal is in the asserted state (based on CR[10])
when the device is operating in synchronous non-read-array mode (such as Read ID,
Read Query, or Read Status), or if the device is operating in asynchronous mode
(CR[15]=1). In these cases, the system software should ignore (mask) the WAIT
signal, because it does not convey any useful information about the validity of what is
appearing on the data bus.
14.5 Data Hold (CR[9])
The Data Output Configuration bit (CR[9]) determines whether a data word remains
valid on the data bus for one or two clock cycles. The processor’s minimum data set-up
time and the flash memory’s clock-to-data output delay determine whether one or two
clocks are needed.
A Data Output Configuration set at 1-clock data hold corresponds to a 1-clock data
cycle; a Data Output Configuration set at 2-clock data hold corresponds to a 2-clock
data cycle. The setting of this configuration bit depends on the system and CPU
characteristics. For clarification, see Figure 32, “Data Output Configuration with WAIT
Signal Delay” on page 70.
A method for determining this configuration setting is shown below.
To set the device at 1-clock data hold for subsequent reads, the following condition
must be satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
As an example, use a clock frequency of 54 MHz and a clock period of 18.5 ns. Assume
the data output hold time is one clock. Apply this data to the formula above for the
subsequent reads:
14 ns + 4 ns ≤ 18.5 ns
This equation is satisfied, and data output will be available and valid at every clock
period. If tDATA is long, hold for two cycles.
Table 28: WAIT Signal Conditions
CONDITION WAIT
CE# = VIH
CE# = VIL
Tri-S tate
Active
OE# No-Effect
Synchronous Array Read Active
Synchronous Non-Array Read Asserted
All Asynchronous Read and all Write Asserted
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
70 Order Number: 313272-06
Note: WAIT shown asserted high (CR[10]=1).
14.6 WAIT Delay (CR[8])
The WAIT configuration bit (CR[8]) controls WAIT signal delay behavior for all
synchronous read-array modes. Its setting depends on the system and CPU
characteristics. The WAIT can be asserted either during, or one data cycle before, a
valid output.
In synchronous linear read array (no-wrap mode CR[3]=1) of 4-, 8-, 16-, or
continuous-word burst mode, an output delay may occur when a burst sequence
crosses its first device-row boundary (16-word boundary). If the burst start address is
4-word boundary aligned, the delay does not occur. If the start address is misaligned to
a 4-word boundary, the delay occurs once per burst-mode read sequence. The WAIT
signal informs the system of this delay.
14.7 Burst Sequence (CR[7])
The burst sequence specifies the synchronous-burst mode data order. When operating
in a linear burst mode (either 4-, 8-, or 16-word burst length with the burst wrap bit
(CR[3]) set, or in continuous burst mode) the device may incur an output delay when
the burst sequence crosses the first 16-word boundary, depending on the starting
address. If the starting address is aligned to a 4-word boundary, there is no delay. If
the starting address is the end of a 4-word boundary, the output delay is one clock
cycle less than the First Access Latency Count; this is the worst-case delay. The delay
takes place only once, and only if the burst sequence crosses a 16-word boundary. The
WAIT pin informs the system of this delay.
Figure 32: Data Output Configuration with WAIT Signal Delay
DQ15-0 [Q]
CLK [C]
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [Q] Valid
Output
1 CLK
Data Hold
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
tCHQV
tCHQV
WAIT (CR.8 = 0)
WAIT (CR.8 = 1)
2 CLK
Data Hold
tCHTL/H
Note 1
Note 1
Note 1
Note 1
Valid
Output
Table 29: Sequence and Burst Length (Sheet 1 of 2)
Start
Addr.
(Dec)
Burst Addressing Sequence (Decimal)
4-Word
Burst
CR[2:0]=001b
8-Word Burst
CR[2:0]=010b
16-Word Burst
CR[2:0]=011b
Continuous Burst
CR[2:0]=111b
November 2007 Datasheet
Order Number: 313272-06 71
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
14.8 Clock Edge (CR[6])
Configuring the valid clock edge enables a flexible memory interface to a wide range of
burst CPUs. Clock configuration sets the device to start a burst cycle, output data, and
assert WAIT on the clock’s rising or falling edge.
14.9 Burst Wrap (CR[3])
The burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within
the burst-length boundary or whether they cross word-length boundaries to perform
linear accesses. No-wrap mode (CR[3]=1) enables WAIT to hold off the system
processor, as it does in the continuous burst mode, until valid data is available. In no-
wrap mode (CR[3]=0), the device operates similarly to continuous linear burst mode
but consumes less power during 4-, 8-, or 16-word bursts.
For example, if CR[3]=0 (wrap mode) and CR[2:0] = 1h (4-word burst), possible linear
burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.
If CR[3]=1 (no-wrap mode) and CR[2:0] = 1h (4-word burst length), then possible
linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. CR[3]=1 not only
enables limited non-aligned sequential bursts, but also reduces power by minimizing
the number of internal read operations.
Wrap (CR[3]=0)
0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...
1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3...14-15-0 1-2-3-4-5-6-7-...
2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4...15-0-1 2-3-4-5-6-7-8-...
3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5...15-0-1-2 3-4-5-6-7-8-9-...
44-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3 4-5-6-7-8-9-10...
55-6-7-0-1-2-3-4 5-6-7...15-0-1...4 5-6-7-8-9-10-11...
66-7-0-1-2-3-4-5 6-7-8...15-0-1...5 6-7-8-9-10-11-12-...
77-0-1-2-3-4-5-6 7-8-9...15-0-1...6 7-8-9-10-11-12-13...
...
...
...
...
...
14 14-15-0-1...13 14-15-16-17-18-19-20-...
15 15-0-1-2-3...14 15-16-17-18-19-...
No-Wrap (CR[3]=1)
0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-...
1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3...15-16 1-2-3-4-5-6-7-...
2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4...16-17 2-3-4-5-6-7-8-...
3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5...17-18 3-4-5-6-7-8-9-...
44-5-6-7-8-9-10-11 4-5-6...18-19 4-5-6-7-8-9-10...
55-6-7-8-9-10-11-12 5-6-7...19-20 5-6-7-8-9-10-11...
66-7-8-9-10-11-12-13 6-7-8...20-21 6-7-8-9-10-11-12-...
77-8-9-10-11-12-13-14 7-8-9...21-22 7-8-9-10-11-12-13...
...
...
...
...
...
14 14-15...28-29 14-15-16-17-18-19-20-...
15 15-16...29-30 15-16-17-18-19-20-21-...
Table 29: Sequence and Burst Length (Sheet 2 of 2)
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
72 Order Number: 313272-06
Setting CR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-
word burst sequences. However, significantly more power may be consumed. The 1-2-
3-4 sequence, for example, consumes power during the initial access, again during the
internal pipeline lookup as the processor reads word 2, and possibly again, depending
on system timing, near the end of the sequence as the device pipelines the next 4-word
sequence. CR[3]=1 while in 4-word burst mode (no-wrap mode) reduces this excess
power consumption.
14.10 Burst Length (CR[2:0])
The Burst Length bit (BL[2:0]) selects the number of words the device outputs in
synchronous read access of the flash memory array. The burst lengths are 4-word, 8-
word, 16-word, and continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 29, “Sequence and Burst Length” on page 70). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
November 2007 Datasheet
Order Number: 313272-06 73
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
15.0 Write State Machine States
This table shows the command state transitions based on incoming commands. Only
one partition can be actively programming or erasing at a time.
Figure 33: Write State Machine — Next State Table (Sheet 1 of 2)
Chi
p
Next State after Com m and In
p
ut
Read
Array
(3 )
Program
Setup
(4,5)
Erase
Setup
(4 ,5 )
Enhanced
Factory
Pgm
Setup
(4 )
BE Confirm,
P/E Resume,
ULB
Confirm
(9 )
Program/
Erase
Suspend
Read
Status
Clear
Status
Register
(6)
Read
ID /Q u ery
(F FH ) (10H/40H ) (20H ) (30H) (D 0H ) (B0H ) (70H) (50H ) (90H, 98H)
Ready R eady Program
Setup
Erase
Setup
EFP
Setup Ready
Lock/C R S etup Ready (Lock Error) Ready R eady (Lock Error)
Setup OTP Busy
Busy
Setup Program Busy
Busy Program Busy Pgm Susp Program Busy
Suspend Program Suspend Pgm Busy Program Suspend
S etup R eady (Error) Erase Busy R eady (Error)
Busy Erase Busy Erase Susp Erase Busy
Suspend Erase
Suspend
Pgm in
Erase
Susp Setup
Erase Suspend Erase Busy Erase Suspend
Setup Program in Erase Suspend Busy
Busy Program in Erase Suspend Busy Pgm Susp in
Erase Susp Program in Erase Suspend Busy
S uspend Program Suspend in Erase Suspend Pgm in Erase
S usp Busy Program Suspend in Erase Suspend
Erase Suspend (Lock Error) Erase Susp Erase Suspend
(Lo ck E rro r)
S etup R eady (Error) EFP B usy Ready (Error)
EFP Busy EFP Bus
y
(7 )
EFP Verify Verif
y
Bus
y
(7 )
Out
p
ut Next State after Com m and In
p
ut
Status
Status
Status
ID /Q u ery
W rite State M achine (W SM ) Next State Table
Output Next State Table
(1)
Lock/C R S etup,
Lock/C R S etup in Erase Susp
OTP Busy
Current Chip
State
(8)
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Erase Suspend,
Pgm In E rase Susp Busy,
P gm S u sp In E ras e S u sp
Pgm Setup,
Erase S etup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
EFP Busy,
V erify B u s y
Lock/C R S etup in Erase
Suspend
Erase
Program
Program in
Erase S uspend
OTP
Enhanced
Factory
Program
Output
does not
change
Array
(3 )
Status Output does not change Status
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
74 Order Number: 313272-06
Notes:
1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command
address.
A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued.
Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state
does not depend on the partition's output state.
For example, if partition #1's output state is Read Array and partition #4's output state is Read Status, every read from
partition #4 (without issuing a new command) outputs the Status register.
2. Illegal commands are those not defined in the command set.
Figure 33: Write State Machine — Next State Table (Sheet 2 of 2)
Chi
p
Next State after Com m and In
p
ut
Lock,
U nlock,
Lock-dow n,
CR setup
(5)
OTP
Setup
(5 )
Lock
Block
Confirm
(9)
Lock-
Down
Block
Confirm
(9 )
Write CR
Confirm
(9 )
Enhanced
Fact Pgm
Exit (blk add
< > W A 0 )
Illegal
com m ands or
EFP data
(2 )
(60H) (C 0H) (01H ) (2FH ) (03H ) (X XXX H) (other codes)
Ready Lock/CR
Setup
OTP
Setup Ready
Lock/CR Setup Ready (Lock Error) Ready Ready Ready Ready (Lock Error)
Setup OTP Busy
Busy Ready
Setup Program Busy N/A
Busy Program Busy Ready
Suspend Program Suspend
Setup R ea dy (E rro r)
Busy Erase Busy Erase Busy Ready
Suspend
Lock/CR
Setup in
Erase Susp
Erase Suspend
S etup P rogram in E rase S uspend B usy
Busy Program in Erase Suspend Busy Erase
Suspend
Suspend Program Suspend in Erase Suspend
Erase Suspend
(Lock Error) Erase Susp Erase Susp Erase Susp Erase Suspend (Lock Error)
Setup R ea dy (E rro r)
EFP Busy EFP Bus
y
(7 )
EFP Verify EFP Bus
y
(7 )
EFP Verify Verif
y
Bus
y
(7 )
Ready EFP Verif
y
(7)
Ready
Out
p
ut Next State after Com m and In
p
ut
Status
Status Array Status
W rite State M achine (W SM ) N ext State Table
O utput Next State Table
(1)
Program
Erase
Program in
Erase Suspend
Current Chip
State
(8)
OTP
Lock/C R S etup in Erase
Suspend
Enhanced
Factory
Program
O utput does
not change
O utput does
not change
WSM
O peration
Completes
N/A
N/A
N/A
N/A
O utput does not change ArrayStatus
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
EFP Busy,
V e rify B u s y
Lock/C R S etup,
Lock/C R S etup in Erase Susp
OTP Busy
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Erase Suspend,
Pgm In Erase Susp Busy,
P g m S u sp In E ra se S u s p
November 2007 Datasheet
Order Number: 313272-06 75
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in
undermined data when a partition address is read.
4. Both cycles of 2 cycles commands should be issued to the same partition address. If they are issued to different partitions,
the second write determines the active partition. Both partitions will output status information when read.
5. If the WSM is active, both cycles of a 2 cycle command are ignored. This differs from previous Numonyx devices.
6. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy, Erase Busy, Pgm
Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase
Suspend).
7. EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if Block Address = address at EFP Confirm
command. Any other commands are treated as data.
8. The "current state" is that of the WSM, not the partition.
9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then
move to the Ready State.
10. In Erase suspend, the only valid two cycle commands are "Program Word", "Lock/Unlock/Lockdown Block", and
"CR Write". In Program suspend or Program suspend in Erase suspend, both cycles of all two cycle commands will be
ignored.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
76 Order Number: 313272-06
16.0 Common Flash Interface
This appendix defines the data structure or “database” returned by the Common Flash
Interface (CFI) Query command. Software should parse this structure to gain critical
information such as block size, density, x8/x16, and electrical specifications. Once this
information has been obtained, the software will know which command sets to use to
enable flash writes, block erases, and otherwise control the flash component. The
Query is part of an overall specification for multiple command set and control interface
descriptions called Common Flash Interface, or CFI.
16.1 Query Structure Output
The Query database allows software to obtain information for controlling the flash
device. This section describes the device’s CFI-compliant interface that allows access to
Query data.
Query data are presented on the lowest-order data outputs (DQ0-7) only. The
numerical offset value is the address relative to the maximum bus width supported by
the device. On this family of devices, the Query table device starting address is a 10h,
which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ0-7)
and 00h in the high byte (DQ8-15).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 00h on the upper byte in this mode.
Table 30: Summary of Query Structure Output as a Function of Device and Mode
Device Hex Offset Hex Code ASCII Value
Device Addresses
00010: 51 “Q”
00011: 52 “R”
00012: 59 “Y”
Table 31: Example of Query Structure Output of x16 Devices (Sheet 1 of 2)
Word Addressing: Byte Addressing:
Offset Hex Code Value Offset Hex Code Value
A[X:0] DQ[15:0] AX - A0DQ[7:0]
00010h 0051 “Q” 00010h 0051 “Q”
00011h 0052 “R” 00011h 0052 “R”
00012h 0059 “Y” 00012h 0059 “Y”
00013h P IDLO PrVendor 00013h P IDLO PrVendor
00014h P IDHI ID # 00014h P IDLO ID #
November 2007 Datasheet
Order Number: 313272-06 77
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
16.2 Query Structure Overview
The Query command causes the flash component to display the Common Flash
Interface (CFI) Query structure or “database.” The structure sub-sections and address
locations are summarized below.
Table 32: Query Structure
Notes:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32K-word).
3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.
16.3 Block Status Register
The Block Status Register indicates whether an erase operation completed successfully
or whether a given block is locked or can be accessed for flash program/erase
operations.
Block Erase Status (BSR.1) allows software to determine the success of the last block
erase operation. BSR.1 can be used just after power-up to verify that the VCC supply
was not accidentally removed during an erase operation.
00015h PLO PrVendor 00015h P IDHI ID #
00016h PHI TblAdr 00016h ... ...
00017h A IDLO AltVendor 00017h
00018h A IDHI ID # 00018h
... ... ... ...
Table 31: Example of Query Structure Output of x16 Devices (Sheet 2 of 2)
Word Addressing: Byte Addressing:
Offset Hex Code Value Offset Hex Code Value
A[X:0] DQ[15:0] AX - A0DQ[7:0]
Offset Sub-Section Name Descri
p
tion(1)
00000h Manufacturer Code
00001h Device Code
(
BA+2
)
h(2) Block Status re
g
ister Block-specific information
00004-Fh Reserved Reserved for vendor-specific information
00010h CFI query identification string Command set ID and vendor data offset
0001Bh System interface information Device timing & voltage information
00027h Device geometry definition Flash device layout
P(3) Primary Intel-specific Extended Query Table Vendor-defined additional information specific
to the Primary Vendor Algorithm
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
78 Order Number: 313272-06
Table 33: Block Status Register
Notes:
1. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32K-word).
16.4 CFI Query Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Table 34: CFI Identification
Offset Len
g
th Description Add.
V
alue
(BA+2)h
(1)
1 Block Lock Status Register BA+2 --00 or --01
BA+2 (bit 0): 0 or 1
BA+2 (bit 1): 0 or 1
BSR 2–7: Reserved for future use BA+2 (bit 2–7): 0
BSR.0 Block lock status
0 = Unlocked
1 = Locked
BSR.1 Block lock-down status
0 = Not locked down
1 = Locked down
Offset Length Description Add.
Hex
Code Value
10h 3 Query-unique ASCII string “QRY“ 10: --51 "Q"
11: --52 "R"
12: --59 "Y"
13h 2 Primary vendor command set and control interface ID code. 13: --03
16-bit ID code for vendor-specified algorithms 14: --00
15h 2 Extended Query Table primary algorithm address 15: --39
16: --00
17h 2 Alternate vendor command set and control interface ID code. 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00
November 2007 Datasheet
Order Number: 313272-06 79
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Table 35: CFI Identification
Offset Length Description Add.
Hex
Code Value
1Bh 1 1B: --17 1.7V
1Ch 1 1C: --19 1.9V
1Dh 1 1D: --B4 11.4V
1Eh 1 1E: --C6 12.6V
1Fh 1 “n” such that t
yp
ical sin
g
le word
p
ro
g
ram time-out = 2n
μ
-sec 1F: --04 16μs
20h 1 “n” such that t
yp
ical max. buffer write time-out = 2n
μ
-sec 20: --00 NA
21h 1 “n” such that t
yp
ical block erase time-out = 2n m-sec 21: --0A 1s
22h 1 “n” such that t
yp
ical full chi
p
erase time-out = 2n m-sec 22: --00 NA
23h 1 “n” such that maximum word
p
ro
g
ram time-out = 2n times t
yp
ical 23: --04 256μs
24h 1 “n” such that maximum buffer write time-out = 2n times t
yp
ical 24: --00 NA
25h 1 “n” such that maximum block erase time-out = 2n times t
yp
ical 25: --03 8s
26h 1 “n” such that maximum chi
p
erase time-out = 2n times t
yp
ical 26: --00 NA
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
80 Order Number: 313272-06
16.5 Device Geometry Definition
Table 36: Device Geometry Definition
Offset Len
g
th Description Code
27h 1“n” such that device size = 2nin number of bytes 27: See table below
76543210
28h 2 — — — — x64 x32 x16 x8 28: --01 x16
15 14 13 12 11 10 9 8
————————29:--00
2Ah 2“n” such that maximum number of bytes in write buffer = 2n2A: --00 0
2B: --00
2Ch 1 2C:
2Dh 4 Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:
30:
31h 4 Erase Block Region 2 Information 31:
bits 0–15 = y, y+1 = number of identical-size erase blocks 32:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:
34:
35h 4 Reserved for future erase block region information 35:
36:
37:
38:
See table below
See table below
See table below
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
3. Symmetrically blocked partit
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
See table below
Address 32 Mbit
–B –T –B –T –B –T
27: --16 --16 --17 --17 --18 --18
28: --01 --01 --01 --01 --01 --01
29: --00 --00 --00 --00 --00 --00
2A: --00 --00 --00 --00 --00 --00
2B: --00 --00 --00 --00 --00 --00
2C: --02 --02 --02 --02 --02 --02
2D: --07 --3E --07 --7E --07 --FE
2E: --00 --00 --00 --00 --00 --00
2F: --20 --00 --20 --00 --20 --00
30: --00 --01 --00 --01 --00 --01
31: --3E --07 --7E --07 --FE --07
32: --00 --00 --00 --00 --00 --00
33: --00 --20 --00 --20 --00 --20
34: --01 --00 --01 --00 --01 --00
35: --00 --00 --00 --00 --00 --00
36: --00 --00 --00 --00 --00 --00
37: --00 --00 --00 --00 --00 --00
38: --00 --00 --00 --00 --00 --00
128 Mbit64 Mbit
November 2007 Datasheet
Order Number: 313272-06 81
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
16.6 Numonyx-Specific Extended Query Table
Table 37: Primary Vendor-Specific Extended Query
Offset(1) Len
g
th Description Hex
P = 39h (Optional flash features and commands)
A
dd. Code
V
alue
(P+0)h 3 Primary extended query table 39: --50 "P"
(P+1)h Unique ASCII string “PRI“ 3A: --52 "R"
(P+2)h 3B: --49 "I"
(P+3)h 1 Major version number, ASCII 3C: --31 "1"
(P+4)h 1 Minor version number, ASCII 3D: --33 "3"
(P+5)h 4 Optional feature and command support (1=yes, 0=no) 3E: --66
(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 3F: --0B
(P+7)h “1” then another 31 bit field of Optional features follows at 40: --00
(P+8)h the end of the bit–30 field. 41: --00
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Pagemode read supported bit 7 = 0 No
bit 8 Synchronous read supported bit 8 = 1 Yes
bit 9 Simultaneous operations supported bit 9 = 1 Yes
bit 10 Feature Space supported bit 10 = 0 No
bit 11 = 1 Yes
(P+9)h 1 42: --01
bit 0 Pro
g
ram supported after erase suspend bit 0 = 1 Yes
(P+A)h 2 Block status register mask 43: --03
(P+B)h bits 2–15 are Reserved; undefined bits are “0” 44: --00
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes
(P+C)h 1 45: --18 1.8V
(P+D)h 1 46: --C0 12.0V
bit 11 Stepping ID supported (IAS Purposes only)
Reserved for internal Intel use (Eas)
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
82 Order Number: 313272-06
Table 38: Protection Register Information
Table 39: Burst Read Information for A/D-muxed Device
Offset(1) Len
g
th Description Hex
P = 39h (Optional flash features and commands)
A
dd. Code
V
alue
(P+E)h 1 47: --01 1
(P+F)h 4 Protection Field 1: Protection Description 48: --80 80h
(P+10)h This field describes user-available One Time Pro
g
rammable 49: --00 00h
(P+11)h (OTP) Protection register bytes. Some are pre-programmed 4A: --03 8 byte
(P+12)h 4B: --03 8 bytewith device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Offset(1) Len
g
th Description Hex
P = 39h (Optional flash features and commands)
A
dd. Code
V
alue
(P+13)h 1 4C: --00 0 byte
(P+14)h 1 4D: --03 3
(P+15)h 1 4E: --01 4
(P+16)h 1 Synchronous mode read capability configuration 2 4F: --02 8
(P+17)h 1 50: --07 Cont
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data out
p
ut width.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 4
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read
p
a
g
e buffer.
Table 40: Partition and Erase-block Region Information
Offset
(1) See table below
P = 39h Description
A
ddress
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+18)h (P+18)h 1 51: 51:Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
84 Order Number: 313272-06
Partition Region 1 Information
O
ff
set
(1) See table below
P = 39h Description
A
ddress
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+19)h (P+19)h Number of identical partitions within the partition region 2 52: 52:
(P+1A)h (P+1A)h 53: 53:
(P+1B)h (P+1B)h 1 54: 54:
(P+1C)h (P+1C)h 1 55: 55:
(P+1D)h (P+1D)h 1 56: 56:
(P+1E)h (P+1E)h 1 57: 57:
(P+1F)h (P+1F)h Partition Region 1 Erase Block Type 1 Information 4 58: 58:
(P+20)h (P+20)h bits 0–15 = y, y+1 = number of identical-size erase blocks 59: 59:
(P+21)h (P+21)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 5A: 5A:
(P+22)h (P+22)h 5B: 5B:
(P+23)h (P+23)h Partition 1 (Erase Block Type 1) 25C:5C:
(P+24)h (P+24)h Minimum block erase cycles x 1000 5D: 5D:
(P+25)h (P+25)h 1 5E: 5E:
(P+26)h (P+26)h 1 5F: 5F:
(P+27)h Partition Region 1 Erase Block Type 2 Information 4 60:
(P+28)h bits 0–15 = y, y+1 = number of identical-size erase blocks 61:
(P+29)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 62:
(P+2A)h (bottom parameter device only) 63:
(P+2B)h Partition 1 (Erase block Type 2) 2 64:
(P+2C)h Minimum block erase cycles x 1000 65:
(P+2D)h 1 66:
(P+2E)h 1 67:
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
November 2007 Datasheet
Order Number: 313272-06 85
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Partition Region 2 Information
Offset
(1) See table below
P = 39h Description
A
ddress
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+2F)h (P+27)h Number of identical partitions within the partition region 2 68: 60:
(P+30)h (P+28)h 69: 61:
(P+31)h (P+29)h 1 6A: 62:
(P+32)h (P+2A)h 1 6B: 63:
(P+33)h (P+2B)h 1 6C: 64:
(P+34)h (P+2C)h 1 6D: 65:
(P+35)h (P+2D)h Partition Region 2 Erase Block Type 1 Information 4 6E: 66:
(P+36)h (P+2E)h bits 0–15 = y, y+1 = number of identical-size erase blocks 6F: 67:
(P+37)h (P+2F)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 70: 68:
(P+38)h (P+30)h 71: 69:
(P+39)h (P+31)h Partition 2
(
Erase block T
y
pe 1
)
2 72: 6A:
(P+3A)h (P+32)h Minimum block erase cycles x 1000 73: 6B:
(P+3B)h (P+33)h 1 74: 6C:
(P+3C)h (P+34)h 1 75: 6D:
(P+35)h Partition Region 2 Erase Block Type 2 Information 4 6E:
(P+36)h bits 0–15 = y, y+1 = number of identical-size erase blocks 6F:
(P+37)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 70:
(P+38)h 71:
(P+39)h Partition 2 (Erase Block Type 2) 272:
(P+3A)h Minimum block erase cycles x 1000 73:
(P+3B)h 1 74:
(P+3C)h 1 75:
Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Partition 2 (Erase Block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 2 (Erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permit
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
86 Order Number: 313272-06
Partition and Erase-block Region Information
Notes:
1. The variable P is a pointer which is defined at CFI offset 15h.
2. TPD - Top parameter device; BPD - Bottom parameter device.
3. Partition: Each partition is 4Mb in size. It can contain main blocks OR a combination of both main and parameter blocks.
4. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains all the
partitions that are made up of main blocks only. B. contains the partition that is made up of the parameter and the main
blocks.
Address 32 Mbit
–
B
–
T
–
B
–
T
–
B
–
T
51: --02 --02 --02 --02 --02 --02
52: --01 --07 --01 --0F --01 --1F
53: --00 --00 --00 --00 --00 --00
54: --11 --11 --11 --11 --11 --11
55: --00 --00 --00 --00 --00 --00
56: --00 --00 --00 --00 --00 --00
57: --02 --01 --02 --01 --02 --01
58: --07 --07 --07 --07 --07 --07
59: --00 --00 --00 --00 --00 --00
5A: --20 --00 --20 --00 --20 --00
5B: --00 --01 --00 --01 --00 --01
5C: --64 --64 --64 --64 --64 --64
5D: --00 --00 --00 --00 --00 --00
5E: --01 --01 --01 --01 --01 --01
5F: --02 --02 --02 --02 --02 --02
60: --06 --01 --06 --01 --06 --01
61: --00 --00 --00 --00 --00 --00
62: --00 --11 --00 --11 --00 --11
63: --01 --00 --01 --00 --01 --00
64: --64 --00 --64 --00 --64 --00
65: --00 --02 --00 --02 --00 --02
66: --01 --06 --01 --06 --01 --06
67: --02 --00 --02 --00 --02 --00
68: --07 --00 --0F --00 --1F --00
69: --00 --01 --00 --01 --00 --01
6A: --11 --64 --11 --64 --11 --64
6B: --00 --00 --00 --00 --00 --00
6C: --00 --01 --00 --01 --00 --01
6D: --01 --02 --01 --02 --01 --02
6E: --07 --07 --07 --07 --07 --07
6F: --00 --00 --00 --00 --00 --00
70: --00 --20 --00 --20 --00 --20
71: --01 --00 --01 --00 --01 --00
72: --64 --64 --64 --64 --64 --64
73: --00 --00 --00 --00 --00 --00
74: --01 --01 --01 --01 --01 --01
75: --02 --02 --02 --02 --02 --02
76: --X --X --X --X --X --X
X signifies Stepping ID number. See Table C12, above, for more details.
64Mbit 128Mbit
November 2007 Datasheet
Order Number: 313272-06 87
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Appendix A Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please
contact your local Numonyx representative.
Table 41: 38F Type Stacked Components
PF 38F 5070 M0 Y 0 B 0
Package
Designator
Product Line
Designator
Product Die/
Density
Configuration
NOR Flash
Product Family
Voltage/NOR
Flash CE#
Configuration
Parameter /
Mux
Configuration
Ballout
Identifier
Device
Details
PF =
SCSP, RoHS
RD =
SCSP,
Leaded
Stacked
NOR Flash +
RAM
Char 1 = Flash
die #1
Char 2 = Flash
die #2
Char 3 =
RAM die #1
Char 4 =
RAM die #2
(See
Table 43,
“38F / 48F
Density
Decoder”
on page 88
for details)
First character
applies to Flash
die #1
Second character
applies to Flash
die #2
(See Table 44,
“NOR Flash
Family
Decoder” on
page 89 for
details)
V =
1.8 V Core
and I/O;
Separate Chip
Enable per
die
(See
Table 45,
“Voltage /
NOR Flash
CE#
Configurati
on
Decoder”
on
page 89 for
details)
0 =
No parameter
blocks; Non-
Mux I/O
interface
(See
Ta ble 4 6,
“Paramete
r / Mux
Configurati
on
Decoder”
on
page 89 for
details)
B =
x16D
Ballout
(See
Table 4
7,
“Ballout
Decoder
” on
page 90
for
details)
0 =
Original
released
version of
this
product
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
88 Order Number: 313272-06
Table 42: 48F Type Stacked Components
PC 48F 4400 P0 V B 0 0
Package
Designator
Product Line
Designator
Product Die/
Density
Configuration
NOR Flash
Product Family
Voltage/NOR
Flash CE#
Configuration
Parameter /
Mux
Configuration
Ballout
Identifier
Device
Details
PC =
Easy BGA,
RoHS
RC =
Easy BGA,
Leaded
JS =
TSOP, RoHS
TE =
TSOP,
Leaded
PF =
SCSP, RoHS
RD =
SCSP,
Leaded
Stacked
NOR Flash
only
Char 1 = Flash
die #1
Char 2 = Flash
die #2
Char 3 = Flash
die #3
Char 4 = Flash
die #4
(See
Ta ble 4 3,
“38F / 48F
Density
Decoder”
on page 88
for details)
First character
applies to Flash
dies #1 and #2
Second character
applies to Flash
dies #3 and #4
(See Table 44,
“NOR Flash
Family
Decoder” on
page 89 for
details)
V =
1.8 V Core
and 3 V I/O;
Virtual Chip
Enable
(See
Table 45,
“Voltage /
NOR Flash
CE#
Configurati
on
Decoder”
on
page 89 for
details)
B =
Bottom
parameter;
Non-Mux I/O
interface
(See
Ta ble 4 6,
“Paramete
r / Mux
Configurati
on
Decoder”
on
page 89 for
details)
0 =
Discrete
Ballout
(See
Ta b l e 4
7,
“Ballout
Decoder
” on
page 90
for
details)
0 =
Original
released
version of
this
product
Table 43: 38F / 48F Density Decoder
Code Flash Density RAM Density
0 No Die No Die
1 32-Mbit 4-Mbit
2 64-Mbit 8-Mbit
3 128-Mbit 16-Mbit
4 256-Mbit 32-Mbit
5 512-Mbit 64-Mbit
6 1-Gbit 128-Mbit
7 2-Gbit 256-Mbit
8 4-Gbit 512-Mbit
9 8-Gbit 1-Gbit
A 16-Gbit 2-Gbit
B 32-Gbit 4-Gbit
C 64-Gbit 8-Gbit
D 128-Gbit 16-Gbit
E 256-Gbit 32-Gbit
F 512-Gbit 64-Gbit
November 2007 Datasheet
Order Number: 313272-06 89
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Table 44: NOR Flash Family Decoder
Code Family Marketing Name
C C3 Numonyx Advanced+ Boot Block Flash Memory
JJ3v.D Numonyx Embedded Flash Memory
L L18 / L30 Numonyx StrataFlash® Wireless Memory
M M18 Numonyx StrataFlash® Cellular Memory
P P30 / P33 Numonyx StrataFalsh® Embedded Memory
W W18 / W30 Numonyx Wireless Flash Memory
0(zero) - No Die
Table 45: Voltage / NOR Flash CE# Configuration Decoder
Code I/O Voltage
(Volt) Core Voltage (Volt) CE# Configuration
Z 3.0 1.8 Seperate Chip Enable per die
Y1.8 1.8 Seperate Chip Enable per die
X 3.0 3.0 Seperate Chip Enable per die
V 3.0 1.8 Virtual Chip Enable
U 1.8 1.8 Virtual Chip Enable
T 3.0 3.0 Virtual Chip Enable
R3.0 1.8 Virtual Address
Q1.8 1.8 Virtual Address
P3.0 3.0 Virtual Address
Table 46: Parameter / Mux Configuration Decoder
Code, Mux
Identification Number of Flash Die Bus Width Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 4
0 = Non Mux
1 = AD Mux1
2= AAD Mux
3 =Full" AD
Mux2
Any NA Notation used for stacks that contain no parameter blocks
B = Non Mux
C = AD Mux
F = "Full" Ad
Mux
1
X16
Bottom - - -
2BottomTop--
3 Bottom Bottom Top -
4 Bottom Top Bottom Top
2
X32
Bottom Bottom - -
4 Bottom Bottom Top Top
Numonyx™ Wireless Flash Memory (W18) with AD Multiplexed IO
Datasheet November 2007
90 Order Number: 313272-06
T = Non Mux
U = AD Mux
W = "Full" Ad
Mux
1
X16
Top - - -
2 Top Bottom - -
3 Top Top Bottom -
4 Top Bottom Top Bottom
2
X32
Top Top - -
4 Top Top Bottom Bottom
1. Only Flash is Muxed and RAM is non-Muxed
2. Both Flash and RAM are AD-Muxed
Table 46: Parameter / Mux Configuration Decoder
Code, Mux
Identification Number of Flash Die Bus Width Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 4
Table 47: Ballout Decoder
Code Ballout Definition
0 (Zero) SDiscrete ballout (Easay BGA and TSOP)
B x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus)
C x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus)
Q QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus)
U x32SH ballout, 106 ball (x32 NOR only Share Bus)
V x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus
W x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus
