LTC2376-16
1
237616fa
For more information www.linear.com/LTC2376-16
TYPICAL APPLICATION
FEATURES DESCRIPTION
16-Bit, 250ksps, Low Power
SAR ADC with 97dB SNR
The LTC
®
2376-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC. Op-
erating from a 2.5V supply, the LTC2376-16 has a ±VREF
fully differential input range with VREF ranging from 2.5V
to 5.1V. The LTC2376-16 consumes only 3.4mW and
achieves ±0.5LSB INL maximum, no missing codes at
16 bits with 97dB SNR.
The LTC2376-16 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 250ksps
throughput with no cycle latency makes the LTC2376-16
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing exter-
nal timing considerations. The LTC2376-16 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
The LTC2376-16 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
32k Point FFT fS = 250ksps, fIN = 2kHz
APPLICATIONS
n 250ksps Throughput Rate
n ±0.5LSB INL (Max)
n Guaranteed 16-Bit No Missing Codes
n Low Power: 3.4mW at 250ksps, 3.4µW at 250sps
n 97dB SNR (Typ) at fIN = 2kHz
n –125dB THD (Typ) at fIN = 2kHz
n Digital Gain Compression (DGC)
n Guaranteed Operation to 125°C
n 2.5V Supply
n Fully Differential Input Range ±VREF
n VREF Input Range from 2.5V to 5.1V
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Lead MSOP and 4mm × 3mm DFN Packages
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
FREQUENCY (kHz)
0 25 50 75
125
100
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237616 TA02
SNR = 97.1dB
THD = –125dB
SINAD = 97.1dB
SFDR = 128dB
20Ω
VREF
0V
VREF
0V 20Ω
3300pF
6800pF
6800pF
+
VREF
SAMPLE CLOCK
237616 TA01
10µF 0.1µF
2.5V
REF
1.8V TO 5V
2.5V TO 5.1V
47µF
(X5R, 0805 SIZE)
REF GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
REF/DGC
LTC2376-16
VDD OVDD
IN+
IN
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
LTC2376-16
2
237616fa
For more information www.linear.com/LTC2376-16
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF) ................................................. 6V
Analog Input Voltage (Note 3)
IN+, IN ......................... (GND 0.3V) to (REF + 0.3V)
REF/DGC Input (Note 3) .... (GND 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3) ........................... (GND 0.3V) to (OVDD + 0.3V)
(Notes 1, 2)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
CHAIN
VDD
GND
IN+
IN
GND
REF
REF/
DGC
TOP VIEW
DE PACKAGE
16-LEAD (4mm
×
3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
CHAIN
VDD
GND
IN+
IN
GND
REF
REF/
DGC
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2376CMS-16#PBF LTC2376CMS-16#TRPBF 237616 16-Lead Plastic MSOP 0°C to 70°C
LTC2376IMS-16#PBF LTC2376IMS-16#TRPBF 237616 16-Lead Plastic MSOP –40°C to 85°C
LTC2376HMS-16#PBF LTC2376HMS-16#TRPBF 237616 16-Lead Plastic MSOP –40°C to 125°C
LTC2376CDE-16#PBF LTC2376CDE-16#TRPBF 23766 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2376IDE-16#PBF LTC2376IDE-16#TRPBF 23766 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Digital Output Voltage
(Note 3) ........................... (GND 0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2376C ................................................ 0°C to 70°C
LTC2376I .............................................40°C to 85°C
LTC2376H .......................................... 40°C to 125°C
Storage Temperature Range .................. 65°C to 150°C
http://www.linear.com/product/LTC2376-16#orderinfo
LTC2376-16
3
237616fa
For more information www.linear.com/LTC2376-16
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 2kHz, VREF = 5V l94.6 97 dB
fIN = 2kHz, VREF = 5V, (H-Grade) l94.5 97 dB
SNR Signal-to-Noise Ratio fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 5V, REF/DGC = GND
fIN = 2kHz, VREF = 2.5V
l
l
l
95.3
94.5
92.1
97
96.4
95
dB
dB
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
fIN = 2kHz, VREF = 5V, REF/DGC = GND, (H-Grade)
fIN = 2kHz, VREF = 2.5V, (H-Grade)
l
l
l
95.2
94.3
91.8
97
96.4
95
dB
dB
dB
THD Total Harmonic Distortion fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 5V, REF/DGC = GND
fIN = 2kHz, VREF = 2.5V
l
l
l
–125
–125
–123
–103
–101
–103
dB
dB
dB
SFDR Spurious Free Dynamic Range fIN = 2kHz, VREF = 5V l104 126 dB
–3dB Input Bandwidth 34 MHz
Aperture Delay 500 ps
Aperture Jitter 4 ps
Transient Response Full-Scale Step 3.46 µs
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range (IN+) (Note 5) l–0.05 VREF + 0.05 V
VIN Absolute Input Range (IN) (Note 5) l–0.05 VREF + 0.05 V
VIN+ – VIN Input Differential Voltage Range VIN = VIN+ – VINl–VREF +VREF V
VCM Common-Mode Input Range lVREF/2–
0.1
VREF/2 VREF/2+
0.1
V
IIN Analog Input Leakage Current l±1 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
45
5
pF
pF
CMRR Input Common Mode Rejection Ratio fIN = 125kHz 86 dB
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
CONVERTER CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l16 Bits
No Missing Codes l16 Bits
Transition Noise 0.15 LSBRMS
INL Integral Linearity Error (Note 6) l–0.5 ±0.2 0.5 LSB
DNL Differential Linearity Error l–0.5 ±0.1 0.5 LSB
BZE Bipolar Zero-Scale Error (Note 7) l–4 0 4 LSB
Bipolar Zero-Scale Error Drift 1 mLSB/°C
FSE Bipolar Full-Scale Error (Note 7) l–13 ±2 13 LSB
Bipolar Full-Scale Error Drift ±0.05 ppm/°C
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2376-16
4
237616fa
For more information www.linear.com/LTC2376-16
ADC TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l250 ksps
tCONV Conversion Time l1.9 3 µs
tACQ Acquisition Time tACQ = tCYC – tHOLD (Note 10) l3.46 µs
tHOLD Maximum Time Between Acquisitions l540 ns
tCYC Time Between Conversions l4 µs
tCNVH CNV High Time l20 ns
tBUSYLH CNV to BUSY Delay CL = 20pF l13 ns
tCNVL Minimum Low Time for CNV (Note 11) l20 ns
tQUIET SCK Quiet Time from CNV(Note 10) l20 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l2.375 2.5 2.625 V
OVDD Supply Voltage l1.71 5.25 V
IVDD
IOVDD
IPD
IPD
Supply Current
Supply Current
Power Down Mode
Power Down Mode
250ksps Sample Rate
250ksps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF)
Conversion Done (IVDD + IOVDD + IREF, H-Grade)
l
l
l
1.36
0.05
0.9
0.9
1.7
90
140
mA
mA
µA
µA
PDPower Dissipation
Power Down Mode
Power Down Mode
250ksps Sample Rate
Conversion Done (IVDD + IOVDD + IREF)
Conversion Done (IVDD + IOVDD + IREF, H-Grade)
3.4
2.25
2.25
4.25
225
315
mW
µW
µW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
REFERENCE INPUT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Reference Voltage (Note 5) l2.5 5.1 V
IREF Reference Input Current (Note 9) l0.16 0.2 mA
VIHDGC High Level Input Voltage REF/DGC Pin l0.8VREF V
VILDGC Low Level Input Voltage REF/DGC Pin l0.2VREF V
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l0.8 • OVDD V
VIL Low Level Input Voltage l0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IO = –500µA lOVDD 0.2 V
VOL Low Level Output Voltage IO = 500µA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 µA
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2376-16
5
237616fa
For more information www.linear.com/LTC2376-16
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCK SCK Period (Notes 11, 12) l10 ns
tSCKH SCK High Time l4 ns
tSCKL SCK Low Time l4 ns
tSSDISCK SDI Setup Time From SCK(Note 11) l4 ns
tHSDISCK SDI Hold Time From SCK(Note 11) l1 ns
tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l13.5 ns
tDSDO SDO Data Valid Delay from SCKCL = 20pF (Note 11) l9.5 ns
tHSDO SDO Data Remains Valid Delay from SCKCL = 20pF (Note 10) l1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSYCL = 20pF (Note 10) l5 ns
tEN Bus Enable Time After RDL(Note 11) l16 ns
tDIS Bus Relinquish Time After RDL (Note 11) l13 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 250kHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 and
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
0.2*OVDD
50% 50%
237616 F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
Figure 1. Voltage Levels for Timing Specifications
LTC2376-16
6
237616fa
For more information www.linear.com/LTC2376-16
TYPICAL PERFORMANCE CHARACTERISTICS
32k Point FFT fS = 250ksps,
fIN = 2kHz SNR, SINAD vs Input Frequency
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input level,
fIN = 2kHz
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code DC Histogram
OUTPUT CODE
–1.0
INL ERROR (LSB)
–0.2
0.0
0.2
0.4
0.6
0.8
–0.4
–0.6
–0.8
1.0
237616 G01
–32768 –16384 0 16384
32768
FREQUENCY (kHz)
0 25
125
1007550
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237616 G04
SNR = 97.1dB
THD = –125dB
SINAD = 97.1dB
SFDR = 128dB
OUTPUT CODE
–0.5
DNL ERROR (LSB)
0.4
0.3
0.2
0.1
0.0
–0.4
–0.3
–0.2
–0.1
0.5
237616 G02
–32768 –16384 0 16384
32768
CODE
σ = 0.15
0
COUNTS
40000
20000
100000
60000
120000
80000
140000
237616 G03
–2 1 0 1
2
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 250ksps, unless otherwise noted.
INPUT LEVEL (dB)
96.0
96.5
97.0
97.5
–40 –30 –20 –10
SNR
SINAD
REFERENCE VOLTAGE (V)
SNR, SINAD (dBFS)
98.0
97.0
97.5
237616 G08
94.0
94.5
95.0
95.5
96.0
96.5
2.5 3.0 3.5 4.0 4.5
5.0
SINAD
SNR
HARMONICS, THD (dBFS)
–100
–110
237616 G09
–150
–135
–140
–145
–130
–125
–120
–115
–105
THD
3RD
REFERENCE VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5
5.0
2ND
FREQUENCY (kHz)
SNR, SINAD (dBFS)
98.0
97.5
237616 G05
93.0
93.5
95.5
95.0
94.0
97.0
96.5
96.0
0 25 50 75 100
125
SNR
SINAD
FREQUENCY (kHz)
HARMONICS, THD (dBFS)
–80
237616 G06
–140
–130
–120
–110
–100
–90
0 25 50 75 100
125
3RD
2ND
THD
LTC2376-16
7
237616fa
For more information www.linear.com/LTC2376-16
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature
Shutdown Current vs Temperature CMRR vs Input Frequency
Reference Current
vs Reference Voltage
INL/DNL vs Temperature
Full-Scale Error vs Temperature Offset Error vs Temperature
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
REF = 5V, fSMPL = 250ksps, unless otherwise noted.
FREQUENCY (kHz)
0 604020 80 100
120
70
CMRR (dB)
85
80
75
100
95
90
237616 G17
0
REFERENCE CURRENT (mA)
0.08
0.06
0.02
0.04
0.18
0.16
0.14
0.12
0.1
237616 G18
REFERENCE VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5
5.0
TEMPERATURE (°C)
SNR, SINAD (dBFS)
98.0
237616 G10
96.0
96.5
97.0
97.5
–55 –35 –15 5 25 45 65 85 105
125
SINAD
SNR
TEMPERATURE (°C)
HARMONICS, THD (dBFS)
–110
237616 G11
–140
–135
–125
–130
–120
–115
–55 –35 –15 5 25 45 65 85 105
125
THD
2ND
3RD
TEMPERATURE (°C)
INL/DNL ERROR (LSB)
0.5
237616 G12
–0.5
–0.3
–0.1
0.1
0.3
–55 25 45 65–35 –15 5 85 105
125
MAX INL
MAX DNL
MIN DNL
MIN INL
TEMPERATURE (°C)
FULL-SCALE ERROR (LSB)
2.0
237616 G13
–2.0
0
1.0
0.5
1.5
–1.0
–0.5
–1.5
–55 4525–35 –15 5 8565 105
125
–FS
+FS
TEMPERATURE (°C)
POWER SUPPLY CURRENT (mA)
1.4
1.2
237616 G15
0
0.2
0.4
0.6
0.8
1.0
–55 –35 –15 5 25 45 65 85 105
125
IVDD
IREF
IOVDD
TEMPERATURE (°C)
OFFSET ERROR (LSB)
1.0
0.5
237616 G14
–1.0
–0.5
0
–55 –35 –15 5 25 45 65 85 105
125
TEMPERATURE (°C)
POWER-DOWN CURRENT (µA)
45
40
35
30
237616 G16
0
5
10
15
20
25
–55 –35 –15 5 25 45 65 85 105
125
IVDD + IOVDD + IREF
LTC2376-16
8
237616fa
For more information www.linear.com/LTC2376-16
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2376-16 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2376-16 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by 0VDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+, IN (Pins 4, 5): Positive and Negative Differential
Analog Inputs.
REF (Pin 7): Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47µF ceramic capacitor
(X5R, 0805 size).
REF/DGC (Pin 8): When tied to REF, digital gain compression
is disabled and the LTC2376-16 defines full-scale accord-
ing to the ±VREF analog input range. When tied to GND,
digital gain compression is enabled and the LTC2376-16
defines full-scale with inputs that swing between 10% and
90% of the ±VREF analog input range.
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by 0VDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by 0VDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy-chain is input. Logic levels are
determined by 0VDD.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by 0VDD.
SDO (Pin 14): Serial Data Output. The conversion result or
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by 0VDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1µF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTIONS
REF = 5V
LTC2376-16
IN
+
V
DD
= 2.5V
OVDD = 1.8V to 5V
IN
CHAIN
CNV
GND
BUSY
REF/DGC
SDO
SCK
RDL/SDI
CONTROL LOGIC
16-BIT SAMPLING ADC SPI
PORT
+
237616 BD01
LTC2376-16
9
237616fa
For more information www.linear.com/LTC2376-16
TIMING DIAGRAM
POWER-DOWNCONVERT
ACQUIREHOLD
D13D15 D14 D2 D1 D0
SDO
SCK
CNV
CHAIN, RDL/SDI = 0
BUSY
237616 TD01
Conversion Timing Using the Serial Interface
LTC2376-16
10
237616fa
For more information www.linear.com/LTC2376-16
OVERVIEW
The LTC2376-16 is a low noise, low power, high speed
16-Bit successive approximation register (SAR) ADC.
Operating from a single 2.5V supply, the LTC2376-16
supports a large and flexible ±VREF fully differential input
range with VREF ranging from 2.5V to 5.1V, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2376-16 achieves ±0.5LSB INL
max, no missing codes at 16 bits and 97dB SNR.
Fast 250ksps throughput with no cycle latency makes
the LTC2376-16 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the con-
version time, easing external timing considerations. The
LTC2376-16 dissipates only 3.4mW at 250ksps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
The LTC2376-16 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
CONVERTER OPERATION
The LTC2376-16 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN pins
to sample the differential analog input voltage. A rising
edge on the CNV pin initiates a conversion. During the
conversion phase, the 16-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 VREF/65536) using
the differential comparator. At the end of conversion, the
CDAC output approximates the sampled analog input. The
ADC control logic then prepares the 16-bit digital output
code for serial transfer.
APPLICATIONS INFORMATION
Figure 2. LTC2376-16 Transfer Function
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
237616 F02
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 – 1LSB
–FSR/2
FSR = +FS – –FS
1LSB = FSR/65536
TRANSFER FUNCTION
The LTC2376-16 digitizes the full-scale voltage of 2 × REF
into 216 levels, resulting in an LSB size of 152µV with
REF = 5V. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
RON
40Ω
CIN
45pF
RON
40Ω
REF
REF
CIN
45pF
IN
+
IN
BIAS
VOLTAGE
237616 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2376-16
ANALOG INPUT
The analog inputs of the LTC2376-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
shown in Figure 3. The diodes at the input provide ESD
protection. In the acquisition phase, each input sees ap-
proximately 45pF (CIN) from the sampling CDAC in series
with 40Ω (RON) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
the CIN capacitors during acquisition. During conversion,
the analog inputs draw only a small leakage current.
LTC2376-16
11
237616fa
For more information www.linear.com/LTC2376-16
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high im-
pedance inputs of the LTC2376-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2376-16. The ampli-
fier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC inputs draw.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
20Ω
3300pF
6600pF
20Ω
500Ω
LPF2
LPF1
BW = 600kHz
BW = 48kHz
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
SINGLE-ENDED-
INPUT SIGNAL
LTC2376-16
IN+
IN
237616
F04
6800pF
6800pF
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Single-Ended-to-Differential Conversion
For single-ended input signals, a single-ended to differential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2376-16. The LT
®
6350 ADC
driver is recommended for performing single-ended-to-
differential conversions. The LT6350 is flexible and may
be configured to convert single-ended signals of various
amplitudes to the ±5V differential input range of the
LTC2376-16. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2376-16 up to 125°C.
Figure 5a shows the LT6350 being used to convert a 0V
to 5V single-ended input signal. In this case, the first
amplifier is configured as a unity gain buffer and the single-
ended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5b,
the LT6350 drives the LTC2376-16 to near full data sheet
performance.
The LT6350 can also be used to buffer and convert large
true bipolar signals which swing below ground to the ±5V
differential input range of the LTC2376-16 in order to
maximize the signal swing that can be digitized. Figure6a
shows the LT6350 being used to convert a ±10V true bi-
polar signal for use by the LTC2376-16. In this case, the
first amplifier in the LT6350 is configured as an inverting
amplifier stage, which acts to attenuate and level shift the
input signal to the 0V to 5V input range of the LTC2376-16.
In the inverting amplifier configuration, the single-ended
input signal source no longer directly drives a high imped-
ance input of the first amplifier. The input impedance is
instead set by resistor RIN. RIN must be chosen carefully
based on the source impedance of the signal source.
Higher values of RIN tend to degrade both the noise and
distortion of the LT6350 and LTC2376-16 as a system.
Figure 4. Input Signal Chain
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noise contribution of the buffer and to help minimize distur-
bances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
LTC2376-16
12
237616fa
For more information www.linear.com/LTC2376-16
R1, R2, R3 and R4 must be selected in relation to RIN to
achieve the desired attenuation and to maintain a balanced
input impedance in the first amplifier. Table 1 shows the
resulting SNR and THD for several values of RIN, R1, R2,
R3 and R4 in this configuration. Figure 6b shows the re-
sulting FFT when using the LT6350 as shown in Figure 6a.
Table 1. SNR, THD vs RIN for ±10V Single-Ended Input Signal.
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
2k 499 499 2k 402 96.4 –101
10k 2.49k 2.49k 10k 2k 96.3 –92
100k 24.9k 24.9k 100k 20k 96.3 –98
Fully Differential Inputs
To achieve the full distortion performance of the
LTC2376-16, a low distortion fully differential signal source
driven through the LT6203 configured as two unity gain
buffers as shown in Figure 7 can be used to get the full
data sheet THD specification of –125dB.
APPLICATIONS INFORMATION
LT6350
R1 = 499Ω
R2 = 499Ω
R3 = 2k
R4 = 402Ω
VCM = VREF/2
V
CM
237616 F06a
OUT1
RINT RINT
RIN = 2k
OUT2
8
4
5
2
1
+
+
+
220pF
10µF
200pF
0V
5V
–10V
10V
0V
0V
5V
Digital Gain Compression
The LTC2376-16 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be be-
tween 10% and 90% of the ±VREF analog input range. To
enable digital gain compression, bring the REF/DGC pin
low. This feature allows the LT6350 to be powered off of
a single +5.5V supply since each input swings between
0.5V and 4.5V as shown in Figure 8. Needing only one
Figure 6a. LT6350 Converting a ±10V Single-Ended Signal
to a ±5V Differential Input Signal
Figure 6b. 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 6a
Figure 7. LT6203 Buffering a Fully Differential Signal Source
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237616 F06b
FREQUENCY (kHz)
0 25
125
1007550
SNR = 96.4dB
THD = –100.6dB
SINAD = 95.2dB
SFDR = 103.3dB
LT6203
237616 F07
0V
5V
0V
5V
31
2
+
0V
5V
57
6
+
0V
5V
LT6350
VCM = VREF/2
237616 F05a
0V
5V
0V
5V
OUT1
RINT RINT
OUT2
8
4
5
2
1
+
+
+
0V
5V
FREQUENCY (kHz)
0 25
125
1007550
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237616 F05b
SNR = 96.4dB
THD = –108.6dB
SINAD = 96dB
SFDR = 109.5dB
Figure 5a. LT6350 Converting a 0V-5V Single-Ended
Signal to a ±5V Differential Input Signal
Figure 5b. 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
LTC2376-16
13
237616fa
For more information www.linear.com/LTC2376-16
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237616 F09b
FREQUENCY (kHz)
0 25 50 75
125
100
SNR = 95.5dB
THD = –97.1dB
SINAD = 93.5dB
SFDR = 99.6dB
Figure 9b. 32k Point FFT Plot
with fIN = 2kHz for Circuit Shown
in Figure 9a
Figure 8. Input Swing of the LTC2376 with Gain
Compression Enabled
APPLICATIONS INFORMATION
positive supply to power the LT6350 results in additional
power savings for the entire system.
Figure 9a shows how to configure the LT6350 to accept a
±10V true bipolar input signal and attenuate and level shift
the signal to the reduced input range of the LTC2376-16
when digital gain compression is enabled. Figure 9b
shows an FFT plot with the LTC2376-16 being driven by
the LT6350 with digital gain compression enabled.
ADC REFERENCE
The LTC2376-16 requires an external reference to define
its input range. A low noise, low temperature drift refer-
ence is critical to achieving the full data sheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and
high accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2376-16. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications. The LTC6655-5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2376-16 up to 125°C. We recommend bypassing the
LTC6655-5 with a 47µF ceramic capacitor (X5R, 0805
size) close to the REF pin.
The REF pin of the LTC2376-16 draws charge (QCONV) from
the 47µF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
IREF = QCONV/tCYC. The DC current draw of the REF pin,
IREF, depends on the sampling rate and output code. If
the LTC2376-16 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSBs.
When idling, the REF pin on the LTC2376-16 draws only
a small leakage current (< 1µA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 10, IREF quickly goes from approximately
CNV
IDLE
PERIOD
IDLE
PERIOD
237616 F10
Figure 10. CNV Waveform Showing Burst Sampling
Figure 9a. LT6350 Configured to Accept a ±10V Input Signal While Running Off of a
Single 5.5V Supply When Digital Gain Compression Is Enabled in the LTC2376-16
237616 F08
5V
4.5V
0.5V
0V
LT6350
3.01k
4.32k
VCM
237616 F09a
OUT1
RINT RINT
RIN = 15k
OUT2
V
8
4
5
2
1
6
V+3
+
+
20Ω
3300pF
20Ω
6.04k
1k
VCM
1k
0.5V
4.5V
0.5V
4.5V
5V
5.5V
47µF
10µF
10µF
LTC2376-16
REF/DGC
IN+REF VDD
2.5V
IN
LTC6655-5VIN
VOUT_S
VOUT_F
–10V
10V
0V
6800pF
6800pF
LTC2376-16
14
237616fa
For more information www.linear.com/LTC2376-16
Figure 11. 32k Point FFT with fIN = 2kHz of the LTC2376-16
FREQUENCY (kHz)
0 25
125
1007550
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
237616 F11
SNR = 97.1dB
THD = –125dB
SINAD = 97.1dB
SFDR = 128dB
APPLICATIONS INFORMATION
0µA to a maximum of 0.2mA at 250ksps. This step in DC
current draw triggers a transient response in the reference
that must be considered since any deviation in the refer-
ence output voltage will affect the accuracy of the output
code. In applications where the transient response of the
reference is important, the fast settling LTC6655-5 refer-
ence is also recommended.
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2376-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 11 shows that the LTC2376-16 achieves
a typical SINAD of 97dB at a 250kHz sampling rate with
a 2kHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 11 shows
that the LTC2376-16 achieves a typical SNR of 97dB at a
250kHz sampling rate with a 2kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD=20log V22+V32+V42++ VN
2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
POWER CONSIDERATIONS
The LTC2376-16 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2376-16 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Power Supply Sequencing
The LTC2376-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2376-16
has a power-on-reset (POR) circuit that will reset the
LTC2376-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20µs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
LTC2376-16
15
237616fa
For more information www.linear.com/LTC2376-16
TIMING AND CONTROL
CNV Timing
The LTC2376-16 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up
the LTC2376-16. Once a conversion has been initiated,
it cannot be restarted until the conversion is complete.
For optimum performance, CNV should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion is
in progress. To ensure that no errors occur in the digitized
results, any additional transitions on CNV should occur
within 40ns from the start of the conversion or after the
conversion has been completed. Once the conversion has
completed, the LTC2376-16 powers down and begins
acquiring the input signal.
Acquisition
A proprietary sampling architecture allows the LTC2376-16
to begin acquiring the input signal for the next conver-
sion 527ns after the start of the current conversion. This
extends the acquisition time to 3.46µs, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2376-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 3µs.
Auto Power-Down
The LTC2376-16 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2376-16 as the sampling frequency is reduced.
Since power is consumed only during a conversion, the
LTC2376-16 remains powered-down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 12.
APPLICATIONS INFORMATION
DIGITAL INTERFACE
The LTC2376-16 has a serial digital interface. The flexible
OVDD supply allows the LTC2376-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
20MHz, a 250ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2376-16 is simple and
straightforward to use. The following sections describe the
operation of the LTC2376-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy-chained.
SAMPLING RATE (kHz)
0 50 100
250
200150
0
POWER SUPPLY CURRENT (mA)
1.0
0.8
0.4
0.2
0.6
1.6
1.4
1.2
237616 F12
IVDD
IREF IOVDD
Figure 12. Power Supply Current of the LTC2376-16
Versus Sampling Rate
LTC2376-16
16
237616fa
For more information www.linear.com/LTC2376-16
APPLICATIONS INFORMATION
Normal Mode, Single Device
When CHAIN = 0, the LTC2376-16 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance. If RDL/SDI is low, SDO is driven.
Figure 13 shows a single LTC2376-16 operated in normal
mode with CHAIN and RDL/SDI tied to ground. With RDL/
SDI grounded, SDO is enabled and the MSB(D15) of the
new conversion data is available at the falling edge of
BUSY. This is the simplest way to operate the LTC2376-16.
CNV
LTC2376-16
BUSY
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
SDO
SCK
237616 F13a
RDL/SDI
CHAIN
237616 F13
CONVERT CONVERT
tACQ
tACQ = tCYC – tHOLD
POWER-DOWNPOWER-DOWN
CNV
CHAIN = 0
BUSY
SCK
SDO
RDL/SDI = 0
tBUSYLH
tDSDOBUSYL
tSCK
tHSDO
tSCKH tQUIET
tSCKL
tDSDO
tCONV
tCNVH
tHOLD
ACQUIRE
tCYC
tCNVL
D15 D14 D13 D1 D0
1 2 3 14 15 16
ACQUIRE
Figure 13. Using a Single LTC2376-16 in Normal Mode
LTC2376-16
17
237616fa
For more information www.linear.com/LTC2376-16
APPLICATIONS INFORMATION
Normal Mode, Multiple Devices
Figure 14 shows multiple LTC2376-16 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2376-16 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 14,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO.
237616 F14a
RDLB
RDLA
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2376-16 SDO
A
SCK
RDL/SDI
CNV
LTC2376-16 SDO
B
SCK
RDL/SDI
CHAIN BUSY
CHAIN
237616 F14
D15A
SDO
SCK
CNV
BUSY
CHAIN = 0
RDL/SDIB
RDL/SDIA
D15BD14BD1BD0B
D13B
D14AD13AD1AD0A
Hi-Z Hi-ZHi-Z
tEN
tHSDO
tDSDO tDIS
tSCKL
tSCKH
tCNVL
1 2 3 14 15 16 17 18 19 30 31 32
tSCK
CONVERT
CONVERT
tQUIET
tCONV
tHOLD
tBUSYLH
POWER-DOWN
ACQUIRE ACQUIRE
POWER-DOWN
Figure 14. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
LTC2376-16
18
237616fa
For more information www.linear.com/LTC2376-16
APPLICATIONS INFORMATION
OVDD
237616 F15a
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2376-16
BUSY
SDO
B
SCK
RDL/SDI
CNV
LTC2376-16
SDO
A
SCK
RDL/SDI
CHAIN
OV
DD
CHAIN
Chain Mode, Multiple Devices
When CHAIN = OVDD, the LTC2376-16 operates in chain
mode. In chain mode, SDO is always enabled and RDL/SDI
serves as the serial data input pin (SDI) where daisy-chain
data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 15 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 16 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
237616 F15
D0A
D1A
D14A
D15A
D13B
D14B
D15B
SDOB
SDOA = RDL/SDIB
RDL/SDIA = 0
D0B
D1B
D13A
D14A
D15AD0A
D1A
1 2 3 14 15 16 17 18 30 31 32
tDSDOBUSYL
tSSDISCK
tHSDISCK
tBUSYLH
tCONV
tHOLD
tHSDO
tDSDO
tSCKL
tSCKH
tSCKCH
tCNVL
tCYC
CONVERT
CONVERT
SCK
CNV
BUSY
CHAIN = OVDD
tQUIET
POWER-DOWN
POWER-DOWN
ACQUIREACQUIRE
Figure 15. Chain Mode Timing Diagram
LTC2376-16
19
237616fa
For more information www.linear.com/LTC2376-16
BOARD LAYOUT
To obtain the best performance from the LTC2376-16
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital clocks
or signals alongside analog signals or underneath the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1783A, the
evaluation kit for the LTC2376-16.
Partial Top Silkscreen