1/53
AN1762
APPLICATION NOTE
December 2003
1 INTRODUCTION
The L6205, L6206, L6207 are highly integrated, mixed-signal power ICs that allow the user to easily design a
control system for two-phase bipolar stepper motors, multiple DC motors and a wide range of inductive loads.
Figu re 1 to Figu re 3 s how the L6205, L6206, L6207 block di agram s. Eac h IC integ rates eight Power DMOS plus
other added features for safe operation and flexibility. T he L6207 also features a constant t
OFF
PWM current
control technique (
Synchronous mode
) for each of the two full bridges.
Figure 1. L6205 block diagram.
D99IN1091A
GATE
LOGIC
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
V
BOOT
5V
10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
BRIDGE B
SENSE
B
OCD
A
OCD
B
by Vincenzo Marano
L6205, L6206, L6207 DUAL FULL BRIDGE DRIVERS
Modern motion control applications need more flexibility that can be addressed only with specialized IC
products. The L6205, L6206, L6207 are dual full bridge drivers ICs specifically developed to drive a wide
range of motors. These ICs are one-chip cost effective solutions that include sever al unique circuit design
features. These features allow the devices to be used in many applications including DC and stepper motor
drivi ng. The principal aim of this developm ent project was to produce easy to use, ful ly protected pow er ICs.
In addi tion se veral k ey functi ons s uch as protection circuit and PWM cur rent c ontrol dr astic ally reduce ex ter-
nal components count to meet requirements for many different applications.
AN1762 APP LICATION NOTE
2/53
Figure 2. L6206 block diagram.
Figure 3. L6207 block diagram.
D99IN1088A
GATE
LOGIC
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
V
BOOT
5V
10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
BRIDGE B
SENSE
B
PROGCL
B
OCD
B
OCD
A
PROGCL
A
OCD
A
OCD
B
D99IN1085A
GATE
LOGIC
OCD
A
OCD
B
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
VREF
A
V
BOOT
5V10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR ONE SHOT
MONOSTABLE MASKING
TIME
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
SENSE
COMPARATOR
BRIDGE B
RC
A
+
-
SENSE
B
VREF
B
RC
B
PWM
3/53
AN1762 APPLICATION NOTE
Table of Contents
1 INTRODUCTION................................................................................................................................1
2 MAIN DIFFERENCES BETW EEN L6205 , L6206, L6207 .... ................. ............ .............. ............... ....4
3 DES IGN ING AN A PPLICA TION WI TH L620 5, L6206 , L6207 ................ . ..................................... . ....4
3.1 Current Ratings........................................................................................................................4
3.2 Vol tage Ratings and Op erating Range .... ..................................... . ..................................... . ....4
3.3 Ch oosing the Bulk Capacitor. ..................................... . ..................................... . .......................6
3.4 Layout Consid erations .............................................................................................................7
3.5 Sensing Resistors...... ......................................................... .....................................................9
3.6 Charge pump external components... .... ................... ................... ................... ................... ....10
3.7 Shari ng the Charge Pump Circuitry .......................................................................................11
3.8 Reference Voltage fo r PWM Current Control (L6207 ONLY)............... . ................ ................. 12
3.9 Input Logic pins......................................................................................................................13
3.10 EN pins...................................................................................................................................13
3.11 Program mab le off-time Monost able (L6207 ON LY)............................................... . ..............14
3.11.1 Off-time Selection and minimum on-time (L6207 ONLY)................................................16
3.11.2 Slow Decay Mode (L6207 ONLY ) .......................................... .........................................17
3.12 Over Current Protectio n........................................................................................................18
3.13 Adjusting the Ove r Current Detection tri p point (L6206 ONLY) ............................................21
3.14 Paralleling two Full Bridges................................ . ................................ ..................................23
3.14.1 Paralleling t wo Ful l Bridges to get a single Full Bridge ....................................................23
3.14.2 Paralleling th e four Half Bridges to get a single Half Bridge.............................................26
3.15 Power Managem ent. ................ ........................ ..................... ................... . ............. ...............27
3.15.1 Maximum o utpu t current vs. selectable devices..............................................................27
3.15.2 P owe r Dissipation Formulae for different sequences.................... ................... . ..............28
4 APPLICATION EXAMPLE (L6207)..................................................................................................32
4.1 Decay mode, sensing resistors and reference voltage..........................................................32
5 APPE N DIX - EVAL UATION BOARDS.. ........................................................ ...................................33
5.1 PractiSPIN..............................................................................................................................33
5.2 EVAL6205N ...........................................................................................................................34
5.2.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....35
5.3 EVAL6206N ...........................................................................................................................39
5.3.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....40
5.4 EVAL6206PD.........................................................................................................................44
5.4.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....45
5.5 EVAL6207N ...........................................................................................................................49
5.5.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....50
6 REFERENCES.................................................................................................................................53
AN1762 APP LICATION NOTE
4/53
2 MAIN DIFFERENC ES BETWE EN L6205, L6206, L6207
L6205, L6206 and L6207 are DMOS Dual Full Bridge ICs.
L6205 (see F igure 1) includes logic for CMOS/TTL interface, a charge pump that provide auxiliary voltage to
drive the high-side DMOS, non dissipative over current protection circuitry on the high-side DMOS, with fixed
trip point set at 5.6 A (see
Over Current Protection
Section), over tem perat ure protection, Under Voltage Lock-
Out for reliable start-up.
In addition, L6206 gives the possibility of adjusting the trip point of the over current protection for each of the
two full-bridges (through two external resistors), and its internal open-drain mosfets (see
Over Current Protec-
tion
S ecti on) are not internal ly connecte d to
EN
pins but to separat e
OCD
pins,
allo wing easier e xternal diagnos-
ti cs and overcurrent managem ent.
L6207 has Over Current protection function with fixed trip point set at 5.6 A and internal open-drain mosfets
connected to
EN
pins, as the L6205, but it also integrates tw o PWM current controller for each of the two full-
bridges (see
Programmable off-time Monostable
section).
3 DESIGNI NG AN APPLICATION WITH L6205, L6206, L6207
3.1 Current Ratings
With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first ap-
prox imation, limited by the R
DS(ON)
of the DMOS themselves and could reach very high values. L6205, L6206,
L6207
Out
pins and the two V
SA
and V
SB
pins are rated for a maximum of 2.8A r.m.s. and 5.6A peak (typical
values), corresponding to a total (for the whole IC) 5.6A rms ( 11.2A peak). These values are meant to avoid
damaging metal structures, including the metallization on the die and bond wires. In practical applications,
though, maximum allowable current is less than these values, due to power dissipation limits (
see
Power
Management
section
). The devices have a built-in Over Current Detection (OCD) that provides protection
against short circuits between the outputs and between an output and ground (
see
Over Current Protection
section
).
3.2 Voltage Ratin gs an d Operat ing Range
The L6205, L6206, L6207 requires a single suppl y voltage (V
S
), for the motor supply . Internal voltag e regu lators
provide the 5V and 10V required for the internal circuitry. The operating range for V
S
is 8 to 52V. To prevent
working into undesir abl e low supply voltage an
Under Voltage Loc k Out
(
UVLO
) circuit shuts down the device
when supply voltage falls below 6V; to resume normal operating condi tions, V
S
must then exceed 7V. The hys-
teresis is provided to avoid false intervention of the UVLO function during fast V
S
ringings. It should be noted,
however, that DMOS's R
DS(ON)
is a function of the V
S
supply voltage. Actually, when V
S
is less than 10V,
R
DS(ON)
is adversely affected, and this is particularly true for the High Side DMOS that are driven from V
BOOT
supply. This supply is obtained through a charge pump from the internal 10V supply, which will tend to reduce
its output voltage when V
S
goes below 10V. Figure 4 shows the supply voltage of the high side gate drivers
(V
BOOT
- V
S
) versus the supply voltage (V
S
).
5/53
AN1762 APPLICATION NOTE
Figure 4. High side gate drivers sup ply voltage versu s sup ply voltage.
Note that V
S
must be c onnected to both V
SA
and V
SB
since the bootstrap voltage (at V
BOOT
pin) i s the same for
the tw o H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60V. However V
S
should be kept below 52V, since in normal working conditions the DMOS see a V
ds
voltage that will exceed V
S
supply. In par tic ular, during a phase change ( when each output of the same H-bridge sw itches from V
S
to GND
or vice versa, for example to reverse the current in the load) at the beginning of the dead-time (when all the
DMOS are off) the
SENSE
pin sees a negative spike due to a not negligible parasitic inductance of the PCB
path from the pin to G ND. This spike is followed by a stable negative voltage due to the drop on R
SENSE
. One
of the two
OUT
pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forw ard
reco very time of the integrated freewheeling di ode and the forward voltage drop acr oss it (see Figure 5). Typical
durati on of this spike is 30ns . At the same time, the other
OUT
pin of the sam e bridge sees a vol tage above V
S
,
due to the PCB in ductance and v oltage drop acr oss the h igh-side (integr ated) freewheeling diode, as the current
rever ses direction and flows into the bulk capacitor . It turns out that the highest differential voltage can be ob-
served between the two
OUT
pins of the same bridge, during the dead-time at a phase change, and this must
always be kept below 60V [3].
Figure 5. Currents and voltages d uri ng the
dead tim e
at a pha se chan ge.
VS [V]
VBOOT - VS
[V]
6
6.4
6.8
7.2
7.6
8
8 8.5 9 9.5 10 10.5
V
S
SENSE
OUT1
OUT2
RSENSE*I
RSENSE*I+VF(Diode)
PC B Pa r a s i ti c
Inductance
PCB Parasitic
Inductance
Bulk Capacitor
Equivalent Circuit
ESR
ESL
RSENSE
VS+VF(Diode)
Dangerous
High Differential Voltage
AN1762 APP LICATION NOTE
6/53
Figu re 6 shows the voltage waveforms at the two OUT pins r eferring to a pos sible practical situation, w ith a peak
output current of 2.8A, V
S
= 52V, R
SENSE
= 0.33
Ω
, T
J
= 25°C (approximately) and a good PCB layout. B elow
ground spike amplitude is -2.65V for one output; the other
OUT
pin is at about 57V . In these conditions, total
differ ential v oltage reaches almost 60V, which is the a bsolute max imum rating for the DMOS. Keeping differ en-
tial voltage between two Output pins belonging to the same Full Bridge within rated values is a must that can
be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), accord-
ing to current peaks and chopping style and adopting good layout practices to minimize PCB parasitic induc-
tances (see below) [3].
Figu re 6. V ol ta ge a t th e tw o outputs during the
dead time
at a pha se chan ge.
3.3 Choosing the Bulk Capacitor
Sinc e the bulk capacitor, placed between V
S
and
GND
pi ns, is char ged and discharged during IC operation, its
AC current capability
must be greater than the r.m.s. value of the charge/discharge current. In the case of a
PWM current regulation, the current flows from the capacitor to the IC during the on-time (t
ON
) and from the IC
(implementing a fast decay current recirculation technique) or from the power supply (implementing a slow de-
cay current recirculation technique) to the capacitor during the off-time (t
OFF
). The r.m.s. value of the current
flowing into the bulk capacito r depends on peak output current, output current rippl e, sw itchin g frequency, duty-
cycle and chopping style. It also depends on power supply characteristics. A power supply with poor high fre-
quency performances (or long, inductive connections to the IC) will cause the bulk capacitor to be recharged
slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s.
current in the capacitor, however, does not exceed the r.m.s. output current. Bulk capacitor value (
C
) and the
ESR
determine the amount of voltage ripple on the capacitor itself and on the IC. In slow decay, neglecting the
dead-time
and output cur rent ripple, and assuming that during the
on-time
the capacitor is not recharged by the
power supply, the voltage at the end of the
on-time
is:
,
so the supply voltage ripple is:
,
Out 2
Out 1
VSIOUT
–ESR tON
C
---------+
⋅
I
OUT ESR tON
C
---------+
⋅
7/53
AN1762 APPLICATION NOTE
where I
OUT
is the outp ut current. Wit h f ast decay, i nstead, recirculating current r echarges the capacitor, caus ing
the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is
close to the maximum recommended supply voltage (52V). In fast decay the supply voltage ripple is about:
,
always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple
and the dead-tim e. Usually (if C > 100 µF) the capacitance role is much less than the ESR, then supply v oltage
ripple can be estimated as:
I
OUT
· ESR in slow decay
2 · I
OUT
· ESR in fast decay
For Example, i f a maximum r i pple of 500mV is all owed and I
OUT
= 2A, the capac itor ESR should be low er than:
in slow decay, and
in fast decay.
Actually, cur rent sunk by V
SA
and V
SB
pins of the device is subject to higher peaks due to reverse recovery
charge of internal freewheeling diodes. D uration of these peaks is, tough, very short, and can be filtered using
a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the V
SA
, V
SB
and GND pins of the IC. Bulk capac itor will be chosen with
maximum operating voltage
25% gr eater than the
maximum supply voltage, considering also power supply tolerances. For example, with a 48V nominal pow er
supply, with 5% tol eranc e, maximum voltage is 50.4V, then operati ng voltage for the capacitor s hould be at l east
63V.
3.4 Layout Considerations
Working with devices that combine high power switches and control logic in the same IC, careful attention has
to be paid to the PCB lay out. In extreme cases, Power DM OS commutati on can i nduce nois es that could c ause
improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt
paths, or cond ucted through G ND or Supply connectio ns. Logic connec tions, es pecial ly hi gh-i mpedance nodes
(act ually all logic inputs, see further ), must be kept far from switching nodes and paths. With the L6205, L6206,
L6207, in particular , external components for the charge pump circuitry should be connected together through
short paths, since these components are subject to voltage and current switching at relatively high frequency
(600kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 7).
IOUT 2 ESR⋅tON tOFF
+
C
----------------------------+
⋅
ESR 0.5V
2A
------------
<250mΩ=
ESR 1
2
--- 0.5V
2A
------------
⋅< 125mΩ=
AN1762 APP LICATION NOTE
8/53
Figu re 7. Typical Applicat i on an d Layou t su ggestions .
High cur rent GN D tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the
negative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typi-
cally a 100nF ÷200nF ceramic would suffice), since electrolytic capacitors show a poor high frequency perfor-
manc e. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to
V
SA
, V
SB
and GND. On the L6205, L6206 , L6207 GND pins are the
Logic
GND, since onl y the quiescent cur rent
flows through them. Logic GND and Pow er GND should be connected together in a
single point
, the bulk ca-
pacitor, to keep noise in the Power GND fr om affecting Logic GN D. Specific car e should be paid layouting the
path from the
SENSE
pins through the sensing resistor s to the negative terminal of the bulk capacitor (Power
Ground) . These tracks must be as short as possible in order to minimize parasitic inductances that can cause
danger ous voltage spikes on
SENSE
and
OUT
pins (see the
Voltage Ratings and Operating Range
section);
for the same reason the capacitors on V
SA
, V
SB
and G ND should be very close to the GND and supply pins.
Refer to the Sensing Resistors section for information on selecting the sense resistors. Traces that connect to
V
SA
, V
SB
, SENSE
A
, SENSE
B
, and the four
OUT
pins must be designed with adequate width, since high currents
are flowing through these traces, and layer changes should be avoided. Should a layer change prove neces-
sary, multiple and large via holes have to be used. A wide GND copper area can be used to improve power
dissipation for the device.
Figu re 8 shows two typical situations that must be avoided. An important considerati on about the location of the
bulk capaci t ors is the abi lity to abs orb the inductiv e energy fr om the load, without all owing the s upply voltage to
exceed the maximum rating. The diode shown in Figure 8 prevents the recirculation current from reaching the
capacitor s and will result in a hi gh voltage on the IC pins th at can destroy the device. H aving a switch or a power
connection that c an dis connect the c apacitors fr om the IC, w hile there is still cur rent in the motor, will a lso result
in a high voltage transient since there is no capacitance to absorb the recirculation current.
+
-
VS = 8 ÷ 52 V
GND
GND GND
GND
SENSEA
SENSEB
VSA VSB
VBOOT CP
OUT1B OUT2B
OUT1A OUT2A
D1 D2
R1
RS1 RS2
C3
C4
C1
C2
L 6205, L6206, L6207
Motors or
other loads
Logic
GND
9/53
AN1762 APPLICATION NOTE
Figure 8. Two situations that must be avoided.
3.5 Sensing Resistors
Each motor winding current is flowing through the corr esponding sensing resistor, causing a voltage dr op that
can be used, by the logic (integrated in the L6207; an external logic can be used with L6205 and L6206), to
control the peak value of the load current. Two issues must be taken into account when choosing the R
SENSE
value:
– The sensing resistor dissipates energy and provides dangerous negative voltages on the
SENSE
pin
during the current recirculation. For thi s reason the resistance of this c om pon ent shoul d be kept l ow.
– The voltage drop across RSENSE is compared with a reference voltage (on Vref pin) by the internal c om-
parator (L6 207 only). The lo wer is the RSENSE value, the higher is the peak curre nt error du e t o noise
on Vref pin and to the input offs et of the current sense comparator: too small values of RSENSE must be
avoided.
A good compromis e i s calculating the sensi ng res istor value so that the voltage drop, corresponding to the peak
current in the load (I
peak
), is about 0.5 V: R
SENSE
= 0.5 V / I
peak
.
It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous neg-
ative spik es on
SENSE
pins. Wire-w ounded resistor s c annot be used here, whi le Metall ic film res istors ar e rec-
ommended for their high peak current capability and low inductance. For the same reason the connections
between the
SENSE
pins, C6, C7, V
SA
, V
SB
and
GND
pins (see Figure 7) must be taken as short as possible
(see also the
Layout Considerations
section).
The average power dissipated by the sensing resistor is:
Fast Decay Recirculation: P
R
≈
I
rms2
· R
SENSE
Slow Decay Recir culation: P
R
≈
I
rms2
· R
SENSE
· D,
D is the duty-cycle of the PWM current control, I
rms
is the r.m.s. value of the load current.
GND
GND
GND
GND
SENSE
A
SENSE
B
V
SA
V
SB
R5
C7
C6
L6205, L6206, L6207
DON ’T conne ct the Logi c GND h ere
Voltage drop du e to current in s ens e
path can dis turb lo gic GND.
DON’T put a di ode here!
Rec ircul ating c urrent c ann ot flo w i nto t he
bulk c apaci t or and causes a high v olt age
spike that c an des troy the IC .
+
-
V
S
= 8 ÷ 52 V
AN1762 APP LICATION NOTE
10/53
Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissi-
pated power:
,
where I
pk
is the peak value of the load current.
Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and re-
duce the inductance.
R
SENSE
tolerance reflects on the peak current error: 1% resistors should be preferred.
The following table show s R
SENSE
recommended values (to ha ve 0.5V d rop on it) and power ratings for typical
examples of current peak values.
3.6 Charge pump external components
An internal oscillator, with its output at
CP
pin, switches from GND to 10V w ith a typical frequency of 600kHz
(see Figure 9).
Figu re 9. Cha rge Pum p .
When the oscillator output is at ground, C
5
is charged by V
S
through D
2
. When it rises to 10V, D
2
is rev er se
biased and the charge flows from C
5
to C
8
through D
1
, so the V
BOOT
pin, after a few cycles, reaches the max-
imum voltage of V
S
+ 10V - V
D1
- V
D2
, which supplies the high-side gate drivers.
With a differenti al vol tage betw een V
S
and V
BOOT
of about 9V and both the bridges swit ching at 50kHz, the typ-
ical current drawn by the V
BOOT
pin is 1.85 mA.
Ipk RSENSE Value
[Ω]
RSENSE Power Rating
[W] Alternatives
0.5 1 0.25
1 0.5 0.5 2 X 1Ω, 0.25W paralleled
1.5 0.33 0.75 3 X 1Ω, 0.25W paralleled
2 0.25 1 4 X 1Ω, 0.25W paralleled
PRIpk2RSENSE
⋅≈
L6205, L6206, L6207
VS + 10 V - VD1
VS - VD1
f = 600 kHz
VSA VSB
VBOOT CP
D1 D2
R4
C8
C5
RDS(ON) = 70Ω
10 V
10 V
5 V
RDS(ON) = 70Ω
To High-Side
Gate Drivers
10 V
f = 600 kHz
Charge Pump
Oscillator
VS + 10 V - VD1 - VD2
11/53
AN1762 APPLICATION NOTE
Resistor
R4
is added to r educe the maxi mum cur rent i n the external components and to r educe the slew r ate of
the rising and falling edges of the voltage at the
CP
pin, in order to minimize interferences w ith the rest of the
cir cuit. For the same reason care must be taken in r ealiz ing the PC B layout of
R4
,
C5
,
D1
,
D2
connections ( see
also the
Layout Considerations
section). Recommended values for the charge pump circuitry are:
D1, D2 : 1N4148
R4 : 100
Ω (1/8 W)
C5 : 10nF 100V ceramic
C8 : 220nF 25V ceramic
Due to the high charge pump frequency, fast diodes ar e requi red. C onnecting the cold side of the bulk capacitor
(C8) to V
S
instead of GND the average current in the external diodes during operation is less than 10 mA (with
R4 = 100
Ω
); at startup ( when V
S
is provided to the IC) is less than 200 mA while the reverse voltage is about
10 V in all condi tions. 1N4148 diodes withstand about 200 mA DC (1 A peak ), and the maximum reverse v oltage
is 75 V, so they should fit for the majority of applications.
3.7 Sharing the Charge Pump Circuitry
If more than one device is used in the application, it's possible to use the charge pump from one L6205, L6206
or L6207 to supply the V
BOOT
pins of several ICs. The unused
CP
pins on the slaved devices are left uncon-
nected, as shown in Figure 10. A 100nF capacitor (C8) should be connected to the V
BOOT
pin of each device.
Supply voltage pins (V
S
) of the devices sharing the charge pump must be connected together.
The higher the number of devices sharing the same char ge pump, the lowe r will be the d ifferential voltage avail-
able for gate drive (V
BOOT
- V
S
), causing a higher R
DS(ON)
for the high s ide DMO S, s o higher dissipating po wer .
In this case it's recommended to omit the resistor on the
CP
pin, obtaining a higher current capability of the
charge pump circuitry.
Better per formance can als o be obtained using a 33nF capacitor for C5 and using s chottky diodes (for ex ample
BAT47 are recommended).
Sharing the same char ge pump ci rcuitr y fo r more than 3÷4 devices is not r ecommended, sinc e it wil l reduce the
V
BOOT
voltage increasing the high-side MOS on-resistance and thus power dissipation.
Figu re 10 . Sha r in g th e c harge pu m p cir c ui tr y.
V
SA
V
SB
V
BOOT
CP
C18 = 100 nF
To High-Side
Gate Drivers
V
SA
V
SB
V
BO OT
C8 = 100nF
To High-Side
Gate Dr iver s
To other Devi ces
CP
L6205, L6206, L6207
L6205, L6206, L6207
D1 = BAT47 D2 = BAT47
C5 = 33nF
AN1762 APP LICATION NOTE
12/53
3.8 Reference Voltage for PWM Current Control (L6207 ONLY)
The L6207 has two analog inputs, V
refA
and V
refB
, connected to the internal sense comparators, to control the
peak val ue of the motor current thr ough th e integrated PWM circuitry . In ty pical applic ations these p ins ar e con-
nected together , in order to obtain the same cur rent i n the two m otor windings. A fixed referenc e vol tage can be
easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC
or the rest of the application) and GND.
A very simple way to obtain a var iable voltage without using a DAC is to low-pass filter a PWM output of a µC
(see Figure 11).
Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be:
where D
µC
is the duty-cycle of the PWM output of the µC.
Assuming that the µC output impedance is lower than 1k
Ω,
with R
LP
= 56k
Ω
, R
DIV
= 15k
Ω
, C
LP
= 10nF and a
µC PW M switchi ng fr om 0 to 5V at 100kHz, the low pass fi lter tim e consta nt is about 0.12 ms an d the remai ning
ripple on the V
re f
voltage will be about 20 mV. Using higher values for R
LP
, R
DIV
and C
LP
will reduce the ripple,
but the reference voltage w ill take mor e time to vary after changing the duty -cycle of the µC PWM, and too high
values of R
LP
will als o increase the im pedance of the V
ref
net at low frequen cies, causing a poor nois e immunity.
As sensing resistor values are typically kept small, a small noise on V
ref
input pins might cause a considerable
error in the output cur rent. It's then recomm ended to decouple these pins with cerami c capaci tors of some tens
of nF, placed very close to V
ref
and GND pins. Note that V
ref
pins cannot be left unconnec ted, while, if connected
to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to c ut down
(IC) power consumption and clear the load current is pulling down the
EN
pins. With very small reference volt-
age, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of t
ON
(see
the
Programmable off-time Monostable
section).
Figure 11. Obtaining a vari able voltage thr ough a PW M outpu t of a µC.
Vref 5V DµCRDIV
⋅⋅
R
LP RDIV
+
-----------------------------------------=
RLP
CLP
Vref
GND
PWM Output
of a µC
RDIV
13/53
AN1762 APPLICATION NOTE
3.9 I np ut Log ic pins
IN1
A
, IN2
A
, I N 1
B
, IN2
B
are CM OS /TTL compa tible logic i nput pins . The input comparator has been realized with hys-
ter esis t o ensure t he require d noise i mmuni ty. Typ ical val ues for tur n-on and t urn-of f thresh olds ar e V
th,ON
= 1.8V and
V
th,OFF
= 1.3 V. Pins are ESD protected (s ee Figure 12 ) (2kV human- body electro- static discharge), and can be d irectly
connec ted to the logi c outp uts of a µC; a ser ies resis tor is gen erall y not r ecommende d, as i t could hel p induct ed nois e
to di sturb the inputs . All l ogi c pins e nforce a specifi c behavior and cannot be left unconnect ed.
Figure 12. Logic i nput pins.
3.1 0EN pi ns
The
EN
A
, EN
B
pins are, ac tually, bi-directional: as an input, with a comparator similar to the other logic input pins (TTL/
CMOS with hysteresis), they control t he stat e of the PowerDMOS. When each of the t wo pins i s at a l ow logic level,
al l the PowerDMOS of the cor responding H-bridge (A or B) are t urned off. In L6205 and L6207 the EN pins are also
connected to the two corresponding open drain outputs of the pr otect ion circuits that will pull the pins to GND if over
current in the corresponding H-bridge or over temperature conditions exist. In L6206 the open drain output s are on
separate pi ns, O C D
A
and OCD
B
, al lowing eas ie r external di agnostic s and overcur rent management. For th is reason,
with L6205 and L6207 (and L6206 if EN pins are connected to DIAG pins) EN pins must be driven through a series
resistor of 2.2k
Ω
m i nimum (for 5V logic), t o allow the voltag e at the pin t o be pulled below the turn-o ff thr eshold.
A capacitor (C
EN
in Fi gure 13) connec ted between each EN pin and GND is also r ecommended, to reduce the r.m.s.
value of the output cur rent when overcurrent conditions persi st (see
Over Current Protection
section). EN pin must
n ot be left unconnected.
Figure 13. ENA and ENB in put pi ns.
5V
D01IN1329
ESD
PROTECTION
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
A
or EN
B
OCD
A
or OCD
B
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
A
or EN
B
EN
A
or EN
B
L6205, L6207 L6206
AN1762 APP LICATION NOTE
14/53
3.11 Programmab le off-time Monostab le (L6207 ONL Y)
The L6207 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be-
tween the source of the two lower power MOS transistors and ground, as shown in Figure 14. As the current in
the load builds up the voltag e across the sens e re sistor increases pr oportionally . When the voltage drop ac ross
the sense resistor becomes greater than the voltage at the reference input (VREF
A
or VRE F
B
) the sense com-
parator triggers the monostable switc hing the low-side MOS off. The low-side MOS remain off for the time set
by the monostable and the motor current recirculates in the upper path. When the monostable times out the
bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays
the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 14. PWM Current Control Circuitry (L6207 ONLY).
Figure 15 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the R C pin voltage and the status of the bridge. Immediately after the low-side Power MOS turns on, a
high peak current flow s through the sen sing resistor due to the rev ers e recovery of the freewheeling diodes . The
L620 7 provides a 1
µs
Blanki ng Time t
BLANK
that inhibits the com parator output s o that this current spike cannot
prematurely re-trigger the monostable.
DRIVERS
+
DEAD TIME
S
Q
RDRIVERS
+
DEAD TIME
2H 1H
2L 1L
OUT2A(or B)
SENSEA(or B)
RSENSE
D02IN1352
RCA(or B)
ROFF
COFF
VREFA(or B)
IOUT
OUT1A(or B)
+
+
-
-
1µs
5mA
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
MONOSTABLE
RESET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
LOADA
(or B)
BLANKING TIME
MONOSTABLE
VSA (or B)
TO GATE LOGIC
(0) (1)
15/53
AN1762 APPLICATION NOTE
Figure 15. PWM Output Current Regulatio n Waveforms (L6207 ONLY).
Figur e 16 shows the magnitude of the Off Time t
OFF
versus C
OFF
and R
OFF
values. It can be approximately
calculated from the equations:
t
RCFALL
= 0.6 · R
OFF
· C
OFF
t
OFF
= t
RCFALL
+ t
DT
= 0.6 · R
OFF
· C
OFF
+ t
DT
where R
OFF
and C
OFF
are the external component values and t
DT
is the internally generated Dead Time with:
20K
Ω
≤
R
OFF
≤
100K
Ω
0.47nF
≤
C
OFF
≤
100nF
t
DT
= 1µs (typical value)
Therefore:
t
OFF(MIN)
= 6.6µs
t
OFF(MAX)
= 6ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
The capacitor value chosen for C
OFF
also affects the Ri se Time t
RCRISE
of the voltage at the pin RC
A
(or RC
B
).
The Rise Time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time t
ON
, which depends by motors and supply parameters, has to
OFF BCDDA
t
ON
t
OFF
BC
ON
2.5V
0Slow Decay Slow Decay
1µs t
BLANK
t
RCRISE
t
RCRISE
SYNCHRONOUS RECTIFICATION
1µs t
BLANK
5V
V
RC
V
SENSE
V
REF
I
OUT
V
REF
R
SENSE
D02IN1351
t
OFF
1µs t
DT
1µs t
DT
t
RCFALL
t
RCFALL
AN1762 APP LICATION NOTE
16/53
be bigger than t
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
ON
can not be smaller than the minimum on time t
ON(MIN)
.
t
RCRISE
= 600 · C
OFF
3.11.1 Off-time Selection and minim um on-time (L6207 ONLY)
Figur e 16 also shows the lower limit for the on time t
ON
for having a good PWM current regulation capacity. It
has to be said that t
ON
is always bigger than t
ON(MIN)
because the device imposes this condition, but it can be
smaller than t
RCRISE
- t
DT
. In this last case the device continues to work but the off time t
OFF
is not more con-
stant.
So, small C
OFF
value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for C
OFF
, the more influential will be the noises on the cir cuit
performance.
Figure 16. Off-time selection and minimum on-time (L6207 ON LY).
tON tON MIN()
>1.5µs (typ. value )=
tON tRCRISE tDT
–>
0.1 1 10 100
1
10
100
1.10 3
1.10 4
Co ff [nF]
to f f [us]
0.1 1 10 100
1
10
100
Coff [nF]
to n ( m in ) [ u s]
R = 20 k
Ω
R = 47 k
Ω
R = 100 kΩ
17/53
AN1762 APPLICATION NOTE
3.11.2 Slow Decay Mode (L6207 ONLY)
Figu re 17 s hows the operation of the bridge i n the Sl ow De cay mode. At the start of the off ti me, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the s ynchro-
nous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 17. Slow Decay Mode Output Stage Configuration s
In some conditions (short off-time, ver y low regulated current, high motor winding L / R) the system may need
an on-time shorter than 1.5µs. In these cases the PWM current controller can loose the regulation.
Figur e 18 shows the operation of the circuit in this condition. W hen the current first reaches the threshold, the
brid ge is turned off for a fixed time and the cur rent decays. During the foll owing on-ti me current increases above
the threshold, but the bridge cannot be turned off until the minimum 1.5µs on-time expires. Since current in-
crea ses more i n ea ch o n-ti me th an i t dec ays during the o ff-time, it keeps growing during each cycle, wi th s teady
state asymptotic value set by duty- cycle and load DC resistance: the resulting peak current will be
I
pk
= V
S
· D / R
LOAD
,
where D = t
ON
/ (t
ON
+ t
OFF
) is the duty-cycle and R
LOAD
is the load DC resistance.
Figure 18. Minimum on-time can cause the PWM controll er to loose the regulation ( L6207 ONLY).
A) ON TIME B) 1µs DEAD TIME C) SYNCHRONOUS
RECTIFICATION D) 1µs DEAD TIME
D01IN1336
needed tON is
less
than 1.5 µs
minimum t
ON
is about 1.5 µs
Vref / RSENSE
AN1762 APP LICATION NOTE
18/53
3.12 Over Current Protection
To implement an Over C urre nt (i.e. short ci rcuit) Protection, a dedicated Over Current D etection (OCD) cir c uitry
(see Figu re 19 for a simpli fied schematic) senses the current in each high side. P ower DMO S are actuall y made
up with thousands of individual identical cells, each carrying a fraction of the total current flow ing. The current
sensing element, connected in par allel to the Power DMOS, is made onl y w ith few such cells , havi ng a 1:N ratio
compared to the power DMOS. The total drain current is split between the output and the sense element ac-
cording to the cell ratio. Sensed current is, then, a small fraction of the output current and will not contribute
significantly to power dissipation.
Figure 19. Over Curren t Detection si mplified ci rcuitry.
+
OVER
TEMPERATURE
I
REF
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
ENA
R
ENA
R
CLA
.
EN
A
OCD
A
PROGCL
A,
+5V
1.2V
-
+
µC or LOGIC
+
OVER TEMPERATURE
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
EN
R
EN
EN
A
+5V
µC or LOGIC
L6206
L6205, L6207
19/53
AN1762 APPLICATION NOTE
This sensed cur rent is co mpared to an inter nall y generated reference ( adj ustable through the exter nal resi stors
R
CLA
and
R
CLB
for L6206) to detec t an over cur rent conditi on. A n i nternal open drain mosfet turns on when the
sum of the currents in the bridges 1A and 2A or 1B and 2B reaches the threshold (5.6A typical value for L6205
and L6207; adjus table through the external resistors
R
CLA
and
R
CLB
for L6206); in L6205 and L6207 the open
drai n are internally c onnected to the
EN
pins; with L6206
OCD
pins s hould be c onnected to
EN
pins to allow the
protection w orking. To ensure an over current protection, connect these pins to an external R C network (see
Figure 19).
Figur e 20 shows the device operating in overcurrent condition (short to ground). When an over current is de-
tected the internal open drain mosfet pull the
EN
pin to GND switching off all 4 pow er DMOS of the interested
bridge and allowing the cur rent to decay. Under a persistent over current condition, like a short to ground or a
shor t between two output pins, the external RC network on the
EN
pin (see Figure 19) reduces the r.m.s. value
of the output curr ent by imposing a fixed disable-time after each over cur rent occurrence. The values of
R
EN
and
C
EN
are se lected to ens ure proper operation of the dev ice under a shor t circui t conditi on. When the curr ent
flowing through the hi gh side DMOS reac hes the OCD threshold (5.6 A typ. for L6205 and L6207, adjustable for
L6206), after an internal propagation delay (t
OCD(ON)
) the open drain starts discharging
C
EN
. When the
EN
pin
voltage falls below the tur n-off thr eshold (V
TH(OFF)
) all the Pow er D MOS turn off after the internal propagation
delay ( t
D(OFF)EN
). The c urrent begins to decay as it ci rculates throu gh the freewheeling diodes. Since the DMOS
are
off
, there is no current flowing through them and no current to sense so the O CD circuit, after a short delay
(t
OCD(OFF)
), switches the internal open drain device off, and
R
EN
can charge
C
EN
. When the voltage at
EN
pin
reaches the turn-on threshold (V
TH(ON)
), after the t
D(ON)EN
delay, the DMOS turn on and the current restarts.
Even if the maximum output current can be very high, the external RC network provides a disable time (t
DISABLE
)
to ensure a safe r.m.s. value (see Figure 20).
Figure 20. Over Current Operation.
The maximum value reached by the current depends on its slew-rate, so on the short circuit nature and supply
voltage, and on the total intervention delay (t
DELAY
). It can be noticed that after the first current peak, the max-
imum value reached by the output current becomes lower, because the capacitor on
EN
pins is discharged start-
ing from a lower voltage, resulting in a shorter t
DELAY
.
The following approximate relatio ns estimate the disable time and the first OCD intervention delay after the short
circuit (worst case).
EN
O ut p ut Cu rrent
VTH(OFF)
tD(OFF)EN
IS OVER
tOCD(ON)
tDIS ABLE
tOC D(OFF)
tDELAY
tEN(FALL)
tEN(RIS E)
VEN(LOW)
EN
Ou tp ut Curr ent
tDISAB LE
VTH(ON )
tD(ON)EN
AN1762 APP LICATION NOTE
20/53
The time the device remains disabled is:
where
V
EN(LOW)
is the minimum voltage reached by the
EN
pin, and can be estimated with the relation:
The total intervention time is
where
t
OCD(OFF)
, t
OCD(ON)
, t
D(ON)EN
, t
D(OFF)EN
, and R
OPDR
are device intrinsic parameters, V
DD
is the pull-up voltage
applied to R
EN
.
The external RC network, C
EN
in par ticular, must be chosen obtaining a r easonable fast OCD intervention (short
t
DELAY
) and a safe dis able ti me (long t
DISABLE
). Figure 21 show s both t
DISABLE
and t
DELAY
as a function of C
EN
:
at least 100µs for t
DISABLE
are recommended, keeping the delay time below 1÷2µs at the same time.
The internal open drain can als o be turned on if the device experiences an
over temperature
(OVT) condition.
The OVT will cause the device to shut down when the die temperature exceeds the OVT threshold
(T
J
>165 °C typ.). S ince the OVT is also connected directly to the gate drive circuits (see Figure 1 to Figure 3),
all the Power DMOS will shut down, even if
EN
pin voltage is still over V
th(OFF)
. When the junction temperature
falls be low the OVT turn-off threshold ( 150 °C ty p.), the open drai n turn off,
C
EN
is recharged up to V
TH(ON)
and
then the PowerDMOS are turned on back.
ENONDRISEENOFFOCDDISABLE tttt )()()( ++=
)(
)(
)( ln
ONTHDD
LOWENDD
ENENRISEEN VV
VV
CRt −
−
⋅⋅=
ENOPDR
OFFOCDENOFFD CR
tt
OFFTHLOWEN eVV ⋅
+
−
⋅= )()(
)()(
ENOFFDFALLENONOCDDELAY tttt )()()( ++=
)(
)( ln
OFFTH
DD
ENOPDRFALLEN VV
CRt ⋅⋅=