1PS9023A 11/20/09
Block Diagram
PI6C49003
Networking Clock Generator
Features
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal such as Saronix-eCera™ SRX7278
• Five PCIe® 100MHz outputs with optional -0.5% spread
spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 48-pin TSSOP package
Description
The PI6C49003 is a clock generator device intended for PCIe®/
networking applications. The device includes fi ve 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe,
two single-ended 50 MHz outputs, one single-ended 32.256MHz
output, and one selectable single-ended 33/66/133 MHz output.
Using a serially programmable SMBUS interface, the PI6C49003
incorporates spread spectrum modulation on the fi ve 100 MHz
HCSL PCIe outputs, and independent frequency margining on the
50MHz output, 33.3333MHz and 66.6666MHz clock outputs.
Pin Confi guration
VDD
14
5100M_OUT(0-4)
50M_OUT(1-2)
33/66/133M_OUT1
32.256M_OUT1
ISET
475 Ohms
1%
GND
10
PD_RESET
SDATA
SCLK
PLL, Dividers,
Buffers, and
Logic
Clock Buffer/
Crystal
Oscillator
25 MHz
crystal or
clock input
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
IREF
NC
NC
VDD
VDD
GND
GND
VDD
GND
VDD
SCLK
SDATA
GND
50M_Out1
50M_Out2
VDD
GND
VDD
32.256M_Out1
GND
NC
NC
PD_RESET
GND
VDD
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDD
GND
VDD
100M_Q2+
100M_Q2-
100M_Q3+
100M_Q3-
VDD
GND
VDD
100M_Q4+
100M_Q4-
33/66/133M_Out1
VDD
GND
VDD
X2
X1
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PI6C49003
Networking Clock Generator
Pin Description
Pin # Pin Name Pin Type Pin Description
1V
DD Power 3.3V Supply Pin
2 IREF Output Connect to 475-Ohm resistor to set HCSL output drive current
3 NC No connect. Leave open
4 NC No connect. Leave open
5V
DD Power 3.3V Supply Pin
6V
DD Power 3.3V Supply Pin
7 GND Power Ground
8 GND Power Ground
9V
DD Power 3.3V Supply Pin
10 GND Power Ground
11 VDD Power 3.3V Supply Pin
12 SCLK Input SMBus compatible input clock. Supports fast mode 400kHz input clock.
13 SDATA I/O SMBus compatible data line
14 GND Power Ground
15 50M_Out1 Output 50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-
Ohm pull-down.
16 50M_Out2 Output 50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-
Ohm pull-down.
17 VDD Power 3.3V Supply Pin
18 GND Power Ground
19 VDD Power 3.3V Supply Pin
20 32.256M_Out1 Output 32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal
110k-Ohm pull-down.
21 GND Power Ground
22 NC
23 NC
24 PD_RESET Input Power down reset - when low all PLL's are powered down and outputs tristated.
SMBus registers are reset to default values.
25 X1 Input Crystal input. Integrated 6pF capacitance
26 X2 Output Crystal output. Integrated 6pF capacitance
27 VDD Power 3.3V Supply Pin
28 GND Power Ground
29 VDD Power 3.3V Supply Pin
30 33/66/133M_Out1 Output 33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has
a nominal 110k-Ohm pull-down.
31 100M_Q4- Output 100MHz HCSL output
32 100M_Q4+ Output 100MHz HCSL output
33 VDD Power 3.3V Supply Pin
34 GND Power Ground
35 VDD Power 3.3V Supply Pin
(Continued)
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Networking Clock Generator
Pin # Pin Name Pin Type Pin Description
36 100M_Q3- Output 100MHz HCSL output
37 100M_Q3+ Output 100MHz HCSL output
38 100M_Q2- Output 100MHz HCSL output
39 100M_Q2+ Output 100MHz HCSL output
40 VDD Power 3.3V Supply Pin
41 GND Power Ground
42 VDD Power 3.3V Supply Pin
43 100M_Q1- Output 100MHz HCSL output
44 100M_Q1+ Output 100MHz HCSL output
45 100M_Q0+ Output 100MHz HCSL output
46 100M_Q0- Output 100MHz HCSL output
47 VDD Power 3.3V Supply Pin
48 GND Power Ground
33/66/100MHz Frequency Margining Table
FS6 FS5 FS4 33M/66M/133M_OUT1
0 0 0 33.3333 MHz
0 0 1 66.6666MHz +2%
0 1 0 66.6666MHz +1%
0 1 1 66.6666MHz +0%
1 0 0 66.6666MHz -2%
1 0 1 66.6666MHz -4%
1 1 0 66.6666MHz -6%
1 1 1 133.3333 MHz
50MHz Frequency Margining Table
FS3 FS2 FS1 FS0 50M_OUT1, 50M_OUT2
0 0 0 0 nominal
0 0 0 1 nominal + 1%
0 0 1 0 nominal + 2%
0 0 1 1 nominal + 3%
0 1 0 0 nominal + 4%
0 1 0 1 nominal + 5%
0 1 1 0 nominal + 6%
0 1 1 1 nominal + 8%
1 0 0 0 nominal + 10%
1 0 0 1 nominal - 1%
1 0 1 0 nominal - 2%
1 0 1 1 nominal - 3%
1 1 0 0 nominal - 4%
1 1 0 1 nominal - 6%
1 1 1 0 nominal - 8%
1 1 1 1 nominal - 10%
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PI6C49003
Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49003 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0010/1
How to Write
1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit
Start
bit d2H Ack Register
offset Ack Byte
Count = N Ack Data Byte
0Ack … Data Byte
N - 1 Ack Stop bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Byte 0: Spread Spectrum Control Register
Bit Description Type Power Up
Condition Output(s)
Affected Notes
7Spread Spectrum Selection for 100 MHz HCSL
PCI-Express clocks RW 0 All 100MHz HCSL
PCI Express outputs
0=spread off
1 = -0.5% down
spread
6Enables hardware or software control of OE bits
(see Byte 0–Bit 6 and Bit 5 Functionality table) RW 0 PD_RESET pin,
bit 5 0 = hardware cntl
1 = software ctrl
5Software PD_RESET bit. Enables or disables all
outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table) RW 1 All outputs 0 = disabled
1 = enabled
4 Frequency margining select bit FS3 RW 1
50M_Out1 and
50M_Out2
See 50MHz Fre-
quency Select Table
on Page 3
3 Frequency margining select bit FS2 RW 0
2 Frequency margining select bit FS1 RW 1
1 Frequency margining select bit FS0 RW 0
0 OE for single-ended 50 MHz output 50M_Out2 RW 1 Single-ended
50MHz output
50M_Out2
0 = disabled
1 = enabled
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit 8
bits 1 bit 8
bits 1 bit 1 bit 8
bits 1 bit 8
bits 1 bit 8
bits 1 bit … 8
bits 1 bit 1 bit
M:
Start
bit
M:
Send
"D2h"
S:
sends
Ack
M:
send
start-
ing
data-
byte
loca-
tion:
N
S:
sends
Ack
M:
Start
bit
M:
Send
"D3h"
S:
sends
Ack
S:
sends
# of
data
bytes
that
will
be
sent:
X
M:
sends
Ack
S:
sends
start-
ing
data
byte
N
M:
sends
Ack …
S:
sends
data
byte
N+X-
1
M: Not
Ac-
knowl-
edge
M:
Stop
bit
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PI6C49003
Networking Clock Generator
Byte 1: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 OE for 32.256M_Out1 RW 1 32.256M_Out1 0 = disabled
1 = enabled
6 OE for 50M_Out1 RW 1 50M_Out1 0 = disabled
1 = enabled
5 OE for 33/66/133M_Out1 RW 1 33/66/133M_Out1 0 = disabled
1 = enabled
4 Reserved R W 1 Not Applicable
3 to 0 Reserved RW 0 Not Applicable
Byte 2: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 Frequency margining select bit FS6 RW 1
33/66/133M_Out1 See 33/66/100MHz
Frequency Select
Table on Page 3
6 Frequency margining select bit FS5 RW 0
5 Frequency margining select bit FS4 RW 0
4 to 0 Reserved R Undefi ned Not Applicable
Byte 3: Control Register
Bit Description Type Power Up Con-
dition Output(s) Affected Notes
7 OE for 100M_Q4 HCSL Output RW 0 100M_Q4 0 = disabled
1 = enabled
5 OE for 100M_Q3 HCSL Output RW 0 100M_Q3 0 = disabled
1 = enabled
4 OE for 100M_Q2 HCSL Output RW 0 100M_Q2 0 = disabled
1 = enabled
2 OE for 100M_Q1 HCSL Output RW 1 100M_Q1 0 = disabled
1 = enabled
1 OE for 100M_Q0 HCSL Output RW 1 100M_Q0 0 = disabled
1 = enabled
3, 6 Reserved RW 0 Not Applicable
0 Reserved R Undefi ned Not Applicable
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6 Bit 5 Description
0XPD_RESET HW pin/signal = enabled
10Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
11Enable all outputs, PD_RESET HW pin/signal = DON'T CARE
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PI6C49003
Networking Clock Generator
Byte 4: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 to 0 Reserved R Undefi ned Not Applicable
Byte 5: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 Revivsion ID bit 3 R 0 Not Applicable
6 Revivsion ID bit 2 R 0 Not Applicable
5 Revivsion ID bit 1 R 0 Not Applicable
4 Revivsion ID bit 0 R 0 Not Applicable
3 Vendor ID bit 3 R 0 Not Applicable
2 Vendor ID bit 2 R 0 Not Applicable
1 Vendor ID bit 1 R 1 Not Applicable
0 Vendor ID bit 0 R 1 Not Applicable
Byte 6: Control Register
Bit Description Type Power Up Condi-
tion Output(s) Affected Notes
7 to 0 Reserved R Undefi ned Not Applicable
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Networking Clock Generator
DC Electrical Characteristics
Unless otherwise specifi ed, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Parameter Symbol Conditions Min Typ Max Units
Operating Supply Volt-
age VDD 3.0 3.6
V
Input High Voltage VIH 2V
DD
Input Low Voltage VIL –0.3 0.8
Input High Voltage VIH SDATA, SCLK 0.7VDD VDD
Input Low Voltage VIL SDATA, SCLK 0.3VDD
Operating Supply Cur-
rent IDD 150 mA
IDD at Output Disable
Condition PD_RESET = 0 5
Internal Pull-Up/Pull-
Down Resistor RPU/RPD
PD_RESET 240 k–Ohm
All single-ended outputs 110
Input Capacitance CIN All input pins 6 pF
Absolute Maximum Ratings1 (Over operating free-air temperature range)
Symbol Parameters Min. Max. Units
VDD 3.3V I/O Supply Voltage -0.5 4.6
VVIH Input High Voltage 4.6
VIL Input Low Voltage -0.5
Ts Storage Temperature -65 150 °C
VESD ESD Protection 2000 V
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Maximum Supply Voltage, VDD ............................................................ 7V
All Inputs and Outputs ...............................................–0.5V to VDD +0.5V
Ambient Operating Temperature .......................................–40°C to +85°C
Storage Temperature ........................................................–65°C to +150°C
Junction Temperature ........................................................................125°C
Peak Soldering Temperature..............................................................260°C
Note:
Stresses greater than those listed under MAX I MUM RAT-
INGS may cause permanent damage to the de vice. This is
a stress rating only and func tion al op er a tion of the device
at these or any other conditions above those indicated in
the operational sections of this spec i fi ca tion is not implied.
Exposure to absolute max i mum rating con di tions for ex-
tended periods may affect re li abil i ty.
Maximum Ratings
(Above which useful life may be impaired. For user guide lines, not tested.)
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Networking Clock Generator
Electrical Characteristics - Single-Ended
Unless otherwise specifi ed, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
Parameter Symbol Conditions Min Typ Max Units
Input Clock Frequency FIN 25 MHz
SCLK Frequency 100 400 kHz
Min. pulse width of
PD_RESET Input 100 ns
Output Frequency
Error FS0, FS6 = 0 0 ppm
Output Frequency
Error 32.256MHz 7
Output Rise/Fall Time tr, tfVDD=3.3V, 0.8V to 2.4V 0.5 1 ns
Output Clock Duty
Cycle Measured at VDD/2 45 50 55 %
High-Level Output
Voltage VOH IOH = -4mA VDD-0.4
High-Level Output
Voltage VOH IOH = -8mA 2.4 V
Low-Level Output
Voltage VOL IOL = 8mA 0.4
Peak-to-Peak Jitter 50 MHz clock output 140 200
ps
33/66/133MHz clock output 125 175
32.256 MHz clock output 115 150
Cycle-to-Cycle Jitter 50 MHz clock output 120 175
33/66/133 MHz clock output 120 160
Clock Stabilization
Time from Power Up 310ms
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Networking Clock Generator
Parameter Symbol Conditions Min Typ Max Units
Output Frequency 100 MHz
Cycle-to-Cycle Jitter TCC/Jitter 150 ps
Peak-to-Peak Phase Jitter Using PCIe jitter measure-
ment method 86
Spread Modulation Percentage -0.5 0 %
Spread Modulation Frequency 32 kHz
Duty Cycle TDC 45 50 55 %
Rising Edge Rate Note 3, 4 0.6 4.0 V/ns
Falling Edge Rate Note 3, 4 0.6 4.0
Output Skew TOSKEW VT = 50%(measurement
threshold) 200 ps
Clock Source DC Impedance,
single ended ZC-DC 50 Ohm
High-Level Output Voltage VOH Note 2, (RS=33-Ohm,
RT=50-Ohm) 0.65 0.71 0.85
V
Low-Level Output Voltage VOL –0.20 0 0.05
IOH @ 6*IREF IOH –13 –14.2 –17 mA
Absolute Crossing Point Voltage VCROSS Note 2, 5, 6 0.25 0.55 V
Variation of VCROSS over all ris-
ing clock edges VCROSS Delta Note 2, 5, 8 140 mV
Average Clock Period Accuracy TPERIOD AVG Note 3, 9, 10 –300 2800 ppm
Absolute Period (including jitter
and spread spectrum) TPERIOD ABS Note 3, 7 9.847 10.203 ns
(Continued)
Electrical Characteristics - 100MHz Differential HCSL Outputs
Unless otherwise specifi ed, VDD=3.3V±10%, Ambient Temperature –40°C to +85°C
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PI6C49003
Networking Clock Generator
Notes:
1. Measured at the end of an 8-inch trace with a 5pF load.
2. Measurement taken from a single-ended waveform.
3. Measurement taken from a differential waveform.
4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the
measurement region for rise and fall time. The 300 mV measurement window is centered on the differen-
tial zero crossing.
5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the
falling edge 100M–.
6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is cross-
ing. Refers to all crossing points for this measurement.
7. Defi nes as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter,
relative PPM tolerance, and spread spectrum modulation.
8. Defi ned as the total variation of all crossing voltages of rising 100M+ and falling 100M–.
9. Refer to section 4.3.2.1 of the PCI Express Base Specifi cation, Revision 1.1 for information regarding
PPM considerations.
10. PPM refers to parts per million and is a DC absolute period accuracy specifi cation. 1 PPM is 1/1,000,000th
of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz.
The period is measured with a frequency counter with measurement window set at 100 ms or greater. With
spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an ad-
ditional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread.
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PI6C49003
Networking Clock Generator
Confi guration test load board termination for HCSL Outputs
Rs
337
5%
Rs
337
5%
Rp
49.97
1%
4757
1%
Rp
49.97
1%
2pF
5% 2pF
5%
Clock#
Clock
TLA
TLB
PI6C49003
Figure 4. Confi guration Test Load Board Termination
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PI6C49003
Networking Clock Generator
Ordering Information(1-3)
Ordering Code Package Code Package Description
PI6C49003AE A 48-pin, Pb-free & Green, TSSOP, (A48)
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffi x = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
.236
.244
.488
.496
.002
.006
SEATING PLANE
.007
.010
.0197
BSC
.004
.008
.319
1
48
12.4
12.6
6.0
6.2
0.50 0.17
0.27 8.1
0.05
0.15
0.09
0.20
X.XX
X.XX DENOTES DIMENSIONS
IN MILLIMETERS
.018
.030
0.45
0.75
.047
1.20 Max
BSC
DOCUMENT CONTROL NO.
PD - 1501
REVISION: G
DATE: 03/09/05
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru-
sions and gate burrs shall not exceed 0.15mm per side.
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion
shall not exceed 0.25mm per side. DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
See Note 3
See Note 4
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
All trademarks are property of their respective owners.
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