AK4397EQP - AKM Semiconductor

[AK4397]

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GENERAL DESCRIPTION

The AK4397 is a high performance premium 32bit DAC for the 192kHz sampling mode of DVD-Audio

including a 32bit digital filter. Using AKM's multi bit architecture for its modulator the AK4397 delivers a

wide dynamic range while preserving linearity for improved THD+N performance. The AK4397 has full

differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for

systems with excessive clock jitter. The AK4397 accepts 192kHz PCM data and 1-bit DSD data, ideal for

a wide range of applications including DVD-Audio and SACD. The AK4397 has a functional compatibility

with the AK4393/4/5 and lower power dissipation.

FEATURES

• 128x Over sampling

• Sampling Rate: 30kHz ∼ 216kHz

• 32Bit 8x Digital Filter (Slow-roll-off option)

Ripple: ±0.005dB, Attenuation: 75dB

• High Tolerance to Clock Jitter

• Low Distortion Differential Output

• DSD data input available

• Digital De-emphasis for 32, 44.1, 48kHz sampling

• Soft Mute

• Digital Attenuator (Linear 256 steps)

• THD+N: −103dB

• DR, S/N: 120dB

• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD

• Master Clock: Normal Speed: 256fs, 384fs, 512fs, 768fs or 1152fs

Double Speed: 128fs, 192fs, 256fs or 384fs

Quad Speed: 128fs or 192fs

DSD: 512fs or 768fs

• Power Supply: 4.75 ∼ 5.25V

• TTL Level Digital I/F

• Package: 44pin LQFP

AK4397

High Performance Premium 32-Bit DAC

[AK4397]

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■ Block Diagram

LRCK/DSDR

SDATA/DSDL

BICK/DCLK

AOUTR-

Control Regi ster

CSN

PCM

Data

Interface

DIF1/DSDL

DIF2/DSDR

DIF0/DCLK DSD

Data

Interface

8X

Interpolator

8X

Interpolator

ΔΣ

Modulator

ΔΣ

Modulator

SCF

AOUTR+

AOUTL-

AOUTL+

CAD0

CAD1

CCLK CDTI P/S MCLK

VREFHR

Clo ck Divi d e r VREFLR

TST1/DZFL

ACKS

PDN SMUTE DFS0

De-emphasis

DATT

Soft Mute

De-emphasis

DATT

Soft Mute

DVDD VSS4 VSS3AVDD VDDL VSS2

DEM0

De-emphasis

Control

DEM1

VREFLH VREFLL

VDDR

VSS1

Block Diagram

[AK4397]

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■ Ordering Guide

AK4397EQ −10 ∼ +70°C 44pin LQFP (0.8mm pitch)

AKD4397 Evaluation Board for AK4397

■ Pin Layout

AOUTLP

AOUTLN

34

NC

33

35

NC 36

NC 37

NC 38

NC 39

VSS3 40

AVDD 41

MCLK 42

VSS4 43

NC 44

VSS2 32

VDDL 31

VREFHL 30

VREFLL 29

NC 28

VREFLR 27

VREFHR

26

VDDR 25

VSS1 24

AOUTRN 23

DVDD 1

PDN 2

BICK/DCL

K

3

SDATA/DSDL 4

LRCK/DSD

R

5

SMUTE/CSN 6

DFS0/CAD0 7

DEM0/CCL

K

8

DEM1/CDT1 9

DIF0/DCL

K

10

DIF1/DSDL 11

22

21

20

19

18

17

16

15

14

13

12

A

OUTRP

NC

TST2/CAD1

TST1/DZFL

A

CKS/DZFR

P/S

NC

DIF2/DSDR

AK4397EQ

Top View

[AK4397]

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PIN/FUNCTION

No. Pin Name I/O Function

1 DVDD - Digital Power Supply Pin, 4.75 ∼ 5.25V

2 PDN I

Power-Down Mode Pin

When at “L”, the AK4397 is in power-down mode and is held in reset.

The AK4397 should always be reset upon power-up.

BICK I Audio Serial Data Clock Pin in PCM Mode

3 DCLK I DSD Clock Pin in DSD mode

SDATA I Audio Serial Data Input Pin in PCM Mode

4 DSDL I DSD Lch Data Input Pin in DSD Mode

LRCK I L/R Clock Pin in PCM Mode

5 DSDR I DSD Rch Data Input Pin in DSD Mode

SMUTE I

Soft Mute Pin in Parallel Mode

When this pin goes “H”, soft mute cycle is initiated.

When returning “L”, the output mute releases.

6

CSN I Chip Select Pin in Serial Mode

DFS0 I Sampling Speed Mode Select Pin in Parallel Mode (Internal pull-down pin)

7 CAD0 I Chip Address 0 Pin in Serial Mode (Internal pull-down pin)

DEM0 I De-emphasis Enable 0 Pin in Parallel Mode

8 CCLK I Control Data Clock Pin in Serial Mode

DEM1 I De-emphasis Enable 1 Pin in Parallel Mode

9 CDTI I Control Data Input Pin in Serial Mode

DIF0 I Digital Input Format 0 Pin in PCM Mode

10 DCLK I DSD Clock Pin in DSD Mode

DIF1 I Digital Input Format 1 Pin in PCM Mode

11 DSDL I DSD Lch Data Input Pin in DSD Mode

DIF2 I Digital Input Format 2 Pin in PCM Mode

12 DSDR I DSD Rch Data Input Pin in DSD Mode

13 NC - No internal bonding.

Connect to GND.

Note: All input pins except internal pull-up/down pins should not be left floating.

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14 P/S I Parallel/Serial Select Pin (Internal pull-up pin)

“L”: Serial Mode, “H”: Parallel Mode

ACKS I Master Clock Auto Setting Mode Pin in Parallel Mode

15 DZFR O Rch Zero Input Detect Pin in Serial Mode

TST1 O

Test 1 Pin in Parallel Mode

Should be open.

16

DZFL O Lch Zero Input Detect Pin in Serial Mode

TST2 I

Test 2 Pin in Parallel Mode (Internal pull-down pin)

Connect to GND.

17

CAD1 I Chip Address 1 Pin in Serial Mode (Internal pull-down pin)

18 NC - No internal bonding.

Connect to GND.

19 NC - No internal bonding.

Connect to GND.

20 NC - No internal bonding.

Connect to GND.

21 NC - No internal bonding.

Connect to GND.

22 AOUTRP O Rch Positive Analog Output Pin

23 AOUTRN O Rch Negative Analog Output Pin

24 VSS1 - Ground Pin

25 VDDR - Rch Analog Power Supply Pin, 4.75 ∼ 5.25V

26 VREFHR I Rch High Level Voltage Reference Input Pin

27 VREFLR I Rch Low Level Voltage Reference Input Pin

28 NC - No internal bonding.

Connect to GND.

29 VREFLL I Lch Low Level Voltage Reference Input Pin

30 VREFHL I Lch High Level Voltage Reference Input Pin

31 VDDL - Lch Analog Power Supply Pin, 4.75 ∼ 5.25V

32 VSS2 - Ground Pin

33 AOUTLN O Lch Negative Analog Output Pin

34 AOUTLP O Lch Positive Analog Output Pin

35 NC - No internal bonding.

Connect to GND.

36 NC - No internal bonding.

Connect to GND.

37 NC - No internal bonding.

Connect to GND.

38 NC - No internal bonding.

Connect to GND.

39 NC - No internal bonding.

Connect to GND.

40 VSS3 - Ground Pin

41 AVDD - Analog Power Supply Pin, 4.75 ∼ 5.25V

42 MCLK I Master Clock Input Pin

43 VSS4 - Ground Pin

44 NC - No internal bonding.

Connect to GND.

Note: All input pins except internal pull-up/down pins should not be left floating.

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■ Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

(1) Parallel Mode (PCM Mode only)

Classification Pin Name Setting

AOUTLP, AOUTLN These pins should be open.

Analog AOUTRP, AOUTRN These pins should be open.

SMUTE This pin should be connected to VSS4.

TST1 This pin should be open.

Digital

TST2 This pin should be connected to VSS4.

(2) Serial Mode

1. PCM Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins should be open.

Analog AOUTRP, AOUTRN These pins should be open.

DIF2, DIF1, DIF0 These pins should be connected to VSS4.

Digital DZFL, DZFR These pins should be open.

2. DSD Mode

• In case of using #3(DCLK), #4(DSDL) and #5(DSDR) pins

Classification Pin Name Setting

AOUTLP, AOUTLN These pins should be open.

Analog AOUTR+, AOUTR− These pins should be open.

DCLK(#10), DSDL(#11), DSDR(#12) These pins should be connected to VSS4.

Digital DZFL, DZFR These pins should be open.

• In case of using #10(DCLK), #11(DSDL) and #12(DSDR) pins

Classification Pin Name Setting

AOUTLP, AOUTLN These pins should be open.

Analog AOUTRP, AOUTRN These pins should be open.

DCLK(#3), DSDL(#4), DSDR(#5) These pins should be connected to VSS4.

Digital DZFL, DZFR These pins should be open.

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ABSOLUTE MAXIMUM RATINGS

(VSS1-4 = 0V; Note 1)

Parameter Symbol min max Unit

Power Supplies:

Analog

Digital

AVDD

VDDL/R

DVDD

−0.3

6.0

V

Input Current, Any pin Except Supplies IIN - ±10 mA

Digital Input Voltage VIND −0.3 DVDD+0.3 V

Ambient Temperature (Power applied) Ta −10 70 °C

Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

Note 2. VSS1-4 must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS1-4 =0V; Note 1)

Parameter Symbol min typ max Unit

Power Supplies:

(Note 3)

Analog

Digital

AVDD

VDDL/R

DVDD

4.75

5.0

5.25

V

Voltage Reference

(Note 4)

“H” voltage reference

“L” voltage reference

VREFH-VREFL

VREFHL/R

VREFLL/R

Δ VREF

AVDD-0.5

VSS

3.0

-

AVDD

-

AVDD

V

Note 1. All voltages with respect to ground.

Note 3. The power up sequence between AVDD and DVDD is not critical.

Note 4. Analog output voltage scales with the voltage of (VREFH − VREFL).

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp× (VREFHL/R − VREFLL/R)/5.

* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

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ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS; Input data=24bit;

RL ≥ 1kΩ; BICK=64fs; Input Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth =

20Hz ~ 20kHz; External Circuit: Figure 18; unless otherwise specified.)

Parameter min typ max Unit

Resolution - - 24 Bits

Dynamic Characteristics (Note 5)

fs=44.1kHz

BW=20kHz

0dBFS

−60dBFS

-

−103

−57

−93

-

dB

fs=96kHz

BW=40kHz

0dBFS

−60dBFS

-

−100

−54

-

dB

THD+N

fs=192kHz

BW=40kHz

BW=80kHz

0dBFS

−60dBFS

−100

−54

−51

-

dB

Dynamic Range (−60dBFS with A-weighted) (Note 6) 114 120 dB

S/N (A-weighted) (Note 7) 114 120 dB

Interchannel Isolation (1kHz) 100 110 dB

DC Accuracy

Interchannel Gain Mismatch - 0.15 0.3 dB

Gain Drift (Note 8) - 20 - ppm/°C

Output Voltage (Note 9) ±2.65 ±2.8 ±2.95 Vpp

Load Capacitance - - 25 pF

Load Resistance (Note 10) 1 - - kΩ

Power Supplies

Power Supply Current

Normal operation (PDN pin = “H”)

AVDD + VDDL/R

DVDD (fs ≤ 96kHz)

DVDD (fs = 192kHz)

-

32

21

27

47

-

41

mA

Power down (PDN pin = “L”) (Note 11)

AVDD+DVDD

-

10

100

μA

Power Supply Rejection (Note 12) - 50 - dB

Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.

Note 6. By Figure 18. External LPF Circuit Example 2.101dB at 16bit data and 118dB at 20bit data.

Note 7. By Figure 18. External LPF Circuit Example 2. S/N does not depend on input bit length.

Note 8. The voltage on (VREFHL/R − VREFLL/R) is held +5V externally.

Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R − VREFLL/R).

AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.

Note 10. Regarding Load Resistance, AC load is 1 kΩ (min) with DC cut capacitor. Please refer to Figure 18. DC load is

1.5kΩ (min) without DC cut capacitor. Please refer to Figure 17. Load Resistance value defines apposite to

ground voltage. Analog performance is sensitive to capacitive load that is connected output pin. Therefore

capacitive load must be minimized.

Note 11. In the power-down mode. P/S pin = DVDD, and all other digital input pins including clock pins

(MCLK, BICK and LRCK) are held VSS4.

Note 12. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFHL/R pin is held +5V.

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SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bi =“0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 13)

±0.01dB

−6.0dB

PB

0

-

22.05

20.0

-

kHz

Stopband (Note 13) SB 24.1 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 14) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 20.0kHz - ±0.2 - dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit=“0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 13)

±0.01dB

−6.0dB

PB

0

-

48.0

43.5

-

kHz

Stopband (Note 13) SB 52.5 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 14) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 40.0kHz - ±0.3 - dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“0”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 13)

±0.01dB

−6.0dB

PB

0

-

96.0

87.0

-

kHz

Stopband (Note 13) SB 105 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 75 dB

Group Delay (Note 14) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response : 0 ∼ 80.0kHz - +0/−1 - dB

Note 13. The passband and stopband frequencies scale with fs. For example, PB = 0.4535×fs (@±0.01dB), SB =

0.546×fs.

Note 14. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of

both channels to input register to the output of analog signal.

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SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 15)

±0.04dB

−3.0dB

PB

0

-

18.2

8.1

-

kHz

Stopband (Note 15) SB 39.2 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 72 dB

Group Delay (Note 14) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 20.0kHz - +0/−5 - dB

SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; DEM=OFF; SLOW bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 15)

±0.04dB

−3.0dB

PB

0

-

39.6

17.7

-

kHz

Stopband (Note 15) SB 85.3 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 72 dB

Group Delay (Note 14) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 40.0kHz - +0/−4 - dB

SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”)

Parameter Symbol min typ max Unit

Digital Filter

Passband (Note 15)

±0.04dB

−3.0dB

PB

0

-

79.1

35.5

-

kHz

Stopband (Note 15) SB 171 kHz

Passband Ripple PR ±0.005 dB

Stopband Attenuation SA 72 dB

Group Delay (Note 14) GD - 28 - 1/fs

Digital Filter + SCF

Frequency Response: 0 ∼ 80.0kHz - +0/−5 - dB

Note 15. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.

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DC CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V)

Parameter Symbol min typ max Unit

High-Level Input Voltage

Low-Level Input Voltage

VIH

VIL

2.4

-

0.8

V

High-Level Output Voltage (Iout = −100μA)

Low-Level Output Voltage (Iout = 100μA)

VOH

VOL

DVDD−0.5

-

0.5

V

Input Leakage Current (Note 16) Iin - - ±10 μA

Note 16. DFS0 and P/S pins have internal pull-up devices, nominally 100kΩ. Therefore DFS0 pin and P/S pin are not

included.

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SWITCHING CHARACTERISTICS

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)

Parameter Symbol min typ max Unit

Master Clock Timing

Frequency

Duty Cycle

fCLK

dCLK

7.7

40

41.472

60

MHz

%

LRCK Frequency (Note 17)

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

Duty Cycle

fsn

fsd

fsq

Duty

30

54

108

45

54

108

216

55

kHz

%

PCM Audio Interface Timing

BICK Period

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

BICK Pulse Width Low

BICK Pulse Width High

BICK “↑” to LRCK Edge (Note 18)

LRCK Edge to BICK “↑” (Note 18)

SDATA Hold Time

SDATA Setup Time

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/128fn

1/64fd

1/64fq

30

20

ns

DSD Audio Interface Timing

DCLK Period

DCLK Pulse Width Low

DCLK Pulse Width High

DCLK Edge to DSDL/R (Note 19)

tDCK

tDCKL

tDCKH

tDDD

1/64fs

160

−20

20

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN High Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

80

50

150

50

ns

Reset Timing

PDN Pulse Width (Note 20)

tPD

150

ns

Note 17. When the normal/double/quad speed modes are switched, AK4397 should be reset by PDN pin or RSTN bit.

Note 18. BICK rising edge must not occur at the same time as LRCK edge.

Note 19. DSD data transmitting device must meet this time.

Note 20. The AK4397 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change,

the AK4397 should be reset by RSTN bit.

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■ Timing Diagram

1/fCLK

tCLKL

VIH

tCLKH

MCLK VIL

dCLK=tCLKH x fCLK, tCLKL x fCLK

1/fs

VIH

LRCK VIL

tBCK

tBCKL

VIH

tBCKH

BICK VIL

Clock Timing

tLRB

LRCK

VIH

BICK VIL

tSDS

VIH

SDATA VIL

tSDH

VIH

VIL

tBLR

Audio Interface Timing (PCM Mode)

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VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)

VIH

DCLK VIL

tDDD

VIH

DSDL

DSDR VIL

tDCKHtDCKL

tDCK

tDDD

Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)

tCSS

CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

C1 C0 R/W A4

tCCKL tCCKH

tCDS tCDH

WRITE Command Input Timing

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CSN

VIH

CCLK VIL

VIH

CDTI VIL

VIH

VIL

D3 D2 D1 D0

tCSW

tCSH

WRITE Data Input Timing

tPD

PDN VIL

Power Down & Reset Timing

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OPERATION OVERVIEW

■ D/A Conversion Mode

In serial mode, the AK4397 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls

PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,

PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4397

should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4397 performs for

only PCM data.

D/P bit Interface

0 PCM

1 DSD

Table 1. PCM/DSD Mode Control

■ System Clock

[1] PCM Mode

The external clocks, which are required to operate the AK4397, are MCLK, BICK and LRCK. MCLK should be

synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the

delta-sigma modulator. When external clocks are changed, the AK4397 should be reset by PDN pin or RSTN bit.

All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4397 is in normal operation

mode (PDN pin = “H”). If these clocks are not provided, the AK4397 may draw excess current because the device utilizes

dynamic refreshed logic internally. If the external clocks are not present, the AK4397 should be in the power-down mode

(PDN pin = “L”) or in the reset mode (RSTN bit = “0”). After exiting reset (PDN pin = “L” → “H”) at power-up etc., the

AK4397 is in power-down mode until MCLK is supplied.

(1) Parallel Mode (P/S pin = “H”)

1. Manual Setting Mode (ACKS pin = “L”)

MCLK frequency is detected automatically and the sampling speed is set by DFS0 pin (Table 2). The MCLK frequency

corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. When DFS0 pin is changed,

the AK4397 should be reset by PDN pin. Quad speed mode is not supported in this mode.

DFS0 pin Sampling Rate (fs)

L Normal Speed Mode 30kHz ∼ 54kHz

H Double Speed Mode 54kHz ∼ 108kHz

Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode)

LRCK MCLK (MHz) BICK

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz

88.2kHz 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A 5.6448MHz

96.0kHz 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A 6.1440MHz

Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)

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2. Auto Setting Mode (ACKS pin = “H”)

MCLK frequency and the sampling speed are detected automatically (Table 4) and DFS0 pin is ignored. DFS0 pin should

be fixed to VSS4 or DVDD.

MCLK Sampling Speed

1152fs Normal (fs≤32kHz)

512fs 768fs Normal

256fs 384fs Double

128fs 192fs Quad

Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode)

LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

Sampling

Speed

32.0kHz N/A N/A N/A N/A 16.3840 24.5760 36.8640

44.1kHz N/A N/A N/A N/A 22.5792 33.8688 N/A

48.0kHz N/A N/A N/A N/A 24.5760 36.8640 N/A

Normal

88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A

96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A

Double

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A

Quad

Table 5. System Clock Example (Auto Setting Mode @Parallel Mode)

(2) Serial Mode (P/S pin = “L”)

1. Manual Setting Mode (ACKS bit = “0”)

MCLK frequency is detected automatically and the sampling speed is set by DFS1-0 bits (Table 6). The MCLK frequency

corresponding to each sampling speed should be provided (Table 7). The AK4397 is set to Manual Setting Mode at

power-up (PDN pin = “L” → “H”). When DFS1-0 bits are changed, the AK4397 should be reset by RSTN bit.

DFS1 bit DFS0 bit Sampling Rate (fs)

0 0 Normal Speed Mode 30kHz ∼ 54kHz

0 1 Double Speed Mode 54kHz ∼ 108kHz

1 0 Quad Speed Mode 120kHz ∼ 216kHz

(default)

Table 6. Sampling Speed (Manual Setting Mode @Serial Mode)

LRCK MCLK (MHz) BICK

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 64fs

32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz

44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz

48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz

88.2kHz 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A 5.6448MHz

96.0kHz 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A 6.1440MHz

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A 11.2896MHz

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A 12.2880MHz

Table 7. System Clock Example (Manual Setting Mode @Serial Mode)

[AK4397]

MS0616-E-03 2012/11

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2. Auto Setting Mode (ACKS bit = “1”)

MCLK frequency and the sampling speed are detected automatically (Table 8) and DFS1-0 bits are ignored. The MCLK

frequency corresponding to each sampling speed should be provided (Table 9).

MCLK Sampling Speed

1152fs Normal (fs≤32kHz)

512fs 768fs Normal

256fs 384fs Double

128fs 192fs Quad

Table 8. Sampling Speed (Auto Setting Mode @Serial Mode)

LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs

Sampling

Speed

32.0kHz N/A N/A N/A N/A 16.3840 24.5760 36.8640

44.1kHz N/A N/A N/A N/A 22.5792 33.8688 N/A

48.0kHz N/A N/A N/A N/A 24.5760 36.8640 N/A

Normal

88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A

96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A

Double

176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A

192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A

Quad

Table 9. System Clock Example (Auto Setting Mode @Serial Mode)

[2] DSD Mode

The external clocks, which are required to operate the AK4397, are MCLK and DCLK. MCLK should be synchronized

with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.

All external clocks (MCLK, DCLK) should always be present whenever the AK4397 is in the normal operation mode

(PDN pin = “H”). If these clocks are not provided, the AK4397 may draw excess current because the device utilizes

dynamic refreshed logic internally. The AK4397 should be reset by PDN pin = “L” after threse clocks are provided. If the

external clocks are not present, the AK4397 should be in the power-down mode (PDN pin = “L”). After exiting

reset(PDN pin = “L” → “H”) at power-up etc., the AK4397 is in the power-down mode until MCLK is input.

DCKS bit MCLK Frequency DCLK Frequency

0 512fs 64fs (default)

1 768fs 64fs

Table 10. System Clock (DSD Mode)

[AK4397]

MS0616-E-03 2012/11

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■ Audio Interface Format

[1] PCM Mode

Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the

DIF2-0 pins (Parallel mode) or DIF2-0 bits (Serial mode) as shown in Table 11. In all formats the serial data is MSB-first,

2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats

by zeroing the unused LSBs.

Mode DIF2 DIF1 DIF0 Input Format BICK Figure

0 0 0 0 16bit LSB justified ≥ 32fs Figure 1

1 0 0 1 20bit LSB justified ≥ 48fs Figure 2

2 0 1 0 24bit MSB justified ≥ 48fs Figure 3 (default)

3 0 1 1 24bit I2S Compatible ≥ 48fs Figure 4

4 1 0 0 24bit LSB justified ≥ 48fs Figure 2

5 1 0 1 32bit LSB justified ≥ 64fs Figure 5

6 1 1 0 32bit MSB justified ≥ 64fs Figure 6

7 1 1 1 32bit I2S Compatible ≥ 64fs Figure 7

Table 11. Audio Interface Format

SDAT

A

BICK

LRCK

SDAT

A

15 14 6 5 4

BICK

0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1

3210 1514

(

32fs

)

(

64fs

)

014

115 16 17 31 0 1 14 15 16 17 31 0 1

15 14 0 15 14 0

Mode 0 Don’t care Don’t care

15:MSB, 0:LSB

Mode 0 15 14 6 5 4 3 2 1 0

Lch Data Rch Data

Figure 1. Mode 0 Timing

SDAT

A

LRCK

BICK

(

64fs

)

091 10 11 12 31 0 1 9 10 11 12 31 0 1

19 0 19 0

Mode 1 Don’t care Don’t care

19:MSB, 0:LSB

SDAT

A

Mode 4 23:MSB, 0:LSB

20 19 0 20 19 0

Don’t care Don’t care

22 21 22 21

Lch Data Rch Data

8

23 23

8

Figure 2. Mode 1, 4 Timing

[AK4397]

MS0616-E-03 2012/11

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LRCK

BICK

(

64fs

)

SDAT

A

0221 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 1 0 Don’t care23

Lch Data Rch Data

23 30 2222423 30

22 1 0 Don’t care

23 2223

Figure 3. Mode 2 Timing

LRCK

BICK

(

64fs

)

SDAT

A

031 2 24 31 0 1 31 0 1

23:MSB, 0:LSB

22 10Don’t care

23

Lch Data Rch Data

23 25 322423 25

22 1 0Don’t care23 23

Figure 4. Mode 3 Timing

LRCK

BICK(128fs)

SDATA

0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1

031 1

BICK(64fs)

SDATA

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0

31

1

30 931 30 20 19 18 9 3120 19 18

31: MSB, 0:LSB

80

18 0

1

Lch Data Rch Data

031 1

Figure 5. Mode 5 Timing

[AK4397]

MS0616-E-03 2012/11

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LRCK

BICK(128fs)

SDATA

0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0

31

1

30 031 30 12 11 10 0 3112 11 10

BICK(64fs)

SDATA

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0

31

1

30 931 30 20 19 18 9 3120 19 18

31: MSB, 0:LSB

80

18 0

1

Lch Data Rch Data

Figure 6. Mode 6 Timing

LRCK

BICK(128fs)

SDATA

0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1

31 031 13 12 11 0 13 12 11

BICK(64fs)

SDATA

0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0

0

1

31 9031 212019 9 021 20 19

31: MSB, 0:LSB

81

28 1

2

Lch Data Rch Data

Figure 7. Mode 7 Timing

[AK4397]

MS0616-E-03 2012/11

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[2] DSD Mode

In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can

invert the polarity of DCLK.

DCLK (64fs)

DCKB=1

DCLK (64fs)

DCKB=0

DSDL,DSDR

Normal

DSDL,DSDR

Phase M odulation

D1

D0 D1 D2

D0 D2 D3

D1 D2 D3

Figure 8. DSD Mode Timing

[AK4397]

MS0616-E-03 2012/11

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■ D/A conversion mode switching timing

RSTN bit

D/A Data

D/A Mode

≥4/fs

≥0

PCM Data DSD Data

PCM Mode DSD Mode

Figure 9. D/A Mode Switching Timing (PCM to DSD)

RSTN bit

D/A Data

D/A Mode

≥4/fs

DSD Data PCM Data

DSD Mode PCM Mode

Figure 10. D/A Mode Switching Timing (DSD to PCM)

Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not

recommended by SACD format book (Scarlet Book).

■ De-emphasis Filter

A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or

disabled with DEM1-0 pins or DEM1-0 bits. In case of double speed and quad speed mode, the digital de-emphasis filter

is always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode

are switched.

DEM1 DEM0 Mode

0 0 44.1kHz

0 1 OFF (default)

1 0 48kHz

1 1 32kHz

Table 12. De-emphasis Control (Normal Speed Mode)

■ Output Volume

The AK4397 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.

These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing

levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition

time of 1 level and all 256 levels is shown in Table 13.

Transition Time

Sampling Speed 1 Level 255 to 0

Normal Speed Mode 4LRCK 1020LRCK

Double Speed Mode 8LRCK 2040LRCK

Quad Speed Mode 16LRCK 4080LRCK

Table 13. ATT Transition Time

[AK4397]

MS0616-E-03 2012/11

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■ Zero Detection

The AK4397 has channel-independent zeros detect function. When the input data at each channel is continuously zeros

for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input

data of each channel is not zero after going DZF pin “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF

pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both

channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect

function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the

polarity of DZF pin.

■ Soft Mute operation

Soft mute operation is performed at digital domain. When SMUTE pin goes to “H” or SMUTE bit goes to “1”, the output

signal is attenuated by −∞ during ATT_DATA × ATT transition time (Table 13) from the current ATT level. When

SMUTE pin is returned to “L” or SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually

changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before attenuating −∞

after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is

effective for changing the signal source without stopping the signal transmission.

SM U T E pin or

SMU TE bit

A

ttenuation

D ZF pin

ATT_Level

-∞

A

OUT

8192/fs

GD GD

(1)

(2)

(3)

(4)

(1)

(2)

Notes:

(1) ATT_DATA × ATT transition time (Table 13). For example, this time is 1020LRCK cycles (1020/fs)

at ATT_DATA=255 in Normal Speed Mode.

(2) Analog output corresponding to digital input has the group delay (GD).

(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued

and returned to ATT level by the same cycle.

(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes

to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.

Figure 11. Soft Mute Function

■ System Reset

The AK4397 should be reset once by bringing PDN pin = “L” upon power-up. The analog section exits power-down

mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during

4/fs.

[AK4397]

MS0616-E-03 2012/11

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■ Power-Down

The AK4397 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).

Figure 12 shows an example of the system timing at the power-down and power-up.

Normal Op eration

Internal

State

PDN

Power-down Normal Op eration

GD GD

“0” data

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK, BICK, LRCK

(1) (3)

(6)

DZFL/DZFR

External

MUTE (5)

(3) (1)

Mute ON

(2)

(4)

Don’t care

Notes:

(1) The analog output corresponding to digital input has the group delay (GD).

(2) Analog outputs are floating (Hi -Z) at the power-down mode.

(3) Click noise occurs at the edge (“↑ ↓”) of PDN signal. This noise is output even if “0” data is input.

(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN pin = “L”).

(5) Please mute the analog output externally if the click noise (3) influences system application.

The timing example is shown in this figure.

(6) DZF pins are “L” in the power-down mode (PDN pin = “L”).

Figure 12. Power-down/up sequence example

[AK4397]

MS0616-E-03 2012/11

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■ Reset Function

When RSTN bit = “0”, the AK4397’s digital section is powered down but the internal register values are not initialized.

The analog outputs go to AVDD/2 voltage and DZF pins of both channels go to “H”. Figure 13 shows the example of

reset by RSTN bit.

Internal

State

RSTN bit

Digital Block

P

d

Normal Op eration

GD GD

“0” data

D/A Out

(Analog)

D/A In

(Digital)

Clock In

MCLK, BICK, LRCK

(1) (3)

DZFL/DZFR

(3) (1)

(2)

Normal Operation

2/fs(5)

Internal

RSTN Timing

2~3/fs (6)3~4/fs (6)

Don’t care

(4)

Notes:

(1) The analog output corresponding to digital input has the group delay (GD).

(2) Analog outputs go to AVDD/2 voltage.

(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.

This noise is output even if “0” data is input.

(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “0”).

(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.

(6) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”

to the internal RSTN bit “1”.

Figure 13. Reset sequence example

[AK4397]

MS0616-E-03 2012/11

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■ Register Control Interface

Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4397. In parallel mode,

the register setting is ignored and the pin setting is ignored in serial mode. When the state of P/S pin is changed, the

AK4397 should be reset by PDN pin. The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting

must be all “L”. Internal registers may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this

interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits)

and Control data (MSB first, 8bits). The AK4397 latches the data on the rising edge of CCLK, so data should be clocked

in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).

Function Parallel mode Serial mode

Auto Setting Mode O O

Manual Setting Mode O O

Audio Format O O

De-emphasis O O

SMUTE O O

DSD Mode X O

Zero Detection X O

Slow roll-off response X O

Digital Attenuator X O

Table 14. Function List (O: Available, X: Not available)

PDN pin = “L” resets the registers to their default values. In serial mode, the internal timing circuit is reset by RSTN bit,

but the registers are not initialized.

CDTI

CCLK

C1

012345678 9 10 11 12 13 14 15

D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3

CSN

C1-C0: Chip Address (C1=CAD1, C0=CAD0)

R/W: READ/WRITE (Fixed to “1”, Write only)

A4-A0: Register Address

D7-D0: Control Data

Figure 14. Control I/F Timing

* The AK4397 does not support the read command.

* When the AK4397 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control

register is inhibited.

* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.

[AK4397]

MS0616-E-03 2012/11

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■ Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN

01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE

02H Control 3 D/P DSDM DCKS DCKB 0 DZFB 0 0

03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Notes:

For addresses from 05H to 1FH, data must not be written.

When PDN pin goes to “L”, the registers are initialized to their default values.

When RSTN bit goes to “0”, the only internal timing is reset and the registers are not initialized to their default values.

When the state of P/S pin is changed, the AK4397 should be reset by PDN pin.

■ Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN

Default 0 0 0 0 0 1 0 1

RSTN: Internal timing reset

0: Reset. All registers are not initialized.

1: Normal Operation (default)

“0” resets the internal timing circuits. The register value will not be initialized.

DIF2-0: Audio data interface modes (Table 11)

Initial value is “010” (Mode 2: 24bit MSB justified).

ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)

0: Disable : Manual Setting Mode (default)

1: Enable : Auto Setting Mode

When ACKS bit = “1”, MCLK frequency and the sampling frequency are detected automatically.

[AK4397]

MS0616-E-03 2012/11

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE

Default 0 0 0 0 0 0 1 0

SMUTE: Soft Mute Enable

0: Normal Operation (default)

1: DAC outputs soft-muted.

DEM1-0: De-emphasis Response (Table 12)

Initial value is “01” (OFF).

DFS1-0: Sampling Speed Control (Table 6)

Initial value is “00” (Normal speed).

When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs at

that time.

SLOW: Slow Roll-off Filter Enable

0: Sharp roll-off filter (default)

1: Slow roll-off filter

DZFM: Data Zero Detect Mode

0: Channel Separated Mode (default)

1: Channel ANDed Mode

If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both

channels are continuously zeros for 8192 LRCK cycles.

DZFE: Data Zero Detect Enable

0: Disable (default)

1: Enable

Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are

always “L”.

[AK4397]

MS0616-E-03 2012/11

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Control 3 D/P DSDM DCKS DCKB 0 DZFB 0 0

Default 0 0 0 0 0 0 0 0

DZFB: Inverting Enable of DZF

0: DZF pin goes “H” at Zero Detection (default)

1: DZF pin goes “L” at Zero Detection

DCKB: Polarity of DCLK (DSD Only)

0: DSD data is output from DCLK falling edge. (default)

1: DSD data is output from DCLK rising edge.

DCKS: Master Clock Frequency Select at DSD mode (DSD only)

0: 512fs (default)

1: 768fs

DSDM: DSD Input Select

0: Input pin: #5, 6, 7 (default)

1: Input pin: #12, 13, 14

When DSDM bit is changed, the AK4397 should be reset by RSTN bit.

D/P: DSD/PCM Mode Select

0: PCM Mode (default)

1: DSD Mode

When D/P bit is changed, the AK4397 should be reset by RSTN bit.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Default 1 1 1 1 1 1 1 1

ATT7-0: Attenuation Level

ATT = 20 log10 (ATT_DATA / 255) [dB]

FFH: 0dB (default)

00H: Mute

[AK4397]

MS0616-E-03 2012/11

- 31 -

SYSTEM DESIGN

Figure 15 show the system connection diagram. Figure 17, Figure 18 and Figure 19 show the analog output circuit

examples. An evaluation board (AKD4397) is available which demonstrates the optimum layout, power supply

arrangements and measurement results.

DVDD

NC

1

PDN

44

2

BICK 3

SDATA 4

LRCK

5

CSN 6

CAD0 7

CCLK 8

CDTI

9

DIF0 10

DIF1 11

VSS4

43

MCL

K

42

AVDD

41

VSS3

40

NC

39

NC

38

NC

3

7

NC

36

NC

3

5

AOUTLP

34

DIF2

12

NC

13

P/S

14

DZFR

1

5

DZFL

16

CAD1

1

7

NC

18

NC

19

NC

20

NC

21

AOUTRP

22

33

32

31

30

29

28

27

26

25

24

23

AOUTLN

VSS2

VDDL

VREFHL

VREFLL

NC

VREFLR

VREFHR

VDDR

VSS1

AOUTRN

AK4397EQ

Top View

Analog5.0V

+ 10u 0.1u

Digital 5.0V

10u 0.1u

+

Ceramic Capacitor

+ Electrolytic Capacitor

+

0.1u

+

10u

+ 10u 0.1u

+

10u 0.1u

Lch

LPF

Rch

LPF Rch

Mute

Lch

Mute

Micro-

Controller

Rch Out

Lch Out

Reset & PD

64fs

Audio Data

fs

Master cloc

k

Notes:

- Chip Address = “00”. LRCK = fs, BICK = 64fs.

- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator

etc.

- VSS1-4 must be connected to the same analog ground plane.

- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and

capacitive load.

- All input pins except pull-down/pull-up pins should not be left floating.

Figure 15. Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial mode)

[AK4397]

MS0616-E-03 2012/11

- 32 -

Analog Ground Digital Ground

System

Controller

DVDD

NC

1

PDN

44

2

BICK3

SDATA4

LRCK

5

CSN6

CAD07

CCLK8

CDTI

9

DFS010

DIF111

DIF2

12

33

AOUTLN

AK4397EQ

13

14

15

16

17

18

19

20

21

22

NC

P/S

DZFR

DZFL

CAD1

NC

AOUTRP

32 VSS2

31 VDDL

30 VREFHL

29 VREFLL

28 NC

27 VREFLR

26 VREFHR

25 VDDR

24 VSS1

23

AOUTRN

VSS4 43

MCL

K

42

AVDD 41

VSS3 40

NC 39

NC 38

NC 37

NC 36

NC 35

AOUTLP 34

Figure 16. Ground Layout

1. Grounding and Power Supply Decoupling

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD,

respectively. AVDD, VDDL/R is supplied from analog supply in system and DVDD is supplied from digital supply in

system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from the point with low impedance

of regulator etc. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be

connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near

as possible.

2. Voltage Reference

The differential Voltage between VREFHL/R and VREFLL/R set the analog output range. VREFHL/R pin is normally

connected to AVDD and VREFLL/R pin is normally connected to VSS. VREFHL/R and VREFLL/R should be

connected with a 0.1µF ceramic capacitor. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor

attached between VREFHL/R pin and VREFLL/R pin eliminates the effects of high frequency noise. All signals,

especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted coupling

into the AK4397.

3. Analog Outputs

The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around

AVDD/2. The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−.

If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the

external summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a

positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for

000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio

passband. Figure 17 shows an example of external LPF circuit summing the differential outputs by an op-amp.

Figure 18 shows an example of differential outputs and LPF circuit example by three op-amps.

[AK4397]

MS0616-E-03 2012/11

- 33 -

1.5k 1.5k

390

1.5k 390

1.5k 1n

+Vop

1n

-Vop

AOUT-

AOUT+

2.2n Analog

Out

AK4397

Figure 17. External LPF Circuit Example 1 for PCM (fc = 99.2kHz, Q=0.704)

Frequency Response Gain

20kHz −0.011dB

40kHz −0.127dB

80kHz −1.571dB

Table 15. Filter Response of External LPF Circuit Example 1 for PCM

330

100u 180

A

OUTL-

10k

3.9

n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1u 10u

10u

NJM5534D

330

100u 180

A

OUTL+

10k

3.9n

1.2k

680

3.3n

6

4

3

2

7

10u

0.1u

0.1

u

10u

NJM5534D 0.1u

+

NJM5534D

0.1u 10u

100

4

3

2

1.0n

620

560

7

+

-

+

-

+

-

+

1.0n

Lch

-15

+15

6

560

Figure 18. External LPF Circuit Example 2 for PCM

1

st Stage 2nd Stage Total

Cut-off Frequency 182kHz 284kHz -

Q 0.637 - -

Gain +3.9dB -0.88dB +3.02dB

20kHz -0.025 -0.021 -0.046dB

40kHz -0.106 -0.085 -0.191dB

Frequency

Response 80kHz -0.517 -0.331 -0.848dB

Table 16. Filter Response of External LPF Circuit Example 2 for PCM

[AK4397]

MS0616-E-03 2012/11

- 34 -

It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass

filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4397 can achieve this filter

response by combination of the internal filter (Table 17) and an external filter (Figure 19).

Frequency Gain

20kHz −0.4dB

50kHz −2.8dB

100kHz −15.5dB

Table 17. Internal Filter Response at DSD mode

1.8k 4.3k

1.0k

1.8k 1.0k

4.3k 270p

+Vop

270p

-Vop

AOUT-

AOUT+

3300p Analog

Out

2.0k

2200p

-

+

2.8Vpp

6.34Vpp

2.8Vpp

Figure 19. External 3rd order LPF Circuit Example for DSD

Frequency Gain

20kHz −0.05dB

50kHz −0.51dB

100kHz −16.8dB

DC gain = 1.07dB

Table 18. 3rd order LPF (Figure 19) Response

[AK4397]

MS0616-E-03 2012/11

- 35 -

PACKAGE

0.15

0.09 ~ 0.20

0.37±0.10

10.0

1.70max

1 11

23

33

44pin LQFP (Unit: mm)

10.0

12.0

34

44

0.80

22

12

12.0

0 ~ 0.2

0°∼10°

0.60

±

0.20

■ Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

[AK4397]

MS0616-E-03 2012/11

- 36 -

MARKING

AK4397EQ

XXXXXXX

A

KM

1

1) Pin #1 indication

2) AKM Logo

3) Date Code: XXXXXXX(7 digits)

4) Marking Code: AK4397

5) Audio 4 pro Logo

REVISION HISTORY

Date (Y/M/D) Revision Reason Page Contents

07/05/11 00 First Edition

08/02/12 01 Error

Correction

25 Description about VCOM pin was deleted.

26 VCOM → AVDD/2

32 2. Voltage Reference

Description about VCOM pin was deleted.

3. Analog Outputs

VCOM → AVDD/2

09/02/25 02 Error

Correction

33 Figure 17 was changed.

Table 15 was changed.

12/11/12 03 Specification

Change

35 PACKAGE

Package dimensions were changed.

[AK4397]

MS0616-E-03 2012/11

- 37 -

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

z Descriptions of external circuits, application circuits, software and other related information contained in this

document are provided only to illustrate the operation and application examples of the semiconductor products. You

are fully responsible for the incorporation of these external circuits, application circuits, software and other related

information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third

parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,

intellectual property, or other rights in the application or use of such information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,

or strategic materials.

z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or

other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety

or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or

perform may reasonably be expected to result in loss of life or in significant injury or damage to person or

property.

z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places

the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer

or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all

claims arising from the use of said product in the absence of such notification.