© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 15 1Publication Order Number:
MC74VHC1GT86/D
MC74VHC1GT86
2−Input Exclusive OR Gate /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT86 is an advanced high speed CMOS 2−input
Exclusive OR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output h as a f ull 5 V C M OS level output swing. T he i nput p rotection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT86 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT86 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
•High Speed: tPD = 4.8 ns (Typ) at VCC = 5 V
•Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
•CMOS−Compatible Outputs: VOH > 0.8 VCC; V OL < 0.1 VCC @Load
•Power Down Protection Provided on Inputs and Outputs
•Balanced Propagation Delays
•Pin and Function Compatible with Other Standard Logic Families
•Chip Complexity: FETs = 83; Equivalent Gates = 16
•Pb−Free Packages are Available
Figure 1. Pinout (Top View)
IN A OUT Y
= 1
IN B
VCC
IN B
IN A
OUT Y
GND
Figure 2. Logic Symbol
1
2
34
5
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MARKING
DIAGRAMS
PIN ASSIGNMENT
1
2
3 GND
IN B
IN A
4
5V
CC
OUT Y
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
H
H
L
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
VM = Device Code
M = Date Code*
G= Pb−Free Package
1
5
VM M G
G
SC−88A/SOT−353/SC−70
DF SUFFIX
CASE 419A
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
1
5
1
5
*Date Code orientation and/or position may vary
depending upon manufacturing location.
(Note: Microdot may be in either location)
1
5
VM M G
G
M
MC74VHC1GT86
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2
MAXIMUM RATINGS
Symbol Characteristics Value Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIN DC Input Voltage −0.5 to +7.0 V
VOUT DC Output Voltage VCC = 0
High or Low State −0.5 to 7.0
−0.5 to VCC + 0.5 V
IIK Input Diode Current −20 mA
IOK Output Diode Current VOUT < GND; VOUT > VCC +20 mA
IOUT DC Output Current, per Pin +25 mA
ICC DC Supply Current, VCC and GND +50 mA
PDPower dissipation in still air SC−88A, TSOP−5 200 mW
qJA Thermal resistance SC−88A, TSOP−5 333 °C/W
TLLead temperature, 1 mm from case for 10 seconds 260 °C
TJJunction temperature under bias +150 °C
Tstg Storage temperature −65 to +150 °C
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
ILatchup Latchup Performance Above VCC and Below GND at 125°C (Note 5) ±500 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended O p e r a t i n g Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Derating − SC−88A Package: –3 mW/°C from 65° to 125°C
− TSOP5 Package: −3 mW/°C f r om 65° to 125°C
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
VCC DC Supply Voltage 3.0 5.5 V
VIN DC Input Voltage 0.0 5.5 V
VOUT DC Output Voltage VCC = 0
High or Low State 0.0
0.0 5.5
VCC V
TAOperating Temperature Range −55 +125 °C
tr , tfInput Rise and Fall Time VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V 0
0100
20 ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
TIME, YEARS
NORMALIZED FAILURE RATE
TJ= 80 C°
TJ= 90 C°
TJ= 100 C°
TJ= 110 C°
TJ= 130 C°
TJ= 120 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
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3
DC ELECTRICAL CHARACTERISTICS
VCC TA = 25°C TA ≤ 85°C−55 ≤ TA ≤ 125°C
Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit
VIH Minimum High−Level
Input Voltage 3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
VIL Maximum Low−Level
Input Voltage 3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
VOH Minimum High−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOH = −50 mA3.0
4.5 2.9
4.4 3.0
4.5 2.9
4.4 2.9
4.4 V
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA 3.0
4.5 2.58
3.94 2.48
3.80 2.34
3.66
V
VOL Maximum Low−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOL = 50 mA3.0
4.5 0.0
0.0 0.1
0.1 0.1
0.1 0.1
0.1 V
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA 3.0
4.5 0.36
0.36 0.44
0.44 0.52
0.52
V
IIN Maximum Input
Leakage Current VIN = 5.5 V or GND 0 to
5.5 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent
Supply Current VIN = VCC or GND 5.5 1.0 20 40 mA
ICCT Quiescent Supply
Current Input: VIN = 3.4 V 5.5 1.35 1.50 1.65 mA
IOPD Output Leakage
Current VOUT = 5.5 V 0.0 0.5 5.0 10 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
Symbo
l
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎ
Test Conditions
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
TA = 25°C
ÎÎÎÎÎ
ÎÎÎÎÎ
TA ≤ 85°C
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
−55 ≤ TA ≤ 125°C
ÎÎ
ÎÎ
ÎÎ
Unit
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Typ
ÎÎÎ
ÎÎÎ
Max
ÎÎÎ
ÎÎÎ
Min
ÎÎÎ
ÎÎÎ
Max
ÎÎÎ
ÎÎÎ
Min
ÎÎÎÎ
ÎÎÎÎ
Max
ÎÎÎÎ
Î
ÎÎ
Î
Î
ÎÎ
Î
ÎÎÎÎ
tPLH,
tPHL
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Maximum Propagation
Delay, Input A or B to Y
ÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎ
VCC = 3.3 ± 0.3 VCL = 15 pF
CL = 50 pF
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
5.0
6.2
ÎÎÎ
Î
Î
Î
ÎÎÎ
11.0
14.5
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
13.0
16.5
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
15.5
19.5
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VCC = 5.0 ± 0.5 VCL = 15 pF
CL = 50 pF
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
3.1
4.2
ÎÎÎ
ÎÎÎ
6.8
8.8
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
8.0
10.0
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
10.0
12.0
ÎÎ
ÎÎ
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
CIN
ÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎ
Maximum Input
Capacitance
ÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
5.5
ÎÎÎ
Î
Î
Î
ÎÎÎ
10
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎ
Î
Î
Î
ÎÎÎ
10
ÎÎÎ
Î
Î
Î
ÎÎÎ
ÎÎÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
10
ÎÎ
ÎÎ
ÎÎ
pF
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Note 6) 11 pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
MC74VHC1GT86
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4
GND
50%A or B
Y
tPHL
tPLH
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Switching Waveforms
Figure 5. Test Circuit
50%
3.0 V
VOH
VOL
ORDERING INFORMATION
Device Package Shipping†
MC74VHC1GT86DFT1 SC−88A / SOT−353 / SC−70
3000 / Tape & Reel
M74VHC1GT86DFT1G SC−88A / SOT−353 / SC−70
(Pb−Free)
MC74VHC1GT86DFT2 SC−88A / SOT−353 / SC−70
M74VHC1GT86DFT2G SC−88A / SOT−353 / SC−70
(Pb−Free)
MC74VHC1GT86DTT1 TSOP−5 / SOT−23 / SC−59
M74VHC1GT86DTT1G TSOP−5 / SOT−23 / SC−59
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC74VHC1GT86
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5
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
1.80 2.200.071 0.087
INCHES
B1.15 1.350.045 0.053
C0.80 1.100.031 0.043
D0.10 0.300.004 0.012
G0.65 BSC0.026 BSC
H−−− 0.10−−−0.004
J0.10 0.250.004 0.010
K0.10 0.300.004 0.012
N0.20 REF0.008 REF
S2.00 2.200.079 0.087
B0.2 (0.008) MM
12 3
45
A
G
S
D 5 PL
H
C
N
J
K
−B−
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
ǒmm
inchesǓ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
MC74VHC1GT86
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6
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
DIM MIN MAX
MILLIMETERS
A3.00 BSC
B1.50 BSC
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
L1.25 1.55
M0 10
S2.50 3.00
123
54 S
AG
L
B
D
H
CJ
__
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
T
SEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC1GT86/D
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