Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB32M x 72 E12/12, 3.3V, Au, EDOMMDL18DSU-001041529. 32M x 72 E13/11, 3.3V, Au, EDOMMDL18DSU-001041529. IBM11M32845CB PRELIMINARY 32M x 72 Chipkill Correct DRAM Module Features * 168-Pin JEDEC Standard, 8-Byte Dual In-line Memory Module * 32M x 72 (Dual Bank) Chipkill Correct EDO DIMM * Performance: tRAC RAS Access Time -5R 50ns tCAC CAS Access Time 19ns tAA Access Time From Address 34ns tRC Cycle Time 101ns tHPC EDO Mode Cycle Time 22ns * Optimized for ECC applications * System Performance Benefits: - Buffered inputs (except RAS) - Reduced noise (32 VSS/VDD pins) - Buffered PDs * Extended Data Out (EDO) Mode, Read-ModifyWrite Cycles * Refresh Modes: RAS-Only, CBR, and Hidden Refresh * 8192 refresh cycles distributed across 128ms * All inputs and outputs are LVTTL compatible * Card sizes: 5.25" x 1.90" x 0.320" * Single 3.3V 0.15V Power Supply * DRAMS in TSOJ Package * Gold contacts Description IBM11M32885B/C is an industry-standard 168-pin 8-byte Dual In-line Memory Module (DIMM) for ECC applications which is organized as a 32M x 72 highspeed memory array and is configured as two 16M x 72 banks. The DIMM uses additional checkbit DRAMs and an ASIC to provide chipkill correction when deployed in existing single-error-correct ECC systems. Presence Detect (PD) and Identification Detect (ID) bits provide information about the DIMM density, addressing, performance, and features. PD bits can be dotted at the system level and activated for each DIMM position using the PD enable (PDE) signal. ID bits also allow detection of card features, and may be dot-or'ed at the system level to provide information for the entire DIMM bank. Improved system performance is provided by the on-DIMM buffering of selected input signals. The specified timings include all buffer, net, and skew delays, which simplifies the memory subsystem design analysis. The RAS signals are not buffered, which preserves the DRAM access specifications of 50ns. All IBM 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. Related products are the x64 and x72 parity (5V) DIMMs and ECC DIMMs (5V and 3.3V). Card Outline (Front) (Back) 20L9836.00 8/98 1 85 10 94 11 95 40 124 41 125 84 168 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Pin Description Pinout RAS0, RAS1, RAS2, RAS3 Row Address Strobe CAS0, CAS1, CAS4, CAS5 Column Address Strobe (Buffered) WE0, WE2 Output Enable (Buffered) A0 - A12 Address Inputs (Buffered) DQx Data Input/Output VCC Power (+3.3V) VSS Ground NC No Connect DU PDE ID0 - ID1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Read/write Input (Buffered) OE0, OE2 PD1 - PD8 Pin# Do Not Use Presence Detects (Buffered) Presence Detect Enable ID Bits Front Side Pin# VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS DU DU VCC WE0 CAS0 NC RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC NC NC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Back Side VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC CAS1 NC RAS1 NC VSS A1 A3 A5 A7 A9 A11 NC VCC NC NC Pin# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front Side VSS OE2 RAS2 CAS4 NC WE2 VCC DU NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VCC Pin# 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back Side VSS NC RAS3 CAS5 NC PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC Note: All pin assignments are consistent for all 8 Byte versions. Ordering Information Part Number Organization Speed Addr. Leads Dimension Power IBM11M32885CB-5RY 32M x 72 5Rns 13/11 Gold 5.25" x 1.65" x 0.320" 3.3V (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module x 72 ECC DIMM Block Diagram (2 Banks, x4 DRAMs) WE0 WE2 OE0 RAS3 CAS0 OE2 RAS2 CAS1 RAS1 CAS4 RAS0 CAS5 ASIC 8 DQ0 DQ1 DQ2 MDQ0-7 CAS0 CAS1 Byte 0 8 MDQ8-15 DRAMS 8 MDQ16-23 Bytes 1 - 7 8 MDQ0-7 DQ71 CAS4 CAS5 8 MDQ8-15 DRAMS 8 CB0 CB1 CB2 CB3 MDQ16-23 CB4 CB5 CB6 CB7 Check Bits Delayed WE, OE A0-12 All DRAMs VCC All DRAMs , Buffers, ASIC VSS 20L9836.00 8/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Truth Table Function Column Address PDE DQx X X X High Impedance Row Col X Valid Data Out Row Col X Valid Data In H Row Col X Valid Data In HL LH Row Col X Valid Data Out, Valid Data In HL H L Row Col X Valid Data Out RAS CAS WE OE Standby H HX Read X X L L H L Early-Write L L L X Late-Write L L HL RMW L L EDO Page Mode - Read 1st Cycle L Row Address Subsequent Cycles L HL H L N/A Col X Valid Data Out EDO Page Mode - Write 1st Cycle L HL L X Row Col X Valid Data In Subsequent Cycles L HL L X N/A Col X Valid Data In EDO Page Mode - RMW 1st Cycle L HL HL LH Row Col X Valid Data Out, Valid Data In Subsequent Cycles L HL HL LH N/A Col X Valid Data Out, Valid Data In RAS-Only Refresh L H X X Row N/A X High Impedance HL L H X X X X High Impedance Read LHL L H L Row Col X Data Out Write LHL L H X Row Col X Data In X X X X X X L Not Affected (PD Bits Valid) CAS-Before-RAS Refresh Hidden Refresh Read Presence Detects Presence Detect Pin -5R Special PD1 (PD1 - PD4: Addressing/Density) 1 1 PD2 0 0 PD3 0 0 PD4 0 0 PD5 (EDO Detection) 1 1 PD6 (PD6 - PD7: Speed) 0 1 PD7 0 0 PD8 (Parity/ECC Designator) 0 0 ID0 (DIMM Type/Width) 0 0 ID1 (Refresh Mode) 0 0 1. PD1-8 are buffered outputs (0 = driven to VOL, 1 = open) 2. ID0-1 are unbuffered outputs (0 = VSS, 1 = open) 3. PDE should be tied high or low at system level if not used (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Absolute Maximum Ratings Symbol Parameter Rating Units Notes -0.5 to 4.6 V 1 VCC Power Supply Voltage VIN Input Voltage -0.5 to min (VCC + 0.5, 4.6) V 1 VOUT Output Voltage -0.5 to min (VCC + 0.5, 4.6) V 1 TOPR Operating Temperature 0 to +70 C 1 TSTG Storage Temperature -55 to +125 C 1 TBD W 1, 2 PD Power Dissipation IOUT Short Circuit Output Current 50 mA 1 Short Circuit Output Current (PD) 60 mA 1 IOUTPD 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated is not implied. Exposure to absolute maximum rating condition for extended periods may affect reliability. 2. Maximum power occurs when all banks are active (refresh cycle). Recommended DC Operating Conditions (TA = 0 to 65C) Symbol Min Typ Max Units Notes Supply Voltage 3.15 3.3 3.45 V 1 VIH Input High Voltage 2.0 -- VCC + 0.3 V 1, 2 VIL Input Low Voltage -0.3 -- 0.8 V 1, 2 VCC Parameter 1. All voltages referenced to VSS. 2. VIH may overshoot to VCC + 1.2V for pulse widths of 4.0ns. Additionally, VIL may undershoot to -2.0V for pulse widths 4.0ns (or 1.0V for 8.0ns). Pulse widths measured at 50% points with amplitude measured peak to DC reference. Capacitance (TA = 0 to +65C, VCC = 3.3V 0.15V) Symbol 20L9836.00 8/98 Max Units Input Capacitance (A0 - A12) 18 pF Input Capacitance (RAS) 100 pF CI3 Input Capacitance (CAS, WE, OE) 18 pF CI4 Input Capacitance (PDE) 18 pF CI01 Input/Output Capacitance (DQx) 18 pF C01 Output Capacitance (PD) 15 pF C02 Output Capacitance (ID) 5 pF CI1 CI2 Parameter (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module DC Electrical Characteristics Symbol (TA = 0 to +65C, VCC = 3.3V 0.15V) 13/11 Addressing Parameter Min Max Units Notes 1, 2, 3 ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min) -- 1804 ma ICC2 Standby Current (TTL) Power Supply Standby Current (RAS = CAS VIH) -- 88 mA ICC3 RAS Only Refresh Current Average Power Supply Current, RAS Only Mode (RAS Cycling, CAS VIH: tRC = tRC min) -- 3520 ma 1, 3, 4 ICC4 EDO Page Mode Current Average Power Supply Current, EDO (Hyper) Page Mode (RAS VIL, CAS, Address Cycling: tHPC = tHPC min) -- 1749 mA 1, 2, 3 ICC5 Standby Current (CMOS) Power Supply Standby Current (RAS = CAS = VCC - 0.2V) -- 44 mA ICC6 CAS before RAS Refresh Current Average Power Supply Current, CAS Before RAS Mode (RAS, CAS, Cycling: tRC = tRC min) -- 2794 mA RAS -34 +34 DQx -10 +10 II(L) Input Leakage Current (0.0 VIN (VCC < 6.0V)), All Other Pins Not Under Test = 0V A CAS, WE, OE, A1-A12 -20 +20 IO(L) Output Leakage Current (DOUT is disabled, 0.0 VOUT VCC) -10 +10 A VOH Output High Level Output "H" Level Voltage (IOUT = -2mA @ 2.4V) 2.4 -- V VOL Output Low level Output "L" Level Voltage (IOUT = +2mA @ 0.4V) -- 0.4 V 1. 2. 3. 4. 1, 3, 4 ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. ICC1, ICC4 depend on output loading. Specified values are obtained with output open. Address can be changed once or less while RAS = VIL. In the case of ICC4, it can be changed once or less when CAS = VIH. Refresh current is specified for 1 bank active and 1 bank standby. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module AC Characteristics (TA = 0 to +65C, VCC = 3.3V 0.15V) 1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 2. An initial pause of 200ms is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles is required. 3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specification of 60ns. 4. AC measurements assume tT = 2ns. . Read, Write, Read-Modify-Write, and Refresh Cycles (Common Parameters) -5R Symbol Parameter Unit Min Max Notes tRC Random Read or Write Cycle Time 89 -- ns tRP RAS Precharge Time 35 -- ns tCP CAS Precharge Time 8 -- ns tRAS RAS Pulse Width 50 100K ns tCAS CAS Pulse Width 8 100K ns tASR Row Address Setup Time 5 -- ns tRAH Row Address Hold Time 8 -- ns tASC Column Address Setup Time 2 -- ns tCAH Column Address Hold Time 7 -- ns tRCD RAS to CAS Delay Time 12 32 ns 1 tRAD RAS to Column Address Delay Time 10 20 ns 2 tRSH RAS Hold Time 13 -- ns tCSH CAS Hold Time 43 -- ns tCRP CAS to RAS Precharge Time 10 -- ns tODD OE to DIN Delay Time 18 -- ns 3 tDZO OE Delay Time from DIN -2 -- ns 4 tDZC CAS Delay Time from DIN -2 -- ns 4 Transition Time (Rise and Fall) 1 30 ns tT 1. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD is greater than the specified tRCD(max) limit, then access time is controlled by tCAC. 2. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 3. Either tCDD or tODD must be satisfied. 4. Either tDZC or tDZO must be satisfied. 20L9836.00 8/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Write Cycle -5R Symbol Parameter Min Max Unit Notes 1 tWCS Write Command Set Up Time 2 -- ns tWCH Write Command Hold Time 9 -- ns tWP Write Command Pulse Width 7 -- ns tRWL Write Command to RAS Lead Time 12 -- ns tCWL Write Command to CAS Lead Time 9 -- ns tDS DIN Setup Time -2 -- ns 2 tDH DIN Hold Time 15 -- ns 2 1. tWCS, tRWD, tCWD and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; If tRWD tRWD(min.), tCWD tCWD(min.) and tAWD tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. 2. Data-in set-up and hold is measured from the latter of the two timings, CAS or WE. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Read Cycle -5R Symbol Parameter Min Max Unit Notes tRAC Access Time from RAS -- 50 ns 1, 2 tCAC Access Time from CAS -- 19 ns 1, 2 tAA Access Time from Address -- 34 ns 1, 2 tOEA Access Time from OE -- 18 ns 1, 2 tRCS Read Command Setup Time 2 -- ns tRCH Read Command Hold Time to CAS 2 -- ns 3 tRRH Read Command Hold Time to RAS 0 -- ns 3 tRAL Column Address to RAS Lead Time 30 -- ns tCLZ CAS to Output in Low-Z 2 -- ns tOES OE setup time prior to CAS 7 -- ns tORD OE setup time prior to RAS (Hidden Refresh) 2 -- ns tCDD CAS to DIN Delay Time 18 -- ns 5 tOEZ Output Buffer Turn-off Delay from OE 2 18 ns 4 tOFF Output Buffer Turn-off Delay 2 18 ns 4, 6 1. 2. 3. 4. Measured with the specified current load and 100pF. Access time is determined by the latter of tRAC, tCAC, tCPA, tAA, tOEA. Either tRCH or tRRH must be satisfied. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 5. Either tCDD or tODD must be satisfied. 6. tOFF is referenced from the rising edge of RAS or CAS , whichever is last. 20L9836.00 8/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Read-Modify-Write Cycle -5R Symbol Parameter Unit Min Max Notes tRWC Read-Modify-Write Cycle Time 123 -- ns tRWD RAS to WE Delay Time 70 -- ns 1 tCWD CAS to WE Delay Time 40 -- ns 1 tAWD Column Address to WE Delay Time 50 -- ns 1 tOEH OE Command Hold Time 7 -- ns 1. tWCS, tRWD, tCWD and tAWD are not restrictive parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; If tRWD tRWD(min.), tCWD tCWD(min.) and tAWD tAWD(min.), the cycle is a Read-Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions are met, the condition of the data (at access time) is indeterminate. EDO Mode Cycle -5R Symbol Parameter Units Min. Max. tHCAS CAS Pulse Width (EDO Page Mode) 8 10K ns tHPC EDO Page Mode Cycle Time (Read/Write) 20 -- ns EDO Page Mode Read Modify Write Cycle Time 63 -- ns tDOH Data-out Hold Time from CAS 10 -- ns tWHZ Output buffer Turn-Off Delay from WE 2 15 ns tWPZ WE Pulse Width to Output Disable at CAS High 10 -- ns tCPRH RAS Hold Time from CAS Precharge 35 -- ns tCPA Access Time from CAS Precharge -- 35 ns tRASP EDO Page Mode RAS Pulse Width 50 200K ns tOEP OE High Pulse Width 10 -- ns tOEHC OE High Hold Time from CAS High 10 -- ns tHPRWC Notes 1 1. Measured with the specified current load and 100pF at VOL = 0.8V and VOH = 2.0V. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Refresh Cycle -5R Symbol Parameter Unit Min Max Notes tCHR CAS Hold Time (CAS before RAS Refresh Cycle) 8 -- ns tCSR CAS Setup Time (CAS before RAS Refresh Cycle) 10 -- ns tWRP WE Setup Time (CAS before RAS Refresh Cycle) 15 -- ns tWRH WE Hold Time (CAS before RAS Refresh Cycle) 8 -- ns tRPC RAS Precharge to CAS Hold Time 3 -- ns tREF -- 128 ms 1 Refresh Period -- 64 ms 2 1. 13/11 addressing: 8096 refreshes for RAS Only Refresh. 2. 13/11 addressing: 4096 refreshes for CBR. Presence Detect Read Cycle -5R Symbol tPD tPDOFF Parameter Unit Notes 10 ns 1 10 ns 2 Min Max PDE to Valid Presence Detect Data -- PDE Inactive to Presence Detects Inactive 0 1. Measured with the specified current load and 100pF. 2. tPDOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 20L9836.00 8/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Read Cycle tRC tRAS tRP VIH RAS VIL tCSH tRCD CAS tRSH VIH tCRP tCAS VIL tRAD tRAL tASR tRAH tASC tCAH VIH Address VIL Row tWRP Column tWRH tRCH tRRH tRCS VIH WE NOTE 1 VIL tAA tOES VIH tOEA OE VIL tDZC tCDD tDZO tODD VIH DIN Hi-Z VIL tCAC tCLZ tOFF tOEZ VOH DOUT Hi-Z VOL Valid Data Out Hi-Z tRAC : "H": or "L" NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Write Cycle (Early Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD tRSH CAS VIH tCRP tCAS VIL tRAD tASR tASC tRAH tCAH VIH Address VIL Row tWRP tWRH Column tWCS VIH WE VIL tWCH tWP NOTE 1 VIH OE VIL tDS tDH VIH DIN Valid Data In VIL VOH DOUT Hi-Z VOL : "H" or "L" 20L9836.00 8/98 NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Write Cycle (Late Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD CAS tCRP tRSH VIH tCAS VIL tRAD tASR tASC tRAH tCAH VIH Address VIL Row tWRP Column tWRH tRCS tCWL VIH WE tWP NOTE 1 VIL tRWL VIH OE tOEH VIL tDH tODD tDZO VIH DIN tDS tWRP tDZC Valid Data In Hi-Z VIL tOEZ tCLZ tOEA VOH DOUT Hi-Z VOL Hi-Z* * tOEH greater than or equal to tCWL : "H" or "L" NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Read-Modify-Write-Cycle tRWC tRAS tRP VIH RAS VIL tCSH tRCD VIH CAS tCRP tRSH tCAS tRAD VIL tASR tASC tRAH tCAH VIH Address Row Column VIL tCWD tRWL tAWD tWRP tWRH tCWL tRWD tWP VIH WE tAA NOTE 1 VIL tRCS tOEH VIH OE tOEA VIL tDZC tDH tDS tDZO VIH DIN Hi-Z tCAC VIL DIN tODD tCLZ tOEZ VOH DOUT Hi-Z VOL DOUT tRAC : "H" or "L" 20L9836.00 8/98 Hi-Z * * tOEH greater than or equal to tCWL NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module EDO Page Mode Read Cycle tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tHCAS CAS VIH tRSH tHCAS VIL tCSH tASR Address tRAH tRAL tASC tCAH tASC tCAH tASC tCAH VIH VIL Row Column 1 Column 2 Column N tRAD tWRP tRCH tRRH tWRH tRCS VIH WE VIL NOTE 1 tCPA tOES tWP tCAC tCAC tCPA tOFF tAA tAA tOEA VIH OE VIL tOEZ tRAC tAA tDOH tCAC tDOH tCLZ VOH DOUT VOL Hi-Z : "H" or "L" Data Out 1 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 29 Data Out 2 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module EDO Page Mode Read Cycle (OE Control) tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tHCAS tRSH tHCAS CAS VIH VIL tCSH tASR Address tRAH tRAL tASC tASC tCAH tCAH tASC tCAH VIH VIL Row Column 1 Column 2 Column N tRAD tWRP tWRH tRCH tRRH tRCS VIH WE VIL NOTE 1 tCAC tCAC tCPA tOES tCPA tAA tAA tOEA tOEHC tOFF tOES tOES tOEHC VIH tOEP OE tOEP VIL tRAC tOEA tOEA tAA tCAC tOEZ tOEZ tOEZ tCLZ VOH DOUT Hi-Z VOL : "H" or "L" 20L9836.00 8/98 Data Out 1 Data Out 2 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module EDO Page Mode Read Cycle (WE Control) tRP tRASP VIH RAS tCPRH VIL tCRP tHPC tRCD tCP tCP tHCAS tRSH tHCAS tHCAS CAS VIH VIL tCSH tASR Address tRAH tRAL tASC tASC tCAH tCAH tCAH VIH VIL Row Column 1 Column 2 tRCH tWRP tWRH tRCS tRCH tRCS tRCH tRRH tCAC tOFF tRCS tWPZ VIH VIL Column N tAA tAA tRAD WE tASC tWPZ NOTE 1 tCAC tOES tCPA tCPA tOEA VIH OE VIL tOEZ tRAC tAA tCAC tWHZ tWHZ tCLZ VOH DOUT Hi-Z VOL : "H" or "L" Data Out 1 Data Out N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 29 Data Out 2 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module EDO Page Mode Early Write Cycle tRP tRASP VIH RAS VIL tCRP tHPC tRCD tCP tCP tHCAS CAS VIH tRSH tHCAS tHCAS VIL tRAD tCSH tASR Address tRAH tASC tCAH tRAL tASC tCAH tASC tCAH VIH Row VIL Column 1 Column 2 Column N tCWL tRWL tWRP tWRH VIH WE VIL tWCH tWCS tWCS tWP tWCS tWP tWCH tWP NOTE 1 tDS DIN tWCH tDH tDS tDH tDS tDH VIH Data In 1 VIL : "H" or "L" Data In 2 Data In N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. OE = Don't care 20L9836.00 8/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module EDO Page Mode Late Write Cycle tRP tRASP VIH RAS VIL tHPC tRCD tCRP tCP tCP tHCAS CAS VIH tRSH tHCAS tHCAS VIL tRAD tCSH tASR Address tRAH tASC tCAH tASC tCAH tCAH VIH Row VIL Column 1 Column 2 tCWL tWRP tWRH VIL Column N tCWL tRCS tRCS tCWL tRCS tWP VIH WE tASC tRWL tWP tWP NOTE 1 tOEH tOEH tOEH VIH OE VIL tODD DIN tDS tDH tODD tDS tDH tODD tDS tDH VIH Hi-Z VIL : "H" or "L" Data In 1 Data In N NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 29 Data In 2 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module EDO Page Mode Read Modify Write Cycle tRP tRASP VIH RAS VIL tHPRWC tCRP tCP tRCD CAS VIH tCP tCAS tCAS tCAS VIL tCSH tASC tASC tRAD tASR Address tRAL tRAH tASC tCAH tCAH tCAH VIH VIL Row Column 1 Column 2 Column N tCPA tCWL tCWL tCPA tAA tAA tRWL tRWD tWRP tAWD tWRH tRCS tRCS tCWD tWP VIH WE VIL NOTE 1 VIH tCWD tWP tOEA tODD tODD tOEZ tCLZ tOEH tOEH tOEA tOEA VIL tODD tOEZ tCLZ tOEZ VOH Hi-Z VOL DOUT tDS DOUT DOUT tDS tDH tDS tDH tDH VIH Hi-Z VIL : "H" or "L" 20L9836.00 8/98 tAWD tCAC tOEH tCLZ DIN tWP tCAC tAA DOUT tRCS tCAC tRAC OE tAWD tCWD DIN DIN DIN NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional. Doing so will facilitate compatibility with future EDO DRAMs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module RAS Only Refresh Cycle tRC tRAS tRP VIH RAS VIL tRPC tCRP VIH CAS VIL tRAH tASR VIH Address Row VIL VOH Hi-Z DOUT VOL : "H" or "L" Note: WE, OE, DIN are "H" or "L" (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module CAS Before RAS Refresh Cycle t RC tRAS tRP VIH RAS VIL t RPC tRPC tCSR tCSR tCP CAS t CHR VIH VIL tWRH tWRH tWRP tWRP VIH WE VIL VIH OE VIL tODD tCDD VOH DIN Hi-Z VOL tOEZ tOFF VOH DOUT Hi-Z VOL : "H" or "L" NOTE: Address is "H" or "L" 20L9836.00 8/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Hidden Refresh Cycle (Read) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL tRSH tRCD tCRP tCHR VIH CAS VIL tRAL tRAD tASR tWRH tWRP tASC tRAH tCAH VIH Address Row Column VIL tRRH tRCS VIH WE tORD VIL tAA VIH tOEA OE VIL tDZC tDZO VIH DIN tCDD tODD Hi-Z VIL tCAC tCLZ tOEZ tOFF VOH DOUT Valid Data Out Hi-Z VOL Hi-Z tRAC : "H" or "L" (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 24 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Hidden Refresh Cycle (Write) tRC tRC tRP tRP tRAS tRAS VIH RAS VIL t RSH tRCD tCHR tCRP CAS VIH VIL tASR tASC tRAH tCAH VIH Address Row Column VIL t WRP tWCS VIH tWRH tWCH tWP WE VIL VIH OE VIL tDH t DS VIH DIN Valid Data VIL VOH DOUT Hi-Z VOL : "H" or "L" 20L9836.00 8/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 25 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Presence Detect Read Cycle vIH PDE vIL tPDOFF* tPD vOH PD1-PD8 Valid Presence Detect vOL *PD pins must be pulled high at next level of assembly (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 26 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Layout Drawing 131.35 5.171 133.35 5.25 Front 48.3 1.90 (2X) 4.00 .157 127.35 5.014 6.35 .250 3.0 .118 (2) 0 3.1877 .1255 42.18 1.661 17.78 .700 1.27 PITCH .050 1.00 WIDTH .039 66.68 2.63 SEE DETAIL A Side Detail A 8.13 SCALE 4/1 .320 MAX. 2.0 .078 3.0 .118 7.08 .279 MIN. R 1.00 .0393 _ 0.10 1.27 + _ .004 .050 + Note: All dimensions are typical unless otherwise stated. 20L9836.00 8/98 Millimeters Inches (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 27 of 29 Discontinued (7/00 - last order; 9/00 - last ship) IBM11M32845CB 32M x 72 Chipkill Correct DRAM Module Revision Log Rev 8/98 Contents of Modification Initial release. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 28 of 29 20L9836.00 8/98 Discontinued (7/00 - last order; 9/00 - last ship) International Business Machines Corp.1998 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant. SA14-XXXX-xx